NSC 5962R8960101SSA, 5962R8960101SRA, 5962R8960101S2A, 5962R8960101BSA, 5962R8960101BRA Datasheet
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54AC574•54ACT574
Octal D-Type Flip-Flop with TRI-STATE
®
Outputs
General Description
The ’AC/’ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered common
Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock
(CP) transition.
The ’AC/’ACT574isfunctionally identical to the ’AC/’ACT374
except for the pinouts.
Features
n ICCand IOZreduced by 50
%
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’AC/’ACT374
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT574 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’ACT574: 5962-89601
Logic Symbols
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
TRI-STATE Output Enable Input
O
0–O7
TRI-STATE Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
DS100256-1
IEEE/IEC
DS100256-4
September 1998
54AC574
•
54ACT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100256 www.national.com
Connection Diagrams
Functional Description
The ’AC/’ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and buffered Output Enable are common
to all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
go to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs Internal Outputs Function
OE
CP D Q O
N
H H L NC Z Hold
H H H NC Z Hold
H N L L Z Load
H N H H Z Load
L N L L L Data Available
L N H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
N=LOW-to-HIGH Transition
NC=No Change
Pin Assignment for DIP,
and Flatpak
DS100256-2
Pin Assignment
for LCC
DS100256-3
www.national.com 2
Logic Diagram
DS100256-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com3
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