NEC UPA603T Datasheet
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μPA603T
P-CHANNEL MOS FET (6-PIN 2 CIRCUITS)
The μPA603T is a mini-mold device provided with two MOS FET circuits. It achieves high-density mounting and saves mounting costs.
FEATURES
•Two MOS FET circuits in package the same size as SC-59
•Complement to μPA602T
•Automatic mounting supported
PACKAGE |
DIMENSIONS |
(in millimeters) |
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+0.1 |
–0.5 |
0.32 |
–0.05+0.1 |
0.16 –0.06+0.1 |
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2.8±0.2 |
0.65 |
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1.5 |
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0 to 0.1 |
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0.95 |
0.95 |
0.8 |
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1.9 |
1.1 to 1.4 |
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2.9 ±0.2 |
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PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
PARAMETER |
SYMBOL |
RATINGS |
UNIT |
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Drain to Source Voltage |
VDSS |
–50 |
V |
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Gate to Source Voltage |
VGSS |
+16 |
V |
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Drain Current (DC) |
ID(DC) |
–100 |
mA |
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Drain Current (pulse) |
ID(pulse)* |
–200 |
mA |
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Total Power Dissipation |
PT |
300 (Total) |
mW |
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Channel Temperature |
Tch |
150 |
˚C |
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Storage Temperature |
Tstg |
–55 to +150 |
˚C |
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* PW ≤ 10 ms, Dury Cycle ≤ 50 %
Document No. G11250EJ1V0DS00 (1st edition) |
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Date Published June 1996 P |
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Printed in Japan |
© |
1996 |
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μPA603T |
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ELECTRICAL CHARACTERISTICS (TA = 25 ˚C) |
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PARAMETER |
SYMBOL |
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TEST CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Drain Cut-off Current |
IDSS |
VDS = –50 V, VGS = 0 |
– |
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–1.0 |
μA |
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Gate Leakage Current |
IGSS |
VGS = |
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– |
– |
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+1.0 |
μA |
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+16 V, VDS = 0 |
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Gate Cut-off Voltage |
VGS(off) |
VDS = –5.0 V, ID = –1.0 μA |
–1.5 |
–1.9 |
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–2.5 |
V |
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Forward Transfer Admittance |
|yfs| |
VDS = –5.0 V, ID = –10 mA |
15 |
– |
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– |
mS |
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Drain to Source On-State Resistance |
RDS(on)1 |
VGS = –4.0 V, ID = –10 mA |
– |
60 |
100 |
Ω |
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Drain to Source On-State Resistance |
RDS(on)2 |
VGS = –10 V, ID = –10 mA |
– |
40 |
60 |
Ω |
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Input Capacitance |
Ciss |
VDS = –5.0 V, VGS = 0, f = 1.0 MHz |
– |
17 |
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– |
pF |
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Output Capacitance |
Coss |
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– |
9 |
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– |
pF |
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Reverse Transfer Capacitance |
Crss |
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– |
1 |
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– |
pF |
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Turn-On Delay Time |
td(on) |
VGS(on) = –4.0 V, RG = 10 Ω, |
– |
45 |
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– |
ns |
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VDD = –5.0 V, ID = –10 mA, RL = 500 Ω |
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Rise Time |
tr |
– |
75 |
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– |
ns |
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Turn-Off Delay Time |
td(off) |
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– |
25 |
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– |
ns |
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Fall Time |
tf |
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– |
80 |
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– |
ns |
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Marking: JA
SWITCHING TIME MEASUREMENT CIRCUIT AND CONDITIONS
PG.
0
VGS
τ |
τ = 1 μs
Duty Cycle ≤ 1 %
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VGS |
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RL |
Gate |
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10 % |
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DUT |
voltage |
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VGS(on) |
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waveform |
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90 % |
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VDD |
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RG |
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ID |
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td(on) |
tr |
td(off) |
tf |
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Drain |
0 |
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current |
10 % |
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10 % |
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waveform |
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ID |
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90 % |
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90 % |
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2