NEC UPA2727UT1A DATA SHEET

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UPA2727UT1A

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA2727UT1A

SWITCHING

N-CHANNEL POWER MOSFET

DESCRIPTION

The μ PA2727UT1A is N-channel MOSFET designed for DC/DC converter applications.

FEATURES

Low on-state resistance

RDS(on)1 = 9.6 mΩ MAX. (VGS = 10 V, ID = 8 A) RDS(on)2 = 15 mΩ MAX. (VGS = 4.5 V, ID = 8 A)

Low QGD

QGD = 3.5 nC TYP. (VDD = 15 V, ID = 16 A)

Thin type surface mount package with heat spreader (8-pin HVSON)

RoHS Compliant

ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)

Drain to Source Voltage (VGS = 0 V)

VDSS

30

V

Gate to Source Voltage (VDS = 0 V)

VGSS

±20

V

Drain Current (DC)

ID(DC)

±16

A

Drain Current (pulse) Note1

ID(pulse)

±96

A

Total Power Dissipation Note2

PT1

1.5

W

Total Power Dissipation (PW = 10 sec) Note2

PT2

4.6

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

−55 to +150

°C

Single Avalanche Current Note3

IAS

16

A

Single Avalanche Energy Note3

EAS

26

mJ

PACKAGE DRAWING (Unit: mm)

1.27

1

 

 

 

 

 

8

 

 

 

 

 

0.2

±0.2

 

 

2

7

 

 

5 ±

5.15

 

 

3

6

 

 

 

 

 

 

4

5

 

 

 

+0.1 −0.05

6 ±0.2

 

 

0.10

S

0.42

5.4 ±0.2

 

 

 

 

0.10 M

 

 

 

 

 

 

 

 

 

 

+0.05 −0

0.27±0.05

1.0MAX.

 

 

 

0.2

 

 

 

0

 

 

 

 

 

1

 

 

 

 

 

0.2

 

1, 2, 3

: Source

 

 

 

 

 

±

 

4

: Gate

 

 

 

 

 

4.1

 

5, 6, 7, 8: Drain

 

 

 

 

 

 

 

 

 

3.65 ±0.2

 

0.6 ±0.15

0.7 ±0.15

EQUIVALENT CIRCUIT

Drain

THERMAL RESISTANCE

 

 

 

Gate

 

 

 

 

 

 

Body

 

 

 

 

 

 

 

 

 

Channel to Ambient Thermal Resistance Note2

Rth(ch-A)

83.3

°C/W

 

 

 

 

 

 

 

 

Diode

 

 

 

 

 

 

 

 

 

Channel to Case (Drain) Thermal Resistance

Rth(ch-C)

2.0

°C/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1%

Source

 

2.Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm

3.Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 μH

Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

Document No. G18300EJ1V0DS00 (1st edition)

 

2006, 2007

 

Date Published May 2007 NS CP(K)

 

 

Printed in Japan

NEC UPA2727UT1A DATA SHEET

μ PA2727UT1A

ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

 

MIN.

TYP.

MAX.

UNIT

Zero Gate Voltage Drain Current

IDSS

VDS = 30 V, VGS = 0 V

 

 

 

10

 

μA

Gate Leakage Current

 

IGSS

VGS = ±20 V, VDS = 0 V

 

 

 

±100

nA

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

 

1.5

 

2.5

V

Forward Transfer Admittance Note

| yfs |

VDS = 10 V, ID = 8 A

 

6

 

 

 

S

Drain to Source On-state Resistance Note

RDS(on)1

VGS = 10 V, ID = 8 A

 

 

7.6

9.6

 

 

RDS(on)2

VGS = 4.5 V, ID = 8 A

 

 

11

15

 

Input Capacitance

 

Ciss

VDS = 15 V,

 

 

1170

 

 

pF

Output Capacitance

 

Coss

VGS = 0 V,

 

 

250

 

 

pF

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

 

90

 

 

pF

Turn-on Delay Time

 

td(on)

VDD = 15 V, ID = 8 A,

 

 

13

 

 

ns

Rise Time

 

tr

VGS = 10 V,

 

 

3.6

 

 

ns

Turn-off Delay Time

 

td(off)

RG = 10 Ω

 

 

41

 

 

ns

Fall Time

 

tf

 

 

 

8

 

 

ns

Total Gate Charge

 

QG

VDD = 15 V,

 

 

11

 

 

nC

Gate to Source Charge

 

QGS

VGS = 5 V,

 

 

3.8

 

 

nC

Gate to Drain Charge

 

QGD

ID = 16 A

 

 

3.5

 

 

nC

Body Diode Forward Voltage Note

VF(S-D)

IF = 16 A, VGS = 0 V

 

 

0.83

 

 

V

Reverse Recovery Time

trr

IF = 16 A, VGS = 0 V,

 

 

27

 

 

ns

Reverse Recovery Charge

Qrr

di/dt = 100 A/μs

 

 

23

 

 

nC

Gate Resistance

 

RG

f = 1 MHz

 

 

2.2

 

 

Ω

Note Pulsed

 

 

 

 

 

 

 

 

 

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

 

 

 

 

 

D.U.T.

L

D.U.T.

 

 

VGS

 

 

 

RG = 25 Ω

 

RL

 

 

 

 

 

VGS

10%

VGS

90%

 

 

 

 

 

 

 

 

 

RG

 

Wave Form

 

 

 

 

50 Ω

 

 

 

0

 

 

 

PG.

VDD

PG.

VDD

 

 

 

 

 

VGS = 20 → 0 V

 

 

 

 

 

VDS

 

 

 

 

 

 

 

 

 

90%

 

 

90%

 

BVDSS

 

VGS

 

 

VDS

 

 

 

 

 

 

 

 

10%

10%

 

 

 

0

 

VDS

0

 

 

 

 

 

 

 

IAS

 

 

 

 

 

 

 

 

 

Wave Form

 

 

 

 

ID

VDS

 

τ

 

 

td(on)

tr

td(off)

tf

VDD

 

 

 

 

 

 

 

 

 

 

 

 

τ = 1 μs

 

 

 

ton

 

toff

 

Starting Tch

Duty Cycle ≤ 1%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

IG = 2 mA R

L

PG.

50 Ω

VDD

2

Data Sheet G18300EJ1V0DS

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