NEC UPA1560H Datasheet

DATA SHEET
COMPOUND FIELD EFFECT POWER TRANSISTOR
PA1560
µ µ
N-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DESCRIPTION
The µPA1560 is N-Channel Power MOS FET Array that built in 4 circuits designed for solenoid, motor and lamp driver.
FEATURES
Full mold package with 4 circuits
4 V driving is possible
Low on-state resistance
DS(on)1
= 165 mΩ MAX. (VGS = 10 V, ID = 1.5 A)
R
DS(on)2
R
= 200 mΩ MAX. (VGS = 4 V, ID = 1.5 A)
Low input capacitance
iss
= 600 pF TYP.
C
ORDERING INFORMATION
PART NUMBER PACKAGE
PA1560H 10-pin SIP
µ
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V) V Gate to Source Voltage (V Gate to Source Voltage (V
DS
= 0 V) V
DS
= 0 V) V Drain Current (DC) I Drain Current (pulse) Total Power Dissipation (T Total Power Dissipation (T
Note1
C
= 25°C) P
A
= 25°C) P Channel Temperature T Storage Temperature T Single Avalanche Current Single Avalanche Energy
Note2
Note2
DSS
GSS(AC)
GSS(DC)
D(DC)
D(pulse)
I
T1
T2
ch
stg
AS
I
AS
E
120 V ±20 V
+ 20, –10 V
±3.0 A
±12 A
28 W
3.7 W
150 °C
–55 to + 150 °C
3.0 A
0.9 mJ
PACKAGE DRAWING (Unit : mm)
2.54
4.0
10 MIN.
1.4
0.5±0.1
26.8 MAX.
10
2.5
1.4
12345678910
0.6±0.1
EQUIVALENT CIRCUIT
3
2468
110
579
ELECTRODE CONNECTION 2, 4, 6, 8
: Gate
3, 5, 7, 9
: Drain
1, 10
: Source
Notes 1.
Remark
PW ≤ 10
2.
Starting T
The diode connected between the gate and source of the transistor serves as a protector against ESD.
s, Duty Cycle ≤ 1 %
µ
ch
= 25 °C, VDD = 60 V, RG = 25
When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. G14283EJ1V0DS00 (1st edition) Date Published April 1999 NS CP(K) Printed in Japan
, V
GS
= 20 V → 0 V
©
1999
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
µ
µ
PA1560
µ µ
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 1.5 A 130 165 m = 4.0 V, ID = 1.5 A 145 200 m
= 10 V, ID = 1.0 mA 1.0 1.8 2.5 V Forward Transfer Admittance | yfs |VDS = 10 V, ID = 1.5 A 2 4.5 S Drain Leakage Current I Gate to Source Leakage Current I Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Turn-on Delay Time t Rise Time t Turn-off Delay Time t Fall Time t Total Gate Charge Q Gate to Source Charge Q Gate to Drain Charge Q Body Diode Forward Voltage V
Reverse Recovery Time t Reverse Recovery Charge Q
DSS
VDS = 120 V, VGS = 0 V 10
GSS
VGS = ±20 V, VDS = 0 V ±10
iss
VDS = 10 V 600 pF
oss
VGS = 0 V 160 pF
rss
f = 1.0 MHz 70 pF
d(on)
ID = 1.5 A 35 ns
r
GS(on)
V
= 10 V 80 ns
d(off)
VDD = 60 V 700 ns
f
RL = 30
G
ID = 3.0 A 28 nC
GS
VDD = 96 V 2.5 nC
GD
VGS = 10 V 9 nC
F(S-D)IF
rr
= 3.0 A, VGS = 0 V 0.9 V
IF = 3.0 A, VGS = 0 V
rr
di/dt = 50 A/
s
µ
250 ns
160 ns 280 nC
µ µ
Ω Ω
A A
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
L
V
DD
PG
RG = 25
50
VGS = 20 0 V
DSS
BV
I
AS
V
I
D
DD
V
DS
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
IG = 2 mA
50
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
R
G
µ
R
RG = 10
τ
V
DD
PG.
V
GS
0
τ = 1 s Duty Cycle 1 %
V
GS
Wave Form
I
D
Wave Form
V
GS
10 %
0
90 %
D
I
10 %
0
t
r
t
d(on)
t
on
V
GS(on)
I
D
t
d(off)
t
off
90 %
90 %
10 %
t
f
2
Data Sheet G14283EJ1V0DS00
[MEMO]
µ
µ
PA1560
µ µ
Data Sheet G14283EJ1V0DS00
3
µ
µ
PA1560
µ µ
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
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M7 98. 8
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