NEC uPA2730TP Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

SWITCHING

P-CHANNEL POWER MOS FET

µµµµ

PA2730TP

DESCRIPTION

PACKAGE DRAWING (Unit: mm)

The µPA2730TP which has a heat spreader is P-Channel
MOS Field Effect Transistor designed for power management
applications of notebook computers and Li-ion battery
protection circuit.

FEATURES

• Low on-state resistance
= 7.0 mΩ MAX. (VGS = –10 V, ID = –7.5 A)

DS(on)1

R

= 10.5 mΩ MAX. (VGS = –4.5 V, ID = –7.5 A)

RDS(on)2

= 12.0 mΩ MAX. (VGS = –4.0 V, ID = –7.5 A)

RDS(on)3

: C

• Low Ciss

= 4670 pF TYP.

iss

• Small and surface mount package (Power HSOP8)

ORDERING INFORMATION

PART NUMBER PACKAGE

PA2730TP Power HSOP8

µ

85

14

5.2

1.44 TYP.

1.49 ±0.21

1.27 TYP.

0.40

0.05 ±0.05

14

4.1 MAX.

2.9 MAX.

85

+0.17
–0.2

+0.10
–0.05

2.0 ±0.2
9

S

0.12 M

1.1 ±0.2

+0.10

1, 2, 3 ; Source
4 ; Gate
5, 6, 7, 8, 9 ; Drain

4.4 ±0.150.8 ±0.2

–0.05

0.15

6.0 ±0.3

ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, All terminals are connected.)

Drain to Source Voltage (VGS = 0 V) V

= 0 V) V

Gate to Source Voltage (V
Drain Current (DC) (T
Drain Current (DC)
Drain Current (pulse)
Total Power Dissipation (TC
Total Power Dissipation (TA

DS

= 25°C) I

C

Note1

Note2

= 25°C) P
= 25°C)

Note1

Channel Temperature T
Storage Temperature Tstg −55 to + 150 °C
Single Avalanche Current
Single Avalanche Energy

Note3

Note3

DSS −30 V
GSS m20 V

D(DC)1 m42 A

I

D(DC)2 m20 A

I

D(pulse) m120 A

T1

P

T2
ch

I

AS −15 A

E

AS

40 W

3W

150 °C

22.5 mJ

EQUIVALENT CIRCUIT

Drain

Body

Gate

Source

Diode

S0.10

Notes 1. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec

s, Duty Cycle ≤ 1%

PW ≤ 10

2.

3. Starting T

µ

= 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V

ch

Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately

degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.

Document No. G15983EJ1V0DS00 (1st edition)
Date Published November 2002 NS CP(K)
Printed in Japan

2002

µµµµ

PA2730TP

ELECTRICAL CHARACTERISTICS (TA = 25°C, Unless otherwise noted, All terminals are connected.)

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Zero Gate Voltage Drain Current I
Gate Leakage Current I
Gate Cut-off Voltage V

DSS

GSS

GS(off)

Forward Transfer Admittance | yfs |
Drain to Source On-state Resi stance R

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t

R
R

DS(on)1

DS(on)2

DS(on)3

iss

oss

rss

d(on)

r

d(off)

f

Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t

GS

GDID

F(S-D)IF

rr

Reverse Recovery Charge Q

VDS = –30 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = –10 V, ID = –1 mA

= –10 V, ID = –7.5 A

V

DS

VGS = –10 V, ID = –7.5 A
VGS = –4.5 V, ID = –7.5 A
VGS = –4.0 V, ID = –7.5 A
VDS = –10 V

–

1.0

14 30 S

4670 pF

–

1

µ

100

m

–

2.5

nA

V

5.7 7.0 mΩ

7.7 10.5 mΩ

8.8 12.0 mΩ

A

VGS = 0 V 1220 pF
f = 1 MHz 760 pF
VDD = –15 V, ID = –7.5 A
VGS = –10 V

20 ns
28 ns

RG = 10 Ω 190 ns

110 ns

G

VDD = –24 V
VGS = –10 V

97 nC

10 nC
= 15 A 32 nC
= 15 A, VGS = 0 V 0.81 V

IF = 15 A, VGS = 0 V 65 ns
di/dt = 100 A/ µs62nC

rr

TEST CIRCUIT 1 AVALANCHE CAPABILITY

PG.

VGS = −20 → 0 V

V

G

R

DD

= 25 Ω

50 Ω

I

D

D.U.T.

I

AS

BV

DSS

V

DS

Starting T

L

DD

V

ch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

I

G

PG.

= −2 mA

50 Ω

R

L

V

DD

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

R

PG.

V

GS(−)

0

τ

µ

= 1 s

τ

Duty Cycle ≤ 1%

G

V

R

L

V

Wave Form

V

DD

V

Wave Form

GS(−)

GS

DS

10%

0

V

DS(−)

90%

V

DS

0

t

d(on)

10% 10%

trt

t

on

V

GS

d(off)tf

t

90%

90%

off

2

Data Sheet G15983EJ1V0DS

TYPICAL CHARACTERISTICS (TA = 25°C)

µµµµ

PA2730TP

dT - Percentage of Rated Power - %

- Drain Current - A

D

I

DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA

120

100

80

60

40

20

0

0 25 50 75 100 125 150 175

TA - Ambient Temperature - °C

FORWARD BIAS SAFE OPERATING AREA

- 1000

DS(on)

R
(at V

Limited

GS

= −10 V)

D(pulse)

I

- 100

D(DC)

I

- 10

- 1

Power Dissipation
Limited

- 0.1

Mounted on a glass epoxy board
(1 inc h × 1 in c h × 0. 8 mm)

= 25°C , Single pulse

T

A

- 0.01

- 0.1 - 1 - 10 - 100
VDS - Drain to Source Voltage - V

PW =
100 µs

1 ms

10 ms

100 ms

10 s

- Total Power Dissipation - W

T

P

TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE

4

3.5
3

2.5
2

1.5
1

0.5
0

0 25 50 75 100 125 150 175

Mounted on a glass epoxy board
(1 inch × 1 inch × 0.8 mm)

A

= 25°C , PW = 10 s , Single pulse

T

TA - Ambient Temperature - °C

- Transient Thermal Resistance - °C/W

th(t)

r

1000

100

10

0.1

0.01

Single pulse

1

100

µ

TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH

R

= 89.3°C/W

th(ch-A)

R

= 3.13°C/W

th(ch-C)

Remark r
(1 inch × 1 inch × 0.8 mm) , T
r

th(ch-A)

: Mounted on a glass epoxy board

: TC = 25°C

th(ch-C)

A

= 25°C

1 m 10 m 100 m 1 10 100 1000

PW - Pulse Width - s

Data Sheet G15983EJ1V0DS

3