NEC UPA1853 Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA1853

P-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

DESCRIPTION

The μPA1853 is a switching device which can be driven directly by a 4-V power source.

The μPA1853 features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on.

FEATURES

∙Can be driven by a 4-V power source

∙Low on-state resistance

RDS(on)1 = 85 mΩ MAX. (VGS = –10 V, ID = –1.5 A)

RDS(on)2 = 152 mΩ MAX. (VGS = –4.5 V, ID = –1.5 A)

RDS(on)3 = 180 mΩ MAX. (VGS = –4.0 V, ID = –1.5 A)

ORDERING INFORMATION

PART NUMBER	PACKAGE
μPA1853GR-9JG	Power TSSOP8

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

PACKAGE DRAWING (Unit : mm)

8	5
	1					:Drain1		1.2 MAX.
	2, 3					:Source1
										1.0±0.05
	4					:Gate1
	5					:Gate2
																	0.25
				6, 7		:Source2
	8					:Drain2
											3° –3+5°°					0.5
											0.1±0.05
1	4															0.6 –0.1+0.15

3.15 ±0.15
3.0 ±0.1	0.145 ±0.055
0.65	0.8 MAX.

0.27 –0.08+0.03

0.10 M

6.4 ±0.2
4.4 ±0.1	1.0 ±0.2
	0.1

Drain to Source Voltage

VDSS

–30

V

EQUIVALENT CIRCUIT

Gate to Source Voltage

VGSS

–20/+5

V

Drain1

Drain2

Drain Current (DC)

ID(DC)

# 2.5

A

Drain Current (pulse) Note1

ID(pulse)

# 10

A

Body

Body

Total Power Dissipation Note2

PT

2.0

W

Gate1

Diode Gate2

Diode

Channel Temperature

Tch

150

°C

Gate

Gate

Storage Temperature

Tstg

–55 to +150

°C

Protection

Source1

Protection

Source2

Diode

Diode

Notes 1.

PW ≤ 10 μs, Duty Cycle ≤ 1 %

2.

Mounted on ceramic substrate of 5000 mm2 x 1.1 mm

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. D12968EJ1V0DS00 (1st edition) Date Published October 1999 NS CP(K) Printed in Japan

The mark shows major revised points.	©		1997, 1999

							μ PA1853
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
	CHARACTERISTICS	SYMBOL	TEST CONDITIONS	MIN.	TYP.	MAX.		UNIT
	Drain Cut-off Current	IDSS	VDS = –30 V, VGS = 0 V			–10		μA
	Gate Leakage Current	IGSS	VGS = # 20 V, VDS = 0 V			# 10		μA
	Gate Cut-off Voltage	VGS(off)	VDS = –10 V, ID = –1 mA	–1.0	–1.7	–2.5		V
	Forward Transfer Admittance	| yfs |	VDS = –10 V, ID = –1.5 A	1	3.6			S
	Drain to Source On-state Resistance	RDS(on)1	VGS = –10 V, ID = –1.5 A		64	85		mΩ
		RDS(on)2	VGS = –4.5 V, ID = –1.5 A		114	152		mΩ
		RDS(on)3	VGS = –4.0 V, ID = –1.5 A		135	180		mΩ
	Input Capacitance	Ciss	VDS = –10 V		520			pF
	Output Capacitance	Coss	VGS = 0 V		200			pF
	Reverse Transfer Capacitance	Crss	f = 1 MHz		82			pF
	Turn-on Delay Time	td(on)	VDD = –10 V		60			ns
	Rise Time	tr	ID = –1.5 A		220			ns
	Turn-off Delay Time	td(off)	VGS(on) = –10 V		800			ns
			RG = 10 Ω
	Fall Time	tf			620			ns
	Total Gate Charge	QG	VDD = –24 V		12			nC
	Gate to Source Charge	QGS	ID = –2.5 A		2			nC
	Gate to Drain Charge	QGD	VGS = –10 V		3			nC
	Diode Forward Voltage	VF(S-D)	IF = 2.5 A, VGS = 0 V		0.73			V

TEST CIRCUIT 1 SWITCHING TIME
	D.U.T.
		RL	VGS			90 %
		VGS	10 %		VGS(on)
		Wave Form
	RG		0
PG.		VDD
	RG = 10 Ω
			ID	90 %		90 %
VGS					ID
		ID	0 10 %			10 %
0
		Wave Form
τ			td(on)	tr	td(off)	tf
τ = 1μ s				ton		toff

Duty Cycle ≤ 1 %

TEST CIRCUIT 2 GATE CHARGE

	D.U.T.
	IG = 2 mA	RL
PG.	50 Ω	VDD

2	Data Sheet D12968EJ1V0DS00

μ PA1853

TYPICAL CHARACTERISTICS (TA = 25°C)

DERATING FACTOR OF FORWARD BIAS

SAFE OPERATING AREA

	100
- %	80
Factor	60
dT - Derating	40
	20
	0	60	90	120	150
	30
	TA - Ambient Temperature - ˚C

DRAIN CURRENT vs.

DRAIN TO SOURCE VOLTAGE

−10

Pulsed

−8

VGS = −10 V

− 4.5 V

- A

Current

−6

Drain-ID

−4

−4.0 V

−2

0

0

−0.2

−0.4

−0.6

−0.8

−1

VDS - Drain to Source Voltage - V

GATE TO SOURCE CUT-OFF VOLTAGE vs.

CHANNEL TEMPERATURE

V	−2
-				VDS = −10 V
Cut-off Voltage
				ID = −1 mA
	−1.8
	−1.6
Source	−1.4
Gate to	−1.2
-
VGS(off)	−1
	−50	0	50	100	150
	Tch	- Channel Temperature - ˚C

FORWARD BIAS SAFE OPERATING AREA

	−100
- A	−10			Limited V)		ID (pulse)		PW
									=
					−10
Current		DS(on)		=			10		1	ms
		R	GS		ID (DC)
		(@V						ms
						100
	−1						ms
ID - Drain
						DC
	−0.1
		Single Pulse
		Mounted on Ceramic
		Substrate of 5000mm2 x 1.1mm
−0.01		PD(FET1) : PD(FET2) = 1:1
	−0.1					−1.0	−10.0			−100.0

VDS - Drain to Source Voltage - V

TRANSFER CHARACTERISTICS

−10

		VDS = −10 V
	−1
- A
Current	−0.1			TA = 125 ˚C
				75 ˚C
- Drain	−0.01			25 ˚C
				−25 ˚C
ID	−0.001
−0.0001		−1.0	−2.0	−3.0	−4.0
	0

VGS - Gate to Source Voltage - V

FORWARD TRANSFER ADMMITTANCE vs.

DRAIN CURRENT

	100			VDS = −10 V
S
Admittance -	10
Transfer			TA = −25 ˚C
yfs | - Forward			25	˚C
	1		75	˚C
			125	˚C
|
	0.1
	−0.1	−1	−10		−100
		ID - Drain Current - A

Data Sheet D12968EJ1V0DS00

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