NEC UPA505T Datasheet
DATA SHEET
2.8 ±0.2
1.5
0.95
1.9
2.9 ±0.2
0.8
1.1 to 1.4
0 to 0.1
0.16
+0.1
–0.06
0.65
+0.1
–0.15
0.32
+0.1
–0.05
0.95
MOS FIELD EFFECT TRANSISTOR
µ
PA505T
N-CHANNEL/P-CHANNEL MOS FET (5-PIN 2 CIRCUITS)
The µPA505T is a mini-mold device provided with two
MOS FET circuits. It achieves high-density mounting and
saves mounting costs.
FEATURES
• Two source common MOS FET circuits in package the
same size as SC-59
• Complementary MOS FETs are provided in one package.
• Automatic mounting supported
PACKAGE DIMENSIONS (in millimeters)
PIN CONNECTION (Top View)
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
PARAMETER SYMBOL RATINGS UNIT
Drain to Source Voltage VDSS 50/–50 V
Gate to Source Voltage VGSS ±20/+–16 V
Drain Current (DC) ID(DC) ±100/+–100 mA
Drain Current (pulse) ID(pulse)* ±200/+–200 mA
Total Power Dissipation PT 300 (TOTAL) mW
Channel Temperature Tch 150 ˚C
Storage Temperature Tstg –55 to +150 ˚C
* PW ≤ 10 ms, Duty Cycle ≤ 50 %
Note The left and right values in the ratings column are correspond to N-ch and P-ch FETs, respectively.
Document No. G11241EJ1V0DS00 (1st edition)
Date Published June 1996 P
Printed in Japan
Marking: FA
1996
µ
PA505T
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain Cut-off Current IDSS VDS = 50/–50 V, VGS = 0 – – 1.0
–1.0
Gate Leakage Current IGSS VGS = ±20/+–16 V, VDS = 0 – – ±1.0
+–10
Gate Cut-off Voltage VGS(off) VDS = 5.0/–5.0 V, ID = 1/–1 µA 0.8 1.4 1.8 V
–1.5 –1.9 –2.5
Forward Transfer Admittance |yfs|VDS = 5.0/–5.0 V, ID = 10/–10 mA 20 – – mS
15
Drain to Source On-State Resistance RDS(on)1 VGS = 4/–4 V, ID = 10/–10 mA – 19 30 Ω
60 100
Drain to Source On-State Resistance RDS(on)2 VGS = 10/–10 V, ID = 10/–10 mA – 15 25 Ω
40 60
Input Capacitance Ciss VDS = 5.0/–5.0 V – 16 – pF
VGS = 0, f = 1.0 MHz
Output Capacitance Coss –12 – pF
Reverse Transfer Capacitance Crss –3 – pF
Turn-On Delay Time t d(on) VDD = 5.0/–5.0 V, ID = 10/–10 mA – 1 7 – ns
VGS(on) = 5.0/–5.0 V
Rise Time tr
Turn-Off Delay Time td(off) –68 – ns
Fall Time tf –38 – ns
RG = 10 Ω, RL = 500 Ω
–10 – ns
10
4
4
40
40
100
80
µ
A
µ
A
Marking: FA
Note The left and right values in above table represent the N-ch and P-ch characteristics, respectively.
2
SWITCHING TIME MEASUREMENT CIRCUIT AND MEASUREMENT CONDITIONS
R
G
PG.
DUT
V
GS
τ = 1 s
µ
τ
Duty Cycle ≤ 1 %
R
L
V
DD
Gate
Voltage
Waveform
Drain
Current
Waveform
V
GS
I
D
0
0
10 %
10 %
t
d(on)
t
d(off)
t
on
t
off
t
r
t
f
10 %
90 %
90 %
90 %
I
D
V
GS(on)
0
(RESISTANCE LOADED)
• N-ch part
µ
PA505T
• P-ch part
PG.
0
V
GS
τ = 1 s
Duty Cycle ≤ 1 %
V
GS
Gate
L
DUT
R
G
R
V
DD
Voltage
Waveform
Drain
Current
Waveform
10 %
V
GS(on)
90 %
D
I
t
d(on)
0
10 %
trt
I
d(off)
t
f
10 %
D
90 %
90 %
τ
µ
3
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