NEC UPA2727UT1A DATA SHEET
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ
PA2727UT1A
SWITCHING
N-CHANNEL POWER MOSFET
DESCRIPTION
The
μ
PA2727UT1A is N-channel MOSFET designed for DC/DC converter applications.
FEATURES
• Low on-state resistance
R
DS(on)1 = 9.6 mΩ MAX. (VGS = 10 V, ID = 8 A)
DS(on)2 = 15 mΩ MAX. (VGS = 4.5 V, ID = 8 A)
R
• Low Q
Q
GD
GD = 3.5 nC TYP. (VDD = 15 V, ID = 16 A)
• Thin type surface mount package with heat spreader (8-pin HVSON)
• RoHS Compliant
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V) VDSS 30 V
Gate to Source Voltage (V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation
Total Power Dissipation (PW = 10 sec)
Channel Temperature T
Storage Temperature T
Single Avalanche Current
Single Avalanche Energy
DS = 0 V) VGSS ±20 V
Note1
Note2
Note3
Note3
Note2
D(DC) ±16 A
D(pulse) ±96 A
I
T1 1.5 W
P
T2 4.6 W
P
ch 150 °C
stg −55 to +150 °C
AS 16 A
I
AS 26 mJ
E
THERMAL RESISTANCE
Channel to Ambient Thermal Resistance
Channel to Case (Drain) Thermal Resistance R
Notes 1. PW ≤ 10
μ
s, Duty Cycle ≤ 1%
2. Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm
3. Starting T
ch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade
the device operation. Steps must be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred.
Note2
th(ch-A) 83.3 °C/W
R
th(ch-C) 2.0 °C/W
PACKAGE DRAWING (Unit: mm)
1.27
1
2
3
4
−0.05
+0.1
0.42
0.10 M
−0
+0.05
0
0.2
6 ±0.2
5.4 ±0.2
3.65 ±0.2
0.6 ±0.15
8
7
6
5
1
4.1 ±0.2
1.0 MAX.
0.27 ±0.05
0.7 ±0.15
EQUIVALENT CIRCUIT
Drain
Gate
μ
H
Source
Body
Diode
5 ±0.2
5.15 ±0.2
0.10 S
1, 2, 3 : Source
4 : Gate
5, 6, 7, 8: Drain
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G18300EJ1V0DS00 (1st edition)
Date Published May 2007 NS CP(K)
Printed in Japan
2006, 2007
μ
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
PA2727UT1A
Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 10
V
Gate Leakage Current IGSS
GS = ±20 V, VDS = 0 V
±100
μ
nA
A
Gate to Source Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.5 V
Note
Forward Transfer Admittance
Drain to Source On-state Resistance
Note
| y
fs | VDS = 10 V, ID = 8 A 6 S
DS(on)1 VGS = 10 V, ID = 8 A 7.6 9.6 mΩ
R
RDS(on)2 VGS = 4.5 V, ID = 8 A 11 15 mΩ
Input Capacitance Ciss VDS = 15 V, 1170 pF
Output Capacitance Coss VGS = 0 V, 250 pF
Reverse Transfer Capacitance Crss f = 1 MHz 90 pF
Turn-on Delay Time td(on) VDD = 15 V, ID = 8 A, 13 ns
Rise Time tr VGS = 10 V, 3.6 ns
Turn-off Delay Time td(off) RG = 10 Ω 41 ns
Fall Time tf 8 ns
Total Gate Charge QG VDD = 15 V, 11 nC
Gate to Source Charge QGS VGS = 5 V, 3.8 nC
Gate to Drain Charge QGD ID = 16 A 3.5 nC
Body Diode Forward Voltage
Note
V
F(S-D) IF = 16 A, VGS = 0 V 0.83 V
Reverse Recovery Time trr IF = 16 A, VGS = 0 V, 27 ns
Reverse Recovery Charge Qrr di/dt = 100 A/μs 23 nC
Gate Resistance RG f = 1 MHz 2.2
Ω
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
G
= 25 Ω
R
PG.
50 Ω
VGS = 20 → 0 V
BV
DSS
I
AS
I
D
V
DD
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
PG.
50 Ω
2
V
DS
Starting T
L
R
V
DD
L
R
V
DD
PG.
V
GS
G
L
R
V
DD
0
τ
μ
τ = 1 s
D.U.T.
ch
Duty Cycle ≤ 1%
V
GS
Wave Form
V
DS
Wave Form
V
GS
10%
0
V
DS
90%
V
DS
0
10% 10%
t
d(on)trtd(off)tf
t
on
90%
V
GS
90%
t
off
Data Sheet G18300EJ1V0DS
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