µ
µ µ
µ
查询UPD16647供应商
DATA SHEET
MOS INTEGRATED CIRCUIT
PD16647
402/384-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)
DESCRIPTION
The µ PD16647 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the
driver circuit operates at 5.0 V. The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed
in 64-value outputs γ -corrected by the internal D/A converter and 10 external power supplies. The clock frequency is
50 MHz MIN. µ PD16647 can be used in TFT-LCD panels conforming to the SVGA standards.
FEATURES
CMOS level input
•
402/384 outputs
•
6 bits (gray scale data) x 3 dots input
•
64-value output by 10 external power supplies and internal D/A converter
•
Output dynamic range : V
•
High-speed data transfer: f
•
Level of γ -corrected power supply can be inverted
•
Input data inversion function (INV)
•
Precharge-less output buffer
•
Logic supply voltage (V
•
Driver supply voltage (V
•
Slim TCP
•
SS2
+ 0.1 V to V
MAX
=50 MHz MIN.(internal data transfer rate at supply voltage V
DD1
) : 3.3 V ± 0.3 V
DD2
) : 5.0 V ± 0.5 V
DD2
−
0.1 V
DD1
of logic circuit =3.0 V)
ORDERING INFORMATION
Part Number Package
PD16647N-xxx TCP (TAB package)
µ
Remark
Document No. S13607EJ2V0DS00 (2nd edition)
Date Published August 1999 NS CP (K)
Printed in Japan
The TCP package is a custom-ordered item. Users are requested to consult with an NEC sales
representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark
••••
shows major revised points.
©
1998
1. BLOCK DIAGRAM
µ
µ
PD16647
µ µ
STHR
D
00 - D05
D
10 - D15
D
20 - D25
V
R,/L
CLK
Osel
INV
STB
Bcont
0
- V
STHL
V
DD1
134-bit bidirectical shift register
1C2
C
C
133
C
134
(3.3 V)
SS1
V
Data register
Latch
V
DD2
9
D/A converter
(5.0 V)
V
SS2
Remark
Output buffer
S1S2S
3
/xxx indicates active lo w signal.
S
402/384
2
Data Sheet S13607EJ2V0DS00
µ
µ
PD16647
µ µ
2. PIN CONFIGURATION (
B
cont
V
SS2
V
DD2
V
DD1
R,/L
INV
STHL
D
20
D
21
D
22
D
23
D
24
D
25
D
10
D
11
D
12
D
13
D
14
D
15
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
CLK S
STB S
D
00
D
01
D
02
D
03
D
04
D
05
STHR
V
SS1
V
DD2
V
SS2
O
sel
PD16647N-xxx)
µ
µ
µ µ
Copper foil
surface
S
402/384
S
401/383
S
400/382
S
399/381
S
212/194
S
211/193
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
S
4
S
3
S
2
S
1
Remark
This figure does not specify the TCP package.
Data Sheet S13607EJ2V0DS00
3
µ
µ
PD16647
µ µ
3. PIN DESCRIPTION
Pin Symbol Pin Name Description
402/384
S1 to S
D00 to D
D10 to D
D20 to D
R,/L Shift direction sel ect input This pin inputs/outputs start pulses in cascade mode.
STHR Right shift start pul se I/O R,/L = H : Inputs start pulse
STHL Left shift start pulse I/O R/L = H : Outputs start pulse
Bcont Bias control This pin can be used to finely control the bias current inside the output
CLK Shift clock input Inputs shift cl ock to shift regist er. Display data is loaded to data register at
STB Latch input Contents of data register are latched at rising edge, transferred to D/A
Osel Selection of number of out puts Selects number of outputs. This pin is int ernal l y pul l ed up t o V
9
V0 to V
INV Data inversion input Input data can be inverted when display data is loaded.
DD1
V
DD2
V
SS1
V
SS2
V
Driver output Output 64 gray-scale analog voltages converted from digital s i gnal s .
1
192
to S
, S
211/193
402/384
to S
)
402/384
Osel = H or open: 402 outputs (S
Osel = L : 384 outputs (S
193
S
05
Display data input Inputs 18-bit-wide display gray scal e data (6 bits) x 3 dots (RGB).
15
25
DX0 : LSB, DX5 : MSB
210
to S
outputs are invalid in 384 outputs .
1
to S
Shift direction of shift register is as follows:
1
402
S
→
→
402
, STHL output
1
, STHR output
S
R,/L = H : STHR input, S
R,/L = L : STHL input, S
R,/L = L : Outputs start pulse
R/L = L : Inputs start pul se
amplifier. In cas es when fine-control is neces sary, connect this pin t o V
using a resistor of 10 to 100kΩ (per IC). When this fine-control function is
not required, short-circuit this pin to V
Function/Bcont
.
DD2
. Refer to 7.
rising edge of this pin. S tart pulse output goes high at ris ing edge of 134th
clock after start pulse has been input, and serves as start pulse to driver in
next stage. 134th clock of dri ver in firs t stage s erves as s tart puls e of dri ver
in next stage.
converter, and output as analog voltage corresponding to display data.
Contents of internal shift register are c leared af ter S TB has been input . One
pulse of this signal is input when
PD16647 is started, and then device
µ
operates normally.
For STB input timi ng, refer to
Osel = H or open : 402 outputs (S
Osel = L : 384 outputs (S
-corrected power supply Inputs γ-corrected power from external source.
γ
SS2
V
≤ V9 ≤ V8 ≤ V7 ≤ V6 ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ V
SS2
V
≤ V0 ≤ V1 ≤ V2 ≤ V3 ≤ V4 ≤ V5 ≤ V6 ≤ V7 ≤ V8 ≤ V9 ≤ V
9. Switching Characteristics Waveform.
1
402/384
1
to S
192
, S
to S
211/193
to S
)
402/384
Maintain gray scale power supply during gray scale voltage output.
INV = H : Inverts and loads input data.
INV = L : Does not invert input data.
Logic circuit power supply 3.3 V ± 0.3 V
Driver circuit power supply 5.0 V ± 0.5 V
Logic ground Ground
Driver ground Ground
)
Bias Current Control
DD1
.
)
DD2
or
DD2
DD2
Caution Be sure to turn on power in the order V
turn off power in the reverse order, to prevent the
sure to observe this power sequence even during a transition period.
4
Data Sheet S13607EJ2V0DS00
DD1
, logic input, V
DD2
, and gray scale power (V0 to V9), and
PD16647 from being damaged by latchup. Be
µ
µ
µ µ
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
µ
µ
PD16647
µ µ
The 10 major points on the γ -characteristic curve of the LCD panel are arbitrarily set by external power supplies V
through V9. If the display data is 00H or 3FH, gray scale voltage V0 or V9 is output. If the display data is in the range
n+1
01H to 3EH, the high-order 3 bits select an external power pair V
n+1
to Vn into eight segments by means of D/A conversion (however, the ranges from V8 to V7 and from V1 to V
of V
, Vn. The low-order 3 bits evenly divide the range
0
are divided into seven segments) to output a 64 gray scale voltage.
DX5(MSB) D
High-order 3 bits
: γ-corrected power selected
n
, V
(V
D
X5
D
X4
000
001
010
011
100
101
110
111
D
X4
D
X3
D
X2
D
X1
D
X0
(LSB)
Low-order 3 bits
n+1
: 3-bit D/A (range V
)
X3
V
n+1-Vn
V
1-V2
V
2-V3
V
3-V4
V
4-V5
V
5-V6
V
6-V7
V
7-V8
V
8-V9
V
n
n
to V
n+1
is divided to 7 or 8 segments)
8
V
n+1
0001001201030114100510161107111
Figure4-1. Relationship between Input Data and
V
0
V
DD2
γ-corrected Voltage
gray scale supply specified
by 00H
7 segments
0
V
1
8 segments
V
2
8 segments
V
3
8 segments
V
4
8 segments
V
5
8 segments
V
6
8 segments
V
7
7 segments
V
8
V
9
V
SS2
07F171F
27 2F 37 3F
gray scale supply specified
by 3FH
Input data (HEX)
Data Sheet S13607EJ2V0DS00
5
Table 4–1. Relationship between Input Data and Output Voltage
D
D
D
D
Input Data
X5
X4
X3
D
X2
00H 000000
01H 000001
02H 000010
03H 000011
04H 000100
05H 000101
06H 000110
07H 000111
08H 001000
09H 001001
0AH001010
0BH001011
0CH001100
0DH001101
0EH001110
0FH001111
10H 010000
11H 010001
12H 010010
13H 010011
14H 010100
15H 010101
16H 010110
17H 010111
18H 011000
19H 011001
1AH011010
1BH011011
1CH011100
1DH011101
1EH011110
1FH011111
20H 100000
21H 100001
22H 100010
23H 100011
24H 100100
25H 100101
26H 100110
27H 100111
28H 101000
29H 101001
2AH101010
2BH101011
2CH101100
2DH101101
2EH101110
2FH101111
30H 110000
31H 110001
32H 110010
33H 110011
34H 110100
35H 110101
36H 110110
37H 110111
38H 111000
39H 111001
3AH111010
3BH111011
3CH111100
3DH111101
3EH111110
3FH111111
D
X1
X0
Output Voltage
V
0
V
+ (V0 – V1) × 6/7
1
V
+ (V0 – V1) × 5/7
1
V
+ (V0 – V1) × 4/7
1
V
+ (V0 – V1) × 3/7
1
V
+ (V0 – V1) × 2/7
1
V
+ (V0 – V1) × 1/7
1
V
1
V
+ (V1 – V2) × 7/8
2
V
+ (V1 – V2) × 6/8
2
V
+ (V1 – V2) × 5/8
2
V
+ (V1 – V2) × 4/8
2
V
+ (V1 – V2) × 3/8
2
V
+ (V1 – V2) × 2/8
2
V
+ (V1 – V2) × 1/8
2
V
2
+ (V2 – V3) × 7/8
V
3
V
+ (V2 – V3) × 6/8
3
V
+ (V2 – V3) × 5/8
3
V
+ (V2 – V3) × 4/8
3
V
+ (V2 – V3) × 3/8
3
V
+ (V2 – V3) × 2/8
3
V
+ (V2 – V3) × 1/8
3
V
3
V
+ (V3 – V4) × 7/8
4
+ (V3 – V4) × 6/8
V
4
V
+ (V3 – V4) × 5/8
4
V
+ (V3 – V4) × 4/8
4
V
+ (V3 – V4) × 3/8
4
V
+ (V3 – V4) × 2/8
4
V
+ (V3 – V4) × 1/8
4
V
4
V
+ (V4 – V5) × 7/8
5
V
+ (V4 – V5) × 6/8
5
V
+ (V4 – V5) × 5/8
5
V
+ (V4 – V5) × 4/8
5
V
+ (V4 – V5) × 3/8
5
V
+ (V4 – V5) × 2/8
5
V
+ (V4 – V5) × 1/8
5
V
5
V
+ (V5 – V6) × 7/8
6
+ (V5 – V6) × 6/8
V
6
V
+ (V5 – V6) × 5/8
6
V
+ (V5 – V6) × 4/8
6
V
+ (V5 – V6) × 3/8
6
V
+ (V5 – V6) × 2/8
6
V
+ (V5 – V6) × 1/8
6
V
6
V
+ (V6 – V7) × 7/8
7
V
+ (V6 – V7) × 6/8
7
V
+ (V6 – V7) × 5/8
7
V
+ (V6 – V7) × 4/8
7
V
+ (V6 – V7) × 3/8
7
V
+ (V6 – V7) × 2/8
7
V
+ (V6 – V7) × 1/8
7
V
7
V
+ (V7 – V8) × 6/7
8
V
+ (V7 – V8) × 5/7
8
V
+ (V7 – V8) × 4/7
8
V
+ (V7 – V8) × 3/7
8
V
+ (V7 – V8) × 2/7
8
+ (V7 – V8) × 1/7
V
8
V
8
V
9
µ
µ
PD16647
µ µ
6
Data Sheet S13607EJ2V0DS00
µ
µ
PD16647
µ µ
4.1
-Corrected Power Circuit
γ
γ
γ γ
The reference power supply of the D/A converter consists of a ladder circuit with a total of 64 resistors, and
resistance Σri between
-corrected power pins consists of seven or eight series resistors, and resistance Σri in the figure below is indicated
γ
as the sum of the seven or eight resistors. The resistance ratio between the
designed to be a value relatively close to the ratio of the
-corrected power pins differs depending on each pair of γ -corrected power pins. One pair of
γ
-corrected power pins (Σri ratio) is
γ
-corrected voltages V1 through V8 (gray scale voltages in 7
γ
steps) used in an actual LCD panel. Under ideal conditions where there is no difference between the two, therefore,
there is no voltage difference between the voltage of the
steps of the resistor ladder circuits of the
8
. As a result, a voltage follower circuit is not necessary.
V
PD16647, and no current flows into the γ -corrected power pins V1 through
µ
-corrected power supplies and the gray scale voltages in 7
γ
Figure4–2
-corrected power pin
γ
V
0
V
1
V
2
V
3
V
4
V
5
V
6
V
7
V
8
-Corrected Power Circuit
γ
γ
.
γ γ
-corrected resister
γ
i
0
R
0 :
1.98 k
i
1
R
1 :
1.72 k
i
2
R
2
:0.86 k
i
3
R
3 :
R
R
R
R
0.99 k
4 :
0.73 k
5 :
0.79 k
6
:1.06 k
7 :
1.58 k
i
4
i
5
i
6
i
7
i
8
7
Ω = Σ r
i=1
8
Ω = Σ r
i=1
8
Ω = Σ r
i=1
8
Ω = Σ r
i=1
Ω = Σ r
i=1
Ω = Σ r
i=1
8
Ω = Σ r
i=1
7
Ω = Σ r
i=1
PD16647
µ
i
i
i
i
8
i
8
i
i
i
Sum of eight
-corrected resistors
γ
6.28 k
Ω
7
R
8 :
i
V
9
Data Sheet S13607EJ2V0DS00
9
µ
µ
PD16647
µ µ
5. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE
Data format : 6 bits x RGB (3 dots)
Input width : 18 bits (1 pixel data)
(1) R,/L = H (right shift)
Output S
Data D00 to D
1
05
2
S
D10 to D
3
S
15
D20 to D
25
4
S
D00 to D
401/383
…
05
…
S
10
15
to D
D
402/384
S
D20 to D
25
(2) R,/L = L (left shift)
Output S
Data D00 to D
1
05
2
S
D10 to D
3
S
15
D20 to D
25
4
S
D00 to D
401/383
…
05
…
S
10
15
to D
D
402/384
S
D20 to D
25
6. OPERATION OF OUTPUT BUFFER
The output buffer consists of an operational amplifier circuit that does not perform precharge operation. Therefore,
driver output current I
VOH1/2
is the charging current to the LCD, and I
VOL1/2
is the discharging current.
Figure6–1.
V
DD2
S
n
V
SS2
LCD panel driving waveform of
Write
(I
VOL1/2/IVOH1/2
)
PD16647
µ
µ
µ µ
Write
VOL1/2/IVOH1/2
(I
)
1 horizontal period
8
Data Sheet S13607EJ2V0DS00
µ
µ
PD16647
µ µ
7. BIAS CURRENT CONTROL FUNCTION/Bcont
It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When
using this function, connect this pin to the stabilized V
DD2
this function, however, short-circuit this pin to V
.
Figure7–1. Bias Current Control Function/Bcont
Bcont
V
DD2
DD2
potential using an external resistor (R
PD16647
µ
R
EXT
EXT
). When not using
Refer to the table below for the percentage of current regulation when using the bias current control function.
Table7–1.
Remark
Current Consumption Regulation Percentage Compared to Normal Mode
EXT
R
SHORT 100 %
10 k
Ω
20 k
Ω
40 k
Ω
80 k
Ω
Current Consumption Regulation Percentage
95 %
91 %
85 %
79 %
Be aware that the above current consumption regulation percentages are not product-
characteristic guaranteed as they are based on the results of simulation.
Caution Because the low-power and bias-current control functions control the bias current in the output
amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the
characteristics of the output amplifier will simultaneously change. Therefore, when using these
functions, be sure to sufficiently evaluate the picture quality.
Data Sheet S13607EJ2V0DS00
9
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (V
Parameter Symbol Ratings Unit
SS1
= V
SS2
= 0 V)
µ
µ
PD16647
µ µ
Logic Supply Voltage V
Driver Supply Voltage V
Input Voltage V
Output Voltage V
Operating Ambient Tem perature T
Storage Temperature T
DD1
DD2
I
O
A
stg
–0.3 to +4.5 V
–0.3 to +6.0 V
–0.3 to V
–0.3 to V
DD1,2
+ 0.3 V
DD1,2
+ 0.3 V
–10 to +75
–55 to +125
Caution If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,
specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the range of the absolute maximum ratings.
Recommended Operating Range (T
Parameter Symbol MIN. TYP. MAX. Unit
Logic Supply Voltage V
Driver Supply Voltage V
High-level Input Voltage V
Low-level Input Voltage V
-corrected Supply Voltage V
γ
Maximum Clock Frequency f
DD1
DD2
IH
IL
0
MAX.
to V
A
= –10 to +75 °C, V
9
V
SS1
SS2
= V
= 0 V)
3.0 3.3 3.6 V
4.5 5.0 5.5 V
DD1
0.7 V
0 0.3 V
SS2
+ 0.1 V
DD1
V
DD1
DD2
– 0.1 V
50 MHz
C
°
C
°
V
V
10
Data Sheet S13607EJ2V0DS00
µ
µ
PD16647
µ µ
Electrical Characteristics (TA = –10 to +75 °C, V
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input Leakage Current I
Pull-up Resistor R
High-level Output Voltage V
Low-level Output Voltage V
Static Current Consumption of I
-corrected Power V
γ
Driver Output Current I
Output Voltage Deviation
Output Swing Difference Deviat i on
Output Voltage Range V
Dynamic Logic Current Consumption I
Dynamic Driver Current Consumption I
IL
vn1
VOH2
VOL2
I
∆
∆
DD1
DD2
D00-D05,D10-D15,D20-D
R,/L,STB
PU
OH
OL
O
V
P-P
V
O
DD1
V
STHR(STHL),IO = −1.0 mA V
STHR(STHL),IO = +1.0 mA 0.5 V
DD1
V
n
DD2
V
OUT
V
DD1
V
OUT
V
DD1
V
DD1
V
OUT
V
Input data (±5) mV
Input data : 00H to 3FH V
No load, V
No load, V
DD1
= 3.3 V
0.3 V, V
±±±±
DD2
= 5.0 V
25
0.5 V, V
±±±±
SS1
= V
±
SS2
1.0
= 0 V)
= 3.3 V 40 100 250 k
DD1
0.5 V
−
V3-V
V4-V
V5-V
V6-V
V7-V
V8-V
= 5.0 V
= 5.0 V
=5.0 V,
Note2
Note2
1
2
3
4
5
6
7
8
9
Note1
Note1
126 253 506
145 291 582
289 579 1158
252 504 1008
343 686 1372
315 631 1262
237 474 948
158 316 632
40 80 160
(−0.12)
0.03 mA
−
0.04 (0.16) mA
±
SS2
+ 0.1 V
10
20 mV
±
DD2
0.1 V
−
0.5 2.5 mA
5.0 10.0 mA
= 3.3 V, V0-V
n+1
= 0.5 V, V1-V
V
−
= 5.0 V V2-V
= 4.4 V, VX = 4.9 V
= 3.3 V, V
DD2
= 0.6 V, VX = 0.1 V
Note1
DD2
DD2
= 5.0 V
DD2
DD2
= 3.3 V
= 3.3 V, V
= 3.3 V, V
=2.5 V
A
µ
Ω
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
Notes 1.
X
V
refers to the output voltage of analog output pins S1 to S
OUT
V
refers to the voltage applied to analog output pins S1 to S
2.
The STB cycle is specified at 31 µ s and f
CLK
= 16 MHz.
Data Sheet S13607EJ2V0DS00
402/384
.
402/384
.
11
µ
µ
PD16647
µ µ
Switching Characteristics (TA =
Parameter Symbol Condition MIN. TYP. MAX. Unit
Start Pulse Delay Time t
Driver Output Delay Time t
Input Capacitance C
PLH1
PHL1
t
PLH2
PLH3
t
PHL2
t
PHL3
t
C
C
I1
I2
I3
<Output Load>
Output
10 to +75
−−−−
C, V
°°°°
DD1
= 3.3 V
0.3 V, V
±±±±
DD2
= 5.0 V
0.5 V, V
±±±±
SS1
= V
SS2
= 0 V)
CL = 15 pF 7 12 ns
712ns
DD2
V
= 5.0 V VO: 0.1 V → 4.9 V 2.2 10
5 kΩ +36 pF 2.9 12
VO: 4.9 V → 0.1 V 2.6 10
3.6 12
s
µ
s
µ
s
µ
s
µ
STHR (STHL), TA = 25 °C1020pF
V0 to V9, TA = 25 °C 100 150 pF
STHR (STHL), other than V0 to V9 , TA = 25 °C1015pF
2.5 kΩ
9 pF
2.5 kΩ
18 pF
9 pF
Timing Requirements (TA =
Parameter Symbol Condition MIN. TYP. M AX. Unit
Clock Pulse Width PW
Clock Low Period PW
Clock High Period PW
Data Setup Time t
Data Hold Time t
Start Pulse Setup Time t
Start Pulse Hold Time t
INV Setup Time t
INV Hold Time t
Start Pulse Low Period t
STB Setup Time t
★
STB Pulse Width PW
Data Invalid Period t
Last Data Timing t
CLK-STB Time t
STB-CLK Time t
10 to +75 °C, V
−−−−
CLK
CLK (L)
CLK (H)
SETUP1
HOLD1
SETUP2
HOLD2
SETUP4
HOLD4
SPL
SPR
SETUP3
STB
INV
LDT
CLK-STB
STB-CLK
DD1
= 3.3 V
0.3 V, V
±±±±
DD2
= 5.0 V
0.5 V, V
±±±±
SS1
= V
SS2
= 0 V)
20 ns
4ns
4ns
4ns
0ns
4ns
0ns
4ns
0ns
2CLK
384 outputs 128 CLKStart Pulse Rise Time t
402 outputs 134 CLK
1CLK
2CLK
1CLK
1CLK
CLK ↑ → STB
STB ↑ → CLK
↑
↑
7ns
7ns
12
Data Sheet S13607EJ2V0DS00
★
9. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H)
µ
µ
PD16647
µ µ
Unless otherwise specified, the input level is VIH = 0.7 V
DD1VSS1VDD1VSS1VDD1VSS1
V
f
t
r
10%
t
90%
12
SPL
t
SETUP3
t
801
800
799
to
2398
D
to
2395
D
to
2392
D
6
D
to
4
D
3
D
to
1
D
2400
D
2397
D
2394
D
DD1VSS1
V
PHL1
t
DD1
, VIL = 0.3 V
DD1VSS1
V
STB-CLK
t
CLK-STB
t
DD1VSS1
V
LDT
t
DD1
STB
PW
.
DD2
6-bit accuracy
Target Voltage ± 0.1 V
PLH21/22
PLH31/32
t
t
Hi-Z
PHL31/32
t
PHL21/22
t
CLK(H)
PW
CLK
PW
CLK(L)
PW
136
3
2
1
135
134
CLK
HOLD2
t
SETUP2
t
STHR
(1st Dr.)
HOLD1
t
SETUP1
t
INV
t
to
405
403
D
D
to
402
400
D
D
to
399
397
D
D
6
D
to
4
D
3
D
to
1
D
INVALID INVALID
n5
D
to
n0
D
PLH1
t
HOLD4
t
SPR
SETUP4
t
t
INVALID INVALID
INV
STHL
(1st Dr.)
Data Sheet S13607EJ2V0DS00
STB
OUT
V
13
µ
µ
PD16647
µ µ
10. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the µ PD16647.
For more details, refer to the
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
PD16647N-xxx : TCP(TAB Package)
µ
Mounting Condition Mounting Method Condition
Thermocompressi on Soldering Heating tool 300 to 350 °C, heating for 2 to 3 sec ; pressure 100g(per
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more mounting methods at a time.
Semiconductor Device Mounting Technology Manual(C10535E).
solder)
ACF
(Adhesive Conductive
Film)
Temporary bonding 70 to 100 °C ; pressure 3 to 8 kg/cm
sec. Real bonding 165 to 180 °C pressure 25 to 45 kg/cm
40secs(When us i ng the anisotropy conductive fi l m SUMIZAC1003 of
Sumitomo Bakelite,Ltd).
2
; time 3 to 5
2
time 30 to
14
Data Sheet S13607EJ2V0DS00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
DD
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
µ
µ
PD16647
µ µ
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S13607EJ2V0DS00
15
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System(C10983E)
Quality Grades to NEC’s Semiconductor Devices(C11531E)
µ
µ
PD16647
µ µ
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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