User’s Manual
μPD78054, 78054Y SUBSERIES
8-BIT SINGLE-CHIP MICROCONTROLLERS
μPD78052 μPD78052Y μPD78053 μPD78053Y μPD78054 μPD78054Y μPD78P054 μPD78055Y μPD78055 μPD78056Y μPD78056 μPD78058Y μPD78058 μPD78P058Y μPD78P058
μPD78052(A)
μPD78053(A)
μPD78054(A)
Document No. U11747EJ5V0UM00 (5th edition)
Date Published April 1998 N CP (K)
© 1992
Printed in Japan
[MEMO]
2
NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
3
FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation.
MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Sun OS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
NEWS and NEWS-OS are trademarks of SONY Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: μPD78P054KK-T, 78P058KK-T, 78P058YKK-T The customer must judge the need for license:
μPD78052GC-×××-8BT, 78052GK-×××-BE9, 78052YGC-×××-8BT
μPD78053GC-×××-8BT, 78053GK-×××-BE9, 78053YGC-×××-8BT
μPD78054GC-×××-8BT, 78054GK-×××-BE9, 78054YGC-×××-8BT μPD78P054GC-3B9, 78P054GC-8BT, 78P054GK-BE9 μPD78055GC-×××-8BT, 78055GK-×××-BE9, 78055YGC-×××-8BT μPD78056GC-×××-8BT, 78056GK-×××-BE9, 78056YGC-×××-8BT μPD78058GC-×××-8BT, 78058GK-×××-BE9, 78058YGC-×××-8BT μPD78P058GC-8BT, 78P058YGC-8BT
μPD78052GC(A)-×××-3B9, 78053GC(A)-×××-3B9, 78054GC(A)-×××-3B9
4
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program” for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.
The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5
5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
•Device availability
•Ordering information
•Product release schedule
•Availability of related technical literature
•Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
•Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.) |
NEC Electronics (Germany) GmbH |
NEC Electronics Hong Kong Ltd. |
Santa Clara, California |
Benelux Office |
Hong Kong |
Tel: 408-588-6000 |
Eindhoven, The Netherlands |
Tel: 2886-9318 |
800-366-9782 |
Tel: 040-2445845 |
Fax: 2886-9022/9044 |
Fax: 408-588-6130 |
Fax: 040-2444580 |
NEC Electronics Hong Kong Ltd. |
800-729-9288 |
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NEC Electronics (France) S.A. |
Seoul Branch |
NEC Electronics (Germany) GmbH |
Velizy-Villacoublay, France |
Seoul, Korea |
Duesseldorf, Germany |
Tel: 01-30-67 58 00 |
Tel: 02-528-0303 |
Tel: 0211-65 03 02 |
Fax: 01-30-67 58 99 |
Fax: 02-528-4411 |
Fax: 0211-65 03 490 |
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NEC Electronics Singapore Pte. Ltd. |
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NEC Electronics (France) S.A. |
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NEC Electronics (UK) Ltd. |
Spain Office |
United Square, Singapore 1130 |
Milton Keynes, UK |
Madrid, Spain |
Tel: 65-253-8311 |
Tel: 01908-691-133 |
Tel: 01-504-2787 |
Fax: 65-250-3583 |
Fax: 01908-670-290 |
Fax: 01-504-2860 |
NEC Electronics Taiwan Ltd. |
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NEC Electronics Italiana s.r.1. |
NEC Electronics (Germany) GmbH |
Taipei, Taiwan |
Milano, Italy |
Scandinavia Office |
Tel: 02-719-2377 |
Tel: 02-66 75 41 |
Taeby, Sweden |
Fax: 02-719-5951 |
Fax: 02-66 75 42 99 |
Tel: 08-63 80 820 |
NEC do Brasil S.A. |
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Fax: 08-63 80 388 |
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Cumbica-Guarulhos-SP, Brasil |
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Tel: 011-6465-6810 |
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Fax: 011-6465-6829 |
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J98. 2 |
6
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Major Revisions in This Edition |
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Page |
Description |
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Throughout |
Addition of μPD78052(A),78053(A), 78054(A) to the applicable types |
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Deletion of μPD78P054Y from the applicable types |
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Deletion of the following package from the μPD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y |
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Subseries: |
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• 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) |
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p. 233 |
Addition of Figure 9-10. Square-Wave Output Operation Timing |
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p. 238 |
Addition of Figure 9-13. Square-Wave Output Operation Timing |
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p. 296 |
Addition of Note to Figure 16-4. Serial Operating Mode Register 0 Format |
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p. 430, 435 |
Addition of (4) Synchronization control and (5) Automatic transmit/receive Interval time to 18.4.3 3-wire |
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serial I/O mode operation with automatic transmit/receive function |
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p. 439 |
Addition of precaution to 19.1 (3) 3-wire serial I/O mode (MSB-/LSB-first switchable) |
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p. 444 |
Change of Figure 19-3. Serial Operating Mode Register 2 Format |
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p. 446 |
Change of Table 19-2. Serial Interface Channel 2 Operating Mode Settings |
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p. 465 |
Correction of Figure 19-10. Receive Error Timing |
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p. 474 |
Addition of 19.4.4 Limitations when UART mode is used |
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p. 577, 578 |
Addition of APPENDIX A DIFFERENCES BETWEEN μPD78054, 78054Y SUBSERIES AND μPD78058F, |
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78058FY SUBSERIES |
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p. 579 to |
APPENDIX B DEVELOPMENT TOOL |
592 |
Entire revision: Support for in-circuit emulator IE-78K0-NS |
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p. 593, 594 |
APPENDIX C EMBEDDED SOFTWARE |
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Entire revision: Deletion of fuzzy inference development support system |
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The mark shows major revised points. |
7
[MEMO]
8
Readers |
This manual has been prepared for user engineers who want to understand the |
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functions of the μPD78054 and 78054Y Subseries and design and develop its |
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application systems and programs. |
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The target products are the products of the following subseries. |
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• μPD78054 Subseries |
: μPD78052, 78053, 78054, 78P054, 78055, 78056, |
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μPD78058, 78P058, 78052(A), 78053(A), 78054(A) |
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• μPD78054Y Subseries |
: μPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, |
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μPD78058Y, 78P058Y |
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Caution |
Of the above members, the following devices with the suffix KK-T should be |
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used only for experiment or function evaluation, because they are not intended |
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for use in equipment that will be mass-produced and require high reliability. |
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μPD78P054KK-T, 78P058KK-T, 78P058YKK-T |
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Purpose |
This manual is intended for users to understand the functions described in the |
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Organization below. |
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Organization |
The μPD78054, 78054Y Subseries manual is separated into two parts: this manual |
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and the instruction edition (common to the 78K/0 Series). |
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μPD78054, 78054Y |
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78K/0 Series |
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Subseries |
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User’s Manual |
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User’s Manual |
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Instruction |
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(This manual) |
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Pin functions |
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CPU functions |
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Internal block functions |
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Instruction set |
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Interrupt |
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Explanation of each instruction |
Other on-chip peripheral functions
9
How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers.
For users who use this document as the manual for the μPD78052(A), 78053(A), and 78054(A):
→The only differences between the μPD78052, 78053, and 78054 and the
μPD78052(A), 78053(A), 78054(A) are the quality grades and packages. (refer to 1.9 Differences between Standard Quality Grade Products and (A) Products).
For the (A) products, read the part numbers in the following manner.
μPD78052 → μPD78052(A)
μPD78053 → μPD78053(A)
μPD78054 → μPD78054(A)
When you want to understand the functions in general:
→ Read this manual in the order of the contents.
To know the μPD78054 and 78054Y Subseries instruction function in detail:
→ Refer to the 78K/0 Series User's Manual: Instructions (U12326E)
How to interpret the register format:
→For the circled bit number, the bit name is defined as a reserved word in RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h.
To learn the function of a register whose register name is known:
→ Refer to Appendix D Register Index.
To know the electrical specifications of the μPD78054 and 78054Y Subseries:
→ Refer to separately available Data Sheet.
To know application examples of the functions provided in the μPD78054 and 78054Y Subseries:
→ Refer to Application Note separately provided.
Caution The application examples in this manual are created for “Standard” quality grade products for general electric equipment. When using the application examples in this manual for purposes which require “Special” quality grades, thoroughly examine the quality grade of each part and circuit actually used.
10
Chapter Organization: This manual divides the descriptions for the μPD78054 and 78054Y Subseries into different chapters as shown below. Read only the chapters related to the device you use.
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Chapter |
μPD78054 |
μPD78054Y |
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Subseries |
Subseries |
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Chapter 1 |
Outline (μPD78054 Subseries) |
Ö |
— |
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Chapter 2 |
Outline (μPD78054Y Subseries) |
— |
Ö |
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Chapter 3 |
Pin Function (μPD78054 Subseries) |
Ö |
— |
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Chapter 4 |
Pin Function (μPD78054Y Subseries) |
— |
Ö |
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Chapter 5 |
CPU Architecture |
Ö |
Ö |
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Chapter 6 |
Port Functions |
Ö |
Ö |
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Chapter 7 |
Clock Generator |
Ö |
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Chapter 8 |
16-Bit Timer/Event Counter |
Ö |
Ö |
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Chapter 9 |
8-Bit Timer/Event Counters 1 and 2 |
Ö |
Ö |
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Chapter 10 |
Watch Timer |
Ö |
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Chapter 11 |
Watchdog Timer |
Ö |
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Chapter 12 |
Clock Output Control Circuit |
Ö |
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Chapter 13 |
Buzzer Output Control Circuit |
Ö |
Ö |
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Chapter 14 |
A/D Converter |
Ö |
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Chapter 15 |
D/A Converter |
Ö |
Ö |
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Chapter 16 |
Serial Interface Channel 0 (μPD78054 Subseries) |
Ö |
— |
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Chapter 17 |
Serial Interface Channel 0 (μPD78054Y Subseries) |
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Ö |
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Chapter 18 |
Serial Interface Channel 1 |
Ö |
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Chapter 19 |
Serial Interface Channel 2 |
Ö |
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Chapter 20 |
Real-Time Output Port |
Ö |
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Chapter 21 |
Interrupt and Test Functions |
Ö |
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Chapter 22 |
External Device Expansion Function |
Ö |
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Chapter 23 |
Standby Function |
Ö |
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Chapter 24 |
Reset Function |
Ö |
Ö |
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Chapter 25 |
ROM Correction |
Ö |
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Chapter 26 |
μPD78P054, μPD78P058 |
Ö |
Ö |
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Chapter 27 |
Instruction Set |
Ö |
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11
Differences between μPD78054 and μPD78054Y Subseries:
The μPD78054 and μPD78054Y Subseries are different in the following functions
of the serial interface channel 0.
Modes of serial interface channel 0 |
μPD78054 |
μPD78054Y |
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Subseries |
Subseries |
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3-wire serial I/O mode |
Ö |
Ö |
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2-wire serial I/O mode |
Ö |
Ö |
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SBI (serial bus interface) mode |
Ö |
— |
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I2C (Inter IC) bus mode |
— |
Ö |
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: Supported |
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: Not supported |
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Legend |
Data significant |
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: Left: higher digit, right: lower digit |
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Active low |
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: ××× (top bar over pin or signal name) |
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Note |
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Footnote |
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Caution |
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Important information |
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Remark |
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Supplement |
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Numerical notation |
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Binary ... ×××× or ××××B |
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Decimal ... ×××× |
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Hexadecimal ... ××××H |
12
Related Documents |
The related documents indicated in this publication may include preliminary |
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versions. However, preliminary versions are not marked as such. |
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Related documents for μPD78054 Subseries |
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Document name |
Document No. |
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Japanese |
English |
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μPD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet |
U12327J |
U12327E |
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μPD78052(A), 78053(A), 78054(A) Data Sheet |
U12171J |
U12171E |
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μPD78P054, 78P058 Data Sheet |
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U10417J |
U10417E |
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μPD78054, 78054Y Subseries User’s Manual |
U11747J |
This manual |
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78K/0 Series User’s Manual, Instruction |
U12326J |
U12326E |
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78K/0 Series Instruction Table |
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U10903J |
— |
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78K/0 Series Instruction Set |
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U10904J |
— |
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μPD78054 Subseries Special Function Register Table |
U10102J |
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78K/0 Series Application Note |
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Basics (III) |
U10182J |
U10182E |
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Floating-point operation program |
IEA-718 |
IEA-1289 |
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Related documents for μPD78054Y Subseries |
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Document name |
Document No. |
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Japanese |
English |
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μPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y Data Sheet |
U10906J |
U10906E |
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μPD78P058Y Data Sheet |
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U10907J |
U10907E |
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μPD78054, 78054Y Subseries User’s Manual |
U11747J |
This manual |
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78K/0 Series User’s Manual, Instruction |
U12326J |
U12326E |
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78K/0 Series Instruction Table |
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U10903J |
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78K/0 Series Instruction Set |
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U10904J |
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μPD78054Y Subseries Special Function Register Table |
U10087J |
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78K/0 Series Application Note |
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Basics (III) |
U10182J |
U10182E |
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Caution The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
13
Development Tool Documents (User’s Manuals)
Document name |
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Document No. |
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Japanese |
English |
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RA78K0 Assembler Package |
Operation |
U11802J |
U11802E |
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Assembly Language |
U11801J |
U11801E |
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Structured Assembly |
U11789J |
U11789E |
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RA78K Series Structured Assembler Preprocessor |
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U12323J |
EEU-1402 |
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CC78K0 C Compiler |
Operation |
U11517J |
U11517E |
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Language |
U11518J |
U11518E |
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CC78K0 C Compiler Application Note |
Programming know-how |
U13034J |
EEA-1208 |
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CC78K Series Library Source File |
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U12322J |
— |
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PG-1500 PROM Programmer |
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U11940J |
U11940E |
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PG-1500 Controller PC-9800 Series (MS-DOS™) Base |
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EEU-704 |
EEU-1291 |
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PG-1500 Controller IBM PC Series (PC DOS™) Base |
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EEU-5008 |
U10540E |
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IE-78K0-NS |
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To be prepared |
To be prepared |
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IE-78001-R-A |
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To be prepared |
To be prepared |
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IE-780308-NS-EM1 |
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To be prepared |
To be prepared |
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IE-780308-R-EM |
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U11362J |
U11362E |
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EP-78230 |
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EEU-985 |
EEU-1515 |
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EP-78054GK-R |
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EEU-932 |
EEU-1468 |
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SM78K0 System Simulator Windows™ Base |
Reference |
U10181J |
U10181E |
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SM78K Series System Simulator |
External component user |
U10092J |
U10092E |
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open interface specifications |
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ID78K0-NS Integrated Debugger |
Reference |
U12900J |
To be prepared |
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ID78K0 Integrated Debugger EWS Base |
Reference |
U11151J |
— |
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ID78K0 Integrated Debugger PC Base |
Reference |
U11539J |
U11539E |
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ID78K0 Integrated Debugger Windows Base |
Guide |
U11649J |
U11649E |
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Caution The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
14
Documents for Embedded Software |
(User’s Manual) |
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Document name |
Document No. |
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|||
|
|
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Japanese |
English |
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|
|
78K/0 Series Real-Time OS |
|
Basics |
U11537J |
U11537E |
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|
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|
|
|
Installation |
U11536J |
U11536E |
|
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OS for 78K/0 Series MX78K0 |
|
Basics |
U12257J |
U12257E |
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Other Documents |
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Document name |
Document No. |
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Japanese |
English |
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IC PACKAGE MANUAL |
|
|
C10943X |
|
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Semiconductor Device Mounting Technology Manual |
C10535J |
C10535E |
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Quality Grade on NEC Semiconductor Devices |
|
|
C11531J |
C11531E |
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NEC Semiconductor Device Reliability/Quality Control System |
C10983J |
C10983E |
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Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) |
C11892J |
C11892E |
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|
|
Guide to Quality Assurance for Semiconductor Devices |
— |
MEI-1202 |
||
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|
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Microcontroller Related Product Guide—Third Party Manufacturers |
U11416J |
— |
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Caution The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
15
[MEMO]
16
TABLE OF CONTENTS
CHAPTER 1 |
GENERAL (μPD78054 Subseries) ............................................................................ |
37 |
||||
1.1 |
Features ............................................................................................................................. |
37 |
||||
1.2 |
Applications ...................................................................................................................... |
38 |
||||
1.3 |
Ordering Information ........................................................................................................ |
38 |
||||
1.4 |
Quality Grade .................................................................................................................... |
39 |
||||
1.5 |
Pin Configuration (Top View) ........................................................................................... |
40 |
||||
1.6 |
78K/0 Series Expansion ................................................................................................... |
43 |
||||
1.7 |
Block Diagram ................................................................................................................... |
45 |
||||
1.8 |
Outline of Function ........................................................................................................... |
46 |
||||
1.9 |
Differences between Standard Quality Grade Products and (A) Products ................. |
48 |
||||
1.10 |
Mask Options .................................................................................................................... |
48 |
||||
CHAPTER 2 |
GENERAL (μPD78054Y Subseries) .......................................................................... |
49 |
||||
2.1 |
Features ............................................................................................................................. |
49 |
||||
2.2 |
Applications ...................................................................................................................... |
50 |
||||
2.3 |
Ordering Information ........................................................................................................ |
50 |
||||
2.4 |
Quality Grade .................................................................................................................... |
50 |
||||
2.5 |
Pin Configuration (Top View) ........................................................................................... |
51 |
||||
2.6 |
78K/0 Series Expansion ................................................................................................... |
54 |
||||
2.7 |
Block Diagram ................................................................................................................... |
56 |
||||
2.8 |
Outline of Function ........................................................................................................... |
57 |
||||
2.9 |
Mask Options .................................................................................................................... |
58 |
||||
CHAPTER 3 PIN FUNCTION (μPD78054 Subseries) .................................................................... |
59 |
|||||
3.1 |
Pin Function List ............................................................................................................... |
59 |
||||
|
3.1.1 |
|
Normal operating mode pins ............................................................................................... |
59 |
||
|
3.1.2 |
|
PROM programming mode pins (PROM versions only) ...................................................... |
63 |
||
3.2 |
Description of Pin Functions ........................................................................................... |
64 |
||||
|
3.2.1 |
|
P00 to P07 (Port 0) .............................................................................................................. |
64 |
||
|
3.2.2 |
|
P10 to P17 (Port 1) .............................................................................................................. |
65 |
||
|
3.2.3 |
|
P20 to P27 (Port 2) .............................................................................................................. |
65 |
||
|
3.2.4 |
|
P30 to P37 (Port 3) .............................................................................................................. |
66 |
||
|
3.2.5 |
|
P40 to P47 (Port 4) .............................................................................................................. |
67 |
||
|
3.2.6 |
|
P50 to P57 (Port 5) .............................................................................................................. |
67 |
||
|
3.2.7 |
|
P60 to P67 (Port 6) .............................................................................................................. |
67 |
||
|
3.2.8 |
|
P70 to P72 (Port 7) .............................................................................................................. |
68 |
||
|
3.2.9 |
|
P120 to P127 (Port 12) ........................................................................................................ |
69 |
||
|
3.2.10 |
|
P130 and P131 (Port 13) ..................................................................................................... |
69 |
||
|
3.2.11 |
AVREF0 .................................................................................................................................. |
69 |
|||
|
3.2.12 |
AVREF1 .................................................................................................................................. |
69 |
|||
|
3.2.13 |
AVDD ..................................................................................................................................... |
70 |
|||
|
3.2.14 |
AVSS ..................................................................................................................................... |
70 |
|||
|
3.2.15 |
|
|
70 |
||
|
|
RESET |
................................................................................................................................. |
|||
|
3.2.16 |
|
X1 and X2 ............................................................................................................................ |
70 |
||
|
3.2.17 |
|
XT1 and XT2 ....................................................................................................................... |
70 |
17
|
3.2.18 |
VDD ....................................................................................................................................... |
70 |
||
|
3.2.19 |
VSS ....................................................................................................................................... |
70 |
||
|
3.2.20 |
VPP (PROM versions only) ................................................................................................... |
70 |
||
|
3.2.21 |
|
IC (Mask ROM version only) ................................................................................................ |
70 |
|
3.3 Input/output Circuits and Recommended Connection of Unused Pins ...................... |
71 |
||||
CHAPTER 4 PIN FUNCTION (μPD78054Y Subseries) .................................................................. |
75 |
||||
4.1 |
Pin Function List ............................................................................................................... |
75 |
|||
|
4.1.1 |
|
Normal operating mode pins ............................................................................................... |
75 |
|
|
4.1.2 |
|
PROM programming mode pins (PROM versions only) ...................................................... |
79 |
|
4.2 Description of Pin Functions ........................................................................................... |
80 |
||||
|
4.2.1 |
|
P00 to P07 (Port 0) .............................................................................................................. |
80 |
|
|
4.2.2 |
|
P10 to P17 (Port 1) .............................................................................................................. |
81 |
|
|
4.2.3 |
|
P20 to P27 (Port 2) .............................................................................................................. |
81 |
|
|
4.2.4 |
|
P30 to P37 (Port 3) .............................................................................................................. |
82 |
|
|
4.2.5 |
|
P40 to P47 (Port 4) .............................................................................................................. |
82 |
|
|
4.2.6 |
|
P50 to P57 (Port 5) .............................................................................................................. |
83 |
|
|
4.2.7 |
|
P60 to P67 (Port 6) .............................................................................................................. |
83 |
|
|
4.2.8 |
|
P70 to P72 (Port 7) .............................................................................................................. |
84 |
|
|
4.2.9 |
|
P120 to P127 (Port 12) ........................................................................................................ |
84 |
|
|
4.2.10 |
|
P130 and P131 (Port 13) ..................................................................................................... |
85 |
|
|
4.2.11 |
|
AVREF0 .................................................................................................................................. |
85 |
|
|
4.2.12 |
AVREF1 .................................................................................................................................. |
85 |
||
|
4.2.13 |
AVDD ..................................................................................................................................... |
85 |
||
|
4.2.14 |
AVSS ..................................................................................................................................... |
85 |
||
|
|
|
|
|
|
|
4.2.15 |
|
RESET ................................................................................................................................. |
85 |
|
|
4.2.16 |
|
X1 and X2 ............................................................................................................................ |
86 |
|
|
4.2.17 |
|
XT1 and XT2 ....................................................................................................................... |
86 |
|
|
4.2.18 |
VDD ....................................................................................................................................... |
86 |
||
|
4.2.19 |
VSS ....................................................................................................................................... |
86 |
||
|
4.2.20 |
VPP (PROM versions only) ................................................................................................... |
86 |
||
|
4.2.21 |
|
IC (Mask ROM version only) ................................................................................................ |
86 |
|
4.3 Input/output Circuits and Recommended Connection of Unused Pins ...................... |
87 |
||||
CHAPTER 5 CPU ARCHITECTURE ................................................................................................ |
91 |
||||
5.1 |
Memory Spaces ................................................................................................................. |
91 |
|||
|
5.1.1 |
|
Internal program memory space .......................................................................................... |
99 |
|
|
5.1.2 |
|
Internal data memory space ................................................................................................ |
100 |
|
|
5.1.3 |
|
Special Function Register (SFR) area ................................................................................. |
100 |
|
|
5.1.4 |
|
External memory space ....................................................................................................... |
100 |
|
|
5.1.5 |
|
Data memory addressing .................................................................................................... |
101 |
|
5.2 |
Processor Registers ......................................................................................................... |
109 |
|||
|
5.2.1 |
|
Control registers .................................................................................................................. |
109 |
|
|
5.2.2 |
|
General registers ................................................................................................................. |
112 |
|
|
5.2.3 |
|
Special Function Register (SFR) ......................................................................................... |
114 |
|
5.3 |
Instruction Address Addressing ..................................................................................... |
118 |
|||
|
5.3.1 |
|
Relative addressing ............................................................................................................. |
118 |
|
|
5.3.2 |
|
Immediate addressing ......................................................................................................... |
119 |
18
|
5.3.3 |
|
Table indirect addressing ..................................................................................................... |
120 |
|
5.3.4 |
|
Register addressing ............................................................................................................. |
120 |
5.4 |
Operand Address Addressing ......................................................................................... |
121 |
||
|
5.4.1 |
|
Implied addressing .............................................................................................................. |
121 |
|
5.4.2 |
|
Register addressing ............................................................................................................. |
122 |
|
5.4.3 |
|
Direct addressing ................................................................................................................. |
123 |
|
5.4.4 |
|
Short direct addressing ........................................................................................................ |
124 |
|
5.4.5 |
|
Special-Function Register (SFR) addressing ...................................................................... |
125 |
|
5.4.6 |
|
Register indirect addressing ................................................................................................ |
126 |
|
5.4.7 |
|
Based addressing ................................................................................................................ |
127 |
|
5.4.8 |
|
Based indexed addressing .................................................................................................. |
128 |
|
5.4.9 |
|
Stack addressing ................................................................................................................. |
128 |
CHAPTER 6 |
PORT FUNCTIONS .................................................................................................... |
129 |
||
6.1 |
Port Functions ................................................................................................................... |
129 |
||
6.2 |
Port Configuration ............................................................................................................ |
134 |
||
|
6.2.1 |
|
Port 0 ................................................................................................................................... |
134 |
|
6.2.2 |
|
Port 1 ................................................................................................................................... |
136 |
|
6.2.3 |
|
Port 2 (μPD78054 Subseries) .............................................................................................. |
137 |
|
6.2.4 |
|
Port 2 (μPD78054Y Subseries) ........................................................................................... |
139 |
|
6.2.5 |
|
Port 3 ................................................................................................................................... |
141 |
|
6.2.6 |
|
Port 4 ................................................................................................................................... |
142 |
|
6.2.7 |
|
Port 5 ................................................................................................................................... |
143 |
|
6.2.8 |
|
Port 6 ................................................................................................................................... |
144 |
|
6.2.9 |
|
Port 7 ................................................................................................................................... |
146 |
|
6.2.10 |
Port 12 ................................................................................................................................. |
148 |
|
|
6.2.11 |
Port 13 ................................................................................................................................. |
149 |
|
6.3 |
Port Function Control Registers ..................................................................................... |
150 |
||
6.4 |
Port Function Operations ................................................................................................. |
156 |
||
|
6.4.1 |
|
Writing to input/output port ................................................................................................... |
156 |
|
6.4.2 |
|
Reading from input/output port ............................................................................................ |
156 |
|
6.4.3 |
|
Operations on input/output port ........................................................................................... |
157 |
6.5 |
Selection of Mask Option ................................................................................................. |
157 |
||
CHAPTER 7 |
CLOCK GENERATOR ................................................................................................ |
159 |
||
7.1 |
Clock Generator Functions .............................................................................................. |
159 |
||
7.2 |
Clock Generator Configuration ....................................................................................... |
159 |
||
7.3 |
Clock Generator Control Register ................................................................................... |
161 |
||
7.4 |
System Clock Oscillator ................................................................................................... |
165 |
||
|
7.4.1 |
|
Main system clock oscillator ................................................................................................ |
165 |
|
7.4.2 |
|
Subsystem clock oscillator .................................................................................................. |
166 |
|
7.4.3 |
|
Scaler ................................................................................................................................... |
168 |
|
7.4.4 |
|
When no subsystem clocks are used .................................................................................. |
168 |
7.5 |
Clock Generator Operations ............................................................................................ |
169 |
||
|
7.5.1 |
|
Main system clock operations ............................................................................................. |
170 |
|
7.5.2 |
|
Subsystem clock operations ................................................................................................ |
171 |
7.6 |
Changing System Clock and CPU Clock Settings ......................................................... |
171 |
||
|
7.6.1 |
|
Time required for switchover between system clock and CPU clock .................................. |
171 |
|
7.6.2 |
|
System clock and CPU clock switching procedure .............................................................. |
173 |
19
CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................. |
175 |
||
8.1 |
Outline of Timers Incorporated in the μPD78054, 78054Y Subseries .......................... |
175 |
|
8.2 |
16-Bit Timer/Event Counter Functions ........................................................................... |
177 |
|
8.3 |
16-Bit Timer/Event Counter Configuration ..................................................................... |
179 |
|
8.4 |
16-Bit Timer/Event Counter Control Registers .............................................................. |
182 |
|
8.5 |
16-Bit Timer/Event Counter Operations .......................................................................... |
191 |
|
|
8.5.1 |
Interval timer operations ...................................................................................................... |
191 |
|
8.5.2 |
PWM output operations ....................................................................................................... |
193 |
|
8.5.3 |
PPG output operations ........................................................................................................ |
196 |
|
8.5.4 |
Pulse width measurement operations ................................................................................. |
197 |
|
8.5.5 |
External event counter operation ......................................................................................... |
204 |
|
8.5.6 |
Square-wave output operation ............................................................................................ |
206 |
|
8.5.7 |
One-shot pulse output operation ......................................................................................... |
208 |
8.6 |
16-Bit Timer/Event Counter Operating Precautions ...................................................... |
212 |
|
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 .............................................................. |
215 |
||
9.1 |
8-Bit Timer/Event Counters 1 and 2 Functions .............................................................. |
215 |
|
|
9.1.1 |
8-bit timer/event counter mode ............................................................................................ |
215 |
|
9.1.2 |
16-bit timer/event counter mode .......................................................................................... |
218 |
9.2 |
8-Bit Timer/Event Counters 1 and 2 Configurations ...................................................... |
220 |
|
9.3 |
8-Bit Timer/Event Counters 1 and 2 Control Registers ................................................. |
223 |
|
9.4 |
8-Bit Timer/Event Counters 1 and 2 Operations ............................................................ |
228 |
|
|
9.4.1 |
8-bit timer/event counter mode ............................................................................................ |
228 |
|
9.4.2 |
16-bit timer/event counter mode .......................................................................................... |
234 |
9.5 |
Cautions on 8-Bit Timer/Event Counters 1 and 2 .......................................................... |
238 |
|
CHAPTER 10 WATCH TIMER ........................................................................................................... |
241 |
||
10.1 |
Watch Timer Functions .................................................................................................... |
241 |
|
10.2 |
Watch Timer Configuration .............................................................................................. |
242 |
|
10.3 |
Watch Timer Control Registers ....................................................................................... |
242 |
|
10.4 |
Watch Timer Operations ................................................................................................... |
246 |
|
|
10.4.1 |
Watch timer operation .......................................................................................................... |
246 |
|
10.4.2 |
Interval timer operation ........................................................................................................ |
246 |
CHAPTER 11 WATCHDOG TIMER ................................................................................................... |
247 |
||
11.1 |
Watchdog Timer Functions .............................................................................................. |
247 |
|
11.2 |
Watchdog Timer Configuration ....................................................................................... |
249 |
|
11.3 |
Watchdog Timer Control Registers ................................................................................. |
250 |
|
11.4 |
Watchdog Timer Operations ............................................................................................ |
253 |
|
|
11.4.1 |
Watchdog timer operation .................................................................................................... |
253 |
|
11.4.2 |
Interval timer operation ........................................................................................................ |
254 |
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ..................................................................... |
255 |
||
12.1 |
Clock Output Control Circuit Functions ......................................................................... |
255 |
|
12.2 |
Clock Output Control Circuit Configuration ................................................................... |
256 |
|
12.3 |
Clock Output Function Control Registers ...................................................................... |
257 |
20
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .................................................................... |
261 |
|||||
|
13.1 |
|
Buzzer Output Control Circuit Functions ............................................................................. |
261 |
||
|
13.2 |
|
Buzzer Output Control Circuit Configuration ....................................................................... |
261 |
||
|
13.3 |
|
Buzzer Output Function Control Registers .......................................................................... |
262 |
||
CHAPTER 14 A/D CONVERTER ....................................................................................................... |
265 |
|||||
14.1 |
A/D Converter Functions .................................................................................................. |
265 |
||||
14.2 |
A/D Converter Configuration ........................................................................................... |
265 |
||||
14.3 |
A/D Converter Control Registers ..................................................................................... |
269 |
||||
14.4 |
A/D Converter Operations ................................................................................................ |
273 |
||||
|
14.4.1 |
|
Basic operations of A/D converter ....................................................................................... |
273 |
||
|
14.4.2 |
|
Input voltage and conversion results ................................................................................... |
275 |
||
|
14.4.3 |
|
A/D converter operating mode ............................................................................................. |
276 |
||
14.5 |
A/D Converter Cautions ................................................................................................... |
278 |
||||
CHAPTER 15 D/A CONVERTER ....................................................................................................... |
281 |
|||||
15.1 |
D/A Converter Functions .................................................................................................. |
281 |
||||
15.2 |
D/A Converter Configuration ........................................................................................... |
282 |
||||
15.3 |
D/A Converter Control Registers ..................................................................................... |
284 |
||||
15.4 |
Operations of D/A Converter ........................................................................................... |
285 |
||||
15.5 |
Cautions Related to D/A Converter ................................................................................. |
286 |
||||
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (μPD78054 Subseries) ...................................... |
287 |
|||||
16.1 |
Serial Interface Channel 0 Functions .............................................................................. |
288 |
||||
16.2 |
Serial Interface Channel 0 Configuration ....................................................................... |
290 |
||||
16.3 |
Serial Interface Channel 0 Control Registers ................................................................. |
294 |
||||
16.4 |
Serial Interface Channel 0 Operations ............................................................................ |
301 |
||||
|
16.4.1 |
|
Operation stop mode ........................................................................................................... |
301 |
||
|
16.4.2 |
|
3-wire serial I/O mode operation ......................................................................................... |
302 |
||
|
16.4.3 |
|
SBI mode operation ............................................................................................................. |
307 |
||
|
16.4.4 |
|
2-wire serial I/O mode operation ......................................................................................... |
333 |
||
|
16.4.5 |
|
|
|
339 |
|
|
|
SCK0/P27 pin output manipulation ...................................................................................... |
||||
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (μPD78054Y Subseries) ................................... |
341 |
|||||
17.1 |
Serial Interface Channel 0 Functions .............................................................................. |
342 |
||||
17.2 |
Serial Interface Channel 0 Configuration ....................................................................... |
344 |
||||
17.3 |
Serial Interface Channel 0 Control Registers ................................................................. |
348 |
||||
17.4 |
Serial Interface Channel 0 Operations ............................................................................ |
356 |
||||
|
17.4.1 |
|
Operation stop mode ........................................................................................................... |
356 |
||
|
17.4.2 |
|
3-wire serial I/O mode operation ......................................................................................... |
357 |
||
|
17.4.3 |
|
2-wire serial I/O mode operation ......................................................................................... |
361 |
||
|
17.4.4 |
I2C bus mode operation ....................................................................................................... |
367 |
|||
|
17.4.5 |
|
Cautions on use of I2C bus mode ........................................................................................ |
385 |
||
|
17.4.6 |
|
Restrictions in I2C bus mode ............................................................................................... |
388 |
||
|
17.4.7 |
|
|
|
|
390 |
|
|
SCK0/SCL/P27 pin output manipulation .............................................................................. |
21
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ............................................................................ |
393 |
||
18.1 |
Serial Interface Channel 1 Functions .............................................................................. |
393 |
|
18.2 |
Serial Interface Channel 1 Configuration ....................................................................... |
394 |
|
18.3 |
Serial Interface Channel 1 Control Registers ................................................................. |
397 |
|
18.4 |
Serial Interface Channel 1 Operations ............................................................................ |
405 |
|
|
18.4.1 |
Operation stop mode ........................................................................................................... |
405 |
|
18.4.2 3-wire serial I/O mode operation ......................................................................................... |
406 |
|
|
18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function ......................... |
409 |
|
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ............................................................................ |
439 |
||
19.1 |
Serial Interface Channel 2 Functions .............................................................................. |
439 |
|
19.2 |
Serial Interface Channel 2 Configuration ....................................................................... |
440 |
|
19.3 |
Serial Interface Channel 2 Control Registers ................................................................. |
444 |
|
19.4 |
Serial Interface Channel 2 Operation .............................................................................. |
452 |
|
|
19.4.1 |
Operation stop mode ........................................................................................................... |
452 |
|
19.4.2 Asynchronous serial interface (UART) mode ...................................................................... |
454 |
|
|
19.4.3 3-wire serial I/O mode ......................................................................................................... |
467 |
|
|
19.4.4 Limitations when UART mode is used ................................................................................. |
474 |
|
CHAPTER 20 REAL-TIME OUTPUT PORT ...................................................................................... |
477 |
||
20.1 |
Real-Time Output Port Functions .................................................................................... |
477 |
|
20.2 |
Real-Time Output Port Configuration ............................................................................. |
478 |
|
20.3 |
Real-Time Output Port Control Registers ....................................................................... |
480 |
|
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS ....................................................................... |
483 |
||
21.1 |
Interrupt Function Types .................................................................................................. |
483 |
|
21.2 |
Interrupt Sources and Configuration .............................................................................. |
484 |
|
21.3 |
Interrupt Function Control Registers .............................................................................. |
488 |
|
21.4 |
Interrupt Servicing Operations ........................................................................................ |
497 |
|
|
21.4.1 Non-maskable interrupt request acknowledge operation .................................................... |
497 |
|
|
21.4.2 Maskable interrupt request acknowledge operation ............................................................ |
500 |
|
|
21.4.3 Software interrupt request acknowledge operation ............................................................. |
503 |
|
|
21.4.4 |
Multiple interrupt servicing ................................................................................................... |
503 |
|
21.4.5 |
Interrupt request reserve ..................................................................................................... |
506 |
21.5 |
Test Functions ................................................................................................................... |
507 |
|
|
21.5.1 Registers controlling the test function .................................................................................. |
507 |
|
|
21.5.2 Test input signal acknowledge operation ............................................................................. |
509 |
|
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ......................................................... |
511 |
||
22.1 |
External Device Expansion Functions ............................................................................ |
511 |
|
22.2 |
External Device Expansion Function Control Register ................................................. |
516 |
|
22.3 |
External Device Expansion Function Timing ................................................................. |
518 |
|
22.4 |
Example of Connection with Memory ............................................................................. |
523 |
|
CHAPTER 23 STANDBY FUNCTION ................................................................................................ |
525 |
||
23.1 |
Standby Function and Configuration .............................................................................. |
525 |
|
|
23.1.1 |
Standby function .................................................................................................................. |
525 |
|
23.1.2 Standby function control register ......................................................................................... |
526 |
22
23.2 |
Standby Function Operations .......................................................................................... |
527 |
|
|
23.2.1 |
HALT mode .......................................................................................................................... |
527 |
|
23.2.2 |
STOP mode ......................................................................................................................... |
530 |
CHAPTER 24 RESET FUNCTION ..................................................................................................... |
533 |
||
24.1 |
Reset Function .................................................................................................................. |
533 |
|
CHAPTER 25 ROM CORRECTION ................................................................................................... |
537 |
||
25.1 |
ROM Correction Functions .............................................................................................. |
537 |
|
25.2 |
ROM Correction Configuration ........................................................................................ |
537 |
|
25.3 |
ROM Correction Control Registers ................................................................................. |
539 |
|
25.4 |
ROM Correction Application ............................................................................................ |
540 |
|
25.5 |
ROM Correction Example ................................................................................................. |
543 |
|
25.6 |
Program Execution Flow .................................................................................................. |
544 |
|
25.7 |
Cautions on ROM Correction ........................................................................................... |
546 |
|
CHAPTER 26 μPD78P054, 78P058 .................................................................................................. |
547 |
||
26.1 |
Memory Size Switching Register (μPD78P054) .............................................................. |
549 |
|
26.2 |
Memory Size Switching Register (μPD78P058) .............................................................. |
550 |
|
26.3 |
Internal Expansion RAM Size Switching Register ......................................................... |
551 |
|
26.4 |
PROM Programming ......................................................................................................... |
552 |
|
|
26.4.1 |
Operating modes ................................................................................................................. |
552 |
|
26.4.2 |
PROM write procedure ........................................................................................................ |
554 |
|
26.4.3 |
PROM reading procedure .................................................................................................... |
558 |
26.5 |
Erasure Procedure (μPD78P054KK-T and 78P058KK-T Only) ...................................... |
559 |
|
26.6 |
Opaque Film Masking the Window (μPD78P054KK-T and 78P058KK-T Only) ............ |
559 |
|
26.7 |
Screening of One-Time PROM Versions ......................................................................... |
559 |
|
CHAPTER 27 INSTRUCTION SET .................................................................................................... |
561 |
||
27.1 |
Legends Used in Operation List ...................................................................................... |
562 |
|
|
27.1.1 Operand identifiers and description methods ...................................................................... |
562 |
|
|
27.1.2 Description of “operation” column ........................................................................................ |
563 |
|
|
27.1.3 Description of “flag operation” column ................................................................................. |
563 |
|
27.2 |
Operation List .................................................................................................................... |
564 |
|
27.3 |
Instructions Listed by Addressing Type ......................................................................... |
572 |
|
APPENDIX A DIFFERENCES BETWEEN μPD78054, 78054Y SUBSERIES AND |
|
||
|
μPD78058F, 78058FY SUBSERIES ........................................................................... |
577 |
|
APPENDIX B DEVELOPMENT TOOLS ............................................................................................ |
579 |
||
B.1 |
Language Processing Software ...................................................................................... |
582 |
|
B.2 |
PROM Writing Tools ......................................................................................................... |
584 |
|
|
B.2.1 |
Hardware ............................................................................................................................. |
584 |
|
B.2.2 |
Software ............................................................................................................................... |
584 |
B.3 |
Debugging Tools ............................................................................................................... |
585 |
|
|
B.3.1 |
Hardware ............................................................................................................................. |
585 |
|
B.3.2 |
Software ............................................................................................................................... |
587 |
23
B.4 |
OS for IBM PC ................................................................................................................... |
589 |
B.5 |
Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A .................. |
589 |
APPENDIX C EMBEDDED SOFTWARE .......................................................................................... |
593 |
|
APPENDIX D REGISTER INDEX ...................................................................................................... |
595 |
|
D.1 |
Register Index ................................................................................................................... |
595 |
APPENDIX E REVISION HISTORY .................................................................................................. |
599 |
24
LIST OF FIGURES (1/8)
Figure No. |
Title |
Page |
3-1. |
Pin Input/Output Circuit of List ....................................................................................................... |
73 |
4-1. |
Pin Input/Output Circuit of List ....................................................................................................... |
89 |
5-1. |
Memory Map (μPD78052, 78052Y) ............................................................................................... |
91 |
5-2. |
Memory Map (μPD78053, 78053Y) ............................................................................................... |
92 |
5-3. |
Memory Map (μPD78054, 78054Y) ............................................................................................... |
93 |
5-4. |
Memory Map (μPD78P054) ........................................................................................................... |
94 |
5-5. |
Memory Map (μPD78055, 78055Y) ............................................................................................... |
95 |
5-6. |
Memory Map (μPD78056, 78056Y) ............................................................................................... |
96 |
5-7. |
Memory Map (μPD78058, 78058Y) ............................................................................................... |
97 |
5-8. |
Memory Map (μPD78P058, μPD78P058Y) ................................................................................... |
98 |
5-9. |
Data Memory Addressing (μPD78052, 78052Y) ........................................................................... |
101 |
5-10. |
Data Memory Addressing (μPD78053, 78053Y) ........................................................................... |
102 |
5-11. |
Data Memory Addressing (μPD78054, 78054Y) ........................................................................... |
103 |
5-12. |
Data Memory Addressing (μPD78P054) ....................................................................................... |
104 |
5-13. |
Data Memory Addressing (μPD78055, 78055Y) ........................................................................... |
105 |
5-14. |
Data Memory Addressing (μPD78056, 78056Y) ........................................................................... |
106 |
5-15. |
Data Memory Addressing (μPD78058, 78058Y) ........................................................................... |
107 |
5-16. |
Data Memory Addressing (μPD78P058, 78P058Y) ...................................................................... |
108 |
5-17. |
Program Counter Configuration .................................................................................................... |
109 |
5-18. |
Program Status Word Configuration ............................................................................................. |
109 |
5-19. |
Stack Pointer Configuration ........................................................................................................... |
111 |
5-20. |
Data to be Saved to Stack Memory ............................................................................................... |
111 |
5-21. |
Data to be Reset from Stack Memory ........................................................................................... |
111 |
5-22. |
General Register Configuration ..................................................................................................... |
113 |
6-1. |
Port Types ..................................................................................................................................... |
129 |
6-2. |
P00 and P07 Block Diagram ......................................................................................................... |
135 |
6-3. |
P01 to P06 Block Diagram ............................................................................................................ |
135 |
6-4. |
P10 to P17 Block Diagram ............................................................................................................ |
136 |
6-5. |
P20, P21, P23 to P26 Block Diagram ........................................................................................... |
137 |
6-6. |
P22 and P27 Block Diagram ......................................................................................................... |
138 |
6-7. |
P20, P21, P23 to P26 Block Diagram ........................................................................................... |
139 |
6-8. |
P22 and P27 Block Diagram ......................................................................................................... |
140 |
6-9. |
P30 to P37 Block Diagram ............................................................................................................ |
141 |
6-10. |
P40 to P47 Block Diagram ............................................................................................................ |
142 |
6-11. |
Block Diagram of Falling Edge Detection Circuit ........................................................................... |
142 |
6-12. |
P50 to P57 Block Diagram ............................................................................................................ |
143 |
6-13. |
P60 to P63 Block Diagram ............................................................................................................ |
145 |
6-14. |
P64 to P67 Block Diagram ............................................................................................................ |
145 |
6-15. |
P70 Block Diagram ........................................................................................................................ |
146 |
6-16. |
P71 and P72 Block Diagram ......................................................................................................... |
147 |
6-17. |
P120 to P127 Block Diagram ........................................................................................................ |
148 |
25
LIST OF FIGURES (2/8)
Figure No. |
Title |
Page |
6-18. |
P130 and P131 Block Diagram ..................................................................................................... |
149 |
6-19. |
Port Mode Register Format ........................................................................................................... |
152 |
6-20. |
Pull-Up Resistor Option Register Format ...................................................................................... |
153 |
6-21. |
Memory Expansion Mode Register Format ................................................................................... |
154 |
6-22. |
Key Return Mode Register Format ................................................................................................ |
155 |
7-1. |
Block Diagram of Clock Generator ................................................................................................ |
160 |
7-2. |
Subsystem Clock Feedback Resistor ............................................................................................ |
161 |
7-3. |
Processor Clock Control Register Format ..................................................................................... |
162 |
7-4. |
Oscillation Mode Selection Register Format ................................................................................. |
164 |
7-5. |
Main System Clock when Writing to OSMS .................................................................................. |
164 |
7-6. |
External Circuit of Main System Clock Oscillator .......................................................................... |
165 |
7-7. |
External Circuit of Subsystem Clock Oscillator ............................................................................. |
166 |
7-8. |
Examples of Incorrect Oscillator Connection ................................................................................ |
166 |
7-9. |
Main System Clock Stop Function ................................................................................................ |
170 |
7-10. |
System Clock and CPU Clock Switching ...................................................................................... |
173 |
8-1. |
16-Bit Timer/Event Counter Block Diagram ................................................................................... |
179 |
8-2. |
16-Bit Timer/Event Counter Output Control Circuit Block Diagram ............................................... |
180 |
8-3. |
Timer Clock Selection Register 0 Format ...................................................................................... |
183 |
8-4. |
16-Bit Timer Mode Control Register Format .................................................................................. |
185 |
8-5. |
Capture/Compare Control Register 0 Format ............................................................................... |
186 |
8-6. |
16-Bit Timer Output Control Register Format ................................................................................ |
187 |
8-7. |
Port Mode Register 3 Format ........................................................................................................ |
188 |
8-8. |
External Interrupt Mode Register 0 Format ................................................................................... |
189 |
8-9. |
Sampling Clock Select Register Format ........................................................................................ |
190 |
8-10. |
Control Register Settings for Interval Timer Operation .................................................................. |
191 |
8-11. |
Interval Timer Configuration Diagram ............................................................................................ |
192 |
8-12. |
Interval Timer Operation Timings .................................................................................................. |
192 |
8-13. |
Control Register Settings for PWM Output Operation ................................................................... |
194 |
8-14. |
Example of D/A Converter Configuration with PWM Output ......................................................... |
195 |
8-15. |
TV Tuner Application Circuit Example ........................................................................................... |
195 |
8-16. |
Control Register Settings for PPG Output Operation .................................................................... |
196 |
8-17. |
Control Register Settings for Pulse Width Measurement with Free-Running Counter and |
|
|
One Capture Register ................................................................................................................... |
197 |
8-18. |
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ........................ |
198 |
8-19. |
Timing of Pulse Width Measurement Operation by Free-Running Counter and |
|
|
One Capture Register (with Both Edges Specified) ...................................................................... |
198 |
8-20. |
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ........ |
199 |
8-21. |
Timing of Pulse Width Measurement Operation with Free-Running Counter |
|
|
(with Both Edges Specified) .......................................................................................................... |
200 |
8-22. |
Control Register Settings for Pulse Width Measurement with Free-Running Counter and |
|
|
Two Capture Registers .................................................................................................................. |
201 |
26
LIST OF FIGURES (3/8)
Figure No. |
Title |
Page |
8-23. |
Timing of Pulse Width Measurement Operation by Free-Running Counter and |
|
|
Two Capture Registers (with Rising Edge Specified) .................................................................... |
202 |
8-24. |
Control Register Settings for Pulse Width Measurement by Means of Restart ............................. |
203 |
8-25. |
Timing of Pulse Width Measurement Operation by Means of Restart |
|
|
(with Rising Edge Specified) ......................................................................................................... |
203 |
8-26. |
Control Register Settings in External Event Counter Mode .......................................................... |
204 |
8-27. |
External Event Counter Configuration Diagram ............................................................................ |
205 |
8-28. |
External Event Counter Operation Timings (with Rising Edge Specified) ..................................... |
205 |
8-29. |
Control Register Settings in Square-Wave Output Mode .............................................................. |
206 |
8-30. |
Square-Wave Output Operation Timing ........................................................................................ |
207 |
8-31. |
Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ............. |
208 |
8-32. |
Timing of One-Shot Pulse Output Operation Using Software Trigger ........................................... |
209 |
8-33. |
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger .............. |
210 |
8-34. |
Timing of One-Shot Pulse Output Operation Using External Trigger |
|
|
(With Rising Edge Specified) ......................................................................................................... |
211 |
8-35. |
16-Bit Timer Register Start Timing ................................................................................................ |
212 |
8-36. |
Timings After Change of Compare Register During Timer Count Operation ................................. |
212 |
8-37. |
Capture Register Data Retention Timing ....................................................................................... |
213 |
8-38. |
Operation Timing of OVF0 Flag ..................................................................................................... |
214 |
9-1. |
8-Bit Timer/Event Counters 1 and 2 Block Diagram ...................................................................... |
221 |
9-2. |
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 .......................................... |
222 |
9-3. |
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 .......................................... |
222 |
9-4. |
Timer Clock Select Register 1 Format ........................................................................................... |
224 |
9-5. |
8-Bit Timer Mode Control Register 1 Format ................................................................................. |
225 |
9-6. |
8-Bit Timer Output Control Register Format .................................................................................. |
226 |
9-7. |
Port Mode Register 3 Format ........................................................................................................ |
227 |
9-8. |
Interval Timer Operation Timings .................................................................................................. |
228 |
9-9. |
External Event Counter Operation Timings (with Rising Edge Specified) ..................................... |
231 |
9-10. |
Square-Wave Output Operation Timing ........................................................................................ |
233 |
9-11. |
Interval Timer Operation Timing .................................................................................................... |
234 |
9-12. |
External Event Counter Operation Timings (with Rising Edge Specified) ..................................... |
236 |
9-13. |
Square-Wave Output Operation Timing ........................................................................................ |
238 |
9-14. |
8-Bit Timer Registers 1 and 2 Start Timing .................................................................................... |
238 |
9-15. |
Event Counter Operation Timing ................................................................................................... |
239 |
9-16. |
Timing after Compare Register Change during Timer Count Operation ....................................... |
239 |
10-1. |
Watch Timer Block Diagram .......................................................................................................... |
243 |
10-2. |
Timer Clock Select Register 2 Format ........................................................................................... |
244 |
10-3. |
Watch Timer Mode Control Register Format ................................................................................. |
245 |
11-1. |
Watchdog Timer Block Diagram .................................................................................................... |
249 |
11-2. |
Timer Clock Select Register 2 Format ........................................................................................... |
251 |
11-3. |
Watchdog Timer Mode Register Format ........................................................................................ |
252 |
27
LIST OF FIGURES (4/8)
Figure No. |
Title |
Page |
12-1. |
Remote Controlled Output Application Example ........................................................................... |
255 |
12-2. |
Clock Output Control Circuit Block Diagram ................................................................................. |
256 |
12-3. |
Timer Clock Select Register 0 Format ........................................................................................... |
258 |
12-4. |
Port Mode Register 3 Format ........................................................................................................ |
259 |
13-1. |
Buzzer Output Control Circuit Block Diagram ............................................................................... |
261 |
13-2. |
Timer Clock Select Register 2 Format ........................................................................................... |
263 |
13-3. |
Port Mode Register 3 Format ........................................................................................................ |
264 |
14-1. |
A/D Converter Block Diagram ....................................................................................................... |
266 |
14-2. |
Handling of AVDD Pin ..................................................................................................................... |
268 |
14-3. |
A/D Converter Mode Register Format ........................................................................................... |
270 |
14-4. |
A/D Converter Input Select Register Format ................................................................................. |
271 |
14-5. |
External Interrupt Mode Register 1 Format ................................................................................... |
272 |
14-6. |
A/D Converter Basic Operation ..................................................................................................... |
274 |
14-7. |
Relations between Analog Input Voltage and A/D Conversion Result ........................................... |
275 |
14-8. |
A/D Conversion by Hardware Start ............................................................................................... |
276 |
14-9. |
A/D Conversion by Software Start ................................................................................................. |
277 |
14-10. |
Example of Method of Reducing Current Dissipation in Standby Mode ........................................ |
278 |
14-11. |
Analog Input Pin Disposition ......................................................................................................... |
279 |
14-12. |
A/D Conversion End Interrupt Request Generation Timing ........................................................... |
280 |
14-13. |
Handling of AVDD Pin ..................................................................................................................... |
280 |
15-1. |
D/A Converter Block Diagram ....................................................................................................... |
282 |
15-2. |
D/A Converter Mode Register Format ........................................................................................... |
284 |
15-3. |
Use Example of Buffer Amplifier .................................................................................................... |
286 |
16-1. |
Serial Bus Interface (SBI) System Configuration Example ........................................................... |
289 |
16-2. |
Serial Interface Channel 0 Block Diagram .................................................................................... |
291 |
16-3. |
Timer Clock Select Register 3 Format ........................................................................................... |
295 |
16-4. |
Serial Operating Mode Register 0 Format ..................................................................................... |
296 |
16-5. |
Serial Bus Interface Control Register Format ................................................................................ |
298 |
16-6. |
Interrupt Timing Specify Register Format ...................................................................................... |
300 |
16-7. |
3-Wire Serial I/O Mode Timings .................................................................................................... |
305 |
16-8. |
RELT and CMDT Operations ......................................................................................................... |
305 |
16-9. |
Circuit of Switching in Transfer Bit Order ...................................................................................... |
306 |
16-10. |
Example of Serial Bus Configuration with SBI .............................................................................. |
307 |
16-11. |
SBI Transfer Timings ..................................................................................................................... |
309 |
16-12. |
Bus Release Signal ....................................................................................................................... |
310 |
16-13. |
Command Signal ........................................................................................................................... |
310 |
16-14. |
Addresses ..................................................................................................................................... |
311 |
16-15. |
Slave Selection with Address ........................................................................................................ |
311 |
16-16. |
Commands .................................................................................................................................... |
312 |
28
LIST OF FIGURES (5/8)
Figure No. |
|
Title |
Page |
16-17. |
Data ............................................................................................................................................... |
312 |
|
16-18. |
Acknowledge Signal ...................................................................................................................... |
313 |
|
16-19. |
BUSY and READY Signals ............................................................................................................ |
314 |
|
16-20. |
RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................. |
319 |
|
16-21. |
RELT and CMDD Operations (Slave) ............................................................................................ |
319 |
|
16-22. |
ACKT Operation ............................................................................................................................ |
320 |
|
16-23. |
ACKE Operations .......................................................................................................................... |
321 |
|
16-24. |
ACKD Operations .......................................................................................................................... |
322 |
|
16-25. |
BSYE Operation ............................................................................................................................ |
322 |
|
16-26. |
Pin Configuration ........................................................................................................................... |
325 |
|
16-27. |
Address Transmission from Master Device to Slave Device (WUP = 1) ....................................... |
327 |
|
16-28. |
Command Transmission from Master Device to Slave Device ..................................................... |
328 |
|
16-29. |
Data Transmission from Master Device to Slave Device .............................................................. |
329 |
|
16-30. |
Data Transmission from Slave Device to Master Device .............................................................. |
330 |
|
16-31. |
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................. |
333 |
|
16-32. |
2-Wire Serial I/O Mode Timings .................................................................................................... |
337 |
|
16-33. |
RELT and CMDT Operations ......................................................................................................... |
338 |
|
16-34. |
|
|
339 |
SCK0/P27 Pin Configuration ......................................................................................................... |
|||
17-1. |
Serial Bus Configuration Example Using I2C Bus ......................................................................... |
343 |
|
17-2. |
Serial Interface Channel 0 Block Diagram .................................................................................... |
345 |
|
17-3. |
Timer Clock Select Register 3 Format ........................................................................................... |
349 |
|
17-4. |
Serial Operating Mode Register 0 Format ..................................................................................... |
351 |
|
17-5. |
Serial Bus Interface Control Register Format ................................................................................ |
352 |
|
17-6. |
Interrupt Timing Specify Register Format ...................................................................................... |
354 |
|
17-7. |
3-Wire Serial I/O Mode Timings .................................................................................................... |
359 |
|
17-8. |
RELT and CMDT Operations ......................................................................................................... |
359 |
|
17-9. |
Circuit of Switching in Transfer Bit Order ...................................................................................... |
360 |
|
17-10. |
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................. |
361 |
|
17-11. |
2-Wire Serial I/O Mode Timings .................................................................................................... |
365 |
|
17-12. |
RELT and CMDT Operations ......................................................................................................... |
366 |
|
17-13. |
Example of Serial Bus Configuration Using I2C Bus ..................................................................... |
367 |
|
17-14. |
I2C Bus Serial Data Transfer Timing .............................................................................................. |
368 |
|
17-15. |
Start Condition ............................................................................................................................... |
369 |
|
17-16. |
Address ......................................................................................................................................... |
369 |
|
17-17. |
Transfer Direction Specification ..................................................................................................... |
369 |
|
17-18. |
Acknowledge Signal ...................................................................................................................... |
370 |
|
17-19. |
Stop Condition ............................................................................................................................... |
370 |
|
17-20. |
Wait Signal .................................................................................................................................... |
371 |
|
17-21. |
Pin Configuration ........................................................................................................................... |
377 |
|
17-22. |
Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) .......... |
379 |
|
17-23. |
Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) .......... |
382 |
|
17-24. |
Start Condition Output ................................................................................................................... |
385 |
|
17-25. |
Slave Wait Release (Transmission) .............................................................................................. |
386 |
29
LIST OF FIGURES (6/8)
Figure No. |
|
Title |
Page |
17-26. |
Slave Wait Release (Reception) .................................................................................................... |
387 |
|
17-27. |
|
|
390 |
SCK0/SCL/P27 Pin Configuration ................................................................................................. |
|||
17-28. |
|
|
390 |
SCK0/SCL/P27 Pin Configuration ................................................................................................. |
|||
17-29. |
Logic Circuit of SCL Signal ............................................................................................................ |
391 |
|
18-1. |
Serial Interface Channel 1 Block Diagram .................................................................................... |
395 |
|
18-2. |
Timer Clock Select Register 3 Format ........................................................................................... |
398 |
|
18-3. |
Serial Operation Mode Register 1 Format ..................................................................................... |
399 |
|
18-4. |
Automatic Data Transmit/Receive Control Register Format .......................................................... |
400 |
|
18-5. |
Automatic Data Transmit/Receive Interval Specify Register Format ............................................. |
401 |
|
18-6. |
3-Wire Serial I/O Mode Timings .................................................................................................... |
407 |
|
18-7. |
Circuit of Switching in Transfer Bit Order ...................................................................................... |
408 |
|
18-8. |
Basic Transmission/Reception Mode Operation Timings .............................................................. |
417 |
|
18-9. |
Basic Transmission/Reception Mode Flowchart ............................................................................ |
418 |
|
18-10. |
Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ...... |
419 |
|
18-11. |
Basic Transmission Mode Operation Timings ............................................................................... |
421 |
|
18-12. |
Basic Transmission Mode Flowchart ............................................................................................. |
422 |
|
18-13. |
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ..................................... |
423 |
|
18-14. |
Repeat Transmission Mode Operation Timing .............................................................................. |
425 |
|
18-15. |
Repeat Transmission Mode Flowchart .......................................................................................... |
426 |
|
18-16. |
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) .................................. |
427 |
|
18-17. |
Automatic Transmission/Reception Suspension and Restart ........................................................ |
429 |
|
18-18. |
System Configuration When the Busy Control Option is Used ..................................................... |
430 |
|
18-19. |
Operation Timings when Using Busy Control Option (BUSY0 = 0) ............................................... |
431 |
|
18-20. |
Busy Signal and Wait Cancel (when BUSY0 = 0) ......................................................................... |
432 |
|
18-21. |
Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ................................ |
433 |
|
18-22. |
Operation Timing of the Bit Slippage Detection Function Through the Busy SIgnal |
|
|
|
(when BUSY0 = 1) ......................................................................................................................... |
434 |
|
18-23. |
Automatic Data Transmit/Receive Interval .................................................................................... |
435 |
|
18-24. |
Operation Timing with Automatic Data Transmit/Receive Function Performed by |
|
|
|
Internal Clock ................................................................................................................................ |
436 |
|
19-1. |
Serial Interface Channel 2 Block Diagram .................................................................................... |
441 |
|
19-2. |
Baud Rate Generator Block Diagram ............................................................................................ |
442 |
|
19-3. |
Serial Operating Mode Register 2 Format ..................................................................................... |
444 |
|
19-4. |
Asynchronous Serial Interface Mode Register Format .................................................................. |
445 |
|
19-5. |
Asynchronous Serial Interface Status Register Format ................................................................ |
447 |
|
19-6. |
Baud Rate Generator Control Register Format ............................................................................. |
448 |
|
19-7. |
Asynchronous Serial Interface Transmit/Receive Data Format ..................................................... |
461 |
|
19-8. |
Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing .. |
463 |
|
19-9. |
Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing ....... |
464 |
|
19-10. |
Receive Error Timing ..................................................................................................................... |
465 |
|
19-11. |
The State of Receive Buffer Register (RXB) and Whether the Receive Completion |
|
|
|
Interrupt Request (INTSR) is Generated ....................................................................................... |
466 |
30