DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P308
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P308 is a model of the µPD75308 equipped with a one-time PROM or EPROM instead of an
internal mask ROM.
µ
Two types are available as the
quantity of many different types of application systems as data can only be written once to the one-time
PROM of this type. Programs can be written and rewritten to the built-in EPROM type making it ideal
for system evaluation.
Detailed functions are described in the followig user's manual. Be sure to read it for designing.
PD75P308. The one-time PROM type is ideal for production of a small
µ
PD75308 User's Manual: IEM-5016
FEATURES
•
µ
PD75308 compatible
• Memory capacity
• Program memory (PROM): 8064 x 8 bits
• Data memory (RAM): 512 x 4 bits
• Can be connected to a pull-up resistor through software: Ports 0-3, 6, 7
• Open-drain input/output: Ports 4 and 5
• Single power source: 5V ± 5%
ORDERING INFORMATION
Part Number Package Internal ROM
µ
PD75P308GF-3B9 80-pin plastic QFP (14 x 20 mm) One-time PROM
µ
PD75P308K 80-pin ceramic WQFN (LCC w/window) EPROM
QUALITY GRADE
Part Number Package Quality Grade
µ
PD75P308GF-001-3B9 80-pin plastic QFP (14 x 20 mm) Standard
µ
PD75P308K 80-pin Ceramic WQFN (LCC w/window) Standard
★
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The function common to the one-time PROM and EPROM types of product is referred to as PROM throughout this document.
Document No. IC-2472B
(O. D. No. IC-7208C)
Date Published November 1993 P
Printed in Japan
The information in this document is subject to change without notice.
The mark ★ shows major revised points.
NEC Corporation 1989
PIN CONFIGURATION
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
COM0
COM1
COM2
COM3
S11
S10S9S8S7S6S5S4S3S2S1S0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35
µ
µ
PD75P308GF-3B9
PD75P308K
RESET
36 37 38 39 40
P73/KR7
P72/KR6
P71/KR5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
X2
X1
PP
V
XT2
XT1
DD
V
P33 (MD3)
P32 (MD2)
P31/SYNC (MD1)
P30/LCDCL (MD0)
P23/BUS
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SBI
µ
PD75P308
BIAS
LC1
LCO
VVV
LC2
P40
P41
P42
P43
SS
V
P50
P51
P52
P53
P01/SCK
P00/INT4
P02/SO/SB0
2
BLOCK DIAGRAM
3
TI0/P13
PTO0/P20
BUZ/P23
SI/SBI/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60KR3/P63,
KR4/P70KR7/P73
BASIC
INTERVAL
TIMER
TIMER/EVENT
COUNTER
INTW
SERIAL
INTERFACE
INTERRUPT
CONTROL
8
BUFFER(16)
INTBT
#0
INTT0
WATCH
TIMER
INTCSI
BIT SEQ.
4
4
4
4
4
P00-P03
P10-P13
P20-P23
P30-P33
/MD0-MD3
P40-P43
PROGRAM
COUNTER(13)
ALU
CY
SP(8)
BANK
PORT0
PORT1
PORT2
PORT3
PORT4
PROGRAM
f
LCD
MEMORY
(PROM)
GENERAL REG.
DECODE
AND
CONTROL
8064 x 8 BITS
DATA
MEMORY
(RAM)
PORT5
PORT6
PORT7
512 x 4 BITS
LCD
CONTROLLER
/DRIVER
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
N
f /2
X
SYSTEM CLOCK
GENERATOR
SUB
MAIN
STAND BY
CONTROL
CPU
CLOCK
f
LCD
4
4
4
24
8
4
3
P50-P53
P60-P63
P70-P73
S0-S23
S24/BP0
-S31/BP7
COM0-COM3
V -V
LCO LC2
BIAS
µ
PD75P308
LCDCL/P30
SYNC/P30
PCL/P22
XT1
V
V
DD
X2
X1XT2
PP
RESET
V
SS
µ
PD75P308
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................. 5
1.1 PORT PINS ................................................................................................................................................. 5
1.2 NON PORT PINS ....................................................................................................................................... 6
1.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................................ 7
★
1.4 NOTES ON USING P00/INT4 AND RESET PINS ..................................................................................... 9
2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308.................................................................. 10
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) ........................................................... 11
3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY ............................................ 11
3.2 PROGRAM MEMORY WRITE PROCEDURE .......................................................................................... 12
3.3 PROGRAM MEMORY READ PROCEDURE ............................................................................................ 13
µ
3.4 ERASURE (
PD75P308K ONLY) ............................................................................................................. 14
4. ELECTRICAL SPECIFICATIONS........................................................................................................ 15
5. PACKAGE DRAWINGS ...................................................................................................................... 28
6. RECOMMENDED SOLDERING CONDITIONS................................................................................. 30
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 31
★
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 32
4
1. PIN FUNCTIONS
1.1 PORT PINS
µ
PD75P308
Pin Name
Input/Output Function 8-Bit I/O When Reset
Also Served
As
P00 Input INT4
P01 Input/Output SCK
P02 Input/Output SO/SB0
P03 Input/Output SI/SBI
P10 INT0
P11 INT1
P12 INT2
Input
P13 TI0
P20 PTO0
P21 —
Input/Output
P22 PCL
P23 BUZ
2
P30*
P31*
P32*
P33*
2
Input/Output
2
2
SYNC
MD2
MD3
P40-43*2Input/Output —
P50-P53*2Input/Output —
P60 KR0
P61 KR1
P62 KR2
Input/Output
P63 KR3
P70 KR4
P71 KR5
P72 KR6
Input/Output
P73 KR7
BP0 S24
BP1 S25
BP2 S26
Output
BP3 S27
BP4 S28
BP5 S29
BP6 S30
Output
BP7 S31
4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.
With noise elimination function
4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.
4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.
Programmable 4-bit input/output port
MD0LCDCL
(PORT3)
MD1
This port can be specified for input/output
in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.
N-ch open-drain 4-bit input/output port
(PORT4)
Data input/output pin for writing and
verifying of program memory (PROM)
(lower 4 bits)
N-ch open-drain 4-bit input/output port
(PORT5)
Data input/output pin for writing and
verifying of program memory (PROM)
(upper 4 bits)
Programmable 4-bit input/output port
(PORT6)
This port can be specified for input/output
in bit units.
Internal pull-up resistors can be specified
in 4-bit units by software.
4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.
1-bit output port (BIT PORT)
Shared with a segment output pin.
X
X
X
High impedance
●●
High impedance
●●
X
Input
InputX
Input
Input
Input
Input
*3
Input/
Output
Circuit
TYPE
B
F -A
F -B
M -C
B -C
E-B
E-B
M-A
M-A
F -A
F -A
G-C
*1
★
*1: Circles indicate schmitt trigger inputs.
2: Can directly drive LED.
3: For BP0-7, V
LC1 indicated below are selected as the input source.
However, the output level is changed depending on BP0-7 and the VLC1 external circuits.
5
1.2 NON PORT PINS
µ
PD75P308
Pin Name
Input/Output Function When Reset
TI0 Input P13
PTO0 Output P20
PCL Input/Output P22
BUZ Input/Output P23 Input E-B
SCK Input/Output P01
SO/SB0 Input/Output P02 Input
SI/SB1 Input/Output P03 Input M -C
Also Served
As
Timer/event counter external event pulse input
Timer/event counter output
Clock output
Fixed frequency output (for buzzer or for trimming
the system clock)
Serial clock input/output
Serial data output
Serial bus input/output
Serial data input
Serial bus input/output
—
Input
Input
Input
Edge detection vector interrupt input (either rising
INT4 Input P00 —
INT0 P10
Input
INT1 P11
INT2 Input P12
KR0-KR3 Input/Output P60-P63
KR4-KR7 Input/Output P70-P73
S0-S23 Output —
★
S24-S31 Output BP0-7
COM0-
COM3
V
LC0-VLC2 ——
Output —
BIAS — —
LCDCL*2Input/Output P30
SYNC*2Input/Output P31
or falling edge detection is effective)
Edge detection vector interrupt input (detection
edge can be selected)
Edge detection testable input (rising edge detection)
Testable input/output(parallel falling edge detection)
Testable input/output(parallel falling edge detection)
Segment signal output
Segment signal output
Common signal output
LCD drive power
External dividing resistor disconnect output
Externally expanded driver clock output
Externally expanded driver sync clock output
—
—
Input
Input
*3
*3
*3
—
High-impedance
Input
Input
To connect the crystal/ceramic oscillator to the main
X1, X2 Input — —
system clock generator.
When inputting the external clock, input the external
clock to pin X1, and the reverse phase of the
external clock to pin X2.
XT1 Input —
XT2 — —
To connect the crystal oscillator to the subsystem
clock generator.
When the external clock is used, in XT1 inputs the
external clock. In this case, pin XT2 must be left
open.
—
Pin XT1 can be used as a 1-bit input (test) pin.
RESET Input —
MD0-MD3 Input/Output P30-P33
System reset input (low level active)
To select mode when writing/verifying of program
memory (PROM)
—
Input
Program voltage application when writing and
VPP ——
verifying of program memory (PROM)
Connect to V
DD during the normal operation
—
Apply +12.5V when writing/verifying EPROM
DD ——
V
VSS ——
Positive power supply
GND
—
—
Input/
Output
Circuit
*1
TYPE
B -C
E-B
E-B
F -A
F -B
B
B -C
B -C
F -A
F -A
G-A
G-C
G-B
—
—
E-B
E-B
—
—
B
E-B
—
—
—
*1: Circles indicate schmitt trigger inputs.
2: These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31.
3: For these display output, V
LCX indicated below are selected as the input source.
S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0
However, display output level varies depending on the particular display output and VLCX external circuit.
6
1.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the
µ
PD75P308
µ
PD75P308.
TYPE A (for TYPE E–B)
DD
V
P–ch
IN
N–ch
Input buffer of CMOS standard
TYPE B
IN
TYPE D (for TYPE E–B, F-A)
data
output
disable
P–ch
OUT
N–ch
Push–pull output that can be set in a output
high–impedance state (both P–ch and N–ch are off)
TYPE E–B
P.U.R.
enable
data
Type D
output
disable
V
DD
P.U.R.
P–ch
IN/OUT
Schmitt trigger input with hysteresis characteristics
TYPE B–C
V
DD
P.U.R.
P–ch
IN
P.U.R. : Pull
P.U.R.
enable
–Up Resistor
Schmitt trigger input with hysteresis characteristics
TYPE E–E
data
output
disable
Type A
P.U.R. : Pull–Up Resistor
P.U.R.
enable
Type D
Type A
Type B
P.U.R. : Pull–Up Resistor
V
DD
P.U.R.
P–ch
IN/OUT
7
µ
PD75P308
TYPE F–A
data
output
disable
TYPE F–B
output
disable
(P)
data
output
disable
P.U.R.
enable
Type D
Type B
P.U.R. : Pull–Up Resistor
P.U.R.
enable
output
disable
(N)
P.U.R. : Pull–Up Resistor
VDD
V
DD
P-ch
N-ch
P–ch
IN/OUT
V
DD
P.U.R.
P–ch
IN/OUT
TYPE G–B
VLC0
P-ch
VLC1
COM
data
VLC2
N-ch
TYPE G–C
VDD
VLC0
VLC1
SEG
data/Bit Port data
VLC2
P-ch N-ch
OUT
N-ch P-ch
P-ch
P-ch
OUT
N-ch
N-ch
TYPE G–A
VLC0
LC1
V
SEG
data
VLC2
P-ch
P-ch
OUT
N-ch
N-ch
TYPE M–A
data
output
disable
IN/OUT
N-ch
Middle voltage input buffer
8
TYPE M-C
V
DD
P.U.R.
µ
PD75P308
data
output
disable
P.U.R.
enable
N-ch
P–ch
IN/OUT
P.U.R. : Pull–Up Resistor
1.4 NOTES ON USING P00/INT4 AND RESET PINS
In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function
µ
to set a test mode (for IC testing) in which the internal operations of the
When a voltage higher than V
during ordinary operation, the
DD is applied to either of these pins, the test mode is set. This means that, even
µ
PD75P308 may be set in the test mode if a noise exceeding VDD is applied.
PD75P308 are tested.
For example, if the wiring length of the P00/INT4 or RESET pin is too long, noise superimposed on the wiring
line of the pin may cause the above problem.
Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise
preventive measures as shown below by using external components.
• Connect diode with low V
and P00/INT4, RESET pin
Diode with
low V
F
P00/INT4, RESET
F between VDD
• Connect capacitor between V
and P00/INT4, RESET pin
V DD V DD
P00/INT4, RESET
DD
V DDV DD
9
µ
PD75P308
2. DIFFERENCES BETWEEN µPD75P308 AND µPD75308
The µPD75P308 is a model of the µPD75308 and is equipped with a PROM instead of a mask ROM.
µ
Programs can be rewritten to the PROM of the
µ
PD75P308 and µPD75308. You should fully consider these differences when you debug or produce your
PD75P308. Table 2-1 shows the differences between the
application system on an experimental basis by using the PROM model, and then proceed to mass-produce
the system by using the mask ROM model.
µ
For the details of the CPU and the internal hardware, refer to
PD75308 User's Manual (IEM-5016).
Table 2-1 Differences between µPD75P308 and µPD75308
Program Memory
Pull-up Resistor Ports 4, 5
Dividing Resistor for LCD
Driving Power Supply
Pin Connection
Electrical Specifications
★
Operating Voltage Range 5V±5% 2.7-6.0V
Package
Others
★
★
Note:
The noise immunity and noise radiation differ between the PROM and mask ROM models. To replace
the PROM model with the mask ROM model in the course of experimental production to mass
production, evaluate your system by using the CS mode (not ES model) of the mask ROM model.
Item
Pins 50-53 P30/MD0-P33/MD3 P30-P33
Pin 57 VPP NC
µ
PD75P308K
• EPROM • PROM (one-time model) • Mask ROM
• 0000H-1F7FH • 0000H-1F7FH • 0000H-1F7FH
• 8064 x 8 bits • 8064 x 8 bits • 8064 x 8 bits
Not provided Mask option
Not provided Mask option
Current dissipations and operating temperature ranges differ between µPD75P308 and
µ
PD75308. For detail, refer to the specification documents of each mode.
80-pin ceramic WQFN
(LCC w/window)
Noise immunity and noise radiation differ because circuit scale and mask layout are
different.
µ
PD75P308GF
80-pin plastic QFP (14 x 20 mm)
µ
PD75308GF
10
µ
PD75P308
3. WRITING AND VERIFYING PROM (PROGRAM MEMORY)
The program memory of the µPD75P308 is a PROM of 8064 x 8 bits. To write data to or verify the contents
of this PROM, the pins listed in the table below are used. Note that no address input pins are provided
because the address is updated by the clock input through the X1 pin.
Pin Name Function
VPP Applies voltage when program memory is written/verified (normally, at VDD potential)
X1, X2
MD0-MD3 These pins select operation mode when program memory is written/verified.
P40-P43 (Lower 4)
P50-P53 (Upper 4)
VDD
Note 1:
Always cover the erasure window of the µPD75P308K with a light-opaque film except when the
These pins input clock that updates address when program memory is written/verified. To X2 pin,
input signal 180º out of phase in respect to signal to X1 pin.
These pins input/output 8-bit data when program memory is written/verified.
Power supply voltage application pin.
Apply 5V ± 5% to this pin during normal operation and 6V when program memory is written/verified.
contents of the program memory are erased.
2:
The one-time PROM model µPD75P308GF is not equipped with a window and therefore, the
contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays.
3.1 OPERATION MODES FOR WRITING/VERIFYING PROGRAM MEMORY
When +6V is applied to the V
DD pin of the
µ
PD75P308 with +12.5V applied to the VPP pin, the µPD75P308
is set in the program memory write/verify mode. In this mode, the following operation modes can be set
by using the MD0-MD3 pins. At this time, pull down the levels of all the other pins to VSS.
VPP
+12.5 V
Operating Mode Specification
VDD
MD0 MD1 MD2 MD3
HLHL
+6 V
LHHH
LLHH
HxHH
Operating Mode
Program memory address 0 clear mode
Write mode
Verify mode
Program inhibit mode
x: L or H
11
µ
PD75P308
3.2 PROGRAM MEMORY WRITE PROCEDURE
The program memory write procedure is as follows. High-speed program memory write is possible.
(1) Ground the unused pins through pull-down resistors. The X1 pin must be low.
(2) Supply 5 V to the V
DD and VPP pins.
(3) Wait for 10 microseconds.
(4) Set program memory address 0 clear mode.
(5) Supply 6 V to the V
DD pin and 12.5 V to the VPP pin.
(6) Set program inhibit mode.
(7) Write data in 1-millisecond write mode.
(8) Set program inhibit mode.
(9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been
written, repeat steps (7) to (9).
(10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times
1 milliseconds.
(11) Set program inhibit mode.
(12) Supply a pulse to the X1 pin four times to update the program memory address by 1.
(13) Repeat steps (7) to (12) to the last address.
(14) Set program memory address 0 clear mode.
(15) Change the voltages of V
DD and VPP pins to 5 V.
(16) Turn off the power supply.
Steps (2) to (12) are illustrated below.
X-time repetition
Write Verify
V
PP
V
PP
V
DD
VDD+1
V
DD
V
DD
X1
P40-P43
P50-P53
MD0
(P30)
Data input
Data
output
Additional
data write
Data input
Address
increment
12
MD1
(P31)
MD2
(P32)
MD3
(P33)
µ
PD75P308
3.3 PROGRAM MEMORY READ PROCEDURE
The contents of the program memory can be read in the following procedure.
(1) Ground the unused pins through pull-down resistors. The X1 pin must be low.
(2) Supply 5 V to the V
DD and VPP pins.
(3) Wait for 10 microseconds.
(4) Set program memory address 0 clear mode.
(5) Supply 6 V to the V
DD pin and 12.5 V to the VPP pin.
(6) Set program inhibit mode.
(7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the
X1 pin four times.
(8) Set program inhibit mode.
(9) Set program memory address 0 clear mode.
(10) Change the voltages of V
DD and VPP pins to 5 V.
(11) Turn off the power supply.
Steps (2) to (9) are illustrated below.
VPP
VDD
P40-P43
P50-P53
VPP
VDD
VDD+1
DD
V
X1
MD0
(P30)
MD1
(P31)
Data output Data output
MD2
(P32)
MD3
(P33)
13
µ
PD75P308
3.4 ERASURE (µPD75P308K ONLY)
The contents of the data programmed to the
program memory to ultraviolet rays.
The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the
ultraviolet rays necessary for complete erasure is 15 W.s/cm
When a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mW/cm
about 15 to 20 minutes is required.
µ
PD75P308 can be erased by exposing the window of the
2
(= ultraviolet ray intensity x erasure time).
2
) is used,
Note 1:
2:
Remarks:
The contents of the program memory may be erased when the µPD75P308 is exposed for a long
time to direct sunlight or the light of fluorescent lamps. To protect the contents from being
erased, mask the window of the program memory with the light-opaque film supplied as an
accessory with the UV EPROM products.
To erase the memory contents, the distance between the ultraviolet ray lamp and the µPD75P308
should be 2.5 cm or less.
The time required for erasure changes depending on the degradation of the ultraviolet ray
lamp and the surface condition (dirt) of the window of the program memory.
14
µ
PD75P308
4. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter Symbol Conditions Rating Unit
Supply Voltage VDD -0.3 to +7.0 V
Supply Voltage V
PP -0.3 to +13.5 V
VI1 Other than ports 4 or 5 -0.3 to VDD+0.3 V
Input Voltage
Output Voltage V
*1
VI2
O -0.3 to VDD+0.3 V
Ports 4 and 5 Open-drain -0.3 to +11 V
1 Pin -15 mA
High-Level Output Current
I
OH
All pins -30 mA
Peak value 30 mA
One pin
Effective value 15 mA
Low-Level Output Current
*2
OH
I
Total of ports 0, 2, 3, 5
Peak value 100 mA
Effective value 60 mA
Peak value 100 mA
Total of ports 4, 6, 7
Effective value 60 mA
Operating Temperature T
Storage Temperature T
*1:
The impedance of the power source (pull-up resistor) must be 50 KΩ minimum when a voltage higher
opt -10 to +70 ° C
stg -65 to +150 °C
than 10V is applied to ports 4 and 5.
2:
Effective value = Peak value x √Duty
15
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a = -10 to +70°C, VDD = 5 to ±5 V)
µ
PD75P308
Oscillator Item Conditions MIN. TYP. MAX. Unit
Ceramic
*3
Crystal Oscilaltion
External Clock X1 input frequency
Recommended
Constants
X1 X2
C1 C2
V
DD
X1 X2
C1 C2
V
DD
X1 X2
µ
PD74HCU04
Oscillation
frequency (fXX)
*1
Oscillation stabilization After VDD came to MIN.
*2
time
frequency (fXX)
*1
of oscillation voltage range
Oscillation stabilization
*2
time
*1
(fX)
X1 input high-, low-level
widths (tXH, tXL)
1.0 5.0
4ms
1.0 4.19 5.0
10 ms
1.0 5.0
100 500 ns
* 1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the
oscillator circuit.
For instruction execution time, refer to AC Characteristics.
2: Time required for oscillation to stabilize after V
DD reaches the minimum value of the oscillation voltage
range or the STOP mode has been released.
3: The oscillators below are recommended.
★
4: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction
µ
execution time: otherwise, one machine cycle is set to less than 0.95
µ
minimum value of 0.95
s.
s, falling short of the rated
*4
MHz
*4
MHz
*4
MHz
★
Caution: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted
line in the figures as follows to avoid adverse influences on the wiring capacity:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential
DD. Do not connect the power source pattern through which a high current flows.
as V
• Do not extract signals from the oscillation circuit.
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS
MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -10 to +70°C)
Manufacturer
Murata
Mfg.
Co., Ltd.
Product Name
External Capacitance [pF]
C1
C2
CSA 2.00MG 30 30 4.75 5.25
CSA 4.19MG 30 30 4.75 5.25
CSA 4.19MGU 30 30 4.75 5.25
CST 4.19MG 30 pF (internal) 30 pF (internal) 4.75 5.25
Oscillation
Voltage Range [V]
MAX.MIN.
16
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a = -10 to +70°C, VDD = 5 V ±5%)
µ
PD75P308
Oscillator Item Conditions MIN. TYP. MAX. Unit
Crystal Oscillation
External Clock XT1 input frequency
Recommended
Constants
XT1 XT2
R
C3 C4
V
DD
XT1 XT2
Open
frequency (fXT)
Oscillation stabilization
*
time
(fXT)
XT1 input high-, low-level
widths (tXTH, tXTL)
32 32.768 35 kHz
1.0 2 s
32 100 kHz
515
µ
s
*: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage
range.
Caution: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line
in the figures as follows to avoid adverse influences on the wiring capacity:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential
as V
DD. Do not connect the power source pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
★
The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the
current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more
easily than the main system clock oscillation circuit. When using the subsystem clock, therefore,
exercise utmost care in wiring the circuit.
CAPACITANCE (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Capacitance CIN f = 1 MHz 15 pF
Output Capacitance COUT Pins other than thosemeasured are at 0 V 15 pF
Input/Output CIO
Capacitance
a = 25°C, VDD = 0 V)
15 pF
17
DC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 5V ±5%)
µ
PD75P308
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
High-Level Input Leakage Current
Low-Level Input Leakage Current
High-Level Output Leakage Current
Low-Level Output Leakage Current
Internal Pull-Up Resistor
LCD Drive Voltage
LCD Output Voltage Deviation
(Common)
LCD Output Voltage Deviation
(Segment)
Supply Current
2
*
2
*
3
*
Symbol
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VOH1
VOH2
VOL1
VOL2
VOL3
ILIH1
ILIH2
ILIH3
ILIL1
ILIL2
ILOH1
ILOH2
ILOL
RLI
VLCD
VODC
VODS
IDD1
IDD2
IDD3
IDD4
Conditions MIN. TYP. MAX. Unit
Ports 2, 3
Ports 0, 1, 6, 7, RESET
Ports 4, 5 Open-drain
X1, X2, XT1
Ports 2, 3, 4, 5
Ports 0, 1, 6, 7, RESET
X1, X2, XT1
Ports 0, 2, 3, IOH = -1mA
6, 7
BIAS
BP0-7 IOH = -100µA*
1
Ports 0, 2, 3, Ports 3, 4, 5
6, 7 IOL = 15mA
IOL = 1.6mA
SB0, 1
Open-drain
BP0-7 IOL = 100µA*
VIN = VDD
Pull-up R ≥ 1kΩ
1
Other than below
X1, X2, XT1
VIN = 10V Ports 4, 5
VIN = 0V
Other than below
X1, X2, XT1
VOUT = VDD Other than below
VOUT = 10V Ports 4.5
VOUT = 0V
Ports 0, 1, 2, 3, 6, 7
(except P00) VIN = 0V
I0 = ±5 µA
I0 = ±1 µA
4.19MHz crystal *
oscillator
C1 = C2 = 22pF
32 kHz *
crystal oscillator
XT1 = 0V
STOP mode
VLCD0 = VLCD
VLCD1 = VLCD x —
VLCD2 = VLCD x —
2.7 V ≤ VLCD ≤ VDD
4
6
*
HALT mode
5
HALT mode
2
3
1
3
0.7 VDD VDD V
0.8 VDD VDD V
0.7 VDD 10 V
VDD-0.5 VDD V
0 0.3 VDD V
0 0.2 VDD V
0 0.4 V
VDD-1.0
VDD-2.0 V
0.4 2.0 V
0.4 V
0.2VDD V
1.0 V
3
µ
20
µ
20
µ
-3
µ
-20
µ
3
µ
20
µ
-3
µ
15 40 80 KΩ
2.5 VDD V
0 ±0.2V V
0 ±0.2V V
515mA
500 1500µA
350 1000
35 100
0.5 20
µ
µ
V
A
A
A
A
A
A
A
A
A
A
* 1: When using two of BP0-BP3 and two of BP4-BP7 for output at the same time.
2: "Voltage deviation" means the difference between the ideal segment or common output value
(VLCDn: = 0, 1, 2) and output voltage.
3: Currents for the built-in pull-up resistor are not included.
4: Including when the subsystem clock is operated.
5: When operated with the subsystem clock by setting the system clock control register (SCC) to
1001 to stop the main system clock operation.
6: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.
18
AC CHARACTERISTICS (Ta = -10 to + 70°C, VDD = 5V ±5%)
Operation Other Than Serial Transfer
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU Clock Cycle Time*
(Minimum Instruction
Execution Time
= 1 Machine Cycle)
TI0 Input Frequency
TI0 Input High-, Low-Level
Widths
Interrupt Input High-, Low-Level
Widths
RESET Low-Level Width
* 1: The CPU clock (Φ) cycle time is determined
by the oscillation frequency of the connected
1
w/main system clock
tCY
w/subsystem clock
fTI
tTIH, tTIL
tINTH,
INT0
tINTL
KR0-7, INT1, 2, 4
tRSL
70
64
60
oscillator, system clock control register
(SCC), and processor clock control register
(PCC).
The figure on the right is cycle time t
supply voltage V
DD characteristics at the
main system clock.
CY vs.
µ
cy
2: 2tCY or 128/fXX depending on the setting of
the interrupt mode register (IM0).
µ
PD75P308
0.95 64
114 122 125
µ
s
µ
s
0 1 MHz
0.48
*2
10
10
t vs V
cy DD
µ
s
µ
s
µ
s
µ
s
(with main system clock)
6
5
4
3
2
Cycle time t [ s]
1
0.5
0 1 2 3 4 5 6
Supply voltage V [V]
DD
19
SERIAL TRANSFER OPERATION
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time
SCK High-, Low-Level Widths
SI Set-Up Time (vs. SCK )
SI Hold Time (vs. SCK )
↓ →
SCK SO Output
Delay Time
★
*: RL and CL are load resistance and load capacitance of the SO output line.
↑
↑
tKCY1
tKH1, tKL1
tSIK1
tKSI1
tKSO1
RL = 1kΩ, CL = 100pF*
Output
Output
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time
SCK High-, Low-Level Widths
SI Set-Up Time (vs. SCK )
SI Hold Time (vs. SCK )
↓ →
SCK SO Output
Delay Time
↑
↑
tKCY2
tKH2, tKL2
tSIK2
tKSI2
tKSO2
RL = 1kΩ, CL = 100pF*
Input
Input
µ
PD75P308
1600 ns
tKCY1/2-50 ns
150 ns
400 ns
250 ns
800 ns
400 ns
100 ns
400 ns
300 ns
★
*: R
L and CL are load resistance and load capacitance of the SO output line.
20
SBI MODE (SCK: internal clock output (master))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time
SCK High-, Low-Level
Widths
SB0, 1 Set-Up Time (vs. SCK )
SB0, 1 Hold Time (vs. SCK )
↓ →
SCK SB0, 1 Output
Delay Time
SCK SB0, 1
↑ → ↓
↓ → ↓
SB0, 1 SCK
SB0, 1 Low-Level Width
SB0, 1 High-Level Width
tKCY3
tKL3
tKH3
↑
tSIK3
↑
tKSI3
tKSO3
tKSB
tSBK
tSBL
tSBH
RL = 1kΩ, CL = 100pF*
µ
PD75P308
1600 ns
tKCY/2
-50
150 ns
tKCY/2 ns
0 250 ns
KCY ns
t
tKCY ns
tKCY ns
tKCY ns
ns
*: RL and CL are load resistance and load capacitance of the SO output line.
SBI MODE (SCK: external clock output (master))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time
SCK High-, Low-Level
Widths
SB0, 1 Set-Up Time (vs. SCK )
SB0, 1 Hold Time (vs. SCK )
↓ →
SCK SB0, 1 Output
Delay Time
↑ →
SCK SB0, 1
↓ →
SB0, 1 SCK
SB0, 1 Low-Level Width
SB0, 1 High-Level Width
L and CL are load resistance and load capacitance of the SO output line.
*: R
↓
↓
t
KCY4
tKL4
tKH4
↑
tSIK4
↑
tKSI4
tKSO4
tSBH
RL = 1kΩ, CL = 100pF*
tKSB
tSBK
tSBL
1600 ns
tKCY/2 ns
★
400 ns
100 ns
0 300 ns
tKCY ns
tKCY ns
tKCY ns
tKCY ns
★
21
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 V
DD
0.2 VDD
Test points
CLOCK TIMING
1/fX
tXL tXH
0.8 VDD
0.2 VDD
µ
PD75P308
TI0 TIMING
X1 input
XT1 input
1/fXT
tXTL tXTH
1/fTI
V
DD –0.5V
0.4 V
V
DD –0.5V
0.4 V
22
tTIL tTIH
TI0
SERIAL TRANSFER TIMING
THREE-LINE SERIAL I/O MODE:
SCK
tKCY1
tKL1 tKH1
tSIK1 tKSI1
µ
PD75P308
SI
SO
TWO-LINE SERIAL I/O MODE:
SCK
tKSO1
tKL
Input data
Output data
tKCY
tKH
SB0,1
tKSO
tSIK tKSI
23
SERIAL TRANSFER TIMING
BUS RELEASE SIGNAL TRANSFER
SCK
t
t
KSB
SBL
SB0,1
COMMAND SIGNAL TRANSFER
µ
PD75P308
KCY3,4
t
t
KL3,4
t
t
SBH
SBK
t
KH3,4
t
KSO3,4
t
SIK3,4
t
KSI3,4
SCK
SB0,1
INTERRUPT INPUT TIMING
INT0, 1, 2, 4
KR0-7
t
KCY3,4
t
KL3,4
t
t
KSB
SBK
t
INTL
t
KH3,4
t
KSO3,4
t
INTH
t
SIK3,4
t
KSI3,4
RESET INPUT TIMING
RESET
24
t
RSL
µ
PD75P308
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
a = -10 to +70°C)
(T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data Retention Supply
Voltage
Data Retention Supply
Current*
1
Release Signal Set Time
Oscillation Stabilization
Wait Time*
2
VDDDR
I
DDDR VDDDR = 2.0V 0.1 10
tSREL
tWAIT
Released by RESET
Released by interrupt
2.0 6.0 V
0
217/fX ms
3
*
µ
µ
ms
A
s
*1: Does not include current folowing through internal pull-up resistor
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable
operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 BTM2 BTM1 BTM0 WAIT time ( ): fX = 4.19 MHz
—0 0— 2
—0 1— 2
—1 0— 2
—1 1— 2
20
/fX (approx. 250 ms)
17
/fX (approx. 31.3 ms)
15
/fX (approx. 7.82 ms)
13
/fX (approx. 1.95 ms)
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation
HALT mode
STOP mode
Data retention mode
DD
V
V
DDDR
t
SREL
STOP instruction
execution
RESET
t
WAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode
STOP mode
Data retention mode
DD
V
STOP instruction execution
VDDDR
tSREL
Operation
mode
Operation
mode
Standby release signal
(interrupt request)
tWAIT
25
µ
PD75P308
DC PROGRAMMING CHARACTERISTICS (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
High-Level Output Voltage
Low-Level Output Voltage
VDD Supply Current
VPP Supply Current
VIH1
VIH2
VIL1
VIL2
ILI
VOH
VOL
IDD
IPP
a = 25 ±5°C, VDD = 6.0±0.25V, VPP = 12.5±0.3V, VSS = 0V)
Other than X1 or X2
X1 and X2
Other than X1 or X2
X1 and X2
VIN = VIL or VIH
IOH = –1 mA
IOL = 1.6 mA
MD0 = VIL, MD1 = VIH
0.7 VDD VDD V
VDD –0.5 VDD V
0 0.3 VDD V
0 0.4 V
VDD –1.0 V
Notes 1: VPP must not exceed +13.5 V, including the overshoot.
2: Apply V
DD before VPP and disconnect it after VPP.
AC PROGRAMMING CHARACTERISTICS (Ta = 25±5°C, VDD = 6.0±0.25V, VPP = 12.5±0.3V, VSS = 0V)
Parameter
Address Set-Up Time*2 (vs.MD0↓)
MD1 Set-Up Time (vs. MD0↓)
Data Set-Up Time (vs. MD0↓)
Address Hold Time*2 (vs.MD0↑)
Data Hold Time (vs. MD0↑)
MD0 ↑→ Data Output Float Delay Time
VPP Set-Up Time (vs. MD3↑)
VDD Set-Up Time (vs. MD3↑)
Initial Program Pulse Width
Additional Program Pulse Width
MD0 Set-Up Time (vs. MD1↑)
MD0 ↓→ Data Output Delay Time
MD1 Hold Time (vs. MD0↑)
MD1 Recovery Time (vs. MD0↓)
Program Counter Reset Time
X1 Input High-/Low- Level Width
X1 Input Frequency
Initial Mode Set Time
MD3 Set-Up Time (vs. MD1↑)
MD3 Hold Time (vs. MD1↓)
MD3 Set-Up Time (vs. MD0↓)
★
★
Address*2 → Data Output Delay Time
Address*2 → Data Output Hold Time
MD3 Hold Time (vs. MD0↑)
MD3 ↓→ Data Output Float Delay Time
Symbol
tAS tAS
tM1S tOES
tDS tDS
tAH tAH
tDH tDH
tDF tDF
tVPS tVPS
tVDS tVCS
tPW tPW
tOPW tOPW
tMOS tCES
tDV tDV
tM1H tOEH
tM1R tOR
tPCR –
tXH,tXL –
fX –
tI –
tM3S –
tM3H –
tM3SR –
tDAD tACC
tHAD tOH
tM3HR –
tDFR –
1
*
MD0 = MD1 = VIL
tM1H + tM1R ≥ 50 µs
When data is read from program memory
When data is read from program memory
When data is read from program memory
When data is read from program memory
When data is read from program memory
Conditions MIN. TYP. MAX. Unit
2
2
2
2
2
0 130 ns
2
2
0.95 1.0 1.05 ms
0.95 21.0 ms
2
2
2
10
0.125
2
2
2
2
0 130 ns
2
10
0.4 V
30 mA
30 mA
µ
1
4.19 MHz
2
2
A
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
*1: These symbols are the corresponding µPD27C256 symbols.
2: The internal address signal is incremented by 1 at the fourth rising edge of X1 input. The internal
address is not connected to any pin.
26
PROGRAM MEMORY WRITE TIMING
VPS
t
tVDS
Data input
DS tDH
t
tPCR tM1S tM1H
tM3S
V
PP
VDD
X1
P40-P43
P50-P53
MD0
MD1
MD2
MD3
VPP
VDD
VDD+1
V
DD
t
I
tXH
Data
output
ttDV tDF tDS tAH
OH
t
M1RtPW
t
MOS
Data input
tOPW
tXL
Data input
tAS
µ
PD75P308
tM3H
PROGRAM MEMORY READ TIMING
V
PP
VDD
X1
P40-P43
P50-P53
MD0
MD1
MD2
VPP
VDD
VDD+1
VDD
t
I
tPCR
tVPS
tVDS
tM3SR
tXL
t
DV
tXH
tHAD
Data output
tDAD
Data output
tM3HR
tDFR
MD3
27
5. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×20)
µ
PD75P308
A
B
64
65
80
F
1
G
H
M
I
P
N
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
41
40
detail of lead end
C
D
S
Q
25
24
J
K
M
L
P80GF-80-3B9-2
ITEM MILLIMETERS INCHES
M
A
B
C
D
F
G
H
I
J
K
L
N
23.6±0.4
20.0±0.2
14.0±0.2
17.6±0.4
1.0
0.8
0.35±0.10
0.15
0.8 (T.P.)
1.8±0.2
0.8±0.2
+0.10
0.15
–0.05
0.15
0.929±0.016
+0.009
0.795
–0.008
+0.009
0.551
–0.008
0.693±0.016
0.039
0.031
+0.004
0.014
–0.005
0.006
0.031 (T.P.)
+0.008
0.071
–0.009
+0.009
0.031
–0.008
+0.004
0.006
–0.003
0.006
P 2.7 0.106
Q
0.1±0.1
0.004±0.004
S 3.0 MAX. 0.119 MAX.
5°±5°
28
80 PIN CERAMIC WQFN
µ
PD75P308
A
B
T
U
E
NOTE
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
K
C
D
W
H
I
G
F
Q
80
S
1
M
J
R
X80KW-80A-1
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
Q
R
S
T
U
W
20.0±0.4
19.0
13.2
14.2±0.4
1.64
2.14
4.064 MAX.
0.51±0.10
0.08
0.8 (T.P.)
1.0±0.2
C 0.5
0.8
1.1
R 3.0
12.0
0.75±0.2
+0.017
0.787
–0.016
0.748
0.520
0.559±0.016
0.065
0.084
0.160 MAX.
0.020±0.004
0.003
0.031 (T.P.)
+0.009
0.039
–0.008
C 0.020
0.031
0.043
R 0.118
0.472
+0.008
0.030
–0.009
29
★
6. RECOMMENDED SOLDERING CONDITIONS
It is recommended that µPD75P308 be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document "Semiconductor
Devices Mounting Manual" (IEI-616).
The soldering methods and conditions are not listed here, consult NEC.
Table 6-1 Soldering Conditions
µ
PD75P308GF-3B9: 80-pin plastic QFP (14 x 20 mm)
µ
PD75P308
Soldering Method Soldering Conditions
Wave Soldering Soldering bath temperature: 260°C max., WS60-162-1
time: 10 seconds max., number of times: 1,
pre-heating temperature: 120°C max. (package surface
temperature), maximum number of days: 2 days*,
(beyond this period, 16 hours of pre-baking is required
at 125°C).
Infrared Reflow Package peak temperature: 230°C, IR30-162-1
time: 30 seconds max. (210°C min.),
number of times: 1, maximum number of days: 2 days*
(beyond this period, 16 hours of pre-baking is required
at 125°C)
VPS Package peak temperature: 215°C, VP15-162-1
Pin Partial Heating Pin temperature: 300°C max., —
*:
Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max.
time: 40 seconds max. (200°C min.),
number of times: 1, maximum number of days: 2 days*
(beyond this period, 16 hours of pre-baking is required
at 125°C)
time: 3 seconds max. (per side)
Symbol for Recommended
Condition
Caution: Do not use two or more soldering methods in combination (except the pin partial heating
method).
Notice
A model that can be soldered under the more stringent conditions (infrared reflow peak
temperature: 235°C, number of times: 2, and an extended number of days) is also available.
For details, consult NEC.
30
µ
PD75P308
APPENDIX A. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
µ
PD75P308:
PROM writing tools
Hardare IE-75000-R
IE-75001-R
IE-75000-R-EM
EP-75308GF-R Emulation prove for µPD75P308GF, provided with 80-pin conversion socket,
PG-1500 PROM programmer
PA-75P308GF PROM programmer adapter solely used for µPD75P308GF. It is connected to
PA-75P308K PROM programmer adapter solely used for µPD75P308K. It is connected to
Software IE Control Program Host machine
PG-1500 Controller • PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)
RA75X Relocatable • IBM PC/ATTM (PC DOSTM Ver.3.1)
Assembler
*1
*2
EV-9200G-80
In-circuit emulator for 75K series
Emulation board for IE-75000-R and IE-75001-R
EV-9200G-80.
PG-1500.
PG-1500.
*1: Maintenance product
2: Not provided with IE-75001-R
3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software.
Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
31
★
APPENDIX B. RELATED DOCUMENTS
µ
PD75P308
32
µ
PD75P308
GENERAL NOTES ON CMOS DEVICES
1 STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled.
The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,
or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic
plate and do not touch the pins of the device.
Handle boards on which MOS devices are mounted similarly .
2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices.
Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow
through the device, causing the device to malfunction. Therefore, fix the input level of the device
by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an
output pin (whose timing is not specified), each pin should be connected to V
a resistor.
Refer to “Processing of Unused Pins” in the documents of each devices.
DD or GND through
3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application.
Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after
the respective operations have been executed.
When using a device with a reset function, be sure to reset the device after power application.
33
[MEMO]
µ
PD75P308
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties by or arising from use of a device described herein or any other
liability arising from use of such device. No license, either express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,
nuclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for the applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products,etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.
34
Loading...