NEC PD23C32340, PD23C32380 Technical data

查询UPD23C32340供应商

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD23C32340, 23C32380

32M-BIT MASK-PROGRAMMABLE ROM

4M-WORD BY 8-BIT (BYTE MODE) / 2M-WORD BY 16-BIT (WORD MODE)

PAGE ACCESS MODE

Description

The µPD23C32340 and µPD23C32380 are 33,554,432 bits mask-programmable ROM. The word organization is

selectable (BYTE mode : 4,194,304 words by 8 bits, WORD mode : 2,097,152 words by 16 bits).

The active levels of OE (Output Enable Input) can be selected with mask-option.

The

PD23C32340 and µPD23C32380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA.

µ

Features

• Pin compatible with NOR Flash Memory

• Word organization

4,194,304 words by 8 bits (BYTE mode)

2,097,152 words by 16 bits (WORD mode)

• Page access mode

BYTE mode : 8 byte random page access (µPD23C32340)

16 byte random page access (

WORD mode :4 word random page access (

8 word random page access (

= 2.7 V to 3.6 V

• Operating supply voltage : V

Operating supply Access time / Power supply current (Active mode) Standby current

voltage Page access time mA (MAX.) (CMOS level input)

V

CC

3.0 V ± 0.3 V 100 / 25 40 55 30

3.3 V ± 0.3 V 90 / 25

CC

ns (MAX.)

PD23C32380)

µ

PD23C32340)

µ

PD23C32380)

µ

PD23C32340

µ

PD23C32380

µ

A (MAX.)

µ

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.

Document No. M15711EJ2V0DS00 (2nd edition)
Date Published February 2003 NS CP(K)
Printed in Japan

The mark shows major revised points.

2001

µµµµ

PD23C32340, 23C32380

Ordering Information

Part Number Package

PD23C32340GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

µ

PD23C32340F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)

µ

PD23C32380GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

µ

PD23C32380F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)

µ

(xxx : ROM code suffix No.)

2

Data Sheet M15711EJ2V0DS

Pin Configurations

/xxx indicates active low signal.

µµµµ

PD23C32340, 23C32380

48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

µµµµ

PD23C32340GZ-xxx-MJH ]

[

µµµµ

PD23C32380GZ-xxx-MJH ]

[

Marking Side

A15

A14

A13

A12

A11

A10

A9

A8

A19

A20

NC

NC

NC

NC

NC

A18

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

WORD, /BYTE

GND

O15, A−1

O7

O14

O6

O13

O5

O12

O4

CC

V

O11

O3

O10

O2

O9

O1

O8

O0

/OE or OE or DC

GND

/CE

A0

A0 to A20 : Address inputs

O0 to O7, O8 to O14 : Data outputs

O15, A–1 : Data output 15 (WORD mode),

LSB Address input (BYTE mode)

WORD, /BYTE : Mode select

/CE : Chip Enable

/OE or OE : Output Enable

V

CC

: Supply voltage

GND : Ground

Note

NC

: No Connection

DC : Don’t Care

Note Some signals can be applied because this pin is not connected to the inside of the chip.

Remark Refer to Package Drawings for the 1-pin index mark.

Data Sheet M15711EJ2V0DS

3

µµµµ

PD23C32340, 23C32380

48-pin TAPE FBGA (8 x 6)

µµµµ

PD23C32340F9-xxx-BC3 ]

[

µµµµ

[

PD23C32380F9-xxx-BC3 ]

Top View Bottom View

6

5

4

3

2

1

ABCDEFGHHGFEDCBA

ABCDEFGH HGFEDCBA

6 A13 A12 A14 A15 A16 WORD, O15, GND 6 GND O15, W ORD, A16 A15 A14 A12 A13

/BYTE A–1 A–1 /BYTE

5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9

4NCNCNCA19O5O12VCCO4 4 O4 V

3 NC NC A18 A20 O2 O10 O11 O3 3 O3 O11 O10 O2 A20 A18 NC NC

2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7

1 A3 A4 A2 A1 A0 /CE /OE or GND 1 GND /OE or /CE A0 A1 A2 A4 A3

OE OE

CC

O12 O5 A19 NC NC NC

A0 to A20 : Address inputs

O0 to O7, O8 to O14 : Data outputs

O15, A–1 : Data output 15 (WORD mode),

LSB Address input (BYTE mode)

WORD, /BYTE : Mode select

/CE : Chip Enable

/OE or OE : Output Enable

V

CC

: Supply voltage

GND : Ground

Note

NC

: No Connection

DC : Don’t Care

Note Some signals can be applied because this pin is not connected to the inside of the chip.

Remark Refer to Package Drawings for the index mark.

4

Data Sheet M15711EJ2V0DS

µµµµ

PD23C32340, 23C32380

Input / Output Pin Functions

Pin name Input / Output Function

WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.

High level : WORD mode (2M-word by 16-bit)

Low level : BYTE mode (4M-word by 8-bit)

A0 to A20

(Address inputs)

O0 to O7, O8 to O14

(Data outputs)

O15, A−1

(Data output 15,

LSB Address input)

/CE

(Chip Enable)

/OE or OE or DC

(Output Enable, Don't care)

V

CC

GND − Ground

NC − Not internally connected. (The signal can be connected.)

Input Address input pins.

A0 to A20 are used differently in the WORD mode and the BYTE mode.

WORD mode (2M-word by 16-bit)

A0 to A20 are used as 21 bits address signals.

BYTE mode (4M-word by 8-bit)

A0 to A20 are used as the upper 21 bits of total 22 bits of address signal.

(The least significant bit (A−1) is combined to O15.)

Output Data output pins.

O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.

WORD mode (2M-word by 16-bit)

The lower 15 bits of 16 bits data outputs to O0 to O14.

(The most significant bit (O15) combined to A−1.)

BYTE mode (4M-word by 8-bit)

8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.

Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.

WORD mode (2M-word by 16-bit)

The most significant output data bus (O15).

BYTE mode (4M-word by 8-bit)

The least significant address bus (A−1).

Input Chip activating signal.

When the OE is active, output states are following.

High level : High-Z

Low level : Data out

Input Output enable signal. The active level of OE is mask option. The active level of OE

can be selected from high active, low active and Don’t care at order.

− Supply voltage

Data Sheet M15711EJ2V0DS

5

Block Diagram

µµµµ

PD23C32340, 23C32380

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

Y-Decoder

Address Input Buffer

X-Decoder

O0

O8

O10O9

O2

O1

O3 O4

Output Buffer

Y-Selector

Memory Cell Matrix

2,097,152 words by 16 bits /

4,194,304 words by 8 bits

O12O11

O5 O6 O7

O14O13

O15, A−1

Logic/InputInput Buffer

WORD, /BYTE

/OE or OE or DC

/CE

6

Data Sheet M15711EJ2V0DS

µµµµ

PD23C32340, 23C32380

Mask Option

The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected

from among " 0 " " 1 " " x " shown in the table below.

Option /OE or OE or DC OE active level

0/OE L

1OE H

x DC Don’t care

Operation modes for each option are shown in the tables below.

Operation mode (Option : 0)

/CE /OE Mode Output state

L L Active Data out

H High-Z

H H or L Standby High-Z

Operation mode (Option : 1)

/CE OE Mode Output state

L L Active High-Z

H Data out

H H or L Standby High-Z

Operation mode (Option : x)

/CE DC Mode Output state

L H or L Active Data out

H H or L Standby High-Z

Remark L : Low level input

H : High level input

Data Sheet M15711EJ2V0DS

7

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit

µµµµ

PD23C32340, 23C32380

Supply voltage V

Input voltage V

Output voltage V

Operating ambient temperature T

Storage temperature T

CC

I

O

A

stg

–0.3 to +4.6 V

–0.3 to VCC+0.3 V

–0.3 to VCC+0.3 V

–10 to +70 °C

–65 to +150 °C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Capacitance (T

Input capacitance C

Output capacitance C

A

= 25 °C)

Parameter Symbol Test condition MIN. TYP. MAX. Unit

f = 1 MHz 10 pF

I

O

12 pF

DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

High level input voltage V

Low level input voltage V

High level output voltage V

Low level output voltage V

Input leakage current I

Output leakage current I

Power supply current I

Standby current I

IH

IL

= –100 µA2.4V

OHIOH

OLIOL

LI

LO

CC1

CC3

= 2.1 mA 0.4 V

V

= 0 V to V

I

V

= 0 V to VCC, Chip deselected –10 +10

O

/CE = V

I

= 0 mA

O

CC

(Active mode),µPD23C32340 40 mA

IL

PD23C32380 55

µ

/CE = VCC – 0.2 V (Standby mode) 30

2.0 VCC + 0.3 V

–0.3 +0.5 V

–10 +10

A

µ

A

µ

A

µ

8

Data Sheet M15711EJ2V0DS

AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)

Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V VCC = 3.3 V ± 0.3 V Unit

µµµµ

PD23C32340, 23C32380

MIN. TYP. MAX. MIN. TYP. MAX.

Address access time t

Page access time t

Address skew time t

Chip enable access time t

Output enable access time t

Output hold time t

Output disable time t

WORD, /BYTE access time t

indicates the following three types of time depending on the condition.

Note t

SKEW

ACC

PAC

SKEW Note 10 10 ns

CE

OE

OH

DF

WB

1) When switching /CE from high level to low level, t

00ns

0 25 0 25 ns

is the time from the /CE low level input point until the

SKEW

100 90 ns

25 25 ns

100 90 ns

25 25 ns

100 90 ns

next address is determined.

2) When switching /CE from low level to high level, t

is the time from the address change start point to the

SKEW

/CE high level input point.

3) When /CE is fixed to low level, t

is the time from the address change start point until the next address is

SKEW

determined.

Since specs are defined for t

only when /CE is active, t

SKEW

is not subject to limitations when /CE is switched

SKEW

from high level to low level following address determination, or when the address is changed after /CE is switched

from low level to high level.

is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to

Remark t

DF

high impedance state output.

AC Test Conditions

Input waveform (Rise

Output waveform

Output load

1TTL + 100 pF

/

Fall time

≤

≤ 5 ns)

≤≤

Test points1.4 V 1.4 V

Test points1.4 V 1.4 V

Data Sheet M15711EJ2V0DS

9

PD23C32340, 23C32380

µµµµ

Cautions on power application

To ensure normal operation, always apply power using /CE following the procedure shown below.

1) Input a high level to /CE during and after power application.

2) Hold the high level input to /CE for 200 ns or longer (wait time).

3) Start normal operation after the wait time has elapsed.

Power Application Timing Chart 1 (When /CE is made high at power application)

Wait time

/CE (Input)

200 ns or longer

CC

V

Power Application Timing Chart 2 (When /CE is made high after power application)

Wait time

/CE (Input)

200 ns or longer

CC

V

Caution Other signals can be either high or low during the wait time.

Normal operation

Normal operation

10

Data Sheet M15711EJ2V0DS

Read Cycle Timing Chart 1

t

SKEW

µµµµ

PD23C32340, 23C32380

t

t

SKEW

SKEW

A0 to A20,
A−1

/OE or OE

O0 to O7,
O8 to O15

Note1

Note3

/CE

(Input)

(Input)

(Input)

(Input)

t

ACC

t

CE

t

OE

Notes 1. During WORD mode, A–1 is O15.

is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to

DF

2. t

high impedance state output.

3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.

t

ACC

Note2

t

DF

t

OH

Data out Data out Data out

High-ZHigh-Z

t

ACC

t

OH

t

OH

Note2

t

DF

Data Sheet M15711EJ2V0DS

11

Read Cycle Timing Chart 2 (Page Access Mode)

µµµµ

PD23C32340, 23C32380

Upper address

A2 to A20
A3 to A20

Page address

Note 2

A–1
A–1

Note 2

, A0, A1
, A0, A1, A2

O0 to O7,
O8 to O15

Note 1

(Input)

/CE (Input)

/OE or OE (Input)

Note 1

(Input)

(Output)

Note 4

t

ACC

t

CE

tOE

Note 5

t

PAC

High-Z High-Z

Data Out

Note 5

tPAC

OH

t

tOH

Data Out Data Out

tOH

tDF

Note 3

Notes 1. The address differs depending on the product as follows.

Part Number Upper address Page address

PD23C32340 A2 to A20 A–1, A0, A1

µ

PD23C32380 A3 to A20 A–1, A0, A1, A2

µ

2. During WORD mode, A–1 is O15.

is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to

DF

3. t

high impedance state output.

4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.

5. The definition of page access time is as follows.

µµµµ

PD23C32340 ]

[

Page access time Upper address (A2 to A20) /CE input condition /OE or OE input condition

inputs condition

t

PAC

µµµµ

[

PD23C32380 ]

Before t

ACC

– t

PAC

Page access time Upper address (A3 to A20) /CE input condition /OE or OE input condition

inputs condition

Before tCE – t

PAC

Before stabilizing of page

address (A–1, A0, A1)

12

t

PAC

Before t

ACC

– t

PAC

Before tCE – t

PAC

Before stabilizing of page

address (A–1, A0, A1, A2)

Data Sheet M15711EJ2V0DS

WORD, /BYTE Switch Timing Chart

µµµµ

PD23C32340, 23C32380

A–1 (Input)

WORD, /BYTE

O0 to O7 (Output)

O8 to O15 (Output)

(Input)

High-Z

t

OH

Data Out Data Out

t

DF

Data Out Data Out

t

ACC

Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active.

Data Out

High-Z

High-Z

t

OH

t

WB

Data Sheet M15711EJ2V0DS

13

Package Drawings

48-PIN PLASTIC TSOP (I) (12x20)

1

48

µµµµ

PD23C32340, 23C32380

detail of lead end

F

G

R

24

P

I

K

NOTES

Each lead centerline is located within 0.10 mm of

1)
its true position (T.P.) at maximum material condition.

"A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)2)

N

Q

25

L
S

E

J

S

S

D

A

C

B

M

M

ITEM MILLIMETERS

A

12.0±0.1

B

0.45 MAX.

C

0.5 (T.P.)
D 0.22±0.05
E

0.1±0.05

1.2 MAX.

F

1.0±0.05G

I

18.4±0.1
J 0.8±0.2
K

0.145±0.05
L 0.5

0.10M

0.10N
P 20.0±0.2

Q3°

S 0.60±0.15

+5°

−3°

0.25R

S48GZ-50-MJH-1

14

Data Sheet M15711EJ2V0DS

48-PIN TAPE FBGA(8x6)

µµµµ

PD23C32340, 23C32380

E

SwB

ZD ZE

B

A

D

ABCDEFGH

INDEX MARK INDEX MARK

SwA

A

y1 S

A2

S

6
5
4
3
2
1

y

S

φφ

e

A1

M

SxbAB

ITEM MILLIMETERS

D

6.0±0.1

E

8.0±0.1

w

0.2

e

0.80

A

0.97±0.10

A1

0.27±0.05

A2

0.70

b

0.45±0.05

0.08

x

0.1

y

0.2

y1

1.00

ZD

1.20

ZE

P48F9-80-BC3

Data Sheet M15711EJ2V0DS

15

PD23C32340, 23C32380

µµµµ

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the µPD23C32340 and µPD23C32380.

Types of Surface Mount Device

PD23C32340GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

µ

PD23C32340F9-BC3 : 48-pin TAPE FBGA (8 x 6)

µ

PD23C32380GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

µ

PD23C32380F9-BC3 : 48-pin TAPE FBGA (8 x 6)

µ

16

Data Sheet M15711EJ2V0DS

PD23C32340, 23C32380

µµµµ

Revision History

Edition/ Page Type of Location Description

Date This Previous revision (Previous edition → This edition)

edition edition

2nd edition/ Throughout Throughout Modification Preliminary Data Sheet → Data Sheet

Feb. 2003 p.9 p.9 Addition AC Characteristics Address skew time (t

Note

p.10 – Addition Cautions on power application

p.11 p.10 Modification Read Cycle Timing Chart 1

p.15 p.14 Modification Package Drawings Preliminary version → Standard version

SKEW

)

Data Sheet M15711EJ2V0DS

17

[MEMO]

µµµµ

PD23C32340, 23C32380

18

Data Sheet M15711EJ2V0DS

PD23C32340, 23C32380

µµµµ

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS

FOR CMOS

Note:

Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or

IL

NMOS devices. If the input of a CMOS device stays in an area that is between V

IH

(MIN.) due to the effects of noise or some other irregularity, malfunction may result.

V

Therefore, not only the input waveform is fixed, but also the waveform changes, it is important

to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS

devices should not be operated in a state where nothing is connected, so input levels of CMOS

devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin

DD

should be connected to V

being an output pin. All handling related to the unused pins must be judged device by device

and related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

(MAX.) and

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet M15711EJ 2V0DS

19

µµµµ

PD23C32340, 23C32380

These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.

•

The information in this document is current as of February, 2003. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

•

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.

•

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Descriptions of circuits, software and other related information in this document are provided for illustrative

•

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•

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M8E 02. 11-1