MOTOROLA MC100LVE222FA, MC100LVE222FAR2 Datasheet

MC100LVE222

Low V oltage 1:15
Differential÷1/÷2 ECL/PECL
Clock Driver

The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL

fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be differential or used
single–ended (with VBB output reference bypassed and connected to
the unused input of a pair). Either of two fully differential clock inputs
may be selected. Each of the four output banks of 2, 3, 4, and 6
differential pairs may be independently configured to fanout 1X or
1/2X of the input frequency. The LVE222 specifically guarantees low
output to output skew. Optimal design, layout, and processing
minimize skew within a device and from lot to lot.

The fsel pins and CLK_Sel pin are asynchronous control inputs.
Any changes may cause indeterminate output states requiring a MR
pulse to resynchronize any 1/2X outputs.

To ensure that the tight skew specification is realized, both sides of
any differential output pair need to be terminated identically even if
only one side is being used. When fewer than all fifteen pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a side are used, then leave all
these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.

The MC100LVE222, as with most ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the L VE222 to
be used for high performance clock distribution in +3.3V systems.
Designers can take advantage of the LVE222’s performance to
distribute low skew clocks across the backplane or the board. In a
PECL environment series or Thevenin line, terminations are typically
used as they require no additional power supplies. All power supply
pins must be connected. For more information on using PECL,
designers should refer to Application Note AN1406/D. For a SPICE
model, see Application Note AN1560/D.

• 200ps Part–to–Part Skew

• 50ps Output–to–Output Skew

• Selectable 1x or 1/2x Frequency Outputs

• Extended Power Supply Range of –3.0V to –5.25V (+3.0V to

+5.25V)

• 52–Lead TQFP Packaging

• ESD > 2000V

• Moisture Sensitivity Level 2,

For Additional Information, See Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”,

Oxygen Index 28 to 34

• Transistor Count = 684 devices

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TQFP

FA SUFFIX

CASE 848D

MARKING DIAGRAM*

MC100L VE

222

AWLYYWW

32

1

*For additional information, see Application Note
AND8002/D

ORDERING INFORMATION

Device Package Shipping

MC100L VE222FA TQFP 800 Units/Tray

MC100L VE222FAR2 TQFP 1500 Tape & Reel

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

 Semiconductor Components Industries, LLC, 1999

February , 2000 – Rev. 2

1 Publication Order Number:

MC100L VE222/D

VCCO

MC100LVE222

Pinout: 52–Lead TQFP (Top View)

VCCO

Qc0

Qc0

Qc1

Qc1

Qc2

Qc2

Qc3

Qc3

VCCONCNC

39 38 37 36 35 34 33 32 31 30 29 28 27

40

VCCO

26

Qd0
Qb2
Qb2
Qb1
Qb1
Qb0
Qb0

VCCO

Qa1
Qa1
Qa0
Qa0

VCCO

41
42
43
44
45
46
47
48
49
50
51
52

12345678910111213

MR

VCC

fsela

MC100LVE222

fselb

CLK0

CLK0

CLK_Sel

CLK1

CLK1

VBB

fselc

fseld

VEE

25
24
23
22
21
20
19
18
17
16
15
14

Qd0

Qd1

Qd1

Qd2

Qd2

Qd3

Qd3

Qd4

Qd4

Qd5

Qd5

VCCO

MR

CLK0
CLK0
CLK1
CLK1

CLK_Sel

V

BB

fsela

fselb

fselc

fseld

LOGIC SYMBOL

÷1

÷2

2

Qa0:1
Qa0:1

FUNCTION TABLE

3

4

6

Qb0:2
Qb0:2

Qc0:3
Qc0:3

Qd0:5
Qd0:5

Input

MR
CLK_Sel
fseln

Function

01

Active

CLK0

÷1

Reset
CLK1

÷2

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2

MC100LVE222

CLK

RESET

Q

Figure 1. Timing Diagram

MAXIMUM RATINGS*

Symbol Parameter Value Unit

V

EE

V

I

I

out

T

A

* Maximum Ratings are those values beyond which damage to the device may occur.

ECL DC CHARACTERISTICS

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

V
V
V
V
V

V

I

IH

I

IL

I

EE

Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V

OH

Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V

OL

Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V

IH

Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V

IL

Output Reference

BB

Voltage
Power Supply Volt-

EE

age
Input HIGH Current 150 150 150 150 µA
Input CLK0, CLK1

LOW Current Others
Power Supply Cur-

rent

Power Supply (VCC = 0V) –8.0 to 0 VDC
Input Voltage (VCC = 0V) 0 to –6.0 VDC
Output Current Continuous

Surge

50

100

mA

Operating Temperature Range –40 to +85 °C

–40°C 0°C 25°C 70°C

–1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V

–3.0 –5.25 –3.0 –5.25 –3.0 –5.25 –3.0 –5.25 V

–300

0.5
122 136 122 136 122 136 125 139 mA

–300

0.5

–300

0.5

–300

0.5

µA

PECL DC CHARACTERISTICS

–40°C 0°C 25°C 70°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

V
V
V
V
V

V
I

IH

I

IL

I

EE

Output HIGH Voltage1.2.215 2.295 2.420 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 V

OH

Output LOW Voltage1.1.470 1.605 1.745 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 V

OL

Input HIGH Voltage

IH

Input LOW Voltage

IL

Output Reference

BB

CC

1.

Voltage
Power Supply Voltage 3.0 5.25 3.0 5.25 3.0 5.25 3.0 5.25 V
Input HIGH Current 150 150 150 150 µA
Input CLK0, CLK1

LOW Current Others
Power Supply Current 122 136 122 136 122 136 125 139 mA

1.

2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V

1.

1.490 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V

1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V

–300

0.5

–300

0.5

–300

0.5

–300

0.5

1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.

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3

µA