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LA-5972P NAWA2
Schematic
50 pgs1.63 Mb0

Compal LA-5972P NAWA2, 3000 G555 Schematic

5 (1)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Cover Page
B
1 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Cover Page
B
1 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Cover Page
B
1 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
AMD Tigris: Caspian Processor with RS880M/SB710/Park-S3 & M93-S3
NAWA2 Schematics Document
Compal Confidential
2009-11-26
ZZZ3
LA5972P
DAZ@
ZZZ3
LA5972P
DAZ@
ZZZ4
LS5971P
DAZ@
ZZZ4
LS5971P
DAZ@
ZZZ1
LA5972P_LS5971P_LS5083P
ZZZ1
LA5972P_LS5971P_LS5083P
ZZZ5
LS5083P
DAZ@
ZZZ5
LS5083P
DAZ@
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Block Diagrams
B
2 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Block Diagrams
B
2 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Block Diagrams
B
2 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Touch Pad
CRT
LPC BUS
page 36
Compal Confidential
uFCBGA-528
page 22
Int.KBD
page 34
USB
conn
X 2
A link Express2
DC/DC Interface.
AMD S1G3 Processor
3.3V 48MHz
Hyper Transport Link
16 x 16
page 33
Fan Control
Power Circuit
uPGA-638 Package
page 38
ATI RS880M
BIOS
page 4,5,6,7
page 34
HD Aud io
page 37
page 10,11,12,13
ATI SB710
page 23,24,25,26,27
page 34
ENE KB926
LCD (LED BL)
Bluetooth
Conn
3.3V 24.576MHz/48M hz
Model Name : NAWA1
page 21
page 36
page 39,40,41,42,43,
44,45,46,47,48
S-ATA
page 28
SATA HDD
Conn.
port 0
CMOS
Camera
USB port 0,1
USB
CDROM
Conn.
page 28
Mini
card
(WL)X1
PCI-Express 1x
port 1
USB port 7 USB port 8 USB port 3 USB port 5
page 32 page 32 page 31 page 32 page 31
page 30
MINI Card x1
WL AN
page 31
port 3port 2
RJ45
page 30
Dual Channel
BANK 0, 1, 2, 3
200pin DDRII-SO-DIMM X2
1.8V DDRII 667 (800)
Memory BUS(DDRII)
page 8,9
Clock Generator
SLG8SP626VTR
page 6 page 20
Thermal Sensor
ADM1032
AR8131/AR8132
LAN(10/100)/1000
ATI PARK-S3 & M93-S3
VRAM 512MB
64M16 x 4
PCI-Express 16x
DDR3 800MHz
page 19
Page 14,15,16,17,18
uFCBGA-528
uFCBGA-631
HDA Codec
CX20671
Phone Jack x2
MIC
page 36
Gen2
5 in 1 socket
page 29
page 29
Card Reader
RTS5138
USB port 2
Caspian
Tigris
USB
conn
X 1
WINBOND
Power Board
page 35
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Notes List
B
3 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Notes List
B
3 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
Notes List
B
3 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
BTO Option Table
BTO Item BOM Structure
Discrete
PARK PARK@
VGA@
1101 001Xb
OF F OFF
+0.9V 0.9V switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS 1.8V switched power rail
+2.5VS
+5 VS
+3 VS
+5 VA LW
+1.8V
2.5V for CPU_VDDA
+3 VA LW
1.8V power rail for CPU VDDIO and DDR
3.3V always on power rail
5V always on power rail
3.3V switched power rail
5V switched power rail
+VSB VSB always on power rail ON ON *
ONON
ON
ON
EC SM Bus1 address
Device
SB710
SM Bus 1 address
ON
OF F
OF F
DDR DIMM1
1001 000Xb
DDR DIMM2
1001 010Xb
1.5V power rail for PCIE Card
+CPU_CORE_0
SB710
SM Bus 0 address
Device
Clock Generator
(SILEGO SLG8SP626)
Address
Address Address
Voltage Rails
VIN
B+
+1.1VS
Adapter power s upply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
External PCI Devices
Device IDSEL#
REQ#/GNT#
Interrupts
ON
+VGA_CORE OFFOFFON
1.1V switched power rail for NB VDDC & VGA
ON
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V)
ON OFF OFF
+CPU_CORE_NB Volta ge for On-die Northbridge of CPU(0.8-1.1V ) ON OFF OFF
ADI ADM1032 (CPU)
+1.2V_HT 1.2V switched power rail ON OFF OFF
ON ON*
ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON ON
S1 S3 S5
ON OFF
ON
N/A N/A N/A
N/AN/AN/A
Power Plane Description
EC SM Bus2 address
Device
Smart Batter y
OFF
OFF
ON
OFF
OFF
OFF
ON
Note : ON* means that this po wer plane is ON only with AC power available, otherwise it is OFF .
OFFON
ON
ON
ON
OFF
ON*
OFF
OFF
ON
New card
Device Address
ON
1001 100X b0001 011X b
0.95-1.2V switched power rail
HEX
98H
9AH
GMT G781-1 (GP U)
1001 101X b
16H
HEX
D2
HEX
90
94
Mini c ard
M93 M93@
HDT debug HDT@
9CH
SB-Temp Sensor
NAWA1_UMA : UMA@/WLAN@/BT@/CMOS@/NEW CARD@
NAWA1_DIS : VGA@/M93@/WLAN@/BT@/NEW CARD@/CMOS@/X76@
UMA UMA@
Wireless LAN WLAN@
Blue Tooth BT@
Camera CMOS@
New Card New Card@
VRAM X76@
+3VS_VGA
+VGA_CPRE
+1.1VS_VGA
+1.8VS_VGA
PARK-S3 power on sequence
RS880M power on sequence
+3VS
(AVDD, VDD33)
+1.8VS
+1.1VS PLL Rails
(PLLVDD, IOPLLVDD)
+NB_CORE
UNPON @
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN1
H_CADIN0
H_CADIP3
H_CADIN2
H_CADIP2
H_CADIP1
H_CADIN3
H_CADIP4
H_CADIN5
H_CADIN4
H_CADIP5
H_CADIN6
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP6
H_CADIP7
H_CADIP10
H_CADIN10
H_CADIN11
H_CADIP11
H_CADIP9
H_CADIN13
H_CADIN12
H_CADIP14
H_CADIP12
H_CADIN14
H_CADIP0
H_CADIN15
H_CADIP15
H_CADIP13
H_CADON15
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
H_CADON[0..15] (10)H_CADIN[0..15](10)
H_CADOP[0..15] (10)
H_CLKIN0(10)
H_CLKIN1(10)
H_CLKIP1(10)
H_CTLIN1(10)
H_CLKIP0(10)
H_CTLIP1(10) H_CTLOP1 (10)
H_CLKOP1 (10)
H_CADIP[0..15](10)
H_CLKOP0 (10)
H_CLKON0 (10)
H_CLKON1 (10)
H_CTLON1 (10)
H_CTLOP0 (10)
H_CTLON0 (10)H_CTLIN0(10)
H_CTLIP0(10)
+1.2V_HT
+1.2V_HT
+1.2V_HT
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 HT I/F
Custom
4 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 HT I/F
Custom
4 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 HT I/F
Custom
4 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
250 mil
Near CPU Socket
VLDT CAP.
VLDT=1.5A
C726C726
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C727
10U_0805_6.3V4Z
C727
10U_0805_6.3V4Z
1
2
C666
10U_0805_6.3V4Z
C666
10U_0805_6.3V4Z
1
2
C755
10U_0805_6.3V4Z
C755
10U_0805_6.3V4Z
1
2
C722
180P_0402_50V8J
C722
180P_0402_50V8J
1
2
C668
180P_0402_50V8J
C668
180P_0402_50V8J
1
2
C725C725
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C664 10U_0805_6.3V4ZC664 10U_0805_6.3V4Z
1 2
HT LINK
JCPU1A
6090022100G_B
ME@
HT LINK
JCPU1A
6090022100G_B
ME@
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A0
VLDT_A1
D1
VLDT_B3
VLDT_B2
AE5
AE4
VLDT_B1
AE3
VLDT_B0
AE2
N5
L0_CADIN_L15
L0_CADIN_H15
P5
M3
L0_CADIN_L14
L0_CADIN_H14
M4
L5
L0_CADIN_L13
L0_CADIN_H13
M5
K3
L0_CADIN_L12
L0_CADIN_H12
K4
H3
L0_CADIN_L11
L0_CADIN_H11
H4
G5
L0_CADIN_L10
L0_CADIN_H10
H5
F3
L0_CADIN_L9
L0_CADIN_H9
F4
E5
L0_CADIN_L8
L0_CADIN_H8
F5
N3
L0_CADIN_L7
L0_CADIN_H7
N2
L1
L0_CADIN_L6
L0_CADIN_H6
M1
L3
L0_CADIN_L5
L0_CADIN_H5
L2
J1
L0_CADIN_L4
L0_CADIN_H4
K1
G1
L0_CADIN_L3
L0_CADIN_H3
H1
G3
L0_CADIN_L2
L0_CADIN_H2
G2
E1
L0_CADIN_L1
L0_CADIN_H1
F1
E3
L0_CADIN_L0
L0_CADIN_H0
E2
L0_CADOUT_H15
T4
L0_CADOUT_L15
T3
L0_CADOUT_H14
V5
L0_CADOUT_L14
U5
L0_CADOUT_H13
V4
L0_CADOUT_L13
V3
L0_CADOUT_H12
Y5
L0_CADOUT_L12
W5
L0_CADOUT_H11
AB5
L0_CADOUT_L11
AA5
L0_CADOUT_H10
AB4
L0_CADOUT_L10
AB3
L0_CADOUT_H9
AD5
L0_CADOUT_L9
AC5
L0_CADOUT_H8
AD4
L0_CADOUT_L8
AD3
L0_CADOUT_H7
T1
L0_CADOUT_L7
R1
L0_CADOUT_H6
U2
L0_CADOUT_L6
U3
L0_CADOUT_H5
V1
L0_CADOUT_L5
U1
L0_CADOUT_H4
W2
L0_CADOUT_L4
W3
L0_CADOUT_H3
AA2
L0_CADOUT_L3
AA3
L0_CADOUT_H2
AB1
L0_CADOUT_L2
AA1
L0_CADOUT_H1
AC2
L0_CADOUT_L1
AC3
L0_CADOUT_H0
AD1
L0_CADOUT_L0
AC1
J5
L0_CLKIN_L1
L0_CLKIN_H1
K5
J3
L0_CLKIN_L0
L0_CLKIN_H0
J2
P3
L0_CTLIN_L1
L0_CTLIN_H1
P4
N1
L0_CTLIN_L0
L0_CTLIN_H0
P1
L0_CLKOUT_H1
Y4
L0_CLKOUT_L1
Y3
L0_CLKOUT_H0
Y1
L0_CLKOUT_L0
W1
L0_CTLOUT_H1
T5
L0_CTLOUT_L1
R5
L0_CTLOUT_H0
R2
L0_CTLOUT_L0
R3
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SMA10
DDRB_SMA7
DDRB_SMA1
DDRB_SMA12
DDRB_SMA6
DDRB_SMA11
DDRB_SMA0
DDRB_SMA9
DDRB_SMA15
DDRB_SMA3
DDRB_SMA5
DDRB_SMA8
DDRB_SMA13
DDRB_SMA2
DDRB_SMA4
DDRB_CKE1
DDRB_SDQ0
DDRB_CKE0
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQS3
DDRB_SDQS3#
DDRA_CLK1
DDRA_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SDQS7
DDRA_CLK0
DDRA_CLK0#
+MCH_REF
DDRB_ODT0
DDRB_ODT1
DDRA_ODT1
DDRA_ODT0
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#DDRA_CLK1#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CKE0
DDRA_CKE1
DDRB_SDM6
DDRB_SDM4
DDRB_SDM2
DDRB_SDM0
DDRB_SDM5
DDRB_SDM3
DDRB_SDM1
DDRB_SDM7
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SWE#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SBS2#
DDRA_SBS1#
DDRA_SBS0#
DDRA_SMA15
DDRA_SMA12
DDRA_SMA14
DDRA_SMA13
DDRA_SMA11
DDRA_SMA10
DDRA_SMA6
DDRA_SMA1
DDRA_SMA7
DDRA_SMA2
DDRA_SMA3
DDRA_SMA8
DDRA_SMA4
DDRA_SMA5
DDRA_SMA9
DDRA_SMA0
DDRB_SMA14
DDRA_SCS1# DDRB_SCS0#
DDRB_SCS1#
DDRA_SCS0#
+MCH_REF
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
VTT_SENSE
DDRB_CKE1 (9)
DDRB_CKE0 (9)
DDRA_SCS0#(8)
DDRA_SCS1#(8) DDRB_SCS0# (9)
DDRB_SCS1# (9)
DDRB_SDQ[63..0](9)
DDRB_SDM[7..0](9) DDRA_SDM[7..0] ( 8)
DDRA_SDQ[63..0] (8)
DDRB_SDQS7(9)
DDRB_SDQS7#(9)
DDRB_SDQS6(9)
DDRB_SDQS5(9)
DDRB_SDQS4(9)
DDRB_SDQS3(9)
DDRB_SDQS2(9)
DDRB_SDQS1(9)
DDRB_SDQS0(9)
DDRB_SDQS6#(9)
DDRB_SDQS5#(9)
DDRB_SDQS4#(9)
DDRB_SDQS3#(9)
DDRB_SDQS2#(9)
DDRB_SDQS1#(9)
DDRB_SDQS0#(9)
DDRA_SDQS3 (8)
DDRA_SDQS2 (8)
DDRA_SDQS1 (8)
DDRA_SDQS0 (8)
DDRA_SDQS3# (8)
DDRA_SDQS2# (8)
DDRA_SDQS1# (8)
DDRA_SDQS0# (8)
DDRA_SDQS4 (8)
DDRA_SDQS4# (8)
DDRA_SDQS5 (8)
DDRA_SDQS5# (8)
DDRA_SDQS6 (8)
DDRA_SDQS6# (8)
DDRA_SDQS7 (8)
DDRA_SDQS7# (8)
DDRB_SRAS# (9)
DDRB_SCAS# (9)
DDRB_SWE# (9)
DDRB_SBS0# (9)
DDRB_SBS1# (9)
DDRB_SBS2# (9)
DDRA_SRAS#(8 )
DDRA_SCAS#(8 )
DDRA_SWE#(8 )
DDRA_SBS0#(8 )
DDRA_SBS1#(8 )
DDRA_SBS2#(8 )
DDRA_SMA[15..0](8) DDRB_SMA[15..0] (9)
DDRB_ODT0 ( 9)
DDRB_ODT1 ( 9)
DDRA_ODT0(8 )
DDRA_ODT1(8 )
DDRB_CLK0 (9)
DDRB_CLK0# (9)
DDRB_CLK1 (9)
DDRB_CLK1# (9)
DDRA_CLK0(8)
DDRA_CLK0#( 8)
DDRA_CLK1(8)
DDRA_CLK1#( 8)
DDRA_CKE0( 8)
DDRA_CKE1( 8)
+1.8V
+0.9V+0.9V
+1.8V
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 DDRII I/F
Custom
5 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 DDRII I/F
Custom
5 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 DDRII I/F
Custom
5 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
Place them close to CPU within 1"
Processor DDR2 Memory Interface
VTT=0.75A
R79
1K_0402_1%
R79
1K_0402_1%
1 2
MEM:DATA
JCPU1C
6090022100G_B
ME@
MEM:DATA
JCPU1C
6090022100G_B
ME@
AD11
MB_DATA63
AF11
MB_DATA62
AF14
MB_DATA61
AE14
MB_DATA60
Y1 1
MB_DATA59
AB11
MB_DATA58
AC12
MB_DATA57
AF13
MB_DATA56
AF15
MB_DATA55
AF16
MB_DATA54
AC18
MB_DATA53
AF19
MB_DATA52
AD14
MB_DATA51
AC14
MB_DATA50
AE18
MB_DATA49
AD18
MB_DATA48
AD20
MB_DATA47
AC20
MB_DATA46
AF23
MB_DATA45
AF24
MB_DATA44
AF20
MB_DATA43
AE20
MB_DATA42
AD22
MB_DATA41
AC22
MB_DATA40
AE25
MB_DATA39
AD26
MB_DATA38
AA25
MB_DATA37
AA26
MB_DATA36
AE24
MB_DATA35
AD24
MB_DATA34
AA23
MB_DATA33
AA24
MB_DATA32
G24
MB_DATA31
G23
MB_DATA30
D26
MB_DATA29
C26
MB_DATA28
G26
MB_DATA27
G25
MB_DATA26
E24
MB_DATA25
E23
MB_DATA24
C24
MB_DATA23
B24
MB_DATA22
C20
MB_DATA21
B20
MB_DATA20
C25
MB_DATA19
D24
MB_DATA18
A21
MB_DATA17
D20
MB_DATA16
D18
MB_DATA15
C18
MB_DATA14
D14
MB_DATA13
C14
MB_DATA12
A20
MB_DATA11
A19
MB_DATA10
A16
MB_DATA9
A15
MB_DATA8
A13
MB_DATA7
D12
MB_DATA6
E11
MB_DATA5
G11
MB_DATA4
B14
MB_DATA3
A14
MB_DATA2
A11
MB_DATA0
MB_DATA1
C11
MA_DATA63
MA_DATA62
AA12
MA_DATA61
AB12
MA_DATA60
AA14
MA_DATA59
AB14
MA_DATA58
W11
MA_DATA57
Y1 2
MA_DATA56
AD13
MA_DATA55
AB13
MA_DATA54
AD15
MA_DATA53
AB15
MA_DATA52
AB17
MA_DATA51
Y1 7
MA_DATA50
Y1 4
MA_DATA49
W14
MA_DATA48
W16
MA_DATA47
AD17
MA_DATA46
Y1 8
MA_DATA45
AD19
MA_DATA44
AD21
MA_DATA43
AB21
MA_DATA42
AB18
MA_DATA41
AA18
MA_DATA40
AA20
Y2 0
MA_DATA39
MA_DATA38
AA22
MA_DATA37
Y2 2
MA_DATA36
W21
MA_DATA35
W22
AA21
MA_DATA34
AB22
MA_DATA33
AB24
MA_DATA32
Y2 4
MA_DATA31
H22
MA_DATA30
H20
MA_DATA29
MA_DATA28
E22
MA_DATA27
E21
J19
MA_DATA26
H24
MA_DATA25
F22
MA_DATA24
F20
MA_DATA23
C23
MA_DATA22
B22
MA_DATA21
F18
MA_DATA20
E18
MA_DATA19
E20
MA_DATA18
D22
MA_DATA17
C19
MA_DATA16
G18
MA_DATA15
G17
MA_DATA14
C17
MA_DATA13
F14
MA_DATA12
E14
MA_DATA11
MA_DATA10
H17
MA_DATA9
E17
MA_DATA8
E15
MA_DATA7
H15
MA_DATA6
E13
MA_DATA5
C13
H12
MA_DATA4
H11
MA_DATA3
G14
MA_DATA2
H14
MA_DATA1
F12
MA_DATA0
G12
AD12
MB_DM7
AC16
MB_DM6
AE22
MB_DM5
AB26
MB_DM4
E25
MB_DM3
A22
MB_DM2
B16
MB_DM0
MB_DM1
A12
AF12
MB_DQS_L7
MB_DQS_H7
AE12
AE16
MB_DQS_L6
MB_DQS_H6
AD16
AF21
MB_DQS_L5
MB_DQS_H5
AF22
AC25
MB_DQS_L4
MB_DQS_H4
AC26
F26
MB_DQS_L3
MB_DQS_H3
E26
A24
MB_DQS_L2
MB_DQS_H2
A23
D16
MB_DQS_L1
MB_DQS_H1
C16
C12
MB_DQS_L0
MB_DQS_H0
B12
MA_DM7
MA_DM6
Y1 3
MA_DM5
AB16
MA_DM4
Y1 9
MA_DM3
AC24
MA_DM2
F24
MA_DM1
E19
MA_DM0
C15
E12
MA_DQS_H7
W12
MA_DQS_L7
W13
MA_DQS_H6
Y1 5
MA_DQS_L6
W15
MA_DQS_H5
AB19
MA_DQS_L5
AB20
MA_DQS_H4
AD23
MA_DQS_L4
AC23
MA_DQS_H3
G22
MA_DQS_L3
G21
MA_DQS_H2
C22
MA_DQS_L2
C21
MA_DQS_H1
G16
MA_DQS_L1
G15
MA_DQS_H0
G13
MA_DQS_L0
H13
C890C890
1.5P_0402_50V9C1.5P_0402_50V9C
1
2
C177C177
1000P_0402_25V8J1000P_0402_25V8J
1
2
C889C889
1.5P_0402_50V9C1.5P_0402_50V9C
1
2
R77 39.2_0402_1%R77 39.2_0402_1%
1 2
T4PAD T4PAD
MEM:CMD/CTRL/CLK
JCPU1B
6090022100G_B
ME@
MEM:CMD/CTRL/CLK
JCPU1B
6090022100G_B
ME@
D10
VTT1
C10
VTT2
B10
VTT4
VTT3
AD10
VTT5
W10
VTT6
AC10
VTT7
AB10
VTT8
AA10
VTT9
A10
V19
MA1_ODT1
U21
MA1_ODT0
V22
MA0_ODT0
MA0_ODT1
T19
MB1_ODT0
MB0_ODT1
Y2 6
MB0_ODT0
W23
W26
RSVD_M2
B18
MB1_CS_L0
MB0_CS_L1
U22
MB0_CS_L0
W25
V26
MA0_CS_L1
U19
V20
MA1_CS_L0
MA1_CS_L1
U20
MA0_CS_L0
T20
K19
MA_ADD15
K24
MA_ADD14
V24
MA_ADD13
K20
MA_ADD12
L22
MA_ADD11
R21
MA_ADD10
K22
MA_ADD9
L19
MA_ADD8
L21
MA_ADD7
M24
MA_ADD6
L20
MA_ADD5
M22
MA_ADD4
M19
MA_ADD3
N22
MA_ADD2
M20
MA_ADD0
MA_ADD1
N21
J21
MA_BANK2
R23
MA_BANK0
MA_BANK1
R20
R19
MA_RAS_L
T22
MA_WE_L
MA_CAS_L
T24
AF10
MEMZN
MEMZP
AE10
VTT_SENSE
Y1 0
MEMVREF
W17
P19
MA_CLK_L3
MA_CLK_H3
P20
Y1 6
MA_CLK_L2
MA_CLK_H2
AA16
E16
MA_CLK_L1
MA_CLK_H1
F16
N19
MA_CLK_L0
MA_CLK_H0
N20
MB_CLK_H3
R26
MB_CLK_L3
R25
MB_CLK_H2
AF18
MB_CLK_L2
AF17
MB_CLK_H1
A17
MB_CLK_L1
A18
MB_CLK_H0
P22
MB_CLK_L0
R22
J22
MA_CKE1
MA_CKE0
J20
MB_CKE0
J25
MB_CKE1
H26
MB_ADD15
MB_ADD14
J24
MB_ADD13
J23
MB_ADD12
W24
MB_ADD11
L25
MB_ADD10
L26
MB_ADD9
T26
MB_ADD8
K26
MB_ADD7
M26
MB_ADD6
L24
MB_ADD5
N25
MB_ADD4
L23
MB_ADD3
N26
MB_ADD2
N23
MB_ADD1
P26
MB_ADD0
N24
P24
MB_BANK2
MB_BANK1
J26
MB_BANK0
U26
R24
MB_RAS_L
U25
MB_CAS_L
U24
MB_WE_L
U23
RSVD_M1
H16
R78
1K_0402_1%
R78
1K_0402_1%
1 2
R76 39.2_0402_1%R76 39.2_0402_1%
1 2
C888C888
1.5P_0402_50V9C1.5P_0402_50V9C
1
2
C178C178
0.1U_0402_16V4Z0.1U_0402_16V4Z
1
2
C891C891
1.5P_0402_50V9C1.5P_0402_50V9C
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_TDO
CPU_HTREF0
CPU_HTREF1
CPU_DBRDY
CPU_TMS
CPU_TEST19
CPU_CLKIN_SC_P
CPU_THERMTRIP#_R
LDT_RST#
H_PWRGD
LDT_STOP#
LDT_STOP#
CPU_SID
CPU_SIC
CPU_CLKIN_SC_N
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_DBREQ#
CPU_TDO
CPU_SVC
CPU_SVD
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST17
CPU_TEST16
CPU_TEST14
CPU_TEST15
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST28_H_PLLCHRZ_P
LDT_RST#
H_PWRGD
LDT_RST#
CPU_TEST23
CPU_SVC
CPU_SVD
CPU_TEST27
H_PROCHOT#
THERMDA_CPU
THERMDC_CPU
EC_SMB_CK2
EC_SMB_DA2
CPU_THERMTRIP#_R
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CPU_VDD1_FB_H
CPU_VDD1_FB_L
CPU_TEST18
HDT_RST#
CPU_TEST12
CPU_TEST25H
CPU_TEST25L
CPU_TEST6
CPU_TEST7
CPU_TEST10
CPU_TEST8
CPU_TEST21
CPU_TEST24
CPU_TRST#
CPU_TDI
CPU_TMS
CPU_TCK
CPU_DBRDY
THERMDA_CPU
THERMDC_CPU
H_PROCHOT#
CPU_TEST20
CPU_TEST23
CPU_TEST25H
CPU_TEST25L
CPU_TEST25L
CPU_TEST25H
CPU_DBREQ#
CPU_TEST10
CPU_TEST18
CPU_TEST19
CPU_TEST22
H_PWRGD(23)
LDT_STOP#(11,23)
LDT_RST#(23)
SB_PWRGD (11,24,33)
CPU_VDDNB_FB_H (47)
CPU_VDDNB_FB_L (47)
CPU_VDD0_FB_H(47)
CPU_VDD0_FB_L(47)
CPU_VDD1_FB_H(47)
CPU_VDD1_FB_L(47)
CLK_CPU_BCLK(20)
CLK_CPU_BCLK#(20)
EC_SMB_DA2 (33)
EC_SMB_CK2 (33)
CPU_SVD (47)
CPU_SVC (47)
H_PROCHOT_R# (23,33)
H_THERMTRIP# (24)
VDDIO (43)
+1.8V
+1.2V_HT
+2.5VDDA
+2.5VS
+3VS
+1.8V
+1.8VS
+1.8VS
+1.8VS
+3VS
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 CTRL
Custom
6 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 CTRL
Custom
6 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 CTRL
Custom
6 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
VDDA=0.25A
Address
1001 100X b
MP(Remove)
MP(Remove)
MP(mask)
close to L35
C9414.7U_0805_10V4Z C9414.7U_0805_10V4Z
1
2
E
B
C
Q9
MMBT3904_NL_SOT23-3
E
B
C
Q9
MMBT3904_NL_SOT23-3
2
3 1
R950 0_0603_5%@R950 0_0603_5%@
1 2
C724 3900P _0402_50V7KC724 3900P _0402_50V7K
1 2
C880C880
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
R455
169_0402_1%
R455
169_0402_1%
12
T24PAD T24PAD
R456 1K_0402_5%R456 1K_0402_5%
1 2
R555300_0402_5%R555300_0402_5%
1 2
+
C918
150U_B2_6.3VM_R35M
+
C918
150U_B2_6.3VM_R35M
1
2
U15
NC7SZ08P5X_NL_SC70-5
@
U15
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1
Y
4
P
5
G
3
R75 300_0402_5%R75 300_0402_5%
1 2
R952 0_0603_5%@R952 0_0603_5%@
1 2
R73 300_0402_5%R73 300_0402_5%
1 2
R135 510_0402_5%
@
R135 510_0402_5%
@
1 2
T3 PADT3 PAD
R140
0_0402_5%@
R140
0_0402_5%@
1 2
C719
0.01U_0402_16V7K
@
C719
0.01U_0402_16V7K
@
1
2
T36PAD T36PAD
T38PAD T38PAD
T21PAD T21PAD
R66 10K_0402_5%R66 10K_0402_5%
1 2
T44 PADT44 PAD
T5PAD T5PAD
R118220_0402_5%
@
R118220_0402_5%
@
12
T34PAD T34PAD
T25 PADT25 PAD
R82 44.2_0402_1%R82 44.2_0402_1%
1 2
R68
0_0402_5%
R68
0_0402_5%
1 2
T39PAD T39PAD
T67PAD T67PAD
R89 44.2_0402_1%R89 44.2_0402_1%
1 2
R549 1K_0402_5%R549 1K_0402_5%
1 2
C721
0.01U_0402_16V7K
@
C721
0.01U_0402_16V7K
@
1
2
C720
0.01U_0402_16V7K
@
C720
0.01U_0402_16V7K
@
1
2
R558
300_0402_5%
R558
300_0402_5%
1 2
T33 PADT33 PAD
R557
300_0402_5%
R557
300_0402_5%
1 2
R120300_0402_5%
@
R120300_0402_5%
@
12
R101 0_0603_5%@R101 0_0603_5%@
1 2
C938
3300P_0402_50V7K
C938
3300P_0402_50V7K
1
2
R144 510_0402_5%
@
R144 510_0402_5%
@
1 2
T31PAD T31PAD
SAMTEC_ASP-68200-07
JP1
@ SAMTEC_ASP-68200-07
JP1
@
2
4
6
8
10
12
14
16
18
20
22
2423
21
19
17
15
13
11
9
7
5
3
1
26
R67 300_0402_5%R67 300_0402_5%
1 2
R72 300_0402_5%R72 300_0402_5%
1 2
R70 390_0402_5%R70
1
390_0402_5%
2
R136 510_0402_5%R136 510_0402_5%
1 2
C296
180P_0402_50V8J
C296
180P_0402_50V8J
1
2
R74 300_0402_5%R74 300_0402_5%
1 2
JCPU1D
6090022100G_B
ME@
JCPU1D
6090022100G_B
ME@
F8
VDDA2
VDDA1
F9
B7
RESET_L
A7
LDTSTOP_L
PWROK
F10
AF4
SID
SIC
AF5
P6
HT_REF0
HT_REF1
R6
F6
VDD0_FB_L
VDD0_FB_H
E6
VDDIO_FB_H
W9
VDDIO_FB_L
Y9
THERMTRIP_L
AF6
PROCHOT_L
AC7
RSVD2
A5
LDTREQ_L
C6
SVC
A6
SVD
A4
RSVD6
C5
RSVD4
B5
RSVD1
A3
A9
CLKIN_L
CLKIN_H
A8
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TDI
TRST_L
AF9
DBREQ_L
E10
TDO
AE9
E9
TEST25_L
TEST25_H
E8
G9
TEST18
TEST19
H10
RSVD8
AA7
TEST9
C2
TEST17
D7
TEST16
E7
TEST15
F7
TEST14
C7
TEST12
AC8
TEST7
C3
TEST6
AA6
THERMDC
W7
THERMDA
W8
Y6
VDD1_FB_L
VDD1_FB_H
AB6
TEST29_H
C9
TEST29_L
C8
TEST24
AE7
TEST23
AD7
TEST22
AE8
AB8
TEST20
TEST21
AF7
TEST28_H
J7
TEST28_L
H8
TEST27
AF8
ALERT_L
AE6
TEST10
K8
TEST8
C4
RSVD3
B3
RSVD5
C1
VDDNB_FB_H
H6
VDDNB_FB_L
G6
RSVD7
D5
KEY2
W18
MEMHOT_L
AA8
RSVD10
H18
RSVD9
H19
KEY1
M11
T35PAD T35PAD
T37 PADT37 PAD
R117220_0402_5%
@
R117220_0402_5%
@
12
R65
0_0402_5%
R65
0_0402_5%
1 2
R951 0_0603_5%@R951 0_0603_5%@
1 2
T2 PADT2 PAD
T26 PADT26 PAD
T41 PADT41 PAD
C206
0.1U_0402_16V4Z
C206
0.1U_0402_16V4Z
1
2
C194
3300P_0402_50V7K
<BOM Structure>
C194
3300P_0402_50V7K
<BOM Structure>
1 2
R71 390_0402_5%@R71 390_0402_5%@
12
R227 0_0402_5%R227 0_0402_5%
1 2
T18PAD T18PAD
L63
MBK1608221YZF_0603
L63
MBK1608221YZF_0603
1 2
T42 PADT42 PAD
U10
ADM1032ARMZ_MSOP8
U10
ADM1032ARMZ_MSOP8
VDD
1
ALERT#
6
THERM#
4
GND
5
D+
2
D-
3
SCLK
8
SDATA
7
T43 PADT43 PAD
T32PAD T32PAD
R143 510_0402_5%R143 510_0402_5%
1 2
R69 300_0402_5%R69 300_0402_5%
1 2
C723
3900P_0402_50V7K
C723
3900P_0402_50V7K
1 2
R556
300_0402_5%
R556
300_0402_5%
1 2
R119220_0402_5%
@
R119220_0402_5%
@
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+CPU_CORE_0
+0.9V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+1.8V
+1.8V
+1.8V
+1.8V +1.8V
+0.9V
+0.9V
+CPU_CORE_NB
+1.8V
+1.8V
+CPU_CORE_1
+CPU_CORE_1
+CPU_CORE_1
+CPU_CORE_1
+CPU_CORE_NB
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 PWR & GND
Custom
7 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 PWR & GND
Custom
7 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
AMD CPU S1G3 PWR & GND
Custom
7 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Between CPU Socket and DIMM
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
Under CPU Socket
Athlon 64 S1
Processor Soc ket
Near CPU Socket
VTT decoupling.
VDD(+CPU_CORE) decoupling.
VDDIO decoupling.
+CPU_CORE_NB decoupling.
C: Change to NPO CAP
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
Athlon 64 S1
Processor Soc ket
VDD0 = 18A VDD1 =18A
VDDNB=3A
VDDIO=3A
VDDNB=4A
(For Tigris)
C883C883
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C920
180P_0402_50V8J
C920
180P_0402_50V8J
1
2
C230
180P_0402_50V8J
C230
180P_0402_50V8J
1
2
C715
180P_0402_50V8J
C715
180P_0402_50V8J
1
2
C944C944
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
JCPU1F
6090022100G_B
ME@
JCPU1F
6090022100G_B
ME@
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS65
VSS64
J4
VSS66
J6
VSS67
J8
VSS68
J10
VSS69
J12
VSS70
J14
VSS71
J16
VSS72
J18
VSS73
K2
VSS74
K7
VSS75
K9
VSS76
K11
VSS77
K13
VSS78
K15
VSS79
K17
VSS80
L6
VSS81
L8
VSS82
L10
VSS83
L12
VSS84
L14
VSS85
L16
VSS86
L18
VSS87
M7
VSS88
M9
VSS89
AC6
VSS90
M17
VSS91
N4
VSS92
N8
VSS93
N10
VSS94
N16
VSS95
N18
VSS96
P2
VSS97
P7
VSS98
P9
VSS99
P11
VSS100
P17
VSS101
R8
VSS102
R10
VSS103
R16
VSS104
R18
VSS105
T7
VSS106
T9
VSS107
T11
VSS108
T13
VSS109
T15
VSS110
T17
VSS111
U4
VSS112
U6
VSS113
U8
VSS114
U10
VSS115
U12
VSS116
U14
VSS117
U16
VSS118
U18
VSS119
V2
VSS120
V7
VSS121
V9
VSS122
V11
VSS123
V13
VSS124
V15
VSS125
V17
VSS126
W6
VSS127
Y2 1
VSS128
Y2 3
VSS129
N6
C943C943
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
C945C945
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
C887C887
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C208C208
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
C215
22U_0805_6.3V6M
C215
22U_0805_6.3V6M
1
2
C207
22U_0805_6.3V6M
C207
22U_0805_6.3V6M
1
2
JCPU1E
6090022100G_B
ME@
JCPU1E
6090022100G_B
ME@
VDD1_25
AC4
VDD1_26
AD2
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_5
VDD0_4
J13
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_15
VDD0_14
L13
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_23
VDD0_22
N11
VDD1_1
P8
VDD1_2
P10
VDD1_3
R4
VDD1_4
R7
VDD1_5
R9
VDD1_6
R11
VDD1_7
T2
VDD1_8
T6
VDD1_9
T8
VDD1_10
T10
VDD1_11
T12
VDD1_12
T14
VDD1_13
U7
VDD1_14
U9
VDD1_15
U11
VDD1_16
U13
VDD1_18
V6
VDD1_19
V8
VDD1_20
V10
VDD1_21
V12
VDD1_22
V14
VDD1_23
W4
VDD1_24
Y2
VDD0_6
J15
VDDNB_1
K16
VDD0_16
L15
M16
VDDNB_2
P16
VDDNB_4
VDDNB_3
T16
VDD1_17
U15
VDDNB_5
V16
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO12
VDDIO11
N17
VDDIO13
P18
VDDIO14
P21
VDDIO15
P23
VDDIO16
P25
VDDIO17
R17
VDDIO18
T18
VDDIO19
T21
VDDIO20
T23
VDDIO21
T25
VDDIO22
U17
VDDIO23
V18
VDDIO24
V21
VDDIO25
V23
VDDIO26
V25
VDDIO27
Y2 5
C222
0.22U_0603_16V4Z
C222
0.22U_0603_16V4Z
1
2
C195
22U_0805_6.3V6M
C195
22U_0805_6.3V6M
1
2
+
C937
220U_D2_4VM_R15
+
C937
220U_D2_4VM_R15
1
2
C718
1000P_0402_25V8J
C718
1000P_0402_25V8J
1
2
C919
180P_0402_50V8J
C919
180P_0402_50V8J
1
2
C886
0.22U_0603_16V4Z
C886
0.22U_0603_16V4Z
1
2
C913
22U_0805_6.3V6M
C913
22U_0805_6.3V6M
1
2
C717
1000P_0402_25V8J
C717
1000P_0402_25V8J
1
2
C309C309
0.01U_0402_16V7K0.01U_0402_16V7K
1
2
C893
1000P_0402_25V8J
C893
1000P_0402_25V8J
1
2
C273
22U_0805_6.3V6M
C273
22U_0805_6.3V6M
1
2
C884C884
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C211C211
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
C892
1000P_0402_25V8J
C892
1000P_0402_25V8J
1
2
C219
180P_0402_50V8J
C219
180P_0402_50V8J
1
2
C302C302
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C914
22U_0805_6.3V6M
C914
22U_0805_6.3V6M
1
2
C209C209
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
+
C643
330U_X_2VM_R6M
+
C643
330U_X_2VM_R6M
1
2
C942C942
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
C915
22U_0805_6.3V6M
C915
22U_0805_6.3V6M
1
2
+
C96
330U_X_2VM_R6M
+
C96
330U_X_2VM_R6M
1
2
C885C885
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C214
22U_0805_6.3V6M
C214
22U_0805_6.3V6M
1
2
C912
22U_0805_6.3V6M
C912
22U_0805_6.3V6M
1
2
C716
180P_0402_50V8J
C716
180P_0402_50V8J
1
2
C307C307
0.01U_0402_16V7K0.01U_0402_16V7K
1
2
C881C881
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C274
180P_0402_50V8J
C274
180P_0402_50V8J
1
2
C308
180P_0402_50V8J
C308
180P_0402_50V8J
1
2
C910
22U_0805_6.3V6M
C910
22U_0805_6.3V6M
1
2
C228
22U_0805_6.3V6M
C228
22U_0805_6.3V6M
1
2
+
C661
330U_X_2VM_R6M
+
C661
330U_X_2VM_R6M
1
2
C301C301
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C300C300
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C276C276
0.01U_0402_16V7K0.01U_0402_16V7K
1
2
C238
22U_0805_6.3V6M
C238
22U_0805_6.3V6M
1
2
C227
22U_0805_6.3V6M
C227
22U_0805_6.3V6M
1
2
C210C210
4.7U_0805_10V4Z4.7U_0805_10V4Z
1
2
C921
180P_0402_50V8J
C921
180P_0402_50V8J
1
2
C922
180P_0402_50V8J
C922
180P_0402_50V8J
1
2
C218
180P_0402_50V8J
C218
180P_0402_50V8J
1
2
C882C882
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
C9C9
0.01U_0402_16V7K0.01U_0402_16V7K
1
2
+
C226
330U_X_2VM_R6M
+
C226
330U_X_2VM_R6M
1
2
C911
22U_0805_6.3V6M
C911
22U_0805_6.3V6M
1
2
C310
180P_0402_50V8J
C310
180P_0402_50V8J
1
2
+
C939
330U_X_2VM_R6M
+
C939
330U_X_2VM_R6M
1
2
C303C303
0.22U_0603_16V4Z0.22U_0603_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRA_SDQ[0..63]
DDRA_SMA[0..15]
DDRA_SDM[0..7]
+V_DDR_MCH_REF
DDRA_SDQ54
DDRA_SDQ10
DDRA_SDQ47
DDRA_SDQ22
DDRA_SDQ9
DDRA_SDQ23
DDRA_SDQ42
DDRA_SDQ34
DDRA_SDQ49
DDRA_SDQ48
DDRA_SDQ61
DDRA_SDQ60
DDRA_SDQ43
DDRA_SDQ35
DDRA_SDQ27
DDRA_SDQ26
DDRA_SDQ17
DDRA_SDQ16
DDRA_SDQ7
DDRA_SDM6
DDRA_SDM1
DDRA_SDQ40
DDRA_SDQS4
DDRA_SDQS2
DDRA_SDQS1
DDRA_SDQS6
DDRA_SDQS4#
DDRA_SDQS1#
DDRA_SDQS6#
DDRA_SDQ21
DDRA_SDQ20
DDRA_SDQ1
DDRA_SCAS#
DDRA_SRAS#
DDRA_SWE#
DDRA_SMA3
DDRA_SMA7
DDRA_SMA2
DDRA_SMA0
DDRA_SMA6
DDRA_SMA1
DDRA_SMA10
DDRA_SMA12
DDRA_SMA5
DDRA_SMA9
DDRA_SMA8
DDRA_SMA4
DDRA_SMA11
DDRA_SCS0#
DDRA_SCS1#
DDRA_CKE1DDRA_CKE0
DDRA_SBS0#
DDRA_SBS1#
DDRA_SMA13
DDRA_SDM3
DDRA_SDQS5
DDRA_SDQ55
DDRA_SDQS5#
DDRA_SDM5
DDRA_SDQS7
DDRA_SDM0
DDRA_SDQS7#
DDRA_SDQ5
DDRA_SDQ59
DDRA_SDQ58
DDRA_SDQ36
DDRA_SDQ44
DDRA_SDQ28
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ8
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM7
DDRA_ODT1
DDRA_ODT0
DDRA_SDM2
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQS3
DDRA_SDQ3
DDRA_SDQS3#
DDRA_SDM4
SB_SMBCLK
SB_SMBDATA
DDRA_SDQ4
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ45
DDRA_SDQ37
DDRA_SDQ6
DDRA_SDQ38
DDRA_SDQ46
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ39
DDRA_SDQ25 DDRA_SDQ29
DDRA_SDQ11
DDRA_SDQ24
DDRA_SBS2#
DDRA_SDQ51
DDRA_SDQ50
DDRA_SDQ0
DDRA_SDQ15
DDRA_SDQ14
DDRA_SMA14
DDRA_SDQ12
DDRA_SDQ32
DDRA_SDQ13
DDRA_SDQ41
DDRA_SDQS2#
DDRA_SDQ33
DDRA_SMA15
DDRA_SMA6
DDRA_SMA7
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_SMA4
DDRA_ODT0
DDRA_SMA2
DDRA_SMA13
DDRA_SMA15
DDRA_SMA11
DDRA_ODT1
DDRA_SCAS#
DDRA_SCS1#
DDRA_SWE#
DDRA_SBS0#
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3
DDRA_SMA5
DDRA_SMA8
DDRA_SMA9
DDRA_SMA12
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA14
DDRA_CKE1
DDRA_SMA[0..15] (5)
DDRA_SDQ[0..63] (5)
DDRA_SDM[0..7] (5 )
DDRA_SCAS#(5)
DDRA_SWE#(5 )
DDRA_SCS1#(5)
DDRA_CKE0( 5)
DDRA_SBS0#(5 )
DDRA_CLK0# (5)
DDRA_CLK0 (5)
DDRA_CLK1# (5)
DDRA_CLK1 (5)
DDRA_SCS0# (5)
DDRA_SRAS# (5)
DDRA_SBS1# (5)
DDRA_SDQS1(5)
DDRA_SDQS2(5)
DDRA_SDQS3 (5)
DDRA_SDQS4(5)
DDRA_SDQS5# (5)
DDRA_SDQS6(5)
DDRA_SDQS0(5)
DDRA_SDQS1#(5)
DDRA_SDQS2#(5)
DDRA_SDQS4#(5)
DDRA_SDQS6#(5)
DDRA_SDQS0#(5)
DDRA_SDQS3# (5)
DDRA_SDQS5 (5)
DDRA_SDQS7# (5)
DDRA_SDQS7 (5)
DDRA_ODT1(5 )
DDRA_ODT0 ( 5)
DDRA_CKE1 (5)
SB_SMBDATA(9,20,24,31)
SB_SMBCLK(9,20,24,31)
DDRA_SBS2#(5 )
+1.8V
+1.8V +1.8V
+3VS
+V_DDR_MCH_REF
+3VS
+V_DDR_MCH_REF
+1.8V
+0.9V
+1.8V
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
DDRII SO-DIMM 1
Custom
8 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
DDRII SO-DIMM 1
Custom
8 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
DDRII SO-DIMM 1
Custom
8 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
DIMM1 REV H:5.2mm (BOT)
EMI
Check layout place
C167 0.1U_0402_16V 4ZC167 0.1U_0402_16V 4Z
1 2
RP3
47_0804_8P4R_5%
RP3
47_0804_8P4R_5%
1 8
2 7
3 6
4 5
C175 0.1U_0402_16V 4Z
@
C175 0.1U_0402_16V 4Z
@
1 2
C894C894
1000P_0402_25V8J1000P_0402_25V8J
1
2
C225 0.1U_0402_16V 4ZC225 0.1U_0402_16V 4Z
1 2
C157 0.1U_0402_16V 4ZC157 0.1U_0402_16V 4Z
1 2
RP9
47_0804_8P4R_5%
RP9
47_0804_8P4R_5%
18
27
36
45
C159 0.1U_0402_16V 4ZC159 0.1U_0402_16V 4Z
1 2
R36 10K_0402_5%R36 10K_0402_5%
1 2
RP10
47_0804_8P4R_5%
RP10
47_0804_8P4R_5%
1 8
2 7
3 6
4 5
C923C923
1U_0402_6.3V4Z1U_0402_6.3V4Z
1
2
R147
1K_0402_1%
R147
1K_0402_1%
1 2
RP13
47_0804_8P4R_5%
RP13
47_0804_8P4R_5%
18
27
36
45
C179 0.1U_0402_16V 4ZC179 0.1U_0402_16V 4Z
1 2
C223 0.1U_0402_16V 4ZC223 0.1U_0402_16V 4Z
1 2
C16 0.1U_0402_16V4ZC16 0.1U_0402_16V4Z
1 2
C176 0.1U_0402_16V 4Z
@
C176 0.1U_0402_16V 4Z
@
1 2
C198 0.1U_0402_16V 4ZC198 0.1U_0402_16V 4Z
1 2
C14
0.1U_0402_16V4Z
C14
0.1U_0402_16V4Z
1
2
C15 0.1U_0402_16V4ZC15 0.1U_0402_16V4Z
1 2
R987 47_0402_5%R987 47_0402_5%
1 2
C936
2.2U_0805_10V6K
C936
2.2U_0805_10V6K
1
2
C17 0.1U_0402_16V4ZC17 0.1U_0402_16V4Z
1 2
C169 0.1U_0402_16V 4ZC169 0.1U_0402_16V 4Z
1 2
C145 0.1U_0402_16V 4ZC145 0.1U_0402_16V 4Z
1 2
JDIMM1
TYCO_292527-4
ME@
JDIMM1
TYCO_292527-4
ME@
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
VSS
DQ11
39
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ41
DQ40
143
VSS
2
DQ4
4
DQ5
6
VSS
8
DM0
10
VSS
12
DQ6
14
DQ7
16
VSS
18
DQ12
20
DQ13
22
VSS
24
DM1
26
VSS
28
CK0
30
CK0#
32
VSS
34
DQ14
36
DQ15
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VSS
48
NC
50
DM2
52
VSS
54
DQ22
56
DQ23
58
VSS
60
DQ28
62
DQ29
64
VSS
66
DQS3#
68
DQS3
70
VSS
72
DQ30
74
DQ31
76
VSS
78
NC/CKE1
80
VDD
82
NC/A15
84
NC/A14
86
VDD
88
A11
90
A7
92
A6
94
VDD
96
A4
98
A2
100
A0
102
VDD
104
BA1
106
RAS#
108
S0#
110
VDD
112
ODT 0
114
NC/A13
116
VDD
118
NC
120
VSS
122
DQ36
124
DQ37
126
VSS
128
DM4
130
VSS
132
DQ38
134
DQ39
136
VSS
138
DQ44
140
DQ45
142
VSS
144
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
VDDSPD
SCL
199
DQS5#
146
DQS5
148
VSS
150
DQ46
152
DQ47
154
VSS
156
DQ52
158
DQ53
160
VSS
162
CK1
164
CK1#
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
SAO
198
SA1
200
GND
202
GND
201
C142 0.1U_0402_16V 4ZC142 0.1U_0402_16V 4Z
1 2
RP4
47_0804_8P4R_5%
RP4
47_0804_8P4R_5%
18
27
36
45
C18 0.1U_0402_16V4ZC18 0.1U_0402_16V4Z
1 2
R988 47_0402_5%R988 47_0402_5%
1 2
R39 10K_0402_5%R39 10K_0402_5%
1 2
RP7
47_0804_8P4R_5%
RP7
47_0804_8P4R_5%
18
27
36
45
C13 0.1U_0402_16V4Z
@
C13 0.1U_0402_16V4Z
@
1 2
RP8
47_0804_8P4R_5%
RP8
47_0804_8P4R_5%
1 8
2 7
3 6
4 5
R148
1K_0402_1%
R148
1K_0402_1%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SDQ[0..63]
DDRB_SMA[0..15]
DDRB_SDM[0..7]
DDRB_SMA14
DDRB_SDQ20
DDRB_SDQ39
DDRB_SDQ38
DDRB_SDQ29
DDRB_SDQ24
DDRB_SDQ51
DDRB_SDQ50
DDRB_SDQ31
DDRB_SDQ28
DDRB_SDQ61
SB_SMBCLK
SB_SMBDATA
DDRB_SDQ27
DDRB_SDQ57
DDRB_SDQ26 DDRB_SDQ30
DDRB_SBS2#
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQ40
DDRB_SDQS4
DDRB_SDQS6
DDRB_SDQS4#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQ41
DDRB_SDQS6#
DDRB_SDQ11
DDRB_SDQ10
DDRB_SDQ1
DDRB_SDQ0
DDRB_SMA3
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA9
DDRB_SMA5
DDRB_SMA12
DDRB_SMA10
DDRB_SMA1
DDRB_CKE0
DDRB_SCS1#
DDRB_SMA8
DDRB_SDM3
DDRB_SBS0#
DDRB_SDQ25
DDRB_SDQ35
DDRB_SDQ34
DDRB_SDM5
DDRB_SDQ18
DDRB_SDQ49
DDRB_SDQ48
DDRB_SDQ9
DDRB_SDQ8
DDRB_SDQ19
DDRB_SDM7
DDRB_SDQ43
DDRB_ODT1
DDRB_SDQ42
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ33
DDRB_SDQ32
DDRB_SDQ56
DDRB_SDQ3
DDRB_SDQ37
DDRB_SDQ7
DDRB_SDQ6
DDRB_SDM6
DDRB_SDM1
DDRB_SRAS#
DDRB_SMA7
DDRB_SMA2
DDRB_SMA0
DDRB_SMA6
DDRB_SMA4
DDRB_SMA11
DDRB_SCS0#
DDRB_CKE1
DDRB_SBS1#
DDRB_SMA13
DDRB_SDQ54
DDRB_SDQS5
DDRB_SDQ55
DDRB_SDQ44
DDRB_SDQS5#
DDRB_SDQ45
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQS7
DDRB_SDM0
DDRB_SDQS7#
DDRB_SDQ5
DDRB_SDQ62
DDRB_SDQ63
DDRB_ODT0
DDRB_SDM2
DDRB_SDQ60
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDM4
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ36
DDRB_SDQ4
DDRB_SDQ16
DDRB_SDQ21
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ17
DDRB_SMA15
DDRB_SCAS#
DDRB_SMA3
DDRB_SMA1
DDRB_SWE#
DDRB_SCS1#
DDRB_SMA10
DDRB_ODT1
DDRB_SBS0#
DDRB_SMA13
DDRB_ODT0
DDRB_SCS0#
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SMA7
DDRB_SMA14
DDRB_SMA11
DDRB_SMA6
DDRB_SMA15
DDRB_CKE1
DDRB_SMA5
DDRB_SMA8
DDRB_SMA12
DDRB_SMA9
DDRB_SBS1#
DDRB_SRAS#
DDRB_SBS2#
DDRB_CKE0
DDRB_SMA[0..15] (5)
DDRB_SDQ[0..63] (5)
DDRB_SDM[0..7] (5 )
DDRB_SCS0# (5)
DDRB_SCS1#(5)
DDRB_SCAS#(5 )
DDRB_SWE#(5 )
DDRB_CKE0(5)
DDRB_SBS0#(5 )
DDRB_SDQS1(5)
DDRB_SDQS2(5)
DDRB_SDQS0(5)
DDRB_SDQS1#(5)
DDRB_SDQS2#(5)
DDRB_SDQS0#(5)
DDRB_SDQS4(5)
DDRB_SDQS6(5)
DDRB_SDQS4#(5)
DDRB_ODT1(5 )
DDRB_SDQS6#(5)
DDRB_SDQS5# (5)
DDRB_SDQS5 (5)
DDRB_ODT0 (5)
DDRB_SDQS7# (5)
DDRB_SDQS7 (5)
DDRB_SRAS# (5)
DDRB_SBS1# (5)
DDRB_SDQS3# (5)
DDRB_SDQS3 (5)
DDRB_CKE1 (5)
SB_SMBDATA(8,20,24,31)
SB_SMBCLK(8,20,24,31)
DDRB_SBS2#(5 )
DDRB_CLK1# (5)
DDRB_CLK1 (5)
DDRB_CLK0# (5)
DDRB_CLK0 (5)
+1.8V
+1.8V
+3VS
+V_DDR_MCH_REF
+3VS
+0.9V
+1.8V
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
DDRII SO-DIMM 2
Custom
9 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
DDRII SO-DIMM 2
Custom
9 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
DDRII SO-DIMM 2
Custom
9 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
DIMM2 REV H:9.2mm (BOT)
C20 0.1U_0402_16V4ZC20 0.1U_0402_16V4Z
1 2
C200 0.1U_0402_16V 4ZC200 0.1U_0402_16V 4Z
12
R989 47_0402_5%R989 47_0402_5%
1 2
R37 10K_0402_5%R37 10K_0402_5%
1 2
C147 0.1U_0402_16V 4ZC147 0.1U_0402_16V 4Z
12
C21 0.1U_0402_16V4ZC21 0.1U_0402_16V4Z
12
R35 10K_0402_5%R35 10K_0402_5%
1 2
C118 0.1U_0402_16V 4ZC118 0.1U_0402_16V 4Z
1 2
C122 0.1U_0402_16V 4ZC122 0.1U_0402_16V 4Z
12
C117 0.1U_0402_16V 4ZC117 0.1U_0402_16V 4Z
1 2
RP1
47_0804_8P4R_5%
RP1
47_0804_8P4R_5%
18
27
36
45
RP14
47_0804_8P4R_5%
RP14
47_0804_8P4R_5%
18
27
36
45
C180 0.1U_0402_16V 4ZC180 0.1U_0402_16V 4Z
12
JDIMM2
FOX_AS0A426-NARN-7F~N
ME@
JDIMM2
FOX_AS0A426-NARN-7F~N
ME@
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
VSS
DQ11
39
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ41
DQ40
143
VSS
2
DQ4
4
DQ5
6
VSS
8
DM0
10
VSS
12
DQ6
14
DQ7
16
VSS
18
DQ12
20
DQ13
22
VSS
24
DM1
26
VSS
28
CK0
30
CK0#
32
VSS
34
DQ14
36
DQ15
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VSS
48
NC
50
DM2
52
VSS
54
DQ22
56
DQ23
58
VSS
60
DQ28
62
DQ29
64
VSS
66
DQS3#
68
DQS3
70
VSS
72
DQ30
74
DQ31
76
VSS
78
NC/CKE1
80
VDD
82
NC/A15
84
NC/A14
86
VDD
88
A11
90
A7
92
A6
94
VDD
96
A4
98
A2
100
A0
102
VDD
104
BA1
106
RAS#
108
S0#
110
VDD
112
ODT 0
114
NC/A13
116
VDD
118
NC
120
VSS
122
DQ36
124
DQ37
126
VSS
128
DM4
130
VSS
132
DQ38
134
DQ39
136
VSS
138
DQ44
140
DQ45
142
VSS
144
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
VDDSPD
SCL
199
DQS5#
146
DQS5
148
VSS
150
DQ46
152
DQ47
154
VSS
156
DQ52
158
DQ53
160
VSS
162
CK1
164
CK1#
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
SAO
198
SA1
200
C146 0.1U_0402_16V 4ZC146 0.1U_0402_16V 4Z
12
C197 0.1U_0402_16V 4ZC197 0.1U_0402_16V 4Z
1 2
C231 0.1U_0402_16V 4ZC231 0.1U_0402_16V 4Z
1 2
C201 0.1U_0402_16V 4ZC201 0.1U_0402_16V 4Z
1 2
RP12
47_0804_8P4R_5%
RP12
47_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP6
47_0804_8P4R_5%
RP6
47_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP2
47_0804_8P4R_5%
RP2
47_0804_8P4R_5%
1 8
2 7
3 6
4 5
C171 0.1U_0402_16V 4ZC171 0.1U_0402_16V 4Z
12
RP5
47_0804_8P4R_5%
RP5
47_0804_8P4R_5%
18
27
36
45
R990 47_0402_5%R990 47_0402_5%
1 2
C933
2.2U_0603_6.3V4Z
C933
2.2U_0603_6.3V4Z
1
2
C19 0.1U_0402_16V4ZC19 0.1U_0402_16V4Z
1 2
RP11
47_0804_8P4R_5%
RP11
47_0804_8P4R_5%
18
27
36
45
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCIE_ITX_PRX_P2
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
SB_TX1N_C
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIN2
H_CADIP2
H_CADIN3
H_CADIP3
H_CTLIN0
H_CTLIP0
H_CTLON0
H_CADIN4
H_CADIP4
H_CADIN5
H_CADIP5
H_CADIN6
H_CADIP6
H_CADIN7
H_CADIP7
H_CADIN8
H_CADIP8
H_CADIN9
H_CADIP9
H_CADIN10
H_CADIP10
H_CTLOP0
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIN13
H_CADIP13
H_CADIN14
H_CADIP14
H_CADIN15
H_CADIP15
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CTLIP1
H_CTLIN1
H_CADON2
H_CTLOP1
H_CADOP2
H_CTLON1
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADON10
H_CADOP10
H_CADON9
H_CADOP9
H_CADOP8
H_CADON8
H_CADIP0
PCIE_ITX_PRX_N2
PCIE_MTX_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_GRX_N10
PCIE_MTX_C_GRX_P13
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0PCIE_MTX_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4 PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_GRX_N4
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N5
PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P1
PCIE_ITX_C_PRX_P2 (30)
PCIE_ITX_C_PRX_N2 (30)
PCIE_PTX_C_IRX_P2(30)
PCIE_PTX_C_IRX_N2(30)
H_CADIP[0..15] (4)
H_CADON[0..15](4) H_CADIN[0..15] (4)
H_CADOP[0..15](4)
SB_RX1P(23)
SB_RX1N(23)
SB_RX0P(23)
SB_RX0N(23)
SB_TX0P (23)
SB_TX1N (23)
SB_TX0N (23)
SB_TX1P (23)
SB_RX3P(23)
SB_RX3N(23)
SB_RX2P(23)
SB_RX2N(23)
SB_TX2P (23)
SB_TX2N (23)
SB_TX3N (23)
SB_TX3P (23)
H_CLKIN0 (4)
H_CLKIP0 (4)
H_CTLIN0 (4)
H_CTLIP0 ( 4)
H_CLKON0(4)
H_CLKOP0( 4)
H_CLKOP1( 4)
H_CLKON1(4)
H_CTLOP0(4)
H_CTLON0( 4)
H_CLKIN1 (4)
H_CLKIP1 (4)
H_CTLIN1 (4)
H_CTLIP1 ( 4)H_CTLOP1(4)
H_CTLON1( 4)
PCIE_MTX_C_GRX_N[0..15] (14)
PCIE_MTX_C_GRX_P[0..15] (14)
PCIE_GTX_C_MRX_P[0..15](14)
PCIE_GTX_C_MRX_N[0..15](14)
PCIE_ITX_C_PRX_P4 (31)
PCIE_ITX_C_PRX_N4 (31)
PCIE_PTX_C_IRX_P4(31)
PCIE_PTX_C_IRX_N4(31)
PCIE_ITX_C_PRX_P1 (31)
PCIE_ITX_C_PRX_N1 (31)
PCIE_PTX_C_IRX_P1(31)
PCIE_PTX_C_IRX_N1(31)
+1.1VS
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880-HT/PCIE
Custom
10 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880-HT/PCIE
Custom
10 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880-HT/PCIE
Custom
10 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
LAN
WLAN
New Card
DP0
GFX_TX0,TX1,TX2 and TX3
RS780M Display Port Support (muxed on GFX)
DP1
GFX_TX4,TX5,TX6 and TX7
AUX0 and HPD0
AUX1 and HPD1
0718 Place within 1"
layout 1:2
0718 Place within 1"
layout 1:2
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA
SA000032710 S IC 216-0752001 A11 RS880M FCBGA528 0FA
C358 0.1U_0402_10V7KVGA@C358 0.1U_0402_10V7KVGA@
1 2
C364 0.1U_0402_10V7KVGA@C364 0.1U_0402_10V7KVGA@
1 2
R56
301_0402_1%
R56
301_0402_1%
1 2
C632 0.1U_0402_10V7KVGA@C632 0.1U_0402_10V7KVGA@
1 2
C636 0.1U_0402_10V7KVGA@C636 0.1U_0402_10V7KVGA@
1 2
C634 0.1U_0402_10V7KVGA@C634 0.1U_0402_10V7KVGA@
1 2
C652 0.1U_0402_10V7KVGA@C652 0.1U_0402_10V7KVGA@
1 2
C650 0.1U_0402_10V7KVGA@C650 0.1U_0402_10V7KVGA@
1 2
C649 0.1U_0402_10V7KVGA@C649 0.1U_0402_10V7KVGA@
1 2
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U20B
RS880M_FCBGA528
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U20B
RS880M_FCBGA528
SB_TX3P
AD5
SB_TX3N
AE5
GPP_TX2P
AA2
GPP_TX2N
AA1
GPP_TX3P
Y1
GPP_TX3N
Y2
W5
SB_RX3N
SB_RX3P
Y5
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3N
GPP_RX3P
W6
SB_TX0P
AD7
SB_TX0N
AE7
SB_TX1P
AE6
SB_TX1N
AD6
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1N
SB_RX1P
Y7
PCE_CALRP(PCE_BCALRP)
AC8
PCE_CALRN(PCE_BCALRN)
AB8
SB_TX2N
AC6
AA5
SB_RX2N
SB_RX2P
AA6
SB_TX2P
AB6
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1N
GPP_RX1P
AD3
GPP_TX0P
AC1
GPP_TX0N
AC2
GPP_TX1P
AB4
GPP_TX1N
AB3
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15N
GFX_RX15P
T3
GFX_TX0P
A5
GFX_TX0N
B5
GFX_TX1P
A4
GFX_TX1N
B4
GFX_TX2P
C3
GFX_TX2N
B2
GFX_TX3P
D1
GFX_TX3N
D2
GFX_TX4P
E2
GFX_TX4N
E1
GFX_TX5P
F4
GFX_TX5N
F3
GFX_TX6P
F1
GFX_TX6N
F2
GFX_TX7P
H4
GFX_TX7N
H3
GFX_TX8P
H1
GFX_TX8N
H2
GFX_TX9P
J2
GFX_TX9N
J1
GFX_TX10P
K4
GFX_TX10N
K3
GFX_TX11P
K1
GFX_TX11N
K2
GFX_TX12P
M4
GFX_TX12N
M3
GFX_TX13P
M1
GFX_TX13N
M2
GFX_TX14P
N2
GFX_TX14N
N1
GFX_TX15P
P1
GFX_TX15N
P2
GPP_TX4P
Y4
GPP_TX4N
Y3
GPP_TX5P
V1
GPP_TX5N
V2
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5N
GPP_RX5P
U7
C37 0.1U_0402_10V7KC37 0.1U_0402_10V7K
1 2
C33 0.1U_0402_10V7KC33 0.1U_0402_10V7K
1 2
C658 0.1U_0402_10V7KVGA@C658 0.1U_0402_10V7KVGA@
1 2
C352 0.1U_0402_10V7KC352 0.1U_0402_10V7K
1 2
C631 0.1U_0402_10V7KVGA@C631 0.1U_0402_10V7KVGA@
1 2
C361 0.1U_0402_10V7KVGA@C361 0.1U_0402_10V7KVGA@
1 2
R267 2K_0402_1%R267 2K_0402_1%
1 2
C614 0.1U_0402_10V7K
WLAN@
C614
WLAN@
0.1U_0402_10V7K
1 2
C646 0.1U_0402_10V7KVGA@C646 0.1U_0402_10V7KVGA@
1 2
C618 0.1U_0402_10V7KC618 0.1U_0402_10V7K
1 2
C653 0.1U_0402_10V7KVGA@C653 0.1U_0402_10V7KVGA@
1 2
C610 0.1U_0402_10V7KC610 0.1U_0402_10V7K
1 2
C651 0.1U_0402_10V7KVGA@C651 0.1U_0402_10V7KVGA@
1 2
C362 0.1U_0402_10V7K
WLAN@
C362 0.1U_0402_10V7K
WLAN@
1 2
C365 0.1U_0402_10V7KVGA@C365 0.1U_0402_10V7KVGA@
1 2
C876 0.1U_0402_10V7KVGA@C876 0.1U_0402_10V7KVGA@
1 2
C629 0.1U_0402_10V7KVGA@C629 0.1U_0402_10V7KVGA@
1 2
C616 0.1U_0402_10V7KC616 0.1U_0402_10V7K
1 2
C366 0.1U_0402_10V7KVGA@C366 0.1U_0402_10V7KVGA@
1 2
R51
301_0402_1%
R51
301_0402_1%
1 2
C637 0.1U_0402_10V7KVGA@C637 0.1U_0402_10V7KVGA@
1 2
C964 0.1U_0402_10V7K
NEWCARD@
C964 0.1U_0402_10V7K
NEWCARD@
1 2
C635 0.1U_0402_10V7KVGA@C635 0.1U_0402_10V7KVGA@
1 2
C623 0.1U_0402_10V7KVGA@C623 0.1U_0402_10V7KVGA@
1 2
C363 0.1U_0402_10V7KVGA@C363 0.1U_0402_10V7KVGA@
1 2
C624 0.1U_0402_10V7KVGA@C624 0.1U_0402_10V7KVGA@
1 2
C638 0.1U_0402_10V7KVGA@C638 0.1U_0402_10V7KVGA@
1 2
C627 0.1U_0402_10V7KVGA@C627 0.1U_0402_10V7KVGA@
1 2
C38 0.1U_0402_10V7KC38 0.1U_0402_10V7K
1 2
C359 0.1U_0402_10V7KVGA@C359 0.1U_0402_10V7KVGA@
1 2
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U20A
RS880M_FCBGA528
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U20A
RS880M_FCBGA528
U19
HT_RXCAD15N
HT_RXCAD15P
U18
U20
HT_RXCAD14N
HT_RXCAD14P
U21
V21
HT_RXCAD13N
HT_RXCAD13P
V20
W21
HT_RXCAD12N
HT_RXCAD12P
W20
Y2 2
HT_RXCAD11N
HT_RXCAD11P
Y2 3
AA24
HT_RXCAD10N
HT_RXCAD10P
AA25
AB25
HT_RXCAD9N
HT_RXCAD9P
AB24
AC24
HT_RXCAD8N
HT_RXCAD8P
AC25
N24
HT_RXCAD7N
HT_RXCAD7P
N25
P25
HT_RXCAD6N
HT_RXCAD6P
P24
P22
HT_RXCAD5N
HT_RXCAD5P
P23
T25
HT_RXCAD4N
HT_RXCAD4P
T24
U24
HT_RXCAD3N
HT_RXCAD3P
U25
V25
HT_RXCAD2N
HT_RXCAD2P
V24
V22
HT_RXCAD1N
HT_RXCAD1P
V23
Y2 5
HT_RXCAD0N
HT_RXCAD0P
Y2 4
AB23
HT_RXCLK1N
HT_RXCLK1P
AA22
T22
HT_RXCLK0N
HT_RXCLK0P
T23
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1N
HT_RXCTL1P
R20
C23
HT_RXCALN
HT_RXCALP
A24
HT_TXCAD15P
P18
HT_TXCAD15N
M18
HT_TXCAD14P
M21
HT_TXCAD14N
P21
HT_TXCAD13P
M19
HT_TXCAD13N
L18
HT_TXCAD12P
L19
HT_TXCAD12N
J19
HT_TXCAD11P
J18
HT_TXCAD11N
K17
HT_TXCAD10P
J20
HT_TXCAD10N
J21
HT_TXCAD9P
G20
HT_TXCAD9N
H21
HT_TXCAD8P
F21
HT_TXCAD8N
G21
HT_TXCAD7P
K23
HT_TXCAD7N
K22
HT_TXCAD6P
K24
HT_TXCAD6N
K25
HT_TXCAD5P
J25
HT_TXCAD5N
J24
HT_TXCAD4P
H23
HT_TXCAD4N
H22
HT_TXCAD3P
F23
HT_TXCAD3N
F22
HT_TXCAD2P
F24
HT_TXCAD2N
F25
HT_TXCAD1P
E24
HT_TXCAD1N
E25
HT_TXCAD0P
D24
HT_TXCAD0N
D25
HT_TXCLK1P
L21
HT_TXCLK1N
L20
HT_TXCLK0P
H24
HT_TXCLK0N
H25
HT_TXCTL0P
M24
HT_TXCTL0N
M25
HT_TXCTL1P
P19
HT_TXCTL1N
R18
HT_TXCALP
B24
HT_TXCALN
B25
C657 0.1U_0402_10V7KVGA@C657 0.1U_0402_10V7KVGA@
1 2
C621 0.1U_0402_10V7KVGA@C621 0.1U_0402_10V7KVGA@
1 2
C641 0.1U_0402_10V7KVGA@C641 0.1U_0402_10V7KVGA@
1 2
C609 0.1U_0402_10V7KC609 0.1U_0402_10V7K
1 2
C357 0.1U_0402_10V7KC357 0.1U_0402_10V7K
1 2
C356 0.1U_0402_10V7KVGA@C356 0.1U_0402_10V7KVGA@
1 2
R32 1.27K_0402_1%R32 1.27K_0402_1%
1 2
C965 0.1U_0402_10V7K
NEWCARD@
C965 0.1U_0402_10V7K
NEWCARD@
1 2
C360 0.1U_0402_10V7KVGA@C360 0.1U_0402_10V7KVGA@
1 2
C32 0.1U_0402_10V7KC32 0.1U_0402_10V7K
1 2
C648 0.1U_0402_10V7KVGA@C648 0.1U_0402_10V7KVGA@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NB_RESET#
GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
NB_ALLOW_LDTSTOP
NB_LDTSTOP#
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
+VDDLTP18
+VDDLT18
+VDDLT18
+AVDD2
GMCH_CRT_R
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_CLK
GMCH_CRT_DATA
+NB_HTPVDD
+NB_PLLVDD
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_LCD_CLK
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_LCD_DATA
POWER_SEL
+VDDLTP18
GMCH_HDMI_CLK
GMCH_HDMI_DATA
CLK_NB_14.318M
CLK_NB_14.318M
GMCH_HDMI_CLK_R2
GMCH_HDMI_DATA_R2
+AVDDQ
+AVDD1
NB_PWRGD_R
NB_PWRGD
POWER_SEL
NB_PWRGD(24)
GMCH_CRT_HSYNC(13,22)
GMCH_CRT_VSYNC(13,22)
CLK_NB_14.318M(20)
CLK_NBGFX(20)
CLK_NBGFX#(20)
CLK_SBLINK_BCLK(20)
CLK_SBLINK_BCLK#(20)
CLK_NBHT(20)
CLK_NBHT#(20)
PLT_RST#(13,14,23,30,31,33)
AUX_CAL(13)
SUS_STAT# (24)
SUS_STAT_R# (13)
ALLOW_LDTSTOP(23)
LDT_STOP#(6,23)
GMCH_TXOUT0+ (21)
GMCH_TXOUT0- (21)
GMCH_TXOUT1+ (21)
GMCH_TXOUT1- (21)
GMCH_TXOUT2+ (21)
GMCH_TXOUT2- (21)
GMCH_TXCLK+ (21)
GMCH_TXCLK- (21)
GMCH_CRT_R(22)
GMCH_CRT_G(22)
GMCH_CRT_B(22)
GMCH_CRT_DATA(22)
GMCH_CRT_CLK(22)
GMCH_LCD_CLK(21)
GMCH_LCD_DATA(21)
POWER_SEL(45)
UMA_ENVDD_R (21)
SB_PWRGD(6,24,33)
ENBKL (33)
UMA_VARIBL (21,33)
+1.8VS
+1.8VS
+VDDA18HTPLL
+VDDA18PCIEPLL
+1.1VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+1.8VS
+1.8VS
+NB_PLLVDD
+NB_HTPVDD
+VDDA18PCIEPLL
+VDDA18HTPLL
+NB_HTPVDD+1.8VS
+1.1VS
+3VS
+NB_PLLVDD
+1.8VS
+3VS
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 VEDIO/CLK GEN
Custom
11 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 VEDIO/CLK GEN
Custom
11 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 VEDIO/CLK GEN
Custom
11 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Strap pin
Strap pin
For RS780M A13
RED: Connected to GND through two separate 140ohm 1% resistor
VDDLTP18=15mA
VDDLT18=0.3A
AVDD=0.11A
AVDDDI=20mA
AVDDQ=4mA
PLLVDD=65mA
PLLVDD18=20mA
VDDA18HTPLL=20mA
VDDA18PCIEPLL=0.12A
POWER_SEL
HIGH 1.0V
1.1VLOW
R566
4.7K_0402_5%
R566
4.7K_0402_5%
1 2
R49 150_0402_1%
UMA@
R49
UMA@
150_0402_1%
1 2
C645
2.2U_0603_6.3V4Z
C645
2.2U_0603_6.3V4Z
1
2
R563 4.7K_0402_5%
UMA@
R563
UMA@
4.7K_0402_5%
1 2
C663
1U_0402_6.3V4Z@
C663
1U_0402_6.3V4Z@
1
2
C22
0.1U_0402_16V4Z
C22
0.1U_0402_16V4Z
1
2
R744 0_0402_5%R744 0_0402_5%
1 2
R469
4.7K_0402_5%
R469
4.7K_0402_5%
12
R280
0_0402_5%
R280
0_0402_5%
1 2
R107 0_0402_5%R107 0_0402_5%
1 2
C87
2.2U_0603_6.3V4Z
C87
2.2U_0603_6.3V4Z
1
2
R59 0_0402_5%R59 0_0402_5%
1 2
L59
FBMA-L11-160808-221LMT_0603
L59
FBMA-L11-160808-221LMT_0603
12
R441
1.27K_0402_1%
@
R441
1.27K_0402_1%
@
1 2
C94
2.2U_0603_6.3V4Z
C94
2.2U_0603_6.3V4Z
1
2
R477
100_0402_5%
@
R477
100_0402_5%
@
12
C874
1U_0402_6.3V4Z@
C874
1U_0402_6.3V4Z@
1
2
L12
MBK1608221YZF_0603
L12
MBK1608221YZF_0603
1 2
R279
1.8K_0402_5%
R279
1.8K_0402_5%
1 2
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U20C
RS880M_FCBGA528
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U20C
RS880M_FCBGA528
VDDA18HTPLL
H17
D8
SYSRESETb
A10
POWERGOOD
C10
ALLOW_LDTSTOP
LDTSTOPb
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC)
D10
A8
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
B8
THERMALDIODE_P
AE8
THERMALDIODE_N
AD8
I2C_CLK
B9
STRP_DATA
B10
T2
GFX_REFCLKN
GFX_REFCLKP
T1
U1
GPP_REFCLKN
GPP_REFCLKP
U2
D14
PLLVSS(NC)
PLLVDD18(NC)
B12
TXOUT_L0P(NC)
A22
TXOUT_L0N(NC)
B22
TXOUT_L1P(NC)
A21
TXOUT_L1N(NC)
B21
TXOUT_L2P(NC)
B20
TXOUT_L2N(DBG_GPIO0)
A20
TXOUT_L3P(NC)
A19
TXOUT_U0P(NC)
B18
TXOUT_L3N(DBG_GPIO2)
B19
TXOUT_U0N(NC)
A18
TXOUT_U1P(PCIE_RESET_GPIO3)
A17
TXOUT_U1N(PCIE_RESET_GPIO2)
B17
TXOUT_U2P(NC)
D20
TXOUT_U2N(NC)
D21
TXOUT_U3P(PCIE_RESET_GPIO5)
D18
TXOUT_U3N(NC)
D19
TXCLK_LP(DBG_GPIO1)
B16
TXCLK_LN(DBG_GPIO3)
A16
TXCLK_UP(PCIE_RESET_GPIO4)
D16
TXCLK_UN(PCIE_RESET_GPIO1)
D17
VDDLTP18(NC)
A13
VSSLTP18(NC)
B13
E17
C_Pr(DFT_GPIO5)
F17
COMP_Pb(DFT _GPIO4)
Y(DFT_GPIO2)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC)
D9
I2C_DATA
A9
TESTMODE
D13
C24
HT_REFCLKP
HT_REFCLKN
C25
SUS_STAT#(PWM_GPIO5)
D12
GREEN(DFT _GPIO1)
E18
BLUE(DFT_GPIO3)
E19
B11
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
A11
DAC_RSET(PWM_GPIO1)
G14
F12
AVDD2(NC)
AVDD1(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVSSQ(NC)
AVDDQ(NC)
H14
VDDLT18_2(NC)
B15
VDDLT33_1(NC)
A14
VDDLT33_2(NC)
B14
VSSLT1(VSS)
C14
VSSLT2(VSS)
D15
VDDLT18_1(NC)
A15
VSSLT3(VSS)
C16
VSSLT4(VSS)
C18
VSSLT5(VSS)
C20
LVDS_DIGON(PCE_TCALRP)
E9
LVDS_BLON(PCE_RCALRP)
F7
LVDS_ENA_BL(PWM_GPIO2)
G12
VSSLT6(VSS)
E20
D7
VDDA18PCIEPLL2
VDDA18PCIEPLL1
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
V4
GPPSB_REFCLKN(SB_REFCLKN)
GPPSB_REFCLKP(SB_REFCLKP)
V3
A7
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
B7
F8
DAC_SDA(PCE_TCALRN)
DAC_SCL(PCE_RCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS)
C22
RSVD
G11
C935
2.2U_0603_6.3V4Z
C935
2.2U_0603_6.3V4Z
1
2
R50 150_0402_1%
UMA@
R50
UMA@
150_0402_1%
1 2
R29
1.27K_0402_1%
@
R29
1.27K_0402_1%
@
1 2
L15
FBMA-L11-160808-221LMT_0603
L15
FBMA-L11-160808-221LMT_0603
12
C95
4.7U_0805_10V4Z
C95
4.7U_0805_10V4Z
1
2
C854
100P_0402_50V8J
@
C854
100P_0402_50V8J
@
1
2
C93
2.2U_0603_6.3V4Z
C93
2.2U_0603_6.3V4Z
1
2
R106 0_0402_5%R106 0_0402_5%
1 2
U42
NC7SZ08P5X_NL_SC70-5
U42
NC7SZ08P5X_NL_SC70-5
B
2
A
1
Y
4
P
5
G
3
C84
1U_0402_6.3V4Z@
C84
1U_0402_6.3V4Z@
1
2
L8
FBMA-L11-160808-221LMT_0603
L8
FBMA-L11-160808-221LMT_0603
12
R42 715_0402_1%R42 715_0402_1%
1 2
R1008
2K_0402_5%
R1008
2K_0402_5%
12
L14
FBMA-L11-160808-221LMT_0603
L14
FBMA-L11-160808-221LMT_0603
12
C924
1U_0402_6.3V4Z@
C924
1U_0402_6.3V4Z@
1
2
L9
FBMA-L11-160808-221LMT_0603
L9
FBMA-L11-160808-221LMT_0603
12
C875
1U_0402_6.3V4Z
@
C875
1U_0402_6.3V4Z
@
1
2
C90
0.1U_0402_16V4Z
C90
0.1U_0402_16V4Z
1
2
R460
10K_0402_5%
@
R460
10K_0402_5%
@
12
C644C644
2.2U_0603_6.3V4Z2.2U_0603_6.3V4Z
1
2
C665
1U_0402_6.3V4Z@
C665
1U_0402_6.3V4Z@
1
2
L56
MBC1608121YZF_0603
L56
MBC1608121YZF_0603
1 2
L13
FBMA-L11-160808-221LMT_0603
L13
FBMA-L11-160808-221LMT_0603
12
R511 0_0402_5%@R511 0_0402_5%@
1 2
L10
FBMA-L11-160808-221LMT_0603
L10
FBMA-L11-160808-221LMT_0603
12
R60
1K_0402_5%
R60
1K_0402_5%
1 2
C86
1U_0402_6.3V4Z@
C86
1U_0402_6.3V4Z@
1
2
C934
2.2U_0603_6.3V4Z
C934
2.2U_0603_6.3V4Z
1
2
R283 300_0402_5%R283 300_0402_5%
12
R45 140_0402_1%
UMA@
R45
UMA@
140_0402_1%
1 2
R565 4.7K_0402_5%
UMA@
R565 4.7K_0402_5%
UMA@
1 2
R564
4.7K_0402_5%
R564
4.7K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+VDDHTTX
+VDDHT
+VDDA18PCIE
+VDDHTRX
+1.1VS
+1.8VS
+1.8VS
+1.2V_HT
+1.1VS
+3VS
+1.1VS
+1.8VS
+NB_CORE
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 PWR/GND
Custom
12 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 PWR/GND
Custom
12 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 PWR/GND
Custom
12 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
FOR Version A11 pop 1.35VS A12
use 1.2V_HT
+1.8VS=W/S=20/10mil For Memory PLL power
+1.1VS=W/S=20/10mil For Memory PLL power
VDDHTTX=0.68A
VDDA18PCIE=0.7A
VDDPCIE=2.5A
VDD33=60mA
VDDHTRX+VDDHT=1.3A
15mA
26mA
VDD18=10mA
NB_CORE=10A
VDDHT=0.6A
VDDHTRX=0.7A
L5
MBK2012221YZF_0805
L5
MBK2012221YZF_0805
12
C28 10U_0805_10V4ZC28 10U_0805_10V4Z
1 2
C430.1U_0402_16V4Z C430.1U_0402_16V4Z
1
2
C49
0.1U_0402_16V4Z
C49
0.1U_0402_16V4Z
1
2
C341
0.1U_0402_16V4Z
C341
0.1U_0402_16V4Z
1
2
C230.1U_0402_16V4Z C230.1U_0402_16V4Z
1
2
PART 6/6
GROUND
U20F
RS780M_FCBGA528
PART 6/6
GROUND
U20F
RS780M_FCBGA528
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT19
VSSAHT18
R25
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y2 1
VSSAHT27
VSSAHT26
AD25
VSS2
D11
VSS3
G8
VSS4
E14
VSS5
E15
VSS7
J12
VSS8
K14
VSS9
M11
VSS10
L15
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y1 8
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS32
VSS31
AE20
VSSAPCIE1
A2
VSSAPCIE2
B1
VSSAPCIE3
D3
VSSAPCIE4
D5
VSSAPCIE5
E4
VSSAPCIE6
G1
VSSAPCIE7
G2
VSSAPCIE8
G4
VSSAPCIE9
H7
VSSAPCIE10
J4
VSSAPCIE11
R7
VSSAPCIE12
L1
VSSAPCIE13
L2
VSSAPCIE14
L4
VSSAPCIE15
L7
VSS34
K11
VSSAPCIE16
M6
VSSAPCIE17
N4
VSSAPCIE18
P6
VSSAPCIE19
R1
VSSAPCIE20
R2
VSSAPCIE21
R4
VSSAPCIE22
V7
VSSAPCIE23
U4
VSSAPCIE24
V8
VSSAPCIE25
V6
VSSAPCIE26
W1
VSSAPCIE27
W2
VSSAPCIE28
W4
VSSAPCIE29
W7
VSSAPCIE30
W8
VSSAPCIE31
Y6
VSSAPCIE32
AA4
VSSAPCIE33
AB5
VSSAPCIE34
AB1
VSSAPCIE35
AB7
VSSAPCIE36
AC3
VSSAPCIE37
AC4
VSSAPCIE38
AE1
VSSAPCIE39
AE4
VSSAPCIE40
AB2
VSS1
AE14
VSSAHT20
H20
VSS33
AB21
VSS6
J15
C4410U_0805_10V4Z C4410U_0805_10V4Z
1
2
C3610U_0805_10V4Z C3610U_0805_10V4Z
1
2
L11
MBK2012221YZF_0805
L11
MBK2012221YZF_0805
12
C51
0.1U_0402_16V4Z
C51
0.1U_0402_16V4Z
1
2
L4
MBK2012221YZF_0805
L4
MBK2012221YZF_0805
12
L71
MBK2012221YZF_0805
L71
MBK2012221YZF_0805
12
C350.1U_0402_16V4Z C350.1U_0402_16V4Z
1
2
C929 1U_0402_6.3V4ZC929 1U_0402_6.3V4Z
1 2
PART 5/6
POWER
U20E
RS880M_FCBGA528
PART 5/6
POWER
U20E
RS880M_FCBGA528
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_7
VDDHT_6
T16
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y2 0
VDDHTTX_6
W19
VDDHTTX_8
VDDHTTX_7
V18
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_5
VDDHTRX_4
D22
F9
VDD18_1
G9
VDD18_2
AE11
VDD18_MEM2(NC)
VDD18_MEM1(NC)
AD11
J10
VDDA18PCIE_1
P10
VDDA18PCIE_3
VDDA18PCIE_2
K10
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_14
VDDA18PCIE_13
AE9
W9
VDDA18PCIE_7
VDDA18PCIE_6
H9
VDDPCIE_1
A6
VDDPCIE_2
B6
VDDPCIE_3
C6
VDDPCIE_4
D6
VDDPCIE_5
E6
VDDPCIE_6
F6
VDDPCIE_7
G7
VDDPCIE_8
H8
VDDPCIE_9
J9
M10
VDDA18PCIE_5
VDDA18PCIE_4
L10
VDDC_1
K12
VDDC_2
J14
VDDC_3
U16
VDDPCIE_11
M9
VDDC_4
J11
VDDC_5
K15
VDDPCIE_10
K9
VDDC_6
M12
VDDC_7
L14
VDDC_8
L11
VDDC_9
M13
VDDC_10
M15
VDDC_11
N12
VDDC_12
N14
VDDC_13
P11
VDDC_14
P13
VDDC_15
P14
VDDC_16
R12
VDDC_17
R15
VDDC_18
T11
VDDC_19
T15
VDDC_20
U12
VDDC_21
T14
VDD33_1(NC)
H11
VDD33_2(NC)
H12
VDD_MEM1(NC)
AE10
VDD_MEM2(NC)
AA11
VDD_MEM3(NC)
Y1 1
VDD_MEM4(NC)
AD10
VDD_MEM6(NC)
VDD_MEM5(NC)
AC10
AB10
VDDA18PCIE_8
T10
VDDC_22
J16
VDDPCIE_12
L9
VDDA18PCIE_9
R10
VDDPCIE_13
P9
VDDPCIE_14
R9
VDDPCIE_15
T9
VDDPCIE_16
V9
VDDPCIE_17
U9
VDDA18PCIE_15
U10
B23
VDDHTRX_7
VDDHTRX_6
A23
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_13
VDDHTTX_12
M17
C260.1U_0402_16V4Z C260.1U_0402_16V4Z
1
2
C931
0.1U_0402_16V4Z
C931
0.1U_0402_16V4Z
1
2
C342
0.1U_0402_16V4Z
C342
0.1U_0402_16V4Z
1
2
C940
4.7U_0805_10V4Z
C940
4.7U_0805_10V4Z
1
2
L3
FBMA-L11-201209-221LMA30T_0805
L3
FBMA-L11-201209-221LMA30T_0805
1 2
0.1U_0402_16V4Z
C24C24
0.1U_0402_16V4Z
1
2
C40
0.1U_0402_16V4Z
C40
0.1U_0402_16V4Z
1
2
C3400.1U_0402_16V4Z C3400.1U_0402_16V4Z
1
2
C31
4.7U_0805_10V4Z
C31
4.7U_0805_10V4Z
1
2
C3370.1U_0402_16V4Z C3370.1U_0402_16V4Z
1
2
C345
0.1U_0402_16V4Z
C345
0.1U_0402_16V4Z
1
2
C339 0.1U_0402_16V4ZC339
1
0.1U_0402_16V4Z
2
C928
0.1U_0402_16V4Z
C928
0.1U_0402_16V4Z
1
2
C48
0.1U_0402_16V4Z
C48
0.1U_0402_16V4Z
1
2
C45
4.7U_0805_10V4Z
C45
4.7U_0805_10V4Z
1
2
SBD_MEM/DVO_I/F
PAR 4 OF 6
U20D
RS780M_FCBGA528
SBD_MEM/DVO_I/F
PAR 4 OF 6
U20D
RS780M_FCBGA528
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
MEM_A5(NC)
AB14
MEM_A6(NC)
AD14
MEM_A7(NC)
AD13
MEM_A8(NC)
AD15
MEM_A9(NC)
AC16
MEM_A10(NC)
AE13
MEM_A11(NC)
AC14
MEM_A13(NC)
MEM_A12(NC)
Y1 4
AD16
MEM_BA0(NC)
AE17
MEM_BA2(NC)
MEM_BA1(NC)
AD17
W12
MEM_RASb(NC)
Y1 2
MEM_CASb(NC)
AD18
MEM_WEb(NC)
AB13
MEM_CSb(NC)
AB18
MEM_ODT(NC)
MEM_CKE(NC)
V14
V15
MEM_CKN(NC)
MEM_CKP(NC)
W14
MEM_DM0(NC)
W17
MEM_DM1/DVO_D8(NC)
AE19
MEM_DQS0P/DVO_IDCKP(NC)
Y1 7
MEM_DQS0N/DVO_IDCKN(NC)
W18
MEM_DQS1P(NC)
AD20
MEM_DQS1N(NC)
AE21
MEM_DQ0/DVO_VSYNC(NC)
AA18
MEM_DQ1/DVO_HSYNC(NC)
AA20
MEM_DQ2/DVO_DE(NC)
AA19
MEM_DQ3/DVO_D0(NC)
Y1 9
MEM_DQ4(NC)
V17
MEM_DQ5/DVO_D1(NC)
AA17
MEM_DQ6/DVO_D2(NC)
AA15
MEM_DQ7/DVO_D4(NC)
Y1 5
MEM_DQ8/DVO_D3(NC)
AC20
MEM_DQ9/DVO_D5(NC)
AD19
MEM_DQ10/DVO_D6(NC)
AE22
MEM_DQ11/DVO_D7(NC)
AC18
MEM_DQ12(NC)
AB20
MEM_DQ13/DVO_D9(NC)
AD22
MEM_DQ14/DVO_D10(NC)
AC22
MEM_DQ15/DVO_D11(NC)
AD21
AE12
MEM_COMPN(NC)
MEM_COMPP(NC)
AD12
MEM_VREF(NC)
AE18
IOPLLVDD18(NC)
AE23
IOPLLVSS(NC)
AD23
IOPLLVDD(NC)
AE24
C338
0.1U_0402_16V4Z
C338
0.1U_0402_16V4Z
1
2
C88 0.1U_0402_16V4ZC88
1
0.1U_0402_16V4Z
2
C89
1U_0402_6.3V4Z
C89
1U_0402_6.3V4Z
1
2
C29 4.7U_0805_10V4ZC29 4.7U_0805_10V4Z
1 2
+
C27 330U_D2E_2.5VM
+
C27 330U_D2E_2.5VM
1
2
C340.1U_0402_16V4Z C340.1U_0402_16V4Z
1
2
C250.1U_0402_16V4Z C250.1U_0402_16V4Z
1
2
C930 1U_0402_6.3V4ZC930 1U_0402_6.3V4Z
1 2
C85
0.1U_0402_16V4Z
C85
0.1U_0402_16V4Z
1
2
C336
0.1U_0402_16V4Z
C336
0.1U_0402_16V4Z
1
2
C3430.1U_0402_16V4Z C3430.1U_0402_16V4Z
1
2
C612
4.7U_0805_10V4Z
C612
4.7U_0805_10V4Z
1
2
C47
4.7U_0805_10V4Z
C47
4.7U_0805_10V4Z
1
2
C925
0.1U_0402_16V4Z
C925
0.1U_0402_16V4Z
1
2
C30 10U_0805_10V4ZC30 10U_0805_10V4Z
1 2
C50
0.1U_0402_16V4Z
C50
0.1U_0402_16V4Z
1
2
C344
0.1U_0402_16V4Z
C344
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GMCH_CRT_VSYNC(11,22)
AUX_CAL(11)
SUS_STAT_R#(11) PLT_RST# (11,14,23,30,31,33)
GMCH_CRT_HSYNC(11,22)
+3VS
+3VS
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 STRAPS
Custom
13 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 STRAPS
Custom
13 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document N umber Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
RS880 STRAPS
Custom
13 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS880m)
0 : Enable (RS880M)
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
DFT_GPIO1: LOAD_EEPROM_STRAPS
RS780 DFT_GPIO1
RS780 use HSYNC to enable SIDE PORT
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS880M)
1 : Disable(RS880M)
RS780 use HSYNC to enable SIDE PORT
R560 3K _0402_5%R560 3K_0402_5%
12
R281 3K _0402_5%R281 3K_0402_5%
12
D29
CH751H-40_SC76@
D29
CH751H-40_SC76@
2 1
R559 3K _0402_5%@R559 3K_0402_5%@
12
R284 150_0402_1%@R284 150_0402_1%@
1 2
R282 3K _0402_5%
@
R282 3K _0402_5%
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
CLK_PCIE_VGA
CLK_PCIE_VGA#
PLT_RST#
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N15
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P10
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P[0..15](10)
PCIE_GTX_C_MRX_N[0..15](10)
PCIE_MTX_C_GRX_P[0..15](10)
PCIE_MTX_C_GRX_N[0..15](10)
CLK_PCIE_VGA(20)
CLK_PCIE_VGA#(20)
PLT_RST#
VGA_VARIBL (21,33)
VGA_ENVDD (21)
VGA_PWROK(44)
VGA_TXCLK+ (21)
VGA_TXCLK- (21)
VGA_TXOUT0+ (21)
VGA_TXOUT0- ( 21)
VGA_TXOUT1+ (21)
VGA_TXOUT1- ( 21)
VGA_TXOUT2+ (21)
VGA_TXOUT2- ( 21)
+VGA_PCIE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
PARK-S3 PCIE/LVDS
B
14 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
PARK-S3 PCIE/LVDS
B
14 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5972P
1.0
PARK-S3 PCIE/LVDS
B
14 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
add at 8/11
change at 8/11
C105 0.1U_0402_10V7K
VGA@
C105 0.1U_0402_10V7K
VGA@
1 2
C132 0.1U_0402_10V7K
VGA@
C132 0.1U_0402_10V7K
VGA@
1 2
10K_0402_5%
R907VGA@ R907VGA@
10K_0402_5%
1 2
C126 0.1U_0402_10V7K VGA@C126 0.1U_0402_10V7K VGA@
1 2
C101 0.1U_0402_10V7K VGA@C101 0.1U_0402_10V7K VGA@
1 2
R293 10K_0402_5%
PARK@
R293 10K_0402_5%
PARK@
12
LVTMDP
LVDS CONTROL
M9X-S2/S3 + Park-S3
U40F
PARK@
LVTMDP
LVDS CONTROL
M9X-S2/S3 + Park-S3
U40F
PARK@
DIGON
AB12
TXCLK_LN_DPE3N
TXCLK_LP_DPE3P
AK14
AL15
TXCLK_UN_DPF3N
TXCLK_UP_DPF3 P
AJ19
AH20
TXOUT_L0N_DPE2N
TXOUT_L0P_DPE2P
AJ15
AH16
TXOUT_L1N_DPE1N
TXOUT_L1P_DPE1P
AK16
AL17
TXOUT_L2N_DPE0N
TXOUT_L2P_DPE0P
AJ17
AH18
TXOUT_L3N
TXOUT_L3P
AK18
AL19
TXOUT_U0N_DPF2N
TXOUT_U0P_DPF2P
AK20
AL21
TXOUT_U1N_DPF1N
TXOUT_U1P_DPF1P
AJ21
AH22
TXOUT_U2N_DPF0N
TXOUT_U2P_DPF0P
AK22
AL23
TXOUT_U3N
TXOUT_U3P
AJ23
AK24
VARY_BL
AB11
R1591.27K_0402_1% VG A@ R1591.27K_0402_1% VGA@
1 2
C111 0.1U_0402_10V7K
VGA@
C111 0.1U_0402_10V7K
VGA@
1 2
C131 0.1U_0402_10V7K VGA@C131 0.1U_0402_10V7K VGA@
1 2
10K_0402_5%
R292VGA@ R292VGA@
10K_0402_5%
1 2
C123 0.1U_0402_10V7K VGA@C123 0.1U_0402_10V7K VGA@
1 2
C127 0.1U_0402_10V7K VGA@C127 0.1U_0402_10V7K VGA@
1 2
C133 0.1U_0402_10V7K VGA@C133 0.1U_0402_10V7K VGA@
1 2
C97 0.1U_0402_10V7K VGA@C97 0.1U_0402_10V7K VGA@
1 2
C135 0.1U_0402_10V7K
VGA@
C135 0.1U_0402_10V7K
VGA@
1 2
R127
0_0402_5%@
R127
0_0402_5%@
1 2
C106 0.1U_0402_10V7K VGA@C106 0.1U_0402_10V7K VGA@
1 2
C98 0.1U_0402_10V7K
VGA@
C98 0.1U_0402_10V7K
VGA@
1 2
C109 0.1U_0402_10V7K VGA@C109 0.1U_0402_10V7K VGA@
1 2
C113 0.1U_0402_10V7K
VGA@
C113 0.1U_0402_10V7K
VGA@
1 2
C125 0.1U_0402_10V7K
VGA@
C125 0.1U_0402_10V7K
VGA@
1 2
C124 0.1U_0402_10V7K VGA@C124 0.1U_0402_10V7K VGA@
1 2
C129 0.1U_0402_10V7K
VGA@
C129 0.1U_0402_10V7K
VGA@
1 2
0_0402_5%
R128VGA@ R128VGA@
0_0402_5%
1 2
C102 0.1U_0402_10V7K
VGA@
C102 0.1U_0402_10V7K
VGA@
1 2
C104 0.1U_0402_10V7K
VGA@
C104 0.1U_0402_10V7K
VGA@
1 2
C136 0.1U_0402_10V7K
VGA@
C136 0.1U_0402_10V7K
VGA@
1 2
C112 0.1U_0402_10V7K VGA@C112 0.1U_0402_10V7K VGA@
1 2
C100 0.1U_0402_10V7K
VGA@
C100 0.1U_0402_10V7K
VGA@
1 2
C108 0.1U_0402_10V7K VGA@C108 0.1U_0402_10V7K VGA@
1 2
C99 0.1U_0402_10V7K
VGA@
C99 0.1U_0402_10V7K
VGA@
1 2
U40
M93-S3
M93@
U40
M93-S3
M93@
C128 0.1U_0402_10V7K VGA@C128 0.1U_0402_10V7K VGA@
1 2
C107 0.1U_0402_10V7K
VGA@
C107 0.1U_0402_10V7K
VGA@
1 2
C110 0.1U_0402_10V7K VGA@C110 0.1U_0402_10V7K VGA@
1 2
C130 0.1U_0402_10V7K
VGA@
C130 0.1U_0402_10V7K
VGA@
1 2
C103 0.1U_0402_10V7K VGA@C103 0.1U_0402_10V7K VGA@
1 2
C83 0.1U_0402_10V7K
VGA@
C83 0.1U_0402_10V7K
VGA@
1 2
R3332K_0402_5% VGA@ R3332K_0402_5% VGA@
1 2
C134 0.1U_0402_10V7K VGA@C134 0.1U_0402_10V7K VGA@
1 2
PCI EXPRESS INTERFACE
CLOCK
CALIBRATION
M9X-S2/S3 + Park-S3
U40A
PARK@
PCI EXPRESS INTERFACE
CLOCK
CALIBRATION
M9X-S2/S3 + Park-S3
U40A
PARK@
PWRGOOD
N10
PCIE_CALRN
AA22
PCIE_CALRP
Y2 2
AK32
PCIE_REFCLKN
PCIE_REFCLKP
AK30
PCIE_RX0N
AE31
PCIE_RX0P
AF30
PCIE_RX10N
R31
PCIE_RX10P
T30
P28
PCIE_RX11P
PCIE_RX11N
R29
N31
PCIE_RX12P
PCIE_RX12N
P30
PCIE_RX13N
M2 8
PCIE_RX13P
N29
L31
PCIE_RX14N
PCIE_RX14P
M3 0
K30
PCIE_RX15P
PCIE_RX15N
L29
AD28
PCIE_RX1N
PCIE_RX1P
AE29
AC31
PCIE_RX2P
PCIE_RX2N
AD30
AB28
PCIE_RX3P
PCIE_RX3N
AC29
AA31
PCIE_RX4P
PCIE_RX4N
AB30
Y2 8
PCIE_RX5P
PCIE_RX5N
AA29
W31
PCIE_RX6P
PCIE_RX6N
Y3 0
V28
PCIE_RX7P
PCIE_RX7N
W29
U31
PCIE_RX8P
PCIE_RX8N
V30
T28
PCIE_RX9P
PCIE_RX9N
U29
PERSTB
AL27
PCIE_TX0N
PCIE_TX0P
AG31
AH30
PCIE_TX10N
PCIE_TX10P
U23
U24
PCIE_TX11N
PCIE_TX11P
T27
T26
PCIE_TX12N
PCIE_TX12P
T23
T24
PCIE_TX13N
PCIE_TX13P
P26
P27
PCIE_TX14N
PCIE_TX14P
P23
P24
PCIE_TX15N
PCIE_TX15P
N26
M2 7
PCIE_TX1N
PCIE_TX1P
AF28
AG29
PCIE_TX2N
PCIE_TX2P
AF26
AF27
PCIE_TX3N
PCIE_TX3P
AD26
AD27
PCIE_TX4N
PCIE_TX4P
AB25
AC25
PCIE_TX5N
PCIE_TX5P
Y2 4
Y2 3
PCIE_TX6N
PCIE_TX6P
AB26
AB27
PCIE_TX7N
PCIE_TX7P
Y2 6
Y2 7
PCIE_TX8N
PCIE_TX8P
W23
W24
PCIE_TX9N
PCIE_TX9P
U26
V27
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA_ENBKL
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_CLK
VGA_CRT_DATA
VGA_LCD_CLK
VGA_LCD_DATA
THM_ALERT#
VGA_SMB_CK2_R
GPU_THERMAL_D-
GPU_THERMAL_D+ VGA_SMB_DA2_R
GPU_THERMAL_D+
GPU_THERMAL_D-
GPIO21_BBEN
VGA_CRT_HSYNC2
GPU_GPIO9
GPU_GPIO13
GPU_GPIO12
GPU_GPIO0
GPU_GPIO2
GPU_GPIO1
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_VSYNC2
GPU_GPIO11
GPU_GPIO8
+VREFG_GPU
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO9
GPU_GPIO12
GPU_GPIO8
GPU_GPIO13
GPU_GPIO11
VGA_PWRSEL
VGA_CRT_HSYNC2
VGA_CRT_VSYNC2
GPIO21_BBEN TEST_EN
VGA_PWRSEL
GPIO28_TDO
GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS
GPIO26_TCK
GPU_GPIO4
GPU_GPIO3
GPU_GPIO3
GPU_GPIO4
TEST_EN
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
CLK_XTALIN
+DPC_VDD10
+DPC_PVDD
+DPC_PVDD
+DPC_VDD10
+DPC_VDD18
+DPC_VDD18
R_27M_SSC
XTALOUT_XTL
27MCLK_SSIC
CLK_XTALOUTXTALOU T_XTL
CLK_XTALIN 27MCLK_SSIC
R_27M_SSC
VRAM_ID0
VRAM_ID1
VRAM_ID2
+AVDD
+VDD1DI
+VDD2DI
+A2VDD
+A2VDDQ
+AVDD
+VDD1DI
+A2VDD
+VDD2DI
+A2VDDQ
VGA_SMB_DA2_R
VGA_SMB_CK2_R
THM_ALERT#
CLK_XTALOUT
CLK_XTALIN
VGA_LCD_DATA
VGA_LCD_CLK
GPU_GPIO8
VGA_ENBKL(33)
VGA_CRT_R (22)
VGA_CRT_G (22)
VGA_CRT_B (22)
VGA_CRT_HSYNC (22)
VGA_CRT_VSYNC (22)
VGA_CRT_CLK (22)
VGA_CRT_DATA (22)
VGA_LCD_CLK(21)
VGA_LCD_DATA(21)
VGA_PWRSEL(44)
GPIO21_BBEN(17)
27M_CLK(20)
TEST_EN(16)
ACIN(25,33, 39)
27M_SSC(20)
VRAM_ID0(16)
VRAM_ID1(16)
VRAM_ID2(16)
VGA_SMB_CK2 (33)
VGA_SMB_DA2 (33)
+3VS_VGA
+3VS_VGA
+1.8VS_VGA
+3VS_VGA
+3VS_VGA
+VGA_PCIE
+1.8VS_VGA
+1.8VS_VGA
+3VS_VGA
+DPLL_VDDC
+1.8VS_VGA +DPLL_PVDD
+1.8VS_VGA
+1.8VS_VGA
+1.8VS_VGA
+3VS_VGA
+1.8VS_VGA
+DPLL_PVDD
+DPLL_VDDC+VGA_PCIE
+3VS_VGA
+3VS_VGA
+3VS_VGA
+1.8VS_VGA
Title
Size Document Number Rev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PART Y WITHOUT PRIOR WR ITTEN CONSENT OF COM PAL ELECTRONICS, INC.
Issued Date
Deciphered D ate
LA-5972P
1.0
PARK-S3 Main Generic/MSIC
C
15 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PART Y WITHOUT PRIOR WR ITTEN CONSENT OF COM PAL ELECTRONICS, INC.
Issued Date
Deciphered D ate
LA-5972P
1.0
PARK-S3 Main Generic/MSIC
C
15 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet o f
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PART Y WITHOUT PRIOR WR ITTEN CONSENT OF COM PAL ELECTRONICS, INC.
Issued Date
Deciphered D ate
LA-5972P
1.0
PARK-S3 Main Generic/MSIC
C
15 49Thursday, December 10, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
VGA Thermal Sensor G781-1P8F
Closed to GPU
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
HSYNCAUD[1]
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
ENABLE EXTERNAL BIOS ROM
GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB
GPIO1TX_DEEMPH_EN PCIE TRANSMI TTER DE-EMPHASIS ENABLED
GPIO9 VGA EN ABLEDBIF_VGA DIS
VIP_DEVICE_STRAP_ENA V2SYN C IGNORE VIP DEVICE STRAPS
GPIO_22_ROMCSB
GPIO2
STRAPS
PCIE GNE2 ENABLED
DESCRIPTION OF DEFAULT SETTINGSPIN
GPIO[13:11]ROMIDCFG(2:0)
RECOMMENDED SETTINGS
BIF_GEN2_EN_A
SERIAL ROM TYPE OR MEMORY APERT URE SIZE SELECT
CONFIGURATION STRAPS
BIOS_ROM_EN
VSYNCAUD[0]
H2SYNC
GPIO8
GPIO21
GENERICC
0
0
0
0
0
0
11
0
001
0
0
0
H2SYNC
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
GENERICC
GPIO21_BB_EN
AMD RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
STRAPS
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
Spread Spectrum For EMI
08/11
300mA
120mA
70mA
45mA
130mA
50mA
1.5mA
add at 8/11
add at 8/11
add at 8/11
EMI request
add at 8/17
20mA
200mA
130mA
C1008
1U_0402_6.3V4Z
PARK@
C1008
1U_0402_6.3V4Z
PARK@
1
2
R217 10K_0402_5%VGA@R217 10K_0402_5%VGA@
12
R481
499_0402_1%
VGA@
R481
499_0402_1%
VGA@
1 2
R713
10K_0402_5%
VGA@
R713
10K_0402_5%
VGA@
12
C696
1U_0402_6.3V4Z
VGA@
C696
1U_0402_6.3V4Z
VGA@
1
2
C1022
22P_0402_50V8J VGA@
C1022
22P_0402_50V8J VGA@
1
2
R843
0_0402_5%
R843
@ 0_0402_5%@
1 2
R1018 10K_0402_5%@ R1018 10K_0402_5%@
12
C1014
1U_0402_6.3V4Z
VGA@
C1014
1U_0402_6.3V4Z
VGA@
1
2
R230 10K_0402_5%@R230 10K_0402_5%@
12
C950
1U_0402_6.3V4Z
@
C950
1U_0402_6.3V4Z
@
1
2
L40
BLM15BD121SN1D_0402
PARK@
L40
BLM15BD121SN1D_0402
PARK@
12
L99
BLM15BD121SN1D_0402
PARK@
L99
BLM15BD121SN1D_0402
PARK@
12
R294 10K_0402_5%@R294 10K_0402_5%@
1 2
L97
BLM15BD121SN1D_0402
VGA@
L97
BLM15BD121SN1D_0402
VGA@
12
C57
0.1U_0402_10V6K
VGA@
C57
0.1U_0402_10V6K
VGA@
1
2
R840
0_0402_5%
R840
@ 0_0402_5%@
1 2
C1004
10U_0603_6.3V6M
PARK@
C1004
10U_0603_6.3V6M
PARK@
1
2
C1006
0.1U_0402_10V6K
PARK@
C1006
0.1U_0402_10V6K
PARK@
1
2
R108 10K_0402_5%@R108 10K_0402_5%@
12
R303 10K_0402_5%@R303 10K_0402_5%@
1 2
R234 10K_0402_5%@R234 10K_0402_5%@
12
C949
0.1U_0402_10V6K
@
C949
0.1U_0402_10V6K
@
1
2
R311
150_0402_1%
VGA@
R311
150_0402_1%
VGA@
12
C1010
10U_0603_6.3V6M
PARK@
C1010
10U_0603_6.3V6M
PARK@
1
2
Q54A
2N7002DW-T/R7_SOT363-6
VGA@
Q54A
2N7002DW-T/R7_SOT363-6
VGA@
61
2
C1012
0.1U_0402_10V6K
PARK@
C1012
0.1U_0402_10V6K
PARK@
1
2
C694
1U_0402_6.3V4Z
VGA@
C694
1U_0402_6.3V4Z
VGA@
1
2
T69 PADT69 PAD
L23
BLM15BD121SN1D_0402
VGA@
L23
BLM15BD121SN1D_0402
VGA@
12
R332
249_0402_1%
VGA@
R332
249_0402_1%
VGA@
12
R315
10K_0402_5%
VGA@
R315
10K_0402_5%
VGA@
1 2
R305 10K_0402_5%@R305 10K_0402_5%@
1 2
R231 10K_0402_5%@R231 10K_0402_5%@
12
C708
2200P_0402_50V7K
VGA@C708
2200P_0402_50V7K
VGA@
1 2
C322
10U_0603_6.3V6M
PARK@
C322
10U_0603_6.3V6M
PARK@
1
2
C1003
0.1U_0402_10V6K
VGA@
C1003
0.1U_0402_10V6K
VGA@
1
2
R908
715_0402_1%
VGA@R908
715_0402_1%
VGA@
1 2
C1040
10U_0603_6.3V6M
@
C1040
10U_0603_6.3V6M
@
1
2
R714
10K_0402_5%
VGA@
R714
10K_0402_5%
VGA@
12
C999
0.1U_0402_10V6K
VGA@
C999
0.1U_0402_10V6K
VGA@
1
2
D4
RB751V_SOD323@
D4
RB751V_SOD323@
21
R482
499_0402_1%
VGA@R482
499_0402_1%
VGA@
1 2
C1015
10U_0603_6.3V6M
VGA@
C1015
10U_0603_6.3V6M
VGA@
1
2
R287 10K_0402_5%@R287 10K_0402_5%@
1 2
C1009
0.1U_0402_10V6K
PARK@
C1009
0.1U_0402_10V6K
PARK@
1
2
C951
10U_0603_6.3V6M
VGA@
C951
10U_0603_6.3V6M
VGA@
1
2
C324
10U_0603_6.3V6M
VGA@
C324
10U_0603_6.3V6M
VGA@
1
2
C953
0.1U_0402_10V6K
VGA@
C953
0.1U_0402_10V6K
VGA@
1
2
C1042
0.1U_0402_10V6K
VGA@
C1042
0.1U_0402_10V6K
VGA@
1
2
C55
0.1U_0402_10V6K
VGA@
C55
0.1U_0402_10V6K
VGA@
1
2
R297 10K_0402_5%@R297 10K_0402_5%@
1 2
C1007
10U_0603_6.3V6M
PARK@
C1007
10U_0603_6.3V6M
PARK@
1
2
C1013
0.1U_0402_10V6K
VGA@
C1013
0.1U_0402_10V6K
VGA@
1
2
Y6
27MHZ_20P_7A27000010
VGA@
Y6
27MHZ_20P_7A27000010
VGA@
1 2
C1021
22P_0402_50V8J VGA@
C1021
22P_0402_50V8J VGA@
1
2
R300
10K_0402_5%
@R300
10K_0402_5%
@
1 2
C1001
10U_0603_6.3V6M
VGA@
C1001
10U_0603_6.3V6M
VGA@
1
2
C58
0.1U_0402_10V6K
VGA@
C58
0.1U_0402_10V6K
VGA@
1
2
R236 10K_0402_5%@R236 10K_0402_5%@
12
R235 10K_0402_5%@R235 10K_0402_5%@
12
R301
10K_0402_5%
@R301
10K_0402_5%
@
1 2
C998
1U_0402_6.3V4Z
VGA@
C998
1U_0402_6.3V4Z
VGA@
1
2
L98
BLM15BD121SN1D_0402
PARK@
L98
BLM15BD121SN1D_0402
PARK@
12
R483 5.11K_0402_1%@R483 5.11K_0402_1%@
1 2
R842
0_0402_5%@
R842
0_0402_5%@
1 2
R582 82.5_0402_1%
@
R582
@
82.5_0402_1%
12
C1041
1U_0402_6.3V4Z
@
C1041
1U_0402_6.3V4Z
@
1
2
U26
G780P81U_MSOP8
VGA@
U26
G780P81U_MSOP8
VGA@
VDD1
1
ALERT#
6
THERM#
4
GND
5
2
D+
D-
3
SCLK
8
SDATA
7
R841
33_0402_1% @
R841
33_0402_1% @
1 2
R160
100_0402_1%
@
R160
100_0402_1%
@
12
L101
BLM15BD121SN1D_0402
VGA@
L101
BLM15BD121SN1D_0402
VGA@
12
C137
0.1U_0402_16V4Z
VGA@
C137
0.1U_0402_16V4Z
VGA@
1
2
R972
1M_0402_5%
VGA@
R972
1M_0402_5%
VGA@
12
R233 10K_0402_5%@R233 10K_0402_5%@
12
C323
10U_0603_6.3V6M
VGA@
C323
10U_0603_6.3V6M
VGA@
1
2
C1011
1U_0402_6.3V4Z
PARK@
C1011
1U_0402_6.3V4Z
PARK@
1
2
R3404.7K_0402_5% VGA@ R3404. 7K_0402_5% VGA@
12
R299 10K_0402_5%@R299 10K_0402_5%@
1 2
C1005
1U_0402_6.3V4Z
PARK@
C1005
1U_0402_6.3V4Z
PARK@
1
2
R215 10K_0402_5%@R215 10K_0402_5%@
12
R228 10K_0402_5%@R228 10K_0402_5%@
12
R216 10K_0402_5%@R216 10K_0402_5%@
12
R341 4.7K_0402_5%VGA@R341 4.7K_0402_5%VGA@
12
R232 10K_0402_5%VGA@R232 10K_0402_5%VGA@
12
L100
BLM15BD121SN1D_0402
PARK@
L100
BLM15BD121SN1D_0402
PARK@
12
C1000
10U_0603_6.3V6M
VGA@
C1000
10U_0603_6.3V6M
VGA@
1
2
R308
150_0402_1%
VGA@
R308
150_0402_1%
VGA@
12
L96
BLM15BD121SN1D_0402
VGA@
L96
BLM15BD121SN1D_0402
VGA@
12
R342 4.7K_0402_5%VGA@R342 4.7K_0402_5%VGA@
12
C56
0.1U_0402_10V6K
PARK@
C56
0.1U_0402_10V6K
PARK@
1
2
C1002
1U_0402_6.3V4Z
VGA@
C1002
1U_0402_6.3V4Z
VGA@
1
2
C952
1U_0402_6.3V4Z
VGA@
C952
1U_0402_6.3V4Z
VGA@
1
2
Q54B
2N7002DW-T/R7_SOT363-6
VGA@Q54B
2N7002DW-T/R7_SOT363-6
VGA@
3
5
4
R309
150_0402_1%
VGA@
R309
150_0402_1%
VGA@
12
L24
BLM15BD121SN1D_0402
VGA@
L24
BLM15BD121SN1D_0402
VGA@
12
U46
ASM3P2872AF-06OR_TSOT-23-6@
U46
ASM3P2872AF-06OR_TSOT-23-6@
XIN/CLKIN
3
VSS
6
MODOUT
5
VDD
4
REFOUT
1
XOU T
2
C695
1U_0402_6.3V4Z
PARK@
C695
1U_0402_6.3V4Z
PARK@
1
2
R310
150_0402_1%
VGA@
R310
150_0402_1%
VGA@
12
R298 10K_0402_5%@R298 10K_0402_5%@
1 2
L83
BLM15BD121SN1D_0402
VGA@
L83
BLM15BD121SN1D_0402
VGA@
12
R229 10K_0402_5%@R229 10K_0402_5%@
12
R302 10K_0402_5%@R302 10K_0402_5%@
1 2
DPA
DPB
DVO
I2C
GENERAL PURPOSE I/O
DAC1
DAC2
DDC/AUX
THERMAL
PLL/CLOCK
DPC
M92-S2/M93-S3
M92-S2/M93-S3
M93-S3/M92-S2
M93-S3/M92-S2
M92-S2/M93-S3M92-S2/M93-S3
M9X-S2/S3 + Park-S3
U40B
PARK@
DPA
DPB
DVO
I2C
GENERAL PURPOSE I/O
DAC1
DAC2
DDC/AUX
THERMAL
PLL/CLOCK
DPC
M92-S2/M93-S3
M92-S2/M93-S3
M93-S3/M92-S2
M93-S3/M92-S2
M92-S2/M93-S3M92-S2/M93-S3
M9X-S2/S3 + Park-S3
U40B
PARK@
DMINUS
T2
AF1 4
DPLL_PVSS
DPLL_PVDD
AE14
DPLL_VDDC
AD14
DPLUS
T4
DPC_VSSR#1 / DVPCLK
U1
DVDATA_7 / DVPCNTL_0
AC7
DVPCNTL_1 / TX2M_DPC0N
Y2
DVPCNTL_2/TXCCM_DPC3N
U5
DPC_VSSR#5/ DVPCNT L_MV0
AA1
DVPCNTL_MV1 / T X1P_DPC1P
Y4
DVDATA_0 / DVPDAT A_0
Y7
DVPDATA_1 / T X0M_DPC2N
V2
DPC_VDD18#1/DVPDAT10
AC6
DPC_PVDD / DVPDATA_ 11
W6
DVDATA_9 / DVPDAT A_12
AD7
DVPDATA_13 / T X2P_DPC0P
AA3
DVDATA_8 / DVPDAT A_14
AC8
DPC_VDD10#1/DVPDAT15
AA5
DVDATA_12 / DVPDAT A_16
AE8
DPC_VDD10#2/DVPDAT17
AA6
DVCNTL_0/ DVPDATA_18
AE9
DVDATA_3 / DVPDAT A_19
AB4
DVDATA_1 / DVPDAT A_2
Y8
DVDATA_11 / DVPDAT A_20
AD9
DVDATA_2 / DVPDAT A_21
AB2
DVDATA_10 / DVPDAT A_22
AC10
DPC_VDD18#2/DVPDAT23
AC5
DVPDATA_3/TXCC P_DPC3P
V4
DVDATA_4 DVPDAT A_4
AB7
DPC_VSSR#2 / DVPDAT 5
W1
DVDATA_5 / DVPDAT A_6
AB8
DVPDATA_7 / T X0P_DPC2P
W3
DVDATA_6 / DVPDAT A_8
AB9
DVPDATA_9 / T X1M_DPC1N
W5
AB13
GENERICA
W8
GENERICB
W9
GENERICC
W7
GENERICE_HPD4
GENERICD
AD10
GPIO_0
GPIO_1
U6
U10
P2
GPIO_10_ROMSCK
N6
GPIO_11
N5
GPIO_12
N3
GPIO_13
Y9
GPIO_14_HPD2
N1
GPIO_15_PWRCNTL_0
M4
GPIO_16_SSIN
R6
GPIO_17_THERMAL_INT
W10
GPIO_19_CTF
GPIO_18_HPD3
M2
GPIO_2
T10
P8
GPIO_20_PWRCNTL_1
P7
GPIO_21_BB_EN
N8
GPIO_23_CLKREQB
GPIO_22_ROMCSB
N7
U8
GPIO_3_SMBDATA
U7
GPIO_4_SMBCLK
T9
GPIO_5_AC_BATT
T8
GPIO_6
T7
GPIO_7_BLON
P10
GPIO_9_ROMSI
GPIO_8_ROMSO
P4
H2SYNC
AL13
HPD1
AC14
HSYNC
AH26
L3
JTAG_TDI
JTAG_TCK
L5
K4
JTAG_TMS
JTAG_TDO
L1
JTAG_TRSTB
L6
NC/DDCDATA_AUX3N
NC/DDCCLK_AUX3P
AC20
AD20
R5
TS_FDO
AD17
TSVSS
TSVDD
AC17
VREFG
AC16
VSS1DI
AD23
VSS2DI / NC
AC19
AM28
XTALOUT
XTALIN
AK28
A2VDD / NC
AE20
A2VDDQ / NC
AE17
A2VSSQ
AE19
AUX1N
AUX1P
AD4
AD2
AUX2N
AUX2P
AD11
AD13
AVDD
AG2 4
AVSSQ
AE22
B
AH24
B2 / NC
AK10
B2B / NC
AL9
BB
AG2 5
C / NC
AH12
COMP / NC
AJ9
DDC1CLK
AE6
DDC1DATA
AE5
DDC2CLK
AC11
DDC2DATA
AC13
DDC6CLK
AC1
DDC6DATA
AC3
DDCDATA_AUX5N
DDCCLK_AUX5P
AD16
AE16
G
AL25
G2 / NC
AL11
G2B / NC
AJ1 1
GB
AJ2 5
R
AM26
R2 / NC
AM12
R2B / NC
AK12
R2SET / NC
AG1 3
RB
AK26
RSET
AD22
R1
SDA
SCL
R3
TX0M_DPA2N
TX0P_DPA2P
AG5
AG3
TX1M_DPA1N
AH1
TX1P_DPA1P
AH3
TX2M_DPA0N
TX2P_DPA0P
AK1
AK3
TX3M_DPB2N
TX3P_DPB2P
AM5
AK6
TX4M_DPB1N
TX4P_DPB1P
AH6
AJ7
TX5M_DPB0N
TX5P_DPB0P
AL7
AK8
TXCAM_DPA3N
TXCAP_DPA3P
AF4
AF2
TXCBM_DPB3N
TXCBP_DPB3P
AM3
AK5
V2SYNC
AJ1 3
VDD1DI
AE23
VDD2DI / NC
AD19
VSYNC
AJ2 7
Y / NC
AM10
AB22
NC#2/XO_IN
NC#1/XO_IN2
AC22
TESTEN
AF2 4
VDDR4 / DPCD_CALR
AA12
DVCNTL_2 / TESTEN#2
N9
DPC_VSSR#3 / GND
U3
DPC_PVSS / GND
V6
DPC_VSSR#4 / GND
Y6
DVCNTL_1 / NC
L9
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