Compal LA-4031P, Compaq Presario C700, G7000 Schematic

1

2

3

4

A

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Satna Rosa Platform

2007-07-30

REV:0.2

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/07/26

Title

Cover Sheet

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet

1

o f

42

A

B

C

D

E

1

2

3

4

PCB

File Name : LA-4031P

Compal confidential Spartan 1.1 (Merom +Crestline+ICH8)

ZZZ1

A

B

C

D

E

1

2

3

4

Fan Control

Mobile Yonah/Merom

1

Thermal Sensor

Clock Generator

page 4

uFCPGA-478 CPU

Socket P

ADM1032AR

ICS9LPRS355

page 4,5,6

page 4

page 15

FSB

H_A#(3..31)

533/667/800MHz

H_D#(0..63)

CRT/TV-OUT

NB Crestline

DDR2 -400/533/667

DDR2-SO-DIMM X2

page 16

BANK 0, 1, 2, 3

page 13,14

LVDS Conn

page 7,8,9,10,11,12

Dual Channel

page 17

							2
						USB Card Reader
			DMI			page 27
						USB Conn
						page 27
		PCI BUS		USB2.0			MODEM AMOM
			SB ICH8	AC-LINK/Azalia		Audio Conexant	CX20548
		PCI-E BUS					page 25
	Realtek					CX20561-12Z
						page 24	AMP & Audio Jack
LED	RTL8100CL
			page 18,19,20,21		SATA		ENE P3017 page 26
	page 23					SATA HDD Connector
page 28
		Mini-Card				page 22	3
RTC CKT.	RJ45/11 CONN	WLAN			PATA Master	IDE ODD Connector
page 19	page 23	page 22				page 22
			LPC BUS
Power On/Off CKT.			ENE KB926	SPI	SPI ROM
					25LF080A
page 28			page 30		page 29
DC/DC Interface CKT.		Touch Pad CONN.		Int.KBD
		page 28		page 30			4
page 31

Power Circuit DC/DC

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/07/26

Title

Block Diagram

Page 32,33,34,35,36,37,38

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

Rev

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Custom

LA-4031P

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet

2

o f

42

A

B

C

D

E

D

C

B

A

5

4

3

2

1

Voltage Rails

+5VS

power

+3VS

+1.5VS

plane

+B

+5VALW

+1.8V

+3VALW

+1.25VS

State

+0.9V

D

+VCCP

+CPU_CORE

Symbol Note :

S0

O

O

O

O

: means Digital Ground

S1

O

O

O

O

: means Analog Ground

S3

O

O

O

X

@ : means just reserve , no build

S5 S4/AC

O

O

X

X

DEBUG@ : means just reserve for debug.

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery

X

X

X

X

don't exist

C

External PCI Devices

DEVICE

IDSEL #

REQ/GNT #

PIRQ

LAN

AD17

0

A

SMBUS Control Table

B

I2C / SMBUS ADDRESSING

SERIAL

THERMAL

SOURCE

INVERTER

BATT

SENSOR

SODIMM

CLK CHIP

MINI CARD

LCD

EEPROM

(CPU)

ADM1032

DEVICE

HEX

ADDRESS

SMB_EC_CK1

KB925

X

V

V

X

X

X

X

X

DDR SO-DIMM 0

A0

1 0 1 0 0 0 0 0

SMB_EC_DA1

DDR SO-DIMM 1

A4

1 0 1 0 0 1 0 0

SMB_EC_CK2

KB925

X

X

X

V

X

X

X

X

CLOCK GENERATOR (EXT.)

D2

1 1 0 1 0 0 1 0

SMB_EC_DA2

SMB_CK_CLK1

ICH8

X

X

X

X

V

V

V

X

SMB_CK_DAT1

LCD_CLK

X

X

X

X

X

X

X

V

LCD_DAT

Crestline

BOM: 43152432L03(965GM) & 43152432L04(960GML) with card reader

A

BOM: 43152432L01(965GM) & 43152432L02(960GML) without card reader

Jump-Short: PJP?

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

Deciphered Date

2007/03/26

2006/07/26

Title

Notes List

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

Rev

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-4031P

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet 3 o f 42

5

4

3

2

1

5

4

3

2

1

D

C

B

A

7

H_A#[3..16]

JP2A

H_A#3

J4

H1

H_ADS#

A[3]#

ADDR

ADS#

H_ADS#

7

H_A#6

K5

E2

H_BNR#

A[5]#

BPRI#

H_BPRI#

7

H_A#4

L5

A[4]#

BNR#

H_BNR#

7

H_A#5

L4

G5

H_BPRI#

H_A#7

M3

A[6]#

0GROUP

DEFER#

H5

H_DEFER#

H_DEFER# 7

A[10]#

R10

H_A#11

P5

F1

H_BR0#

H_A#8

N2

A[7]#

F21

H_D RDY#

H_A#9

J1

A[8]#

DRDY#

E1

H_DBSY#

H_DRDY# 7

H_A#10

N3

A[9]#

DBSY#

H_DBSY# 7

H_A#12

P2

A[11]#

BR0#

H_BR0#

7

56_0402_5%

H_A#13

L2

A[12]#

CONTROLLOCK#

D20

H_IERR#

2

1

+VCCP

A[16]#

H_LOCK# 7

1

H_ADSTB#0

M1

2

H_A#14

P4

A[13]#

IERR#

B3

H_INIT#

H_INIT#

19

H_A#15

P1

A[14]#

INIT#

H_A#16

R1

A[15]#

H4

H_LOCK#

C2

0.1U_0402_16V4Z

7

H_ADSTB#0

ADSTB[0]#

RESET#

C1

H_RESET#

H_RESET# 7

H_REQ#0

K3

F3

H_RS#0

7

H_REQ#0

REQ[0]#

RS[0]#

H_RS#0 7

H_REQ#1

H2

F4

H_RS#1

7

H_REQ#1

REQ[1]#

RS[1]#

H_RS#1 7

H_REQ#2

K2

G3

H_RS#2

7

H_REQ#2

REQ[2]#

RS[2]#

H_RS#2 7

H_REQ#3

J3

G2

H_TRDY#

7

H_REQ#3

REQ[3]#

TRDY#

H_TRDY# 7

H_REQ#4

L1

7

H_REQ#4

REQ[4]#

G6

H_HIT#

7

H_A#[17..35]

HIT#

H_HIT#

7

H_A#17

Y2

E4

H_HITM#

A[17]#

HITM#

H_HITM#

7

H_A#18

U5

A[18]#

H_A#19

R3

AD4

A[19]#

1GROUPADDR

BPM[0]#

H_A#20

W6

AD3

A[20]#

BPM[1]#

H_A#21

U4

SIGNALSXDP/ITP

AD1

A[29]#

TRST#

XDP_TRST#

H_A#29

Y4

AB6

H_A#22

Y5

A[21]#

BPM[2]#

AC4

H_A#23

U1

A[22]#

BPM[3]#

AC2

H_A#24

R4

A[23]#

PRDY#

AC1

H_A#25

T5

A[24]#

PREQ#

AC5

XDP_TCK

H_A#26

T3

A[25]#

TCK

AA6

XDP_TDI

A[26]#

TDI

H_A#27

W2

AB3

A[27]#

TDO

H_A#28

W5

AB5

XDP_TMS

A[28]#

TMS

H_A#30

U2

A[30]#

DBR#

C20

DBRESET# 1

@R413 2

XDP_DBRESET#

XDP_DBRESET# 20

H_A#31

V4

0_0402_5%

A[31]#

H_PROCHOT# 37

H_A#32

W3

R13

A[32]#

H_A#33

AA4

THERMAL

H_PROCHOT#

2

1

+VCCP

A[33]#

H_A#34

AB2

68_0402_5%

A[34]#

H_A#35

AA3

D21

A[35]#

PROCHOT#

7

H_ADSTB#1

H_ADSTB#1

V1

A24

H_THERMDA_R1

R14

2

0_0402_5%

H_THERMDA

ADSTB[1]#

THERMDA

B25

H_THERMDC_R1

R15

2

0_0402_5%

H_THERMDC

H_A20M#

A6

THERMDC

19

H_A20M#

A20M#

ICH

C7

H_THERMTRIP#

H_IGNNE#

C4

19

H_FERR#

H_FERR#

A5

FERR#

THERMTRIP#

H_THERMTRIP# 7,19

19

H_IGNNE#

IGNNE#

19

H_STPCLK#

H_STPCLK#

D5

STPCLK#

19

H_INTR

H_INTR

C6

LINT0

H CLK

H_NMI

A22

CLK_CPU_BCLK

19

H_NMI

B4

LINT1

BCLK[0]

CLK_CPU_BCLK 15

19

H_SMI#

H_SMI#

A3

SMI#

BCLK[1]

A21

CLK_CPU_BCLK#

CLK_CPU_BCLK# 15

M4

RSVD[01]

H_THERMDA, H_THERMDC routing together,

N5

RSVD[02]

T2

RSVD[03]

Trace width / Spacing = 10 / 10 mil

V3

B2

RSVD[04]

RESERVED

RSVD[05]

F6

C3

RSVD[06]

For Merom, R14 and R15 are 0ohm

D22

RSVD[07]

D2

RSVD[09]

For Penryn, R14 and R15 are 100ohm.

D3

RSVD[08]

RSVD[10]

Merom Ball-out Rev 1a

CONN@

+VCCP	SP07000FP00	S	SOCKET	TYCO 2-1871873-2 478P H3 CPU	+3VS
	SP07000FD00	S	SOCKET	FOXCONN PZ4782A-274M-41 478P H3

1

R17

1

@R416

@56_0402_5%

10K_0402_5%

2

H_PROCHOT#

E

2B

1

OCP#

2

3

OCP#

20

@Q2

C

@R415 0_0402_5%

MMBT3904_SOT23

L_THERM#

1

2

THERM#

+VCCP

XDP_TDI	R2	1		2	15_0402_5%
XDP_TMS	R3	1		2	39_0402_1%
XDP_TRST#	R7	1		2	560_0402_5%
XDP_TCK	R8	1	2		27_0402_5%

Thermal Sensor ADM1032ARMZ

+3VS

R414

1

2

2

0_0402_5%

C3

+3VS

0.1U_0402_16V4Z

1

1

U1

1

8

SMB_EC_CK2

R426

VDD

SCLK

10K_0402_5%

H_THERMDA

2

7

SMB_EC_DA2

C4

D+

SDATA

@

2

1

H_THERMDC

3

6

2

D-

ALERT#

2200P_0402_50V7K

L_THERM#

4

5

1

THERM#

GND

R427

1

R16

2

ADM1032ARMZ-2REEL_MSOP8

10K_0402_5%

+3VS

@

10K_0402_5%

Address:100_1100

2

30 SMB_EC_DA2

SMB_EC_DA2

SMB_EC_CK2

30 SMB_EC_CK2

PWM Fan Control circuit

+5VS

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25

ACES_85204-02001_2P

1

1

1

1

JP3

D1

C5

C6

1

2

2

0.1U_0402_16V4Z

3

R405

0_0402_5%

RB751V_SOD323 2 4.7U_0805_10V4Z 2

G1

4

G2

1

2

2

ACES_85204-02001

+3VS

F AN

CONN@

@U2

1 2 5 6

1

5

D Q1

@ D26

1

P

G

30

FAN_PWM

INB

O

4

3

RLZ5.1B_LL34

THERM#

2

S

SI3456BDV-T1-E3_TSOP6

INAG

2

4

TC7SH00FU_SSOP5

3

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

Merom(1/3)-AGTL+/XDP

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet

4

o f

42

5

4

3

2

1

D

C

B

A

D

C

B

A

5

4

3

2

1

+VCC_CORE

+VCC_CORE

7

H_D#[0..15]

JP2B

H_D#[32..47]

7

JP2C

H_D#0

E22

Y22

H_D#32

A7

AB20

D[0]#

D[32]#

VCC[001]

VCC[068]

H_D#1

F24

AB24

H_D#33

A9

AB7

D[1]#

D[33]#

VCC[002]

VCC[069]

H_D#2

E26

V24

H_D#34

A10

AC7

D[2]#

D[34]#

VCC[003]

VCC[070]

H_D#3

G22

V26

H_D#35

A12

AC9

D[3]#

DATA

D[35]#

VCC[004]

VCC[071]

H_D#4

F23

V23

H_D#36

A13

AC12

D[4]#

D[36]#

VCC[005]

VCC[072]

H_D#5

G25

T22

H_D#37

A15

AC13

D[5]#

D[37]#

VCC[006]

VCC[073]

H_D#6

E25

U25

H_D#38

A17

AC15

H_D#7

E23

D[6]#

GRP

D[38]#

U23

H_D#39

A18

VCC[007]

VCC[074]

AC17

D[7]#

D[39]#

VCC[008]

VCC[075]

H_D#8

K24

2

Y25

H_D#40

A20

AC18

D[8]#

D[40]#

VCC[009]

VCC[076]

H_D#9

G24

D[9]#

0

GRP

D[41]#

W22

H_D#41

B7

VCC[010]

VCC[077]

AD7

H_D#10

J24

Y23

H_D#42

B9

AD9

D[10]#

D[42]#

VCC[011]

VCC[078]

H_D#11

J23

W24

H_D#43

B10

AD10

H_D#12

H22

D[11]#

DATA

D[43]#

W25

H_D#44

B12

VCC[012]

VCC[079]

AD12

D[12]#

D[44]#

VCC[013]

VCC[080]

H_D#13

F26

AA23

H_D#45

B14

AD14

D[13]#

D[45]#

VCC[014]

VCC[081]

H_D#14

K22

AA24

H_D#46

B15

AD15

H_D#15

H23

D[14]#

D[46]#

AB25

H_D#47

B17

VCC[015]

VCC[082]

AD17

D[15]#

D[47]#

VCC[016]

VCC[083]

7

H_DSTBN#0

H_DSTBN#0

J26

Y26

H_DSTBN#2

H_DSTBN#2 7

B18

AD18

DSTBN[0]#

DSTBN[2]#

VCC[017]

VCC[084]

H_DSTBP#0

H26

AA26

H_DSTBP#2

B20

AE9

7

H_DSTBP#0

DSTBP[0]#

DSTBP[2]#

H_DSTBP#2 7

VCC[018]

VCC[085]

H_DINV#0

H25

U22

H_DINV#2

C9

AE10

7

H_DINV#0

DINV[0]#

DINV[2]#

H_DINV#2 7

VCC[019]

VCC[086]

C10

AE12

7

H_D#[16..31]

H_D#[48..63]

7

VCC[020]

VCC[087]

C12

AE13

H_D#16

H_D#48

VCC[021]

VCC[088]

N22

AE24

C13

AE15

D[16]#

D[48]#

VCC[022]

VCC[089]

H_D#17

K25

AD24

H_D#49

C15

AE17

D[17]#

D[49]#

VCC[023]

VCC[090]

H_D#18

P26

AA21

H_D#50

C17

AE18

D[18]#

D[50]#

VCC[024]

VCC[091]

H_D#19

R23

AB22

H_D#51

C18

AE20

D[19]#

D[51]#

VCC[025]

VCC[092]

H_D#20

L23

AB21

H_D#52

D9

AF9

D[20]#

DATA

D[52]#

VCC[026]

VCC[093]

H_D#21

M24

AC26

H_D#53

D10

AF10

D[21]#

D[53]#

VCC[027]

VCC[094]

H_D#22

L22

AD20

H_D#54

D12

AF12

D[22]#

D[54]#

VCC[028]

VCC[095]

H_D#23

M23

AE22

H_D#55

D14

AF14

H_D#24

P25

D[23]#

GRP

D[55]#

AF23

H_D#56

D15

VCC[029]

VCC[096]

AF15

H_D#25

P23

D[24]#

D[56]#

AC25

H_D#57

D17

VCC[030]

VCC[097]

AF17

D[25]#

D[57]#

VCC[031]

VCC[098]

H_D#26

P22

D[26]#

1

3

D[58]#

AE21

H_D#58

D18

VCC[032]

VCC[099]

AF18

+VCCP

H_D#27

T24

D[27]#

GRP

D[59]#

AD21

H_D#59

E7

VCC[033]

VCC[100]

AF20

H_D#28

R24

AC22

H_D#60

E9

R18

0_0402_5%

D[28]#

D[60]#

VCC[034]

H_D#29

L25

AD23

H_D#61

E10

VCCP[01]

G21

2

1

H_D#30

T25

D[29]#

DATA

D[61]#

AF22

H_D#62

E12

VCC[035]

V6

2

1

D[30]#

D[62]#

VCC[036]

VCCP[02]

1

H_DSTBN#1

L26

AE25

H_DSTBN#3

E15

K6

H_D#31

N25

D[31]#

D[63]#

AC23

H_D#63

E13

VCC[037]

VCCP[03]

J6

R19

0_0402_5%

7

H_DSTBN#1

H_DSTBP#1

M26

DSTBN[1]#

DSTBN[3]#

AF24

H_DSTBP#3

H_DSTBN#3 7

E17

VCC[038]

VCCP[04]

M6

7

H_DSTBP#1

DSTBP[1]#

DSTBP[3]#

H_DSTBP#3 7

VCC[039]

VCCP[05]

+

C7

H_DINV#1

N24

AC20

H_DINV#3

E18

J21

7

H_DINV#1

DINV[1]#

DINV[3]#

H_DINV#3 7

E20

VCC[040]

VCCP[06]

K21

220U_6.3V_M

V_CPU_GTLREF

COMP0

VCC[041]

VCCP[07]

AD26

R26

F7

M21

GTLREF

COMP[0]

VCC[042]

VCCP[08]

2

R20

1

2 @ 1K_0402_5%

TEST1

C23

MISC

U26

COMP1

F9

N21

TEST1

COMP[1]

VCC[043]

VCCP[09]

R21

1

2

@ 1K_0402_5%

TEST2

D25

TEST2

COMP[2]

AA1

COMP2

F10

VCC[044]

VCCP[10]

N6

T1

TEST3

C24

Y1

COMP3

F12

R21

C8

1

2

TEST3

COMP[3]

VCC[045]

VCCP[11]

@ 0.1U_0402_16V4Z

TEST4

AF26

TEST4

F14

VCC[046]

VCCP[12]

R6

T2

TEST5

AF1

E5

H_DPRSTP#

H_DPRSTP#

7,19,37

F15

T21

TEST5

DPRSTP#

1% 1

1% 1

1% 1

1% 1

VCC[047]

VCCP[13]

TEST6

A26

B5

H_DPSLP#

F17

T6

T3

TEST6

DPSLP#

H_DPSLP# 19

VCC[048]

VCCP[14]

D24

H_DPWR#

F18

V21

15

CPU_BSEL2

CPU_BSEL0

B22

BSEL[2]

DPWR#

D6

H_PWRGOOD

H_DPWR# 7

R22

54.90402 2

R23 27.40402 2

R24 54.90402 2

R25 27.40402 2

AA10

VCC[049]

VCCP[15]

C26

+1.5VS

PSI#

H_PSI#

37

VCC[052]

VCCA[01]

15

CPU_BSEL0

CPU_BSEL1

B23

BSEL[0]

PWRGOOD

D7

H_CPUSLP#

H_PWRGOOD 19

AA7

VCC[050]

VCCP[16]

15

CPU_BSEL1

CPU_BSEL2

C21

BSEL[1]

SLP#

AE6

H_PSI#

H_CPUSLP# 7

AA9

VCC[051]

B26

0.5" of CPU pin.Trace

AB9

VCC[060]

VID[5]

AF3

CPU_VID5 37

C9

2

080510U6.3V6M

C10

2

04020.01U16V7K

Merom Ball-out Rev 1a

AA12

VCC[053]

VCCA[02]

CONN@

AA13

VCC[054]

AD6

CPU_VID0 37

AA15

VCC[055]

VID[0]

AF5

1

1

VCC[056]

VID[1]

CPU_VID1 37

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

Resistor placed within

AA17

VCC[057]

VID[2]

AE5

CPU_VID2 37

AA20

VCC[058]

VID[3]

AE3

CPU_VID3 37

AA18

AF4

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

should be at least 25

AB10

VCC[059]

VID[4]

AE2

CPU_VID4 37

VCC[061]

VID[6]

CPU_VID6 37

mils away from any other

AC10

VCC[063]

AB12

toggling signal.

VCC[062]

166

0

1

1

AB14

VCC[064]

VCCSENSE

AF7

VCCSENSE

VCCSENSE 37

Near pin B26

COMP[0,2] trace width is

AB15

VCC[065]

AB17

18 mils. COMP[1,3] trace

AB18

VCC[066]

AE7

VSSSENSE

VSSSENSE 37

VCC[067]

VSSSENSE

200

0

1

0

width is 4 mils.

Merom Ball-out Rev 1a

CONN@

.

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCCP
	1
	R27
	1K_0402_1%	+VCC_CORE
	2
V_CPU_GTLREF			R28
			100_0402_1%	VCCSENSE
	1	1	2
			R30
	R29		100_0402_1%
	2K_0402_1%	1	2	VSSSENSE
	2

Close to CPU pin AD26

Close to CPU pin

within 500mils.

within 500mils.

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

Merom(2/3)-AGTL+/PWR

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Document Number

Rev

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Custom

LA-4031P

1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet 5 o f

42

5

4

3

2

1

D

C

B

A

5

4

3

2

1

+VCC_CORE

Place these capacitors on L8

1 C11

1 C12

1 C13

1 C14

1 C15

1 C16

1 C17

1 C18

D

(North side,Secondary Layer)

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

D

A4

JP2D

P6

VSS[001]

VSS[082]

+VCC_CORE

A8

P21

VSS[002]

VSS[083]

A11

P24

VSS[003]

VSS[084]

A14

R2

VSS[004]

VSS[085]

A16

R5

1

1

1

1

1

1

1

1

VSS[005]

VSS[086]

C19

C20

C21

C22

C23

C24

C25

C26

A19

VSS[006]

VSS[087]

R22

Place these capacitors on L8

A23

R25

AF2

VSS[007]

VSS[088]

T1

(North side,Secondary Layer)

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

VSS[008]

VSS[089]

B6

VSS[009]

VSS[090]

T4

B8

T23

VSS[010]

VSS[091]

B11

T26

VSS[011]

VSS[092]

B13

U3

VSS[012]

VSS[093]

+VCC_CORE

B16

U6

VSS[013]

VSS[094]

B19

U21

VSS[014]

VSS[095]

B21

U24

VSS[015]

VSS[096]

B24

V2

1

1

1

1

1

1

1

1

VSS[016]

VSS[097]

C27

C28

C29

C30

C31

C32

C33

C34

C5

V5

VSS[017]

VSS[098]

Place these capacitors on L8

C8

V22

C11

VSS[018]

VSS[099]

V25

(Sorth side,Secondary Layer)

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

VSS[019]

VSS[100]

C14

VSS[020]

VSS[101]

W1

C16

VSS[021]

VSS[102]

W4

C19

W23

VSS[022]

VSS[103]

C2

W26

VSS[023]

VSS[104]

+VCC_CORE

C22

Y3

VSS[024]

VSS[105]

C25

Y6

VSS[025]

VSS[106]

D1

Y21

VSS[026]

VSS[107]

D4

Y24

1

1

1

1

1

1

1

1

VSS[027]

VSS[108]

C35

C36

C37

C38

C39

C40

C41

C42

D8

AA2

VSS[028]

VSS[109]

Place these capacitors on L8

D11

AA5

C

D13

VSS[029]

VSS[110]

AA8

(Sorth side,Secondary Layer)

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

2 10U_0805_6.3V6M

C

VSS[030]

VSS[111]

D16

VSS[031]

VSS[112]

AA11

Mid Frequence Decoupling

D23

VSS[033]

VSS[114]

AA16

D19

VSS[032]

VSS[113]

AA14

D26

VSS[034]

VSS[115]

AA19

E3

VSS[035]

VSS[116]

AA22

E6

AA25

VSS[036]

VSS[117]

E8

AB1

VSS[037]

VSS[118]

E11

AB4

VSS[038]

VSS[119]

E14

AB8

VSS[039]

VSS[120]

E16

AB11

VSS[040]

VSS[121]

E19

AB13

VSS[041]

VSS[122]

E21

AB16

VSS[042]

VSS[123]

E24

AB19

VSS[043]

VSS[124]

F5

AB23

VSS[044]

VSS[125]

F8

AB26

VSS[045]

VSS[126]

F11

AC3

VSS[046]

VSS[127]

F13

AC6

VSS[047]

VSS[128]

ESR <= 1.5m ohm

F16

AC8

VSS[048]

VSS[129]

F19

AC11

VSS[049]

VSS[130]

Near CPU CORE regulator

F22

VSS[050]

VSS[131]

AC16

F2

AC14

Capacitor > 1980uF

F25

VSS[051]

VSS[132]

AC19

G4

VSS[052]

VSS[133]

AC21

VSS[053]

VSS[134]

G1

AC24

VSS[054]

VSS[135]

G23

AD2

VSS[055]

VSS[136]

G26

AD5

VSS[056]

VSS[137]

+VCC_CORE

H3

AD8

VSS[057]

VSS[138]

H6

AD11

VSS[058]

VSS[139]

220U_D2_2V_Y_LESR9M

1000U 2.5V M H80 LESR8M

H21

AD13

VSS[059]

VSS[140]

H24

AD16

VSS[060]

VSS[141]

J2

AD19

B

VSS[061]

VSS[142]

B

J5

AD22

VSS[062]

VSS[143]

J22

AD25

1

1

1

1

1

VSS[063]

VSS[144]

J25

AE1

VSS[064]

VSS[145]

C45

+

C46 +

C47 +

C48 +

C49

+

K1

AE4

K4

VSS[065]

VSS[146]

AE8

220U_D2_2V_Y_LESR9M

VSS[066]

VSS[147]

K23

AE11

VSS[067]

VSS[148]

2

2

2

2

2

K26

AE14

VSS[068]

VSS[149]

L3

AE16

VSS[069]

VSS[150]

L6

AE19

VSS[070]

VSS[151]

220U_D2_2V_Y_LESR9M

220U_D2_2V_Y_LESR9M

L21

AE23

VSS[071]

VSS[152]

L24

AE26

VSS[072]

VSS[153]

M2

A2

VSS[073]

VSS[154]

M5

AF6

VSS[074]

VSS[155]

@

M22

AF8

VSS[075]

VSS[156]

Place these inside

M25

AF11

VSS[076]

VSS[157]

N1

AF13

socket cavity on L8

VSS[077]

VSS[158]

N4

VSS[078]

VSS[159]

AF16

(North side

N23

VSS[079]

VSS[160]

AF19

Secondary)

N26

VSS[080]

VSS[161]

AF21

P3

A25

VSS[081]

VSS[162]

+VCCP

AF25

VSS[163]

Merom Ball-out Rev 1a

CONN@

.

1 C50

1 C51

1 C52

1 C53

1 C54

1 C55

2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

A

A

Security Classification

2007/03/26

Compal Secret Data

2006/03/10

Title

Compal Electronics, Inc.

Issued Date

Deciphered Date

Merom(3/3)-GND&Bypass

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

Rev

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Document Number

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet

6

o f

42

5

4

3

2

1

D

C

B

A

5

4

5

H_D#[0..63]

U3A

H_A#[3..35] 4

J13

H_A#3

H_A#_3

H_D#0

E2

B11

H_A#4

H_D#_0

H_A#_4

H_D#1

G2

C11

H_A#5

H_D#_1

H_A#_5

H_D#2

G7

M11

H_A#6

H_D#_2

H_A#_6

H_D#3

M6

C15

H_A#7

H_D#_3

H_A#_7

H_D#4

H7

F16

H_A#8

H_D#_4

H_A#_8

H_D#5

H3

L13

H_A#9

H_D#_5

H_A#_9

H_D#6

G4

G17

H_A#10

H_D#_6

H_A#_10

H_D#7

F3

C14

H_A#11

H_D#_7

H_A#_11

H_D#8

N8

K16

H_A#12

H_D#_8

H_A#_12

H_D#9

H2

B13

H_A#13

H_D#_9

H_A#_13

H_D#10

M10

L16

H_A#14

H_D#_10

H_A#_14

H_D#11

N12

J17

H_A#15

H_D#_11

H_A#_15

H_D#12

N9

B14

H_A#16

H_D#_12

H_A#_16

H_D#13

H5

K19

H_A#17

H_D#_13

H_A#_17

H_D#14

P13

P15

H_A#18

H_D#_14

H_A#_18

H_D#15

K9

R17

H_A#19

H_D#_15

H_A#_19

H_D#16

M2

B16

H_A#20

H_D#_16

H_A#_20

H_D#17

W10

H20

H_A#21

H_D#_17

H_A#_21

H_D#18

Y8

L19

H_A#22

H_D#_18

H_A#_22

H_D#19

V4

D17

H_A#23

H_D#_19

H_A#_23

H_D#20

M3

M17

H_A#24

H_D#_20

H_A#_24

H_D#21

J1

N16

H_A#25

H_D#_21

H_A#_25

H_D#22

N5

J19

H_A#26

H_D#_22

H_A#_26

H_D#23

N3

B18

H_A#27

H_D#_23

H_A#_27

H_D#24

W6

E19

H_A#28

H_D#_24

H_A#_28

H_D#25

W9

B17

H_A#29

H_D#_25

H_A#_29

H_D#26

N2

B15

H_A#30

H_D#_26

H_A#_30

H_D#27

Y7

E17

H_A#31

H_D#_27

H_A#_31

H_D#28

Y9

C18

H_A#32

H_D#_28

H_A#_32

H_D#29

P4

A19

H_A#33

H_D#_29

H_A#_33

H_D#30

W3

B19

H_A#34

H_D#_30

H_A#_34

H_D#31

N1

N19

H_A#35

H_D#_31

H_A#_35

H_D#32

AD12

H_D#_32

H_D#33

AE3

G12

H_ADS#

H_ADS#

4

H_D#_33

HOST

H_ADS#

H_D#34

AD9

H17

H_ADSTB#0

H_D#_34

H_ADSTB#_0

H_ADSTB#0 4

H_D#40

AB2

C10

H_DBSY#

H_D#_40

H_DBSY#

H_DBSY# 4

H_D#35

AC9

H_D#_35

H_ADSTB#_1

G20

H_ADSTB#1

H_ADSTB#1 4

H_D#36

AC7

H_D#_36

H_BNR#

C8

H_BNR#

H_BNR#

4

H_D#37

AC14

H_D#_37

H_BPRI#

E8

H_BPRI#

H_BPRI#

4

H_D#38

AD11

H_D#_38

H_BREQ#

F12

H_BR0#

H_BR0#

4

H_D#39

AC11

D6

H_DEFER#

H_D#_39

H_DEFER#

H_DEFER# 4

H_D#41

AD7

H_D#_41

HPLL_CLK

AM5

CLK_MCH_BCLK

CLK_MCH_BCLK 15

H_D#42

AB1

H_D#_42

HPLL_CLK#

AM7

CLK_MCH_BCLK#

CLK_MCH_BCLK# 15

H_D#43

Y3

H8

H_DPWR#

H_D#_43

H_DPWR#

H_DPWR# 5

H_D#44

AC6

K7

H_D RDY#

H_D#_44

H_DRDY#

H_DRDY# 4

H_D#45

AE2

E4

H_HIT#

H_D#_45

H_HIT#

H_HIT#

4

H_D#46

AC5

C6

H_HITM#

H_D#_46

H_HITM#

H_HITM#

4

H_D#47

AG3

G10

H_LOCK#

H_D#_47

H_LOCK#

H_LOCK# 4

H_D#48

AJ9

B7

H_TRDY#

H_D#_48

H_TRDY#

H_TRDY# 4

H_D#49

AH8

H_D#_49

H_D#50

AJ14

H_D#_50

H_D#51

AE9

H_D#_51

H_D#52

AE11

+VCCP

H_D#_52

H_D#53

AH12

K5

H_DINV#0

H_DINV#0 5

H_D#54

AJ5

H_D#_53

H_DINV#_0

L2

H_DINV#1

H_D#_54

H_DINV#_1

H_DINV#1 5

H_D#55

AH5

AD13

H_DINV#2

H_D#_55

H_DINV#_2

H_DINV#2 5

H_D#56

AJ6

AE13

H_DINV#3

1%

1% 1

H_D#_56

H_DINV#_3

H_DINV#3 5

H_D#57

AE7

1

H_D#_57

H_D#58

AJ7

H_DSTBN#_0

M7

H_DSTBN#0

H_DSTBN#0 5

R39

040254.9

2

R40 040254.9 2

H_D#62

AH2

H_D#_58

K3

H_DSTBN#1

H_D#_61

H_DSTBN#_3

H_DSTBN#3 5

H_D#59

AJ2

H_D#_59

H_DSTBN#_1

H_DSTBN#1 5

H_D#60

AE5

H_D#_60

H_DSTBN#_2

AD2

H_DSTBN#2

H_DSTBN#2 5

H_D#61

AJ3

AH11

H_DSTBN#3

H_D#63

AH13

H_D#_62

L7

H_DSTBP#0

H_DSTBP#0 5

H_D#_63

H_DSTBP#_0

K2

H_DSTBP#1

H_DSTBP#_1

H_DSTBP#1 5

AC2

H_DSTBP#2

H_DSTBP#_2

H_DSTBP#2 5

H_SWNG

B3

AJ10

H_DSTBP#3

H_SWING

H_DSTBP#_3

H_DSTBP#3 5

H_RCOMP

C2

H_RCOMP

M14

H_REQ#0

H_REQ#_0

H_REQ#0 4

H_SCOMP

W1

E13

H_REQ#1

H_SCOMP

H_REQ#_1

H_REQ#1 4

H_SCOMP#

W2

A11

H_REQ#2

H_SCOMP#

H_REQ#_2

H_REQ#2 4

H13

H_REQ#3

H_REQ#_3

H_REQ#3 4

4

H_RESET#

H_RESET#

B6

B12

H_REQ#4

H_CPURST#

H_REQ#_4

H_REQ#4

4

H_CPUSLP#

E5

5

H_CPUSLP#

H_CPUSLP#

E12

H_RS#0

H_RS#0

4

H_RS#_0

D7

H_RS#1

H_RS#1

4

H_RS#_1

D8

H_RS#2

H_RS#2

4

B9

H_RS#_2

H_VREF

H_AVREF

A9

H_DVREF

CRESTLINE_1p0

layout note:

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note:

H_RCOMP

/ H_VREF / H_SWNG

Layout Note:

trace width and spacing is 10/20

V_DDR_MCH_REF

trace width and

+VCCP

+VCCP

spacing is 20/20.

2 1

1K0402 1%

2 1

2210603 1%

13,14,35 V_DDR_MCH_REF

V_DDR_MCH_

REF

R44

H_VREF

H_RCOMP

R45

H_SWNG

C61 040216V4Z

1

0.1U_0402_16V4Z

0.1U

2

R49

2 1

1%04022K

C62

R50 040224.91%

2 1

R51

2 1

1%0402100

16V4Z04020.1U

C63

1

1

2

2

within 100 mils from NB

Near B3 pin

5

4

3

2

1

U3B

For Crestline: 20ohm

P36

RSVD1

For Calero: 80.6ohm

P37

RSVD2

SM_CK_0

AV29

M_CLK_DDR0

M_CLK_DDR0 13

R35

BB23

M_CLK_DDR1

N35

RSVD3

SM_CK_1

BA25

M_CLK_DDR2

M_CLK_DDR1 13

AR12

RSVD4

SM_CK_3

AV23

M_CLK_DDR3

M_CLK_DDR2 14

16V4Z

2

2

16V7K

+1.8V

AN13

RSVD5

SM_CK_4

BA23

M_CLK_DDR3 14

RSVD8

SM_CK#_1

M_CLK_DDR#1 13

AR13

RSVD6

M_CLK_DDR#0

AM12

RSVD7

SM_CK#_0

AW30

M_CLK_DDR#0 13

04020.01U_

12

M_CLK_DDR#1

SMRCOMP_VOH

C57

D20

RSVD13

RSVD

SM_CKE_1

BD39

DDR_CKE2_DIMMB

DDR_CKE1_DIMMA 13

0805 C56

R31

J12

AW25

M_CLK_DDR#2

AR37

RSVD10

SM_CK#_4

AW23

M_CLK_DDR#3

M_CLK_DDR#3 14

RSVD9

SM_CK#_3

M_CLK_DDR#2 14

2.2U

1

1

1K_0402_1%

AM36

RSVD11

DDR_CKE0_DIMMA

AL36

RSVD12

SM_CKE_0

BE29

DDR_CKE0_DIMMA 13

AM37

AY32

DDR_CKE1_DIMMA

RSVD14

SM_CKE_3

BG37

DDR_CKE3_DIMMB

DDR_CKE2_DIMMB 14

1

R32

SM_CKE_4

BG20

DDR_CS0_DIMMA#

DDR_CKE3_DIMMB 14

SM_CS#_0

DDR_CS0_DIMMA# 13

3.01K_0402_1%

SM_CS#_1

BK16

DDR_CS1_DIMMA#

DDR_CS1_DIMMA# 13

NA lead free

BG16

DDR_CS2_DIMMB#

H10

SM_CS#_2

BE13

DDR_CS3_DIMMB#

DDR_CS2_DIMMB# 14

16V4Z_

C59

04020.01U16V7K

2 1 2

BC23

RSVD20

MUXING

SM_CS#_3

BK31

SMRCOMP_VOH

DDR_CS3_DIMMB# 14

RSVD29

SMRCOMP_VOL

B51

RSVD21

M_ODT0

. 2

BJ20

RSVD22

SM_ODT_0

BH18

M_ODT0

13

2U

1

1

R33

BF19

RSVD23

SM_ODT_1

BJ14

M_ODT2

M_ODT1

13

+1.8V

0805C58

BH20

RSVD25

SM_ODT_3

BE16

M_ODT3

M

_ODT3

14

1K_0402_1%

BK18

RSVD26

SMRCOMP

30_0402_1%

2

2

BJ18

RSVD27

SM_RCOMP

BL15

R34

2

1

BF23

RSVD28

SM_RCOMP#

BK14

SMRCOMP#

2

1

BG23

R35

30_0402_1%

RSVD30

DDR

SM_RCOMP_VOH

BD24

BL31

SMRCOMP_VOL

RSVD31

SM_RCOMP_VOL

13 DDR_A_MA14

BE24

RSVD32

AR49

0927_Change from 20 ohm to 30 ohm.

BJ29

14 DDR_B_MA14

RSVD33

SM_VREF_0

V_DDR_MCH_REF

BH39

AW4

AW20

RSVD34

SM_VREF_1

+3VS

RSVD35

BK20

R36

C48

RSVD36

PM_EXTTS#0

RSVD37

CLK_MCH_DREFCLK

2

1

D47

B42

CLK_MCH_DREFCLK 15

B44

RSVD38

DPLL_REF_CLK

C42

CLK_MCH_DREFCLK#

10K_0402_5%

C44

RSVD39

DPLL_REF_CLK#

H48

MCH_SSCDREFCLK

CLK_MCH_DREFCLK# 15

A35

RSVD40

DPLL_REF_SSCLK

H47

MCH_SSCDREFCLK#

MCH_SSCDREFCLK 15

R37

B37

RSVD41

DPLL_REF_SSCLK#

MCH_SSCDREFCLK# 15

PM_EXTTS#1

RSVD42

CLK_MCH_3GPLL

2

1

B36

CLK

K44

CLK_MCH_3GPLL 15

B34

RSVD43

PEG_CLK

K45

CLK_MCH_3GPLL#

10K_0402_5%

C34

RSVD44

PEG_CLK#

CLK_MCH_3GPLL# 15

RSVD45

CLKREQ#_B

2

R38

1

AN47

DMI_TXN0

DMI_TXN0

20

DMI_RXN_0

<>

DMI_RXN_1

AJ38

DMI_TXN1

DMI_TXN1

20

10K_0402_5%

AN42

DMI_TXN2

DMI_RXN_2

AN46

DMI_TXN3

DMI_TXN2

20

DMI_RXN_3

AM47

DMI_TXP0

DMI_TXN3

20

DMI_RXP_0

DMI_TXP0

20

MCH_CLKSEL0

P27

AJ39

DMI_TXP1

15 MCH_CLKSEL0

MCH_CLKSEL1

N27

CFG_0

DMI_RXP_1

AN41

DMI_TXP2

DMI_TXP1 20

15 MCH_CLKSEL1

MCH_CLKSEL2

N24

CFG_1

DMI_RXP_2

AN45

DMI_TXP3

DMI_TXP2 20

15 MCH_CLKSEL2

C21

CFG_2

DMI_RXP_3

DMI_TXP3 20

CFG_3

DMI_RXN0

C23

AJ46

DMI_RXN0 20

T4

CFG5

F23

CFG_4

DMI_TXN_0

AJ41

DMI_RXN1

T5

CFG6

N23

CFG_5

DMI_TXN_1

AM40

DMI_RXN2

DMI_RXN1 20

T6

CFG7

G23

CFG_6

DMI_TXN_2

AM44

DMI_RXN3

DMI_RXN2 20

T7

CFG8

J20

CFG_7

DMI

DMI_TXN_3

DMI_RXN3 20

CFG_11

DMI_TXP_2

DMI_RXP2 20

T8

CFG9

C20

CFG_8

CFG

AJ47

DMI_RXP0

DMI_RXP0 20

T9

CFG10

R24

CFG_9

DMI_TXP_0

AJ42

DMI_RXP1

T10

CFG11

L23

CFG_10

DMI_TXP_1

AM39

DMI_RXP2

DMI_RXP1 20

T11

CFG12

J23

CFG_12

DMI_TXP_3

AM43

DMI_RXP3

DMI_RXP3 20

T12

CFG13

E23

E20

CFG_13

K23

CFG_14

T13

CFG16

CFG_15

M20

M24

CFG_16

VID

T44

CFG18

CFG_17

L32

CFG_18

T14

CFG19

N33

T15

CFG20

L35

CFG_19

20,37

DPRSLPVR

PM_BMBUSY#

G36

CFG_20

GRAPHICS

GFX_VID_0

E35

T16

1

DPRSLPVR

20 PM_BMBUSY#

G41

A39

T17

H_DPRSTP#

L39

PM_BM_BUSY#

GFX_VID_1

C38

T18

5,19,37

H_DPRSTP#

PM_EXTTS#0

L36

PM_DPRSTP#

GFX_VID_2

B39

T19

13

PM_EXTTS#0

PM_EXTTS#1

J36

PM_EXT_TS#_0

PM

GFX_VID_3

E36

T20

14

PM_EXTTS#1

PM_PWROK

AW49

PM_EXT_TS#_1

GFX_VR_EN

20,30 PM_PWROK

PWROK

+1.25VM_AXD

PLT_RST#

AV20

18,22

PLT_RST#

RSTIN#

H_THERMTRIP#

N20

4,19 H_THERMTRIP#

THERMTRIP#

DPRSLPVR

CL_CLK

AM49

CL_CLK0

CL_CLK0

20

R41

AK50

CL_DATA0

BJ51

CL_DATA

AT43

M_PWROK

CL_DATA0 20

1K_0402_1%

BK51

NC_1

ME

CL_PWROK

AN49

CL_RST#

M_PWROK 20,30

NC_2

CL_RST#

CL_RST#

20

2

BL50

1

BK50

NC_3

CL_VREF

AM50

CL_VREF

CL_VREF

NC_4

0.1U_0402_16V4Z

BL49

1

BL3

NC_5

R42

NC_6

+1.8V

BL2

NC_7

NC

C60

392_0402_1%

BK1

NC_8

2

BJ1

NC_9

SDVO_CTRL_CLK

H35

E1

K36

2 1

MISC

SDVO_CTRL_DATA

CLKREQ#_B

2

A49

NC_14

A37

A5

NC_10

G39

CLKREQ#_B 15

R43

C51

NC_11

CLK_REQ#

G40

MCH_ICH_SYNC#

MCH_ICH_SYNC# 20

1K_0402_1%

B50

NC_12

ICH_SYNC#

NC_13

A50

NC_15

TEST_1

BK2

NC_16

TEST_2

R32

1

CRESTLINE_1p0

1

1

R46

R47

R48

1K_0402_1%

20K_0402_5%

0_0402_5%

2

0925_Stuff R43 and R46.

2

2

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

CRESTLINE(1/6)-AGTL+/DMI/DDR2

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Date:

Wednesday, October 24, 2007

1

Sheet

7

o f

42

D

C

B

A

5

4

3

2

1

D
	13 DDR_A_D[0..63]		DDR_A_D0
			DDR_A_D1
			DDR_A_D2
			DDR_A_D3
			DDR_A_D4
			DDR_A_D5
			DDR_A_D6
			DDR_A_D7
			DDR_A_D8
			DDR_A_D9
			DDR_A_D10
			DDR_A_D11
			DDR_A_D12
			DDR_A_D13
			DDR_A_D14
			DDR_A_D15
			DDR_A_D16
			DDR_A_D17
			DDR_A_D18
			DDR_A_D19
			DDR_A_D20
			DDR_A_D21
			DDR_A_D22
			DDR_A_D23
			DDR_A_D24
			DDR_A_D25
			DDR_A_D26
			DDR_A_D27
C			DDR_A_D28
			DDR_A_D29
			DDR_A_D30
			DDR_A_D31
			DDR_A_D32
			DDR_A_D33
			DDR_A_D34
			DDR_A_D35
			DDR_A_D36
			DDR_A_D37
			DDR_A_D38
			DDR_A_D39
			DDR_A_D40
			DDR_A_D41
			DDR_A_D42
			DDR_A_D43
			DDR_A_D44
			DDR_A_D45
			DDR_A_D46
			DDR_A_D47
			DDR_A_D48
			DDR_A_D49
			DDR_A_D50
			DDR_A_D51
			DDR_A_D52
			DDR_A_D53
			DDR_A_D54
			DDR_A_D55
			DDR_A_D56
			DDR_A_D57
			DDR_A_D58
			DDR_A_D59
			DDR_A_D60
B			DDR_A_D61
			DDR_A_D62
			DDR_A_D63

A

AR43

AW44

BA45

AY46

AR41

AR45

AT42

AW47

BB45

BF48

BG47

BJ45

BB47

BG50

BH49

BE45

AW43

BE44

BG42

BE40

BF44

BH45

BG40

BF40

AR40

AW40

AT39

AW36

AW41

AY41

AV38

AT38

AV13

AT13

AW11

AV11

AU15

AT11

BA13

BA11

BE10

BD10

BD8

AY9

BG10

AW9

BD7

BB9

BB5

AY7

AT5

AT7

AY6

BB7

AR5

AR8

AR9

AN3

AM8

AN10

AT9

AN9

AM9

AN11

U3D

SA_DQ_0

SA_DQ_1

SA_DQ_2

SA_DQ_3

SA_DQ_4

SA_DQ_5

SA_DQ_6

SA_DQ_7

SA_DQ_8

SA_DQ_9

SA_DQ_10

SA_DQ_11

SA_DQ_12

SA_DQ_13

SA_DQ_14

SA_DQ_15

SA_DQ_16

SA_DQ_17

SA_DQ_18

SA_DQ_19

SA_DQ_20

SA_DQ_21

SA_DQ_22

SA_DQ_23

SA_DQ_24

SA_DQ_25

SA_DQ_26

SA_DQ_27

SA_DQ_28

SA_DQ_29

SA_DQ_30

SA_DQ_31

SA_DQ_32

SA_DQ_33

SA_DQ_34

SA_DQ_35

SA_DQ_36

SA_DQ_37

SA_DQ_38

SA_DQ_39

SA_DQ_40

SA_DQ_41

SA_DQ_42

SA_DQ_43

SA_DQ_44

SA_DQ_45

SA_DQ_46

SA_DQ_47

SA_DQ_48

SA_DQ_49

SA_DQ_50

SA_DQ_51

SA_DQ_52

SA_DQ_53

SA_DQ_54

SA_DQ_55

SA_DQ_56

SA_DQ_57

SA_DQ_58

SA_DQ_59

SA_DQ_60

SA_DQ_61

SA_DQ_62

SA_DQ_63

CRESTLINE_1p0

5

DDR SYSTEM MEMORY A

SA_BS_0 BB19 SA_BS_1 BK19 SA_BS_2 BF29

SA_CAS# BL17

SA_DM_0 AT45 SA_DM_1 BD44 SA_DM_2 BD42 SA_DM_3 AW38 SA_DM_4 AW13 SA_DM_5 BG8 SA_DM_6 AY5 SA_DM_7 AN6

SA_DQS_0 AT46 SA_DQS_1 BE48 SA_DQS_2 BB43 SA_DQS_3 BC37 SA_DQS_4 BB16 SA_DQS_5 BH6 SA_DQS_6 BB2 SA_DQS_7 AP3 SA_DQS#_0 AT47 SA_DQS#_1 BD47 SA_DQS#_2 BC41 SA_DQS#_3 BA37 SA_DQS#_4 BA16 SA_DQS#_5 BH7 SA_DQS#_6 BC1 SA_DQS#_7 AP2

SA_MA_0 BJ19 SA_MA_1 BD20 SA_MA_2 BK27 SA_MA_3 BH28 SA_MA_4 BL24 SA_MA_5 BK28 SA_MA_6 BJ27 SA_MA_7 BJ25 SA_MA_8 BL28 SA_MA_9 BA28 SA_MA_10 BC19 SA_MA_11 BE28 SA_MA_12 BG30 SA_MA_13 BJ16

SA_RAS# BE18 SA_RCVEN# AY20

SA_WE# BA19

DDR_A_BS0 DDR_A_BS1

DDR_A_BS2

DDR_A_CAS#

DDR_A_DM0

DDR_A_DM1 DDR_A_DM2

DDR_A_DM3 DDR_A_DM4 DDR_A_DM5

DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1

DDR_A_DQS2 DDR_A_DQS3

DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6

DDR_A_DQS7 DDR_A_DQS#0

DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3

DDR_A_DQS#4 DDR_A_DQS#5

DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1

DDR_A_MA2 DDR_A_MA3 DDR_A_MA4

DDR_A_MA5 DDR_A_MA6

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9

DDR_A_MA10 DDR_A_MA11

DDR_A_MA12 DDR_A_MA13

DDR_A_RAS#

SA_RCVEN#

DDR_A_WE#

4

DDR_A_BS0 13

DDR_A_BS1 13

DDR_A_BS2 13

DDR_A_CAS# 13

DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_RAS# 13

T22

DDR_A_WE# 13

14 DDR_B_D[0..63]

DDR_B_D0

DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D4

DDR_B_D5

DDR_B_D6

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D11

DDR_B_D12

DDR_B_D13

DDR_B_D14

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D46

DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

DDR_B_D60

DDR_B_D61

DDR_B_D62

DDR_B_D63

AP49

AR51

AW50

AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50

BJ44

BJ43

BL43

BK47

BK49

BK43

BK42

BJ41

BL41

BJ37

BJ36

BK41

BJ40

BL35

BK37

BK13

BE11

BK11

BC11

BC13

BE12

BC12

BG12

BJ10

BL9

BK5

BL5

BK9

BK10

BJ8

BJ6

BF4

BH5

BG1

BC2

BK3

BE4

BD3

BJ2

BA3

BB3

AR1

AT3

AY2

AY3

AU2

AT2

U3E

SB_DQ_0

SB_DQ_1

SB_DQ_2

SB_DQ_3

SB_DQ_4

SB_DQ_5

SB_DQ_6

SB_DQ_7

SB_DQ_8

SB_DQ_9

SB_DQ_10

SB_DQ_11

SB_DQ_12

SB_DQ_13

SB_DQ_14

SB_DQ_15

SB_DQ_16

SB_DQ_17

SB_DQ_18

SB_DQ_19

SB_DQ_20

SB_DQ_21

SB_DQ_22

SB_DQ_23

SB_DQ_24

SB_DQ_25

SB_DQ_26

SB_DQ_27

SB_DQ_28

SB_DQ_29

SB_DQ_30

SB_DQ_31

SB_DQ_32

SB_DQ_33

SB_DQ_34

SB_DQ_35

SB_DQ_36

SB_DQ_37

SB_DQ_38

SB_DQ_39

SB_DQ_40

SB_DQ_41

SB_DQ_42

SB_DQ_43

SB_DQ_44

SB_DQ_45

SB_DQ_46

SB_DQ_47

SB_DQ_48

SB_DQ_49

SB_DQ_50

SB_DQ_51

SB_DQ_52

SB_DQ_53

SB_DQ_54

SB_DQ_55

SB_DQ_56

SB_DQ_57

SB_DQ_58

SB_DQ_59

SB_DQ_60

SB_DQ_61

SB_DQ_62

SB_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY B

Security Classification		Compal Secret Data
Issued Date	2007/03/26		Deciphered Date	2006/03/10

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

SB_BS_0 AY17 SB_BS_1 BG18 SB_BS_2 BG36

SB_CAS# BE17

SB_DM_0 AR50 SB_DM_1 BD49 SB_DM_2 BK45 SB_DM_3 BL39 SB_DM_4 BH12 SB_DM_5 BJ7 SB_DM_6 BF3 SB_DM_7 AW2

SB_DQS_0 AT50 SB_DQS_1 BD50 SB_DQS_2 BK46 SB_DQS_3 BK39 SB_DQS_4 BJ12 SB_DQS_5 BL7 SB_DQS_6 BE2 SB_DQS_7 AV2 SB_DQS#_0 AU50 SB_DQS#_1 BC50 SB_DQS#_2 BL45 SB_DQS#_3 BK38 SB_DQS#_4 BK12 SB_DQS#_5 BK7 SB_DQS#_6 BF2 SB_DQS#_7 AV3

SB_MA_0 BC18 SB_MA_1 BG28 SB_MA_2 BG25 SB_MA_3 AW17 SB_MA_4 BF25 SB_MA_5 BE25 SB_MA_6 BA29 SB_MA_7 BC28 SB_MA_8 AY28 SB_MA_9 BD37 SB_MA_10 BG17 SB_MA_11 BE37 SB_MA_12 BA39 SB_MA_13 BG13

SB_RAS# AV16 SB_RCVEN# AY18

SB_WE# BC17

DDR_B_BS0			DDR_B_BS0 14
DDR_B_BS1
			DDR_B_BS1 14
DDR_B_BS2
			DDR_B_BS2 14
DDR_B_CAS#			DDR_B_CAS# 14
DDR_B_DM0			DDR_B_DM[0..7] 14
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7			DDR_B_DQS[0..7] 14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7			DDR_B_DQS#[0..7] 14
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7			DDR_B_MA[0..13] 14
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_RAS#		DDR_B_RAS# 14
SB_RCVEN#
DDR_B_WE#		T21
		DDR_B_WE# 14

Compal Electronics, Inc.

Title

CRESTLINE((2/6)-DDR2 A/B CH

Size		Document Number						Rev
Custom		LA-4031P						1.0
Date:		Wednesday, October 24, 2007	1	Sheet	8	o f	42

D

C

B

A

5

4

D

For Crestline:2.4kohm

For Calero: 1.5Kohm

C

B

ENABLT

BKLT_CTRL

J40

17

ENABLT

H39

R53

1

2

10K_0402_5%

E39

+3VS

R54

1

2 10K_0402_5%

E40

17 LCD_CLK

LCD_CLK

C37

LCD_DATA

D35

17 LCD_DATA

ENAVDD

K40

17

ENAVDD

L41

2

1

R55

2.4K_0402_1%

L43

N41

N40

17

LVDSAC-

LVDSAC-

D46

LVDSAC+

C45

17

LVDSAC+

LVDSBC-

D44

17

LVDSBC-

LVDSBC+

E42

17

LVDSBC+

17

LVDSA0-

LVDSA0-

G51

LVDSA1-

E51

17

LVDSA1-

LVDSA2-

F49

17

LVDSA2-

17

LVDSA0+

LVDSA0+

G50

LVDSA1+

E50

17

LVDSA1+

LVDSA2+

F48

17

LVDSA2+

17

LVDSB0-

LVDSB0-

G44

LVDSB1-

B47

17

LVDSB1-

LVDSB2-

B45

17

LVDSB2-

LVDSB0+

E44

17

LVDSB0+

LVDSB1+

A47

17

LVDSB1+

LVDSB2+

A45

17

LVDSB2+

TV_COMPS

E27

16

TV_COMPS

TV_LUMA

G27

16

TV_LUMA

TV_CRMA

K27

16

TV_CRMA

F27

J27

L27

2.2K_0402_5%

M35

+3VS

R56 1

2

P33

16

CRT_B

CRT_B

H32

CRT_G

G32

16

CRT_G

K29

CRT_R

J29

16

CRT_R

F29

E29

16

3VDDCCL

3VDDCCL

K33

3VDDCDA

G35

16

3VDDCDA

CRT_HSYNC

F33

16

CRT_HSYNC

C32

CRT_VSYNC

16

CRT_VSYNC

E33

1

3K.1

R57

0402_2

1%_

U3C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CRESTLINE_1p0

For Crestline:1.3kohm

For Calero: 255ohm

A

5

4

3

2

1

Strap Pin Table

010 = FSB 800MHz

CFG[2:0] FSB Freq select

011 = FSB 667MHz

Others = Reserved

CFG5 (DMI select)

0 = DMI x 2

*

D

1 = DMI x 4

R52

+VCCP

PEGCOMP 1

24.9_0402_1%

CFG6

Reserved

PEG_COMPI

N43

2

M43

PEG_COMPO

PEGCOMP trace width

CFG7 (CPU Strap)

0 = Reserved

PEG_RX#_0

J51

and spacing is 20/25 mils.

L51

1 = Mobile CPU

*

PEG_RX#_1

N47

PEG_RX#_2

T45

PEG_RX#_3

T50

0 = Normal mode

PEG_RX#_4

U40

CFG8 (Low power PCIE)

PEG_RX#_5

Y44

1 = Low Power mode

*

PEG_RX#_6

Y40

PEG_RX#_7

AB51

PEG_RX#_8

W49

CFG9

0 = Reverse Lane

LVDS

PEG_RX#_9

AD44

PEG_RX#_10

(PCIE Graphics Lane Reversal)

1 = Normal Operation

*

PEG_RX#_11

AD40

AG46

PEG_RX#_12

AH49

PEG_RX#_13

AG45

PEG_RX#_14

AG41

CFG[11:10]

Reserved

PEG_RX#_15

GRAPHICS

PEG_RX_9

Y48

PEG_RX_0

J50

00 = Reserved

PEG_RX_1

L50

CFG[13:12] (XOR/ALLZ)

01 = XOR Mode Enabled

PEG_RX_2

M47

PEG_RX_3

U44

10 = All Z Mode Enabled

*

PEG_RX_4

T49

11 = Normal Operation(Default)

PEG_RX_5

T41

W45

PEG_RX_6

W41

CFG[15:14]

Reserved

C

PEG_RX_7

AB50

PEG_RX_8

CFG16 (FSB Dynamic ODT)

0 = Disabled

PEG_RX_10

AC45

PEG_RX_11

AC41

1 = Enabled

*

AH47

EXPRESS-PCI

PEG_RX_12

AG49

PEG_TX#_10

AC46

PEG_RX_13

AH45

PEG_RX_14

AG42

CFG[18:17]

Reserved

PEG_RX_15

N45

PEG_TX#_0

U39

0 = No SDVO Device Present

*

PEG_TX#_1

N51

SDVO_CTRLDATA

PEG_TX#_2

TV

U47

1 = SDVO Device Present

PEG_TX#_4

R50

PEG_TX#_3

PEG_TX#_5

T42

0 = Normal Operation

*

Y43

PEG_TX#_6

CFG19 (DMI Lane Reversal)

PEG_TX#_7

W38

(Lane number in Order)

W46

PEG_TX#_8

1 = Reverse Lane

AD39

PEG_TX#_9

PEG_TX#_11

AC49

0 = Only PCIE or SDVO is operational.

*

AC42

PEG_TX#_12

CFG20 (PCIE/SDVO concurrent)

PEG_TX#_13

AE49

AH39

1 = PCIE/SDVO are operating simu.

PEG_TX#_14

AH44

PEG_TX#_15

PEG_TX_0

M45

T38

PEG_TX_1

T46

CFG[17:3] have internal pull up

PEG_TX_2

N50

VGA

PEG_TX_3

R51

CFG[19:18] have internal pull down

PEG_TX_4

B

PEG_TX_7

Y39

PEG_TX_5

U43

PEG_TX_6

W42

Y47

PEG_TX_8

PEG_TX_9

AC38

AD47

PEG_TX_10

AC50

PEG_TX_11

AD43

PEG_TX_12

AG39

PEG_TX_13

AE50

PEG_TX_14

AH43

PEG_TX_15

A

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

CRESTLINE((3/6)-VGA/LVDS/TV

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Date:

Wednesday, October 24, 2007

1

Sheet

9

o f

42

D

C

B

A

5

4

3

2

1

+3VS_DAC_BG

+3VS

+3VS

R58

VCCSYNC 10mA

BLM18PG181SN1D_0603

2

1

.0

2

R59

1

0_0603_5%

1

.0

+1.25VS_DPLLB

+V1.25VS_AXF

+1.25VS

16V7K0402022U

C65

C66

16V4Z04021U.0

C64

16V4Z04021U

80mA

A33

VCCA_CRT_DAC_1

VTT_3

U11

+VCCP

1

1

7U.4

R60

1

1

1

850mA

1

2

+1.25VS

1

2

C439

2

U3H

CRT

VTT_8

10V4Z

16V4Z0402 1U.0

C67

10V4Z0805 10U

10V4Z0805 10U

C69

10V4Z0603 1U

4.7U_0603_6.3V6K

U3

C68

C70

R61

2

2

2

J32

VCCSYNC

VTT_1

U13

1

1

1

1

0_0603_5%

VTT_2

U12

+3VS_DAC_CRT

B33

VCCA_CRT_DAC_2

VTT_4

U9

+

C71

C72

0805

2

2

2

2

0925_Change C439 from 0.47uF to 4.7uF.

5mA

VTT_5

U8

2

VTT_6

U7

A30

U5

220U 6.3V_M

+3VS_DAC_CRT

+3VS

+3VS_DAC_BG

VCCA_DAC_BG

VTT_7

2

BLM18PG181SN1D_0603

B32

VSSA_DAC_BG

VTT_9

U2

.0

2

1

80mA

VTT

VTT_10

U1

R62

T13

+1.25VS_DMI

+1.8V_SM_CK

16V4Z0402 1U.0

VTT_11

16V7K0402022U

C73

C74

+1.25VS_DPLLA

B49

VSSA_LVDS

PLLLVDS

T11

C76

10V4Z08057U.4

R65C77

16V4Z08052U.2

C81

16V4Z04021U.0

+1.25VS

10V4Z080510U

C78

10V4Z080510U

C79

16V4Z04021U.0

C80

+1.8V

1

1

80mA

VCCA_DPLLA

VTT_12

T10

.

R64

+1.25VS_DPLLB

50mA

H49

VCCA_DPLLB

VTT_15

T7

1

47U

1

1

1

2

1

2

150mA

VTT_17

T5

C75

2

0603

2

2

0_0603_5%

1

2

2

+1.25VM_HPLL

AL2

VCCA_HPLL

VTT_16

T6

R63

1

1

1U_WIM32251R0KZF_10%

10mA

+1.25VM_MPLL

AM2

VCCA_MPLL

VTT_18

T3

10V7K

1

2

1000P_0402_50V7K

VTT_20

R3

VTT_19

T2

2

2

+1.8V_TXLVDS

1

A41

VCCA_LVDS

VTT_21

R2

2

C82

B41

VTT_22

R1

+1.25VM_AXD

200mA

+3VS_PEG_BG

2

PEGA A

VCC_AXD_1

AT23

1

2

+1.25VS

5mA

R66

AXD

VCC_AXD_2

AU28

350mA

10V4Z06031U

C83

C84

0_0805_5%

1

1

1

1

+3VS

2

1

K50

VCCA_PEG_BG

VCC_AXD_3

AU24

1

1

080510U

0_0603_5%

AT29

+1.25VS_PEGPLL

+1.25VS

+1.5VS_TVDAC

+1.5VS

1

K49

VCC_AXD_4

AT25

L1

0.1U_0402_16V4Z

VSSA_PEG_BG

VCC_AXD_5

AT30

BLM18PG121SN1D_0603

R67

VCC_AXD_6

2

2

10V4Z

2

1

16V7K0402022U.0

16V4Z04021U.0

1

2

C85

+1.25VS_PEGPLL 20 mils

AU17

VCCA_SM_5

AXF

VCC_DMI

AJ50

+1.25VS_DMI

16V4Z04021U.0

C86

10V4Z080510U

C87

C88

C89

0_0805_5%

2

VCCA_PEG_PLL

VCC_AXD_NCTF

AW18

VCCA_SM_1

POWER

VCC_AXF_1

B23

+V1.25VS_AXF

2

2

2

2

AU19

VCCA_SM_3

VCC_AXF_3

A21

AV19

VCCA_SM_2

VCC_AXF_2

B21

+1.25VM_A_SM

AU18

VCCA_SM_4

100mA

R68

950mA

SM

120mA

+1.25VS

1

2

AT22

VCCA_SM_7

CK

1

0_0805_5%

AT21

VCCA_SM_8

VCC_SM_CK_1

BK24

+1.8V_SM_CK

1

1

1

A

C90 +

C91

C92

C93

AT19

VCCA_SM_9

VCC_SM_CK_2

BK23

AT18

BJ24

AT17

VCCA_SM_10

SM

VCC_SM_CK_3

BJ23

220U_6.3V_M

10U_0805_10V4Z

4.7U_0805_10V4Z

VCCA_SM_11

VCC_SM_CK_4

+1.25VM_HPLL

AR17

2

2

2

2

VCCA_SM_NCTF_1

+1.25VS_DPLLA

R70

+1.25VS

AR16

R69

R71

+1.25VM_A_SM_CK

100mA

1U_0603_10V4Z

VCCA_SM_NCTF_2

VCC_TX_LVDS

A43

100mA

+1.8V_TXLVDS

2

+1.25VS

2

1

TVA CK

10V4Z0805 10U

1

2

C99

10V4Z0603 1U

C100

10V4Z0805 10U

C101

10V4Z0603 1U

C102

16V4Z0402 1U.0

BC29

PEG

VCC_PEG_4

V50

C103

2

04021U.0

MBK2012121YZF_0805

1

VCCA_SM_CK_1

+3VS_HV

0_0603_5%

40mA

BB29

VCCA_SM_CK_2

C40

100mA

1

1

10U_FLC-453232-100K_0.25A_10%

1

1

1

1

1

1

+3VS_TVDACA

C25

VCCA_TVA_DAC_1

HV

VCC_HV_2

B40

C95

C96

C97

C98

40mA

B25

VCCA_TVA_DAC_2

1450mA

0.1U_0402_16V4Z

2 10U_0805_10V4Z

+3VS_TVDACB

C27

VCCA_TVB_DAC_1

2

2

2

2

2

2

2

40mA

B27

VCCA_TVB_DAC_2

VCC_PEG_1

AD511200mA +VCC_PEG

1

+3VS_TVDACC

B28

VCCA_TVC_DAC_1

VCC_PEG_2

W50

A28

VCCA_TVC_DAC_2

VCC_PEG_3

W51

0.1U_0402_16V4Z

V49

250mA

AN2

TV/CRT

DMI

20mils

16V4Z

R72

VCC_PEG_5

75mA

50mAM32

VCCD_CRT

+1.5VS_TVDAC

25mAL29

VCCD_TVDAC

AH50250mA

5mA

N28

VCCD_QDAC

VCC_RXR_DMI_1

+VCCP

+1.25VM_MPLL

+1.5VS_QDAC

VCC_RXR_DMI_2

AH51

+VCC_PEG

R73

+1.25VS

BLM18PG181SN1D_0603

+1.25VM_HPLL

100mA

VCCD_HPLL

LVDSD

VTTLF

VTTLF1

A7

060347U.0 C108

2 C109

060347U.0

2

C110

060347U.0

2

M3V.6 220U

C104

C105

2

1

2

1

U48

F2

10V4Z080510U

MBK2012121YZF_0805

+1.25VS_PEGPLL

VCCD_PEG_PLL

VTTLF2

AH1

1

150mA

J41

VCCD_LVDS_1

VTTLF3

1

1

1

+1.8V_LVDS

H42

VCCD_LVDS_2

1

1

1

+

C106

C107

0.1U_0402_16V4Z

2 10U_0805_10V4Z

+3VS_TVDACC

+3VS

2

2

2

1U.0

CRESTLINE_1p0

10V7K

10V7K

10V7K

022U.0

2

R74

1

_

C111

1

C112

1

_

16V7K0402

2

2

16V4Z0402

+VCCP_D

D2

R75

R76

+VCCP

2

1

2

1

2

1

+3VS_HV

10_0402_5%

0_0402_5%

CH751H-40PT_SOD323-2

+3VS

+3VS_TVDACA

+1.5VS_QDAC

+1.5VS

+3VS

R77

BLM18PG181SN1D_0603

.0

2

1

16V7K0402022U.0

C115

C116

16V4Z04021U.0

2

1

C113

C114

16V4Z04021U.0

100_0603_1%

R78

16V7K0402022U

+1.8V_TXLVDS

1

1

1

1

R79

1022_Change R64, R79 from 0 ohm to 1uH/400mA inductor.

2

1

2

2

+1.8V

2

2

1U_WIM32251R0KZF_10%

C118

1

1

1000P_0402_50V7K

C117

2

2

10U_0805_10V4Z

+3VS_TVDACB

+1.8V_LVDS

+3VS

R81

BLM18PG181SN1D_0603

16V7K0402 022U.0

2

R80

1

10V4Z0805 10U

2

1

+1.8V

16V4Z0402 1U.0

10V4Z0603 1U

0_0603_5%

1

1

C119

1

C120

1

C121

2

C122

2

2

2

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

Security Classification

Compal Secret Data

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

CRESTLINE(4/6)-PWR

Rev

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Document Number

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet

10

o f

42

5

4

3

2

1

D

C

B

A

D

C

B

A

5

4

+VCCP

VCC=1260mA

U3F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

T27

VCC_NCTF_4

VSS_NCTF_1

AC35

T37

VCC_NCTF_5

VSS_NCTF_2

AC36

U24

VCC_NCTF_6

VSS_NCTF_3

AD35

U28

VCC_NCTF_7

VSS_NCTF_4

AD36

V31

VCC_NCTF_8

VSS_NCTF_5

AF33

V35

VCC_NCTF_9

VSS_NCTF_6

0

0

0

AF36

AA19

VCC_NCTF_10

VSS_NCTF_7

.

.

.

AH33

AB17

M3V.6 220U

10V4Z0805 10U

10V4Z0402 22U

10V7K0603 22U

16V4Z0402 1U

VCC_NCTF_11

VSS_NCTF_8

C126

1

C127

C128

C129

C130

AK36

VCC_NCTF_18

VSSNCTFVSS_NCTF_15

AM24

AH35

VCC_NCTF_12

VSS_NCTF_9

AB35

+

1

1

1

1

AH36

VCC_NCTF_13

VSS_NCTF_10

AD19

AH37

AD37

AJ33

VCC_NCTF_14

VSS_NCTF_11

AF17

AJ35

VCC_NCTF_15

VSS_NCTF_12

AF35

2

2

2

2

2

VCC_NCTF_16

VSS_NCTF_13

AK33

AK17

VCC_NCTF_17

VSS_NCTF_14

AK35

AM17

AK37

VCC_NCTF_19

VSS_NCTF_16

AP26

VCC_NCTF_20

VSS_NCTF_17

AD33

AP28

VCC_NCTF_21

NCTF

VSS_NCTF_18

AJ36

AR15

VCC_NCTF_22

VSS_NCTF_19

AA33

AR19

VCC_NCTF_25

AM35

VCC_NCTF_23

VSS_NCTF_20

AL33

VCC_NCTF_24

VSS_NCTF_21

AR28

AL35

AA35

VCC_NCTF_26

VCC

VCC_NCTF_27

AP36

VCC_NCTF_29

AA36

VCC_NCTF_28

AP35

AR35

VCC_NCTF_30

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

POWER

Y33

VCC_NCTF_35

Y35

VCC_NCTF_34

Y36

VCC_NCTF_36

Y37

A3

VCC_NCTF_37

SCB

VSS_SCB1

T30

B2

VCC_NCTF_38

VSS_SCB2

T34

C1

VCC_NCTF_39

VSS_SCB3

T35

BL1

VCC_NCTF_40

VSS_SCB4

U29

BL51

U31

VCC_NCTF_41

VSS

VSS_SCB5

A51

VCC_NCTF_42

VSS_SCB6

U35

VCC_NCTF_44

U32

VCC_NCTF_43

U33

U36

VCC_NCTF_45

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

+VCCP

VCC_AXM_1

AT33

VCC_AXM=970mA

AXM

AT31

VCC_AXM_2

VCC_AXM_3

AK29

AK24

10U

10U

VCC_AXM_4

AK23

1

1

AL24

VCC_AXM_5

10V4Z0805_

10V4Z0805_ C135

C136

VCC_AXM_NCTF_1

VCC

VCC_AXM_6

AJ26

AM32

NCTF

AJ23

VCC_AXM_NCTF_7

AL26

VCC_AXM_NCTF_2

VCC_AXM_7

AL28

VCC_AXM_NCTF_3

2

2

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

AM33

VCC_AXM_NCTF_8

AXM

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

AP33

VCC_AXM_NCTF_12

VCC

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

AR31

VCC_AXM_NCTF_16

VCC_AXM_NCTF_17

0

0

0

0

0

AR32

VCC_AXM_NCTF_18

.

.

.

.

.

AR33

1

040222U

1

040222U

1

04021U

1

04021U

1

04021U

VCC_AXM_NCTF_19

C142

C143

C144

C145

C146

2

10V4Z_

2

10V4Z_

2

16V4Z

2

16V4Z

2

16V4Z

CRESTLINE_1p0

5

4

3

2

1

+VCCP

+VCCP

VCC_AXG=7700mA

VCC=1260mA

U3G

AT35

VCC_1

AT34

T17

VCC_2

VCC_AXG_NCTF_1

AH28

VCC_3

VCC_AXG_NCTF_2

T18

0.1U_0402_16V4Z

AC32

T19

AC31

VCC_5

VCC_AXG_NCTF_3

T21

VCC_4

VCC_AXG_NCTF_4

1 C123

C124

AK32

T22

1

1

AJ31

VCC_6

VCC_AXG_NCTF_5

T23

C125

VCC_7

VCC_AXG_NCTF_6

AJ28

T25

VCC_8

CORE

VCC_AXG_NCTF_7

AH32

VCC_9

VCC_AXG_NCTF_8

U15

2

2

2

AH31

VCC_12

VCC_AXG_NCTF_11

U20

VCC_10

VCC_AXG_NCTF_9

U16

AH29

VCC_11

VCC_AXG_NCTF_10

U17

0.22U_0603_10V7K

4.7U_0805_10V4Z

AF32

U19

VCC

VCC_AXG_NCTF_12

U21

R82

VCC_AXG_NCTF_13

VCC_13

U23

0_0603_5%

VCC_AXG_NCTF_15

V16

1

2

R30

VCC_AXG_NCTF_14

U26

VCC_AXG_NCTF_16

V17

VCC_AXG_NCTF_17

VCC_AXG_NCTF_18

V19

VCC_AXG_NCTF_19

V20

VCC_AXG_NCTF_20

V21

VCC_AXG_NCTF_21

V23

VCC_AXG_NCTF_22

V24

POWER VCC_AXG_NCTF_24

Y16

VCC_AXG_NCTF_23

Y15

VCC_AXG_NCTF_25

Y17

AU32

Y19

3720mA

VCC_SM_1

VCC_AXG_NCTF_26

AU33

VCC_SM_2

VCC_AXG_NCTF_27

Y20

+1.8V

0

AU35

VCC_SM_3

VCC_AXG_NCTF_28

Y21

AV33

VCC_SM_4

VCC_AXG_NCTF_29

Y23

.

AW33

Y24

10V4Z0805 10U

10V4Z0805 10U C132

16V7K0402 01U C133

VCC_SM_5

VCC_AXG_NCTF_30

1

1

1

2

AW35

VCC_SM_6

VCC_AXG_NCTF_31

Y26

C131

+

C134

AY35

VCC_SM_7

VCC_AXG_NCTF_32

Y28

BA32

Y29

BC32

VCC_SM_12

VCC_AXG_NCTF_37

AB19

BA33

VCC_SM_8

VCC_AXG_NCTF_33

AA16

220U_6.3V_M

2

2

2

1

BA35

VCC_SM_9

VCC_AXG_NCTF_34

AA17

BB33

VCC_SM_10

VCC_AXG_NCTF_35

AB16

VCC_SM_11

VCC_AXG_NCTF_36

BC33

VCC_SM_13

SM

VCC_AXG_NCTF_38

AC16

BC35

VCC_SM_14

VCC_AXG_NCTF_39

AC17

BD32

VCC_SM_15

VCC_AXG_NCTF_40

AC19

BD35

AD15

BE32

VCC_SM_16

VCC

VCC_AXG_NCTF_41

AD16

VCC_SM_17

NCTF

VCC_AXG_NCTF_42

BG32

VCC_SM_21

VCC_AXG_NCTF_46

AH16

BE33

VCC_SM_18

VCC_AXG_NCTF_43

AD17

BE35

VCC_SM_19

VCC_AXG_NCTF_44

AF16

BF33

VCC_SM_20

VCC_AXG_NCTF_45

AF19

BF34

AH15

BG33

VCC_SM_22

GFX

VCC_AXG_NCTF_47

AH17

VCC_SM_23

VCC_AXG_NCTF_48

BH34

VCC_SM_25

VCC_AXG_NCTF_50

AJ17

BG35

VCC_SM_24

VCC_AXG_NCTF_49

AH19

BH32

AJ16

BH35

VCC_SM_26

VCC

VCC_AXG_NCTF_51

AJ19

VCC_SM_27

VCC_AXG_NCTF_52

BJ34

VCC_SM_29

VCC_AXG_NCTF_54

AL16

BJ32

VCC_SM_28

VCC_AXG_NCTF_53

AK16

BJ33

AK19

BK32

VCC_SM_30

VCC_AXG_NCTF_55

AL17

VCC_SM_31

VCC_AXG_NCTF_56

BK33

VCC_SM_32

VCC_AXG_NCTF_57

AL19

BK34

VCC_SM_33

VCC_AXG_NCTF_58

AL20

VCC_AXM=970mA

BK35

VCC_SM_34

VCC_AXG_NCTF_59

AL21

BL33

VCC_SM_35

VCC_AXG_NCTF_60

AL23

+VCCP

AU30

VCC_SM_36

VCC_AXG_NCTF_61

AM15

VCC_AXG_NCTF_62

AM16

VCC_AXG_NCTF_63

AM19

VCC_AXG_NCTF_64

AM20

VCC_AXG_NCTF_65

AM21

VCC_AXG=7700mA

R20

VCC_AXG_1

VCC_AXG_NCTF_66

AM23

T14

VCC_AXG_2

VCC_AXG_NCTF_67

AP15

+VCCP

W13

VCC_AXG_3

VCC_AXG_NCTF_68

AP16

W14

AP17

Y12

VCC_AXG_4

VCC_AXG_NCTF_69

AP19

10U_0805_10V4Z

0.1U_0402_16V4Z

VCC_AXG_5

VCC_AXG_NCTF_70

AA20

AP20

AA23

VCC_AXG_6

VCC_AXG_NCTF_71

AP21

VCC_AXG_7

VCC_AXG_NCTF_72

1

1

1

1

1

AA26

VCC_AXG_8

VCC_AXG_NCTF_73

AP23

C137

AA28

VCC_AXG_9

VCC_AXG_NCTF_74

AP24

C138

+

C139

AB21

AR20

C140

C141

AB24

VCC_AXG_10

VCC_AXG_NCTF_75

AR21

1U_0603_10V4Z

2

2

2

2

2

AB29

VCC_AXG_11

VCC_AXG_NCTF_76

AR23

AC20

VCC_AXG_12

GFX

VCC_AXG_NCTF_77

AR24

VCC_AXG_13

VCC_AXG_NCTF_78

10U_0805_10V4Z

AC21

VCC_AXG_14

VCC_AXG_NCTF_79

AR26

AC23

V26

220U_6.3V_M

AC24

VCC_AXG_15

VCC_AXG_NCTF_80

V28

AC26

VCC_AXG_16

VCC

VCC_AXG_NCTF_81

V29

VCC_AXG_17

VCC_AXG_NCTF_82

AD20

VCC_AXG_19

VCC_AXG_NCTF_83

Y31

AC28

VCC_AXG_18

AC29

AD23

VCC_AXG_20

VCC_AXG_21

AW45VCCSM_LF1

AD24

VCC_AXG_22

LF

VCC_SM_LF1

AD28

BC39 VCCSM_LF2

VCC_AXG_23

VCC_SM_LF2

AF21

BE39 VCCSM_LF3

VCC_AXG_24

VCC_SM_LF3

AF26

BD17 VCCSM_LF4

AA31

VCC_AXG_25

SM

VCC_SM_LF4

BD4

VCCSM_LF5

VCC_AXG_26

VCC_SM_LF5

AH20

AW8 VCCSM_LF6

VCC_AXG_27

VCC_SM_LF6

AH21

AT6

VCCSM_LF7

AH23

VCC_AXG_28

VCC

VCC_SM_LF7

16V4Z04021U.0C147

16V4Z04021U.0C148

10V7K060322U.0C149

1

10V7K060322U.0C150

1

10V7K060347U.0C151

1

10V4Z06031UC152

1

10V4Z06031UC153

VCC_AXG_29

1

1

1

AH24

VCC_AXG_30

AH26

VCC_AXG_31

AD31

VCC_AXG_32

2

2

2

2

2

2

2

AJ20

VCC_AXG_33

AN14

VCC_AXG_34

CRESTLINE_1p0

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

CRESTLINE((5/6)-PWR/GND

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Date:

Wednesday, October 24, 2007

1

Sheet

11

o f

42

D

C

B

A

5

4

3

2

1

U3I

A13

VSS_1

VSS_100

AW24

A15

AW29

VSS_2

VSS_101

A17

AW32

VSS_3

VSS_102

A24

AW5

VSS_4

VSS_103

AA21

AW7

VSS_5

VSS_104

AA24

AY10

VSS_6

VSS_105

AA29

AY24

VSS_7

VSS_106

U3J

AB20

AY37

D

VSS_8

VSS_107

AB23

AY42

C46

W11

VSS_9

VSS_108

VSS_199

VSS_287

AB26

AY43

C50

W39

VSS_10

VSS_109

VSS_200

VSS_288

AB28

AY45

C7

W43

VSS_11

VSS_110

VSS_201

VSS_289

AB31

AY47

D13

W47

VSS_12

VSS_111

VSS_202

VSS_290

AC10

AY50

D24

W5

VSS_13

VSS_112

VSS_203

VSS_291

AC13

B10

D3

W7

VSS_14

VSS_113

VSS_204

VSS_292

AC3

B20

D32

Y13

VSS_15

VSS_114

VSS_205

VSS_293

AC39

B24

D39

Y2

VSS_16

VSS_115

VSS_206

VSS_294

AC43

B29

D45

Y41

VSS_17

VSS_116

VSS_207

VSS_295

AC47

B30

D49

Y45

VSS_18

VSS_117

VSS_208

VSS_296

AD1

B35

E10

Y49

VSS_19

VSS_118

VSS_209

VSS_297

AD21

B38

E16

Y5

VSS_20

VSS_119

VSS_210

VSS_298

AD26

B43

E24

Y50

VSS_21

VSS_120

VSS_211

VSS_299

AD29

B46

E28

Y11

VSS_22

VSS_121

VSS_212

VSS_300

AD3

B5

E32

P29

VSS_23

VSS_122

VSS_213

VSS_301

AD41

B8

E47

T29

VSS_24

VSS_123

VSS_214

VSS_302

AD45

BA1

F19

T31

VSS_25

VSS_124

VSS_215

VSS_303

AD49

BA17

F36

T33

VSS_26

VSS_125

VSS_216

VSS_304

AD5

BA18

F4

R28

VSS_27

VSS_126

VSS_217

VSS_305

AD50

BA2

F40

VSS_28

VSS_127

VSS_218

AD8

BA24

F50

VSS_29

VSS_128

VSS_219

AE10

BB12

G1

VSS_30

VSS_129

VSS_220

AE14

BB25

G13

AA32

VSS_31

VSS_130

VSS_221

VSS_306

AE6

BB40

G16

AB32

VSS_32

VSS

VSS_131

VSS_222

VSS_307

AF20

BB44

G19

AD32

VSS_33

VSS_132

VSS_223

VSS_308

AF23

BB49

G24

AF28

VSS_34

VSS_133

VSS_224

VSS_309

AF24

BB8

G28

AF29

VSS_35

VSS_134

VSS_225

VSS_310

AF31

BC16

G29

AT27

VSS_36

VSS_135

VSS_226

VSS_311

AG2

BC24

G33

AV25

VSS_37

VSS_136

VSS_227

VSS_312

AG38

BC25

G42

H50

VSS_38

VSS_137

VSS_228

VSS_313

AG43

BC36

G45

VSS_39

VSS_138

VSS_229

AG47

BC40

G48

C

VSS_40

VSS_139

VSS_230

AG50

BC51

G8

VSS_41

VSS_140

VSS_231

AH3

BD13

H24

VSS_42

VSS_141

VSS_232

AH40

BD2

H28

VSS_43

VSS_142

VSS_233

AH41

BD28

H4

VSS_44

VSS_143

VSS_234

AH7

BD45

H45

VSS_45

VSS_144

VSS_235

AH9

BD48

J11

VSS_46

VSS_145

VSS_236

AJ11

BD5

J16

VSS_47

VSS_146

VSS_237

AJ13

BE1

J2

VSS_48

VSS_147

VSS_238

AJ21

BE19

J24

VSS_49

VSS_148

VSS_239

AJ24

BE23

J28

VSS_50

VSS_149

VSS_240

VSS

AJ29

BE30

J33

VSS_52

VSS_151

VSS_242

AJ32

VSS_51

VSS_150

BE42

J35

VSS_241

AJ43

VSS_53

VSS_152

BE51

J39

VSS_243

AJ45

VSS_54

VSS_153

BE8

AJ49

BF12

K12

VSS_55

VSS_154

VSS_245

AK20

BF16

K47

VSS_56

VSS_155

VSS_246

AK21

BF36

K8

VSS_57

VSS_156

VSS_247

AK26

BG19

L1

VSS_58

VSS_157

VSS_248

AK28

BG2

L17

VSS_59

VSS_158

VSS_249

AK31

BG24

L20

VSS_60

VSS_159

VSS_250

AK51

BG29

L24

VSS_61

VSS_160

VSS_251

AL1

BG39

L28

VSS_62

VSS_161

VSS_252

AM11

BG48

L3

VSS_63

VSS_162

VSS_253

AM13

BG5

L33

VSS_64

VSS_163

VSS_254

AM3

BG51

L49

VSS_65

VSS_164

VSS_255

AM4

BH17

M28

VSS_66

VSS_165

VSS_256

AM41

BH30

M42

VSS_67

VSS_166

VSS_257

AM45

BH44

M46

VSS_68

VSS_167

VSS_258

AN1

BH46

M49

VSS_69

VSS_168

VSS_259

AN38

BH8

M5

VSS_70

VSS_169

VSS_260

AN39

BJ11

M50

VSS_71

VSS_170

VSS_261

AN43

BJ13

M9

B

VSS_72

VSS_171

VSS_262

AN5

BJ38

N11

VSS_73

VSS_172

VSS_263

AN7

BJ4

N14

VSS_74

VSS_173

VSS_264

AP4

BJ42

N17

VSS_75

VSS_174

VSS_265

AP48

BJ46

N29

VSS_76

VSS_175

VSS_266

AP50

BK15

N32

VSS_77

VSS_176

VSS_267

AR11

BK17

N36

VSS_78

VSS_177

VSS_268

AR2

BK25

N39

VSS_79

VSS_178

VSS_269

AR39

BK29

N44

VSS_80

VSS_179

VSS_270

AR44

BK36

N49

VSS_81

VSS_180

VSS_271

AR47

BK40

N7

VSS_82

VSS_181

VSS_272

AR7

BK44

P19

VSS_83

VSS_182

VSS_273

AT10

BK6

P2

VSS_84

VSS_183

VSS_274

AT14

BK8

P23

VSS_85

VSS_184

VSS_275

AT41

BL11

P3

VSS_86

VSS_185

VSS_276

AT49

BL13

P50

VSS_87

VSS_186

VSS_277

AU1

BL19

R49

VSS_88

VSS_187

VSS_278

AU23

BL22

T39

VSS_89

VSS_188

VSS_279

AU29

BL37

T43

VSS_90

VSS_189

VSS_280

AU3

BL47

T47

VSS_91

VSS_190

VSS_281

AU36

C12

U41

VSS_92

VSS_191

VSS_282

AU49

C16

U45

VSS_93

VSS_192

VSS_283

AU51

C19

U50

VSS_94

VSS_193

VSS_284

AV39

C28

V2

VSS_95

VSS_194

VSS_285

AV48

C29

V3

VSS_96

VSS_195

VSS_286

AW1

C33

VSS_97

VSS_196

AW12

C36

VSS_98

VSS_197

CRESTLINE_1p0

AW16

C41

VSS_99

VSS_198

CRESTLINE_1p0

A

Security Classification

2007/03/26

Compal Secret Data

2006/03/10

Title

Compal Electronics, Inc.

Issued Date

Deciphered Date

CRESTLINE((6/6)-PWR/GND

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Wednesday, October 24, 2007

Sheet

12

o f

42

5

4

3

2

1

D

C

B

A

D

C

B

A

5

4

8DDR_A_DQS#[0..7] 8 DDR_A_D[0..63]

8 DDR_A_DM[0..7]

8 DDR_A_DQS[0..7]

7,8 DDR_A_MA[0..14]

Layout Note:

Place near JP34

+1.8V

.2			.2			.2			.2			.2			.0			.0			.0			.0				1
2U	1		2U	1		2U	1		2U	1		2U	1		1U	1		1U	1		1U	1	C164	1U	1	C165
																												220U_6.3V_M
_0805_	2	C157	_0805_	2	C158	_0805_	2	C159	_0805_	2	C160	_0805_	2	C161	_0402_	2	C162	_0402_	2	C163	_0402_	2	@	_0402_	2	@		2
																												+ C156
16V4Z			16V4Z			16V4Z			16V4Z			16V4Z			16V4Z			16V4Z			16V4Z			16V4Z

Layout Note:

Place one cap close to every 2 pullup resistors terminated to +0.9VS

+0.9V

_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0				_1U.0
0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1		0402		1
16V4Z		C166		16V4Z		C167		16V4Z		C168		16V4Z		C169		16V4Z		C170		16V4Z		C171		16V4Z		C172		16V4Z		C173		16V4Z		C174		16V4Z		C175		16V4Z		C176		16V4Z		C177		16V4Z		C178
		2				2				2				2				2				2				2				2				2				2				2				2				2

RP1 DDR_A_MA3 1 DDR_A_MA10 2

DDR_A_MA8	RP3
		1
DDR_A_MA5	2
	RP5

DDR_A_RAS# 1

DDR_CS0_DIMMA# 2

RP7 DDR_A_MA1 1 DDR_A_BS0 2

RP9 DDR_A_WE# 1

DDR_A_CAS# 2

RP11 DDR_CS1_DIMMA# 2 M_ODT1 1

DDR_A_MA11 1

R85

	+0.9V
	RP2	56_0404_4P2R_5%
4	4	1	DDR_CKE0_DIMMA
3	3	2	DDR_A_BS2
56_0404_4P2R_5% RP4		56_0404_4P2R_5%
4	4	1	DDR_A_MA7
3	3	2	DDR_A_MA6
56_0404_4P2R_5% RP6		56_0404_4P2R_5%
4	4	1	DDR_A_MA12
3	3	2	DDR_A_MA9
56_0404_4P2R_5% RP8		56_0404_4P2R_5%
4	4	1	DDR_A_MA4
3	3	2	DDR_A_MA2
56_0404_4P2R_5% RP10		56_0404_4P2R_5%
4	4	1	DDR_A_MA0
3	3	2	DDR_A_BS1

56_0404_4P2R_5% RP12 56_0404_4P2R_5%

34 1 M_ODT0

43 2 DDR_A_MA13

56_0404_4P2R_5%		RP13 56_0404_4P2R_5%
	4	1	DDR_CKE1_DIMMA
2	3	2	DDR_A_MA14
56_0402_5%

Layout Note:

Place these resistor closely JP34,all

trace length Max=1.5"

5

4

16V4Z_0402_1U.0

1

2

C443	0402 1U.0
	16V4Z_

3

2

1

+1.8V

+1.8V

V_DDR_MCH_REF

V_DDR_MCH_REF 7,14,35

1

JP4

2

.2

.0

VREF

VSS

3

4

DDR_A_D6

2U

1

1U

1

VSS

DQ4

DDR_A_D4

5

6

DDR_A_D0

0805_

C154

0402_

C155

9

DQ1

VSS

10

DDR_A_DM0

DDR_A_D1

7

DQ0

DQ5

8

DDR_A_DQS#0

11

VSS

DM0

12

16V4Z

2

16V4Z

2

DDR_A_DQS0

13

DQS0

DQ6

14

DDR_A_D5

DQS0#

VSS

DDR_A_D2

15

VSS

DQ7

16

DDR_A_D7

17

18

DQ2

VSS

DDR_A_D3

19

20

DDR_A_D13

DQ3

DQ12

21

22

DDR_A_D12

DDR_A_D8

VSS

DQ13

23

24

DQ8

VSS

DDR_A_D14

25

26

DDR_A_DM1

DQ9

DM1

27

28

DDR_A_DQS#1

VSS

VSS

M_CLK_DDR0

29

30

M_CLK_DDR0 7

DQS1#

CK0

DDR_A_DQS1

31

32

M_CLK_DDR#0

DQS1

CK0#

M_CLK_DDR#0 7

33

34

DDR_A_D9

VSS

VSS

DDR_A_D11

35

36

DQ10

DQ14

DDR_A_D15

37

38

DDR_A_D10

DQ11

DQ15

39

40

VSS

VSS

DDR_A_D16

41

VSS

VSS

42

DDR_A_D20

43

DQ16

DQ20

44

DDR_A_D17

45

46

DDR_A_D21

DQ17

DQ21

47

48

DDR_A_DQS#2

VSS

VSS

1

49

50

PM_EXTTS#0

7

C444

DQS2#

NC

DDR_A_DQS2

DDR_A_DM2

51

DQS2

DM2

52

53

54

DDR_A_D18

55

VSS

VSS

56

DDR_A_D23

2

DQ18

DQ22

DDR_A_D19

57

58

DDR_A_D22

DQ19

DQ23

59

60

DDR_A_D29

VSS

VSS

DDR_A_D28

61

62

DQ24

DQ28

DDR_A_D24

63

64

DDR_A_D25

DQ25

DQ29

65

66

DDR_A_DM3

VSS

VSS

DDR_A_DQS#3

67

68

DM3

DQS3#

69

70

DDR_A_DQS3

NC

DQS3

71

72

DDR_A_D26

VSS

VSS

DDR_A_D31

73

74

DQ26

DQ30

DDR_A_D27

75

76

DDR_A_D30

DQ27

DQ31

77

78

DDR_CKE0_DIMMA

VSS

VSS

DDR_CKE1_DIMMA

7 DDR_CKE0_DIMMA

79

80

DDR_CKE1_DIMMA 7

CKE0

NC/CKE1

81

82

VDD

VDD

83

84

DDR_A_BS2

NC

NC/A15

DDR_A_MA14

8

DDR_A_BS2

85

86

BA2

NC/A14

87

88

DDR_A_MA12

VDD

VDD

DDR_A_MA11

89

90

A12

A11

DDR_A_MA9

91

92

DDR_A_MA7

A9

A7

DDR_A_MA8

93

94

DDR_A_MA6

A8

A6

95

96

DDR_A_MA5

VDD

VDD

DDR_A_MA4

97

98

A5

A4

DDR_A_MA3

99

100

DDR_A_MA2

A3

A2

DDR_A_MA1

101

102

DDR_A_MA0

A1

A0

103

104

DDR_A_MA10

VDD

VDD

DDR_A_BS1

105

106

DDR_A_BS1 8

A10/AP

BA1

DDR_A_BS0

107

108

DDR_A_RAS#

8

DDR_A_BS0

BA0

RAS#

DDR_A_RAS# 8

DDR_A_WE#

109

110

DDR_CS0_DIMMA#

8

DDR_A_WE#

WE#

S0#

DDR_CS0_DIMMA# 7

111

112

DDR_A_CAS#

VDD

VDD

M_ODT0

8

DDR_A_CAS#

113

114

M_ODT0

7

CAS#

ODT0

DDR_CS1_DIMMA#

115

116

DDR_A_MA13

7 DDR_CS1_DIMMA#

NC/S1#

NC/A13

117

118

M_ODT1

VDD

VDD

7

M_ODT1

119

120

NC/ODT1

NC

121

122

DDR_A_D37

VSS

VSS

DDR_A_D39

123

124

DQ32

DQ36

DDR_A_D36

125

126

DDR_A_D38

DQ33

DQ37

127

128

DDR_A_DQS#4

VSS

VSS

DDR_A_DM4

129

130

DQS4#

DM4

DDR_A_DQS4

131

132

DQS4

VSS

DDR_A_D34

133

134

VSS

DQ38

DDR_A_D35

135

136

DDR_A_D33

DQ34

DQ39

DDR_A_D32

137

138

DQ35

VSS

DDR_A_D45

139

140

VSS

DQ44

DDR_A_D40

141

142

DDR_A_D43

DQ40

DQ45

DDR_A_D44

143

144

DQ41

VSS

DDR_A_DQS#5

145

146

VSS

DQS5#

DDR_A_DM5

147

148

DDR_A_DQS5

DM5

DQS5

149

150

DDR_A_D41

VSS

VSS

DDR_A_D47

151

152

DQ42

DQ46

DDR_A_D46

153

154

DDR_A_D42

DQ43

DQ47

155

156

DDR_A_D49

VSS

VSS

DDR_A_D52

157

158

DQ48

DQ52

DDR_A_D48

159

160

DDR_A_D53

DQ49

DQ53

161

162

VSS

VSS

M_CLK_DDR1

163

164

M_CLK_DDR1 7

NC,TEST

CK1

165

166

M_CLK_DDR#1

DDR_A_DQS#6

VSS

CK1#

M_CLK_DDR#1 7

167

168

DQS6#

VSS

DDR_A_DQS6

169

170

DDR_A_DM6

DQS6

DM6

171

172

DDR_A_D54

VSS

VSS

DDR_A_D51

173

174

DQ50

DQ54

DDR_A_D50

175

176

DDR_A_D55

DQ51

DQ55

177

178

DDR_A_D61

VSS

VSS

DDR_A_D57

179

180

DQ56

DQ60

DDR_A_D60

181

182

DDR_A_D56

DQ57

DQ61

183

184

DDR_A_DM7

VSS

VSS

DDR_A_DQS#7

185

186

DM7

DQS7#

187

188

DDR_A_DQS7

DDR_A_D59

VSS

DQS7

189

190

DQ58

VSS

DDR_A_D58

191

192

DDR_A_D62

DQ59

DQ62

193

194

DDR_A_D63

CLK_SMBDATA

VSS

DQ63

14,15

CLK_SMBDATA

195

196

SDA

VSS

CLK_SMBCLK

197

198

14,15

CLK_SMBCLK

SCL

SAO

+3VS

199

200

VDDSPD

SA1

203

204

16V4Z08052.2U

GND

GND

1

2 1

1

1

16V4Z04020.1U

5%

040210K5%

C180

C179

CONN@

R83 0402

R84

FOX_ASOA426-M4R-TR

2

2

SO-DIMM A

10K_

2

SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4

FOX_AS0A426-M4R-TR_200P

Security Classification

Compal Secret Data

Compal Electronics, Inc.

Issued Date

2007/03/26

Deciphered Date

2006/03/10

Title

DDRII-SODIMM SLOT1

THIS SHEETOFENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRETINFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size

Document Number

Rev

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Custom

LA-4031P

1.0

MAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Date:

Wednesday, October 24, 2007

1

Sheet

13

o f

42

D

C

B

A