Compal LA-2841, Pavilion dv5000 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel

3 3

4 4

A

Calistoga_GM/PM+ICH7-M core logic

2005-12-15

REV:1.0

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-2841

160Thursday, December 15, 2005

E

1.0

of

A

Compal confidential

File Name : LA-2841

ZZZ

B

C

D

E

PCB

1 1

VRAM
128/256MB

page 22,23,24,25

Thermal Sensor
ADM1032

page 4

Fan Control

page 4

uFCBGA-479/uFCPGA-478 CPU

Nvidia
NV71/72M

page 18,19,20,21,26

PCI-E x 16

Intel Calistoga GMCH

LVDS Panel
Interface

2 2

page 16

CRT & TV OUT

page 17

LAN I/F

3.3V 33 MHz

10/100 LAN

3 3

page 35

CardBus Controller

PCI BUS

TI PCI7412

page 32

RTC CKT.

page 29

RJ45 CONN

page 35

Slot 0

page 33

1394

page 32

Card reader

page 32

Touch Pad

Power On/Off CKT.

page 42

Mobile Yonah

page 4, 5, 6

H_A#(3..31)
H_D#(0..63)

FSB

533/667MHz

PCBGA 1466

page 7, 8, 9, 10,11,12

DMI

Intel ICH7-M

mBGA-652

page 27, 28, 29, 30

LPC BUS

ENE KB910/L

page 44

page 42

Int.KBD

BIOS

DDR2 -400/533/667

Dual Channel

PCIE x3

USB2.0

AC-LINK

page 42

page 45

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

Mini-PCIE Card

New Card
Connector x2

USB conn X3

BT Conn

Audio CKT
AMOM

SATA HDD
Connector x2

PATA CDROM
Connector

page 37

page 34

page 41

page 41

page 38

page 31

page 31

Clock Generator
ICS 954306

page 15

MODEM
AMOM

page 39

AMP & Audio Jack

page 40

SPR CONN.

*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DC JACK
*TVOUT CONN

DC/DC Int erface CKT.

4 4

page 47

*USB CONN x1
*CIR x1

page 46

Power Circuit DC/DC

page 48~56

A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-2841

E

1.0

of

260Thursday, December 15, 2005

Voltage Rails

power
plane

State

+B
LDO3
LDO5

+5VALW
+3VALW

+1.8V
+5V

A

+5VS
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.2VS
+VGA_CORE
+0.9VS
+CPU_CORE
+VCCP

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON

X MEANS OFF

1 1

O

O
O
O

O

X

O

O
O
O

X

O

XX

X

OO

OO

X

X

XX X

PCI Devices

EXTERNAL

CARD BUS & 1394

IDSEL# REQ/GNT# PIRQ
AD22 2 C,D,E,G

Load BOM check item

1.U31 GM/PM/GML part number

2.U6 ICH7 part number

3.VRAM part number and Page26 RAM_CFG[0:3]/PCI_DEVID[0:3] modify check

4.For NV73 R510/R75/R533/R168 change to 499ohm

5.U33 NV7x part number

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-2841

360Thursday, December 15, 2005

of

1.0

5

H_A#[3..31]<7>

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

D D

H_REQ#[0..4]<7>

H_ADSTB#0<7>

C C

R17

56_0402_5%

1 2

+VCCP

B B

H_PROCHOT#<53>

1 2

+VCCP

75_0402_5%

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1<7>

CLK_CPU_BCLK<15>

CLK_CPU_BCLK#<15>

H_BPRI#<7>

H_DEFER#<7>

H_DRDY#<7>

H_HITM#<7>

H_LOCK#<7>

H_RESET#<7>

H_RS#[0..2]<7>

H_TRDY#<7>

ITP_DBRESET#<29>

H_DBSY#<7>

H_DPSLP#<28>

H_DPRSTP#<28,53>

H_DPWR#<7>

R18

H_PWRGOOD<28>

H_CPUSLP#<7>

R456 1K_0402_5%@

1 2

R455 51_0402_5%

1 2

H_THERMTRIP#<7,28>

+VCCP

12

R457

56_0402_5%@

B

2

E

3 1

C

Q35

MMBT3904_SOT23@

5

H_ADS#<7>
H_BNR#<7>

H_BR0#<7>

H_HIT#<7>

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2 H_INIT#
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

OCP# <29>

JP16A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47903-2741-42_YONAH

H_DPSLP#

H_DPRSTP#

YONAH

MISC

R437

1 2

56_0402_5%@

R436

1 2

56_0402_5%@

4

DATA GROUP

LEGACY CPU

+VCCP

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

This shall place near CPU

H_D#[0..63] <7>

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

J26
M26
V23
AC20

H23
M24
W24
AD23
G22
N25
Y25
AE24

A6
A5
C4
B3
C6
B4

D5
A3

H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_A20M#
H_FERR#
H_IGNNE#

H_INTR
H_NMI

H_STPCLK#
H_SMI#

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

H_A20M# <28>
H_FERR# <28>
H_IGNNE# <28>
H_INIT# <28>
H_INTR <28>
H_NMI <28>

H_STPCLK# <28>
H_SMI# <28>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ITP_DBRESET#

R181 200_0402_5%@

1 2

2005/03/10 2006/03/10

ITP_TDI
ITP_TMS
ITP_TDO
ITP_BPM#5
ITP_TRST#
ITP_TCK

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4

Thermal Sensor ADM1032AR

2200P_0402_50V7K

+3VS

FAN control

Compal Secret Data

Deciphered Date

2

R6 56_0402_5%

1 2

R3 56_0402_5%

1 2

R2 56_0402_5%

1 2

R1 56_0402_5%

1 2

R4 56_0402_5%

1 2

R5 56_0402_5%

1 2

T27

PAD

T5

PAD

T4

PAD

T3

PAD

T1

PAD

T2

PAD

+3VS

2

C598

0.1U_0402_16V4Z

C592

1 2

R458

1 2

10K_0402_5%

BAS16_SOT23

EN_FAN1<44>

1

H_THERMDA
H_THERMDC

THERM#

+5VS

FAN1

FAN1

D22

3

2

+VCCP

U30

1

VDD

2

D+

3

D­THERM#4GND

ADM1032AR_SOP8

SCLK

SDATA

ALERT#

EC_SMC_2

8

EC_SMD_2

7
6
5

Address:100_1100

EC_SMC_2<44>

EC_SMD_2<44>

C765 10U_1206_16V4Z

1 2

U40

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

+5VS +3VS

12

1SS355_SOD323
D28

1

2

FAN_SPEED1<44>

EC_SMC_2
EC_SMD_2

8

GND

7

GND

6

GND

5

GND

1

1

2

2

1000P_0402_50V7K

C761

C763 10U_0805_10V4Z

C762

1000P_0402_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2841

R551
10K_0402_5%

1 2

ACES_85205-0300

1

2

JP30

1

1
2
3

1.0

of

460Thursday, December 15, 2005

1

5

4

3

2

1

V_CPU_GTLREF

+VCCP

12

R454
1K_0402_1%

12

R451
2K_0402_1%

+CPU_CORE

R442
100_0402_1%

1 2

R441
100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R452

54.9_0402_1%

R439

R453

27.4_0402_1%

D D

Close to CPU pin AD26
within 500mils.

C C

B B

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C586

C587

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

27.4_0402_1%

1

R438

12

54.9_0402_1%

1

2

10U_0805_10V4Z

VCCSENSE<53>
VSSSENSE<53>

H_PSI#<53>

CPU_VID0<53>
CPU_VID1<53>
CPU_VID2<53>
CPU_VID3<53>
CPU_VID4<53>
CPU_VID5<53>
CPU_VID6<53>

V_CPU_GTLREF

CPU_BSEL0<15>
CPU_BSEL1<15>
CPU_BSEL2<15>

+CPU_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP16B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

JP16C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12
AC12
AF12
AE12
AB10

AB9

AA10

AA9

AD10

AD9

AC10

AC9

AF10

AF9

AE10

AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10

A10
D10
C10
F10
E10

B9
A9
D9
C9

F9

E9
B7
A7

F7

YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

POWER, GROUND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOX_PZ47903-2741-42_YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Yonah CPU in mFCPGA479

LA-2841

560Thursday, December 15, 2005

1

1.0

of

5

4

3

2

1

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

South Side Secondary

B B

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

+CPU_CORE

1

+

C37

2

330U_V_2.5VK_R9

1

C13
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

C40
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

C47

330U_V_2.5VK_R9

C584

330U_V_2.5VK_R9

1

2

1

2

1

2

1

2

1

+

2

C23
10U_0805_6.3V6M

C35
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C10
10U_0805_6.3V6M

1

+

C585

2

330U_V_2.5VK_R9@

1

C14
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

1

+

+

C8

@

2

2

330U_V_2.5VK_R9

C583

@

820U_E9_2_5V_M_R7

1

2

+

1

C28
10U_0805_6.3V6M

2

1

C42
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C15
10U_0805_6.3V6M

2

1

+

C576

2

330U_V_2.5VK_R9

1

C34
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

1

C16
10U_0805_6.3V6M

2

1

C1
10U_0805_6.3V6M

2

1

+

North Side Secondary

C578

2

@

820U_E9_2_5V_M_R7

1

C18
10U_0805_6.3V6M

2

1

C41
10U_0805_6.3V6M

2

1

C11
10U_0805_6.3V6M

2

1

C6
10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

ESR <= 1.5m ohm
Capacitor > 1980uF

C19
10U_0805_6.3V6M

C2
10U_0805_6.3V6M

C36
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

1

C30
10U_0805_6.3V6M

2

1

C48
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C12
10U_0805_6.3V6M

2

Mid Frequence Decoupling

+VCCP

1

+

C591

220U_D2_4VM

A A

5

2

1

C43

0.1U_0402_16V4Z

2

1

C44

0.1U_0402_16V4Z

2

4

1

C45

0.1U_0402_16V4Z

2

1

C3

0.1U_0402_16V4Z

2

1

C4

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C5

0.1U_0402_16V4Z

2

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CPU Bypass capacitors

LA-2841

1

of

660Thursday, December 15, 2005

1.0

5

4

3

2

1

H_D#[0..63]<4>

D D

C C

+VCCP

12

12

R462

54.9_0402_1%

+VCCP

R45

R42

12

R466

24.9_0402_1%

12

100_0402_1%

12

200_0402_1%

R461

54.9_0402_1%

B B

A A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R464

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C87

2

0.1U_0402_16V4Z

5

H1
H3
G1

G2

H4

K11

G4

T10

W11

U7

U9
U11
T11

W9

W7

U5

W6
AB7

AA9

W4

W3

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

AA1
AB4
AC9

AB11
AC11

AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5

AD10

AD4
AC8

J13
K13

U1

W1

U31A

F1

HD0#

J1

HD1#
HD2#

J6

HD3#
HD4#

K2

HD5#
HD6#
HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#
HD12#

J3

HD13#
HD14#
HD15#
HD16#
HD17#

T3

HD18#
HD19#
HD20#
HD21#
HD22#
HD23#

T1

HD24#

T8

HD25#

T4

HD26#
HD27#
HD28#

T9

HD29#
HD30#

T5

HD31#
HD32#
HD33#
HD34#
HD35#

Y3

HD36#

Y7

HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#

Y8

HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HVREF0
HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP
HYSCOMP

E4

HXSWING
HYSWING

CALISTOGA_FCBGA1466~D

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HOST

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#
HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R38

221_0603_1%

12

R37

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

H_SWNG0

1

2

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

C82

0.1U_0402_16V4Z

+VCCP+VCCP

12

R463

12

R465

H_A#[3..31] <4>

H_REQ#[0..4] <4>

H_ADSTB#0 <4>
H_ADSTB#1 <4>

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

H_RS#[0..2] <4>

221_0603_1%

H_SWNG1

1

C601

2

100_0402_1%

0.1U_0402_16V4Z

U31B

AE35
AF39
AG35
AH39

AC35
AE39
AF35
AG39

AE37
AF41
AG37
AH41

AC37
AE41
AF37
AG41

AY35

AR1

AW7

AW40
AW35

AT1
AY7

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20
AF10

BA13
BA12
AY20
AU21

AV9
AT9

AK1

AK41

G28

F25

H26

G6
AH33
AH34

K28

CALISTOGA_FCBGA1466~D

Deciphered Date

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SM_RCOMPN
SM_RCOMPP

SM_VREF0
SM_VREF1

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

ICH_SYNC#

DMI

DDR MUXING

PM

2

PAD
PAD

1

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
DPRSLPVR
H_THERMTRIP#
ICH_POK
PLTRST_R#

12

+1.8V

12

R483

12

R481

Compal Secret Data

100_0402_1%

100_0402_1%

DMI_TXN0<29>
DMI_TXN1<29>
DMI_TXN2<29>
DMI_TXN3<29>

DMI_TXP0<29>
DMI_TXP1<29>
DMI_TXP2<29>
DMI_TXP3<29>

DMI_RXN0<29>
DMI_RXN1<29>
DMI_RXN2<29>
DMI_RXN3<29>

DMI_RXP0<29>
DMI_RXP1<29>
DMI_RXP2<29>
DMI_RXP3<29>

M_CLK_DDR0<13>
M_CLK_DDR1<13>
M_CLK_DDR2<14>
M_CLK_DDR3<14>

M_CLK_DDR#0<13>
M_CLK_DDR#1<13>
M_CLK_DDR#2<14>
M_CLK_DDR#3<14>

DDR_CKE0_DIMMA<13>
DDR_CKE1_DIMMA<13>
DDR_CKE2_DIMMB<14>
DDR_CKE3_DIMMB<14>

DDR_CS0_DIMMA#<13>
DDR_CS1_DIMMA#<13>
DDR_CS2_DIMMB#<14>
DDR_CS3_DIMMB#<14>

T17
T11

+1.8V

R40 80.6_0402_1%
R41 80.6_0402_1%

PLT_RST#<27,31,32,34,37>

V_DDR_MCH_REF<13,14>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

M_ODT0<13>
M_ODT1<13>
M_ODT2<14>
M_ODT3<14>

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#<29>
PM_EXTTS#0<13,14>
DPRSLPVR<29,53>

H_THERMTRIP#<4,28>

ICH_POK<29,44>

R98 100_0402_1%

MCH_ICH_SYNC#<27>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

C663

0.1U_0402_16V4Z

2005/03/10 2006/03/10

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP

G_CLKN

D_REF_CLKN

D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

Title

Size Document Number Rev

Custom

Date: Sheet

Description at page15.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

CLK_MCH_DREFCLK#

A27

CLK_MCH_DREFCLK

A26

MCH_SSCDREFCLK#

C40

MCH_SSCDREFCLK

D41

CLKREQB#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

PM_EXTTS#0

DPRSLPVR

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

R71

10K_0402_5%

R79

10K_0402_5%@

1 2

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>

MCH_CLKSEL2 <15>

T6
T9

CFG5 <11>

T7

CFG7 <11>

T12

CFG9 <11>

T10

CFG11 <11>

CFG12 <11>

CFG13 <11>

T8

T16

CFG16 <11>

T14

CFG18 <11>

CFG19 <11>

CFG20 <11>

CLKREQB# <15>

12

Compal Electronics, Inc.

Calistoga (1/6)

LA-2841

1

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

CLK_MCH_DREFCLK# <15>
CLK_MCH_DREFCLK <15>

MCH_SSCDREFCLK# <15>
MCH_SSCDREFCLK <15>

+3VS

of

760Friday, Decemb er 16, 2005

1.0

5

D D

4

3

2

1

DDR_A_BS#0<13>
DDR_A_BS#1<13>
DDR_A_BS#2<13>

DDR_A_DM[0..7]<13>

DDR_A_DQS[0..7]<13>

C C

DDR_A_DQS#[0..7]<13>

DDR_A_MA[0..13]<13>

B B

DDR_A_CAS#<13>
DDR_A_RAS#<13>

DDR_A_WE#<13>

T18 P AD
T19 P AD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U31D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>

DDR_B_BS#0<14>
DDR_B_BS#1<14>
DDR_B_BS#2<14>

DDR_B_DM[0..7]<14>

DDR_B_DQS[0..7]<14>

DDR_B_DQS#[0..7]<14>

DDR_B_MA[0..13]<14>

DDR_B_CAS#<14>

DDR_B_RAS#<14>

DDR_B_WE#<14>

T13 PAD
T15 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U31E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (2/6)

LA-2841

1

1.0

of

860Friday, Decemb er 16, 2005

5

D D

LVDSA0+<16>
LVDSA1+<16>

LVDSA2+<16>
LVDSA0-<16>

LVDSA1-<16>

LVDSA2-<16>

LVDSB0+<16>
LVDSB1+<16>
LVDSB2+<16>

LVDSB0-<16>
LVDSB1-<16>
LVDSB2-<16>

LVDSAC+<16>

LVDSAC-<16>
LVDSBC+<16>
LVDSBC-<16>

C C

B B

GMCH_ENBKL<16>

EDID_CLK_LCD<16>
EDID_DAT_LCD<16>

GMCH_LVDDEN<16>

TV_COMPS<17>
TV_LUMA<17>
TV_CRMA<17>

3VDDCCL<17>

3VDDCDA<17>

CRT_VSYNC<17>
CRT_HSYNC<17>

CRT_B<17>
CRT_G<17>
CRT_R<17>

R482 1.5K_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

4

LVDSA0+
LVDSA1+
LVDSA2+

LVDSA0­LVDSA1­LVDSA2-

LVDSB0+
LVDSB1+
LVDSB2+

LVDSB0­LVDSB1­LVDSB2-

LVDSAC+
LVDSAC­LVDSBC+
LVDSBC-

GMCH_ENBKL

EDID_CLK_LCD
EDID_DAT_LCD

GMCH_LVDDEN

12

R58

12

4.99K_0402_1%

3VDDCCL
3VDDCDA

CRT_VSYNC
CRT_HSYNC
CRT_B

CRT_G
CRT_R

R65

12

255_0402_1%

U31C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

3

+1.5VS_PCIE

R89

PEGCOMP

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D38
F34

G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

EXP_COMPO

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

24.9_0402_1%

1 2

C231 0.1U_0402_16V4ZG71@
C661 0.1U_0402_16V4ZG71@
C230 0.1U_0402_16V4ZG71@
C659 0.1U_0402_16V4ZG71@
C228 0.1U_0402_16V4ZG71@
C657 0.1U_0402_16V4ZG71@
C237 0.1U_0402_16V4ZG71@
C655 0.1U_0402_16V4ZG71@
C238 0.1U_0402_16V4ZG71@
C653 0.1U_0402_16V4ZG71@
C239 0.1U_0402_16V4ZG71@
C651 0.1U_0402_16V4ZG71@
C250 0.1U_0402_16V4ZG71@
C649 0.1U_0402_16V4ZG71@
C677 0.1U_0402_16V4ZG71@
C648 0.1U_0402_16V4ZG71@

C229 0.1U_0402_16V4ZG71@
C662 0.1U_0402_16V4ZG71@
C232 0.1U_0402_16V4ZG71@
C660 0.1U_0402_16V4ZG71@
C233 0.1U_0402_16V4ZG71@
C658 0.1U_0402_16V4ZG71@
C234 0.1U_0402_16V4ZG71@
C656 0.1U_0402_16V4ZG71@
C235 0.1U_0402_16V4ZG71@
C654 0.1U_0402_16V4ZG71@
C236 0.1U_0402_16V4ZG71@
C652 0.1U_0402_16V4ZG71@
C249 0.1U_0402_16V4ZG71@
C650 0.1U_0402_16V4ZG71@
C678 0.1U_0402_16V4ZG71@
C664 0.1U_0402_16V4ZG71@

PEG_RXP[0..15] <18>

PEG_RXN[0..15] <18>

PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15

PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15

2

PEG_M_TXP[0..15] <18>

PEG_M_TXN[0..15] <18>

1

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (3/6)

LA-2841

1

1.0

of

960Friday, Decemb er 16, 2005

5

+VCCP

21

D D

C C

B B

A A

D5

CH751H-40_SC76@

CH751H-40_SC76@

12

+2.5VS

R80

10_0402_5%@

+1.5VS

21

D19

12

+3VS

R520

10_0402_5%@

1

C613

C612

2

4.7U_0805_10V4Z

1

C81

2

1

0.22U_0603_10V7K

2

1

+

C610

220U_D2_4VM

2

1

2

2.2U_0805_16V4Z

MCH_A6

1

C607

2

MCH_D2

C597

0.22U_0603_10V7K

C596

+1.5VS

+VCCP

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U31H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

4

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCDQ_TVDAC

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

1 2

C162

0.1U_0402_16V4Z

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC

1

2

C124

0.1U_0402_16V4Z

+1.5VS

1

C163

2

+1.5VS_PCIE

1

+

C682

2

1

2

C615

10U_1206_6.3V6M

0.1U_0402_16V4Z

220U_D2_4VM

1

2

+3VS

1

C666

2

C115

3

0_0805_5%

1

C665

2

10U_1206_6.3V6M

10U_1206_6.3V6M

L7 BLM11A601S_0603

1 2

1

C116

2

2200P_0402_50V7K

0.1U_0402_16V4Z

1

2

R490

12

+1.5VS

+2.5VS

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

+2.5VS

1

1

C215

C160

2

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

close pin A38

R39

12

0_0805_5%

C117

0.1U_0402_16V4Z

C112

2200P_0402_50V7K

1

2

+2.5VS

1

C225

2

0.1U_0402_16V4Z

close pin G41

1

2

+3VS+3VS_TVBG

2

C110

2200P_0402_50V7K

1

2

0_0805_5%

C111

0.1U_0402_16V4Z

+1.5VS_DPLLA +1.5VS_DPLLB

0.1U_0402_16V4Z

C138

1

2

R52

12

MBK160808_0603

330U_V_2.5VK_R9

UMA@

1

C616

+

2

1

C114

2

L28

1

2

2200P_0402_50V7K

12

R55

0_0805_5%

C109

0.1U_0402_16V4Z

PCI-E/MEM/PSB PLL decoupling

+1.5VS+1.5VS_3GPLL

R99
0_0603_5%

12

1

1

C248

C174

2

2

0.1U_0402_16V4Z

10U_1206_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

C604

1

2

0.1U_0402_16V4Z

R459
0_0603_5%

1

C593

2

10U_1206_6.3V6M

12

1

C280

2

0.1U_0402_16V4Z

@

1

L29

MBK160808_0603

0.1U_0402_16V4Z

330U_V_2.5VK_R9

UMA@

1

C226

C645

1

+

2

2

12

+1.5VS_TVDAC +1.5VS

C113

1

C614

2

0.1U_0402_16V4Z

+1.5VS_HPLL

1

2

1

2

2200P_0402_50V7K

1

C605

2

0.1U_0402_16V4Z

1

C107

2

2200P_0402_50V7K

R46
0_0603_5%

1

C594

2

C106

0.1U_0402_16V4Z

12

C105

R460
0_0603_5%

10U_1206_6.3V6M

0_0805_5%

@

12

R44

1

2

0.1U_0402_16V4Z

12

+1.5VS+1.5VS

+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS _TVDACC

12

+1.5VS+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Docum ent Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (4/6)

LA-2841

1

1.0

of

10 60Friday, December 16, 2005

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C86

2

0.22U_0603_10V7K

1

C173

2

10U_1206_6.3V6M

C C

B B

C164

C600

C595

C606

1

1

C85

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C139

2

2

1U_0603_10V4Z

10U_1206_6.3V6M

1

+

220U_D2_4VM@

2

1

+

220U_D2_4VM@

2

+VCCP

U31F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

C603

+1.8V

0.47U_0603_10V7K

1

1

C602

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U31G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

MCH_AT41
MCH_AM41

C669

1

1

C668

2

2

0.47U_0603_10V7K

0.47U_0603_10V7K

Place near pin AT41 & AM41

1

1

C83

C222

2

C125

2

0.1U_0402_16V4Z

1

2

0.47U_0603_10V7K

Place near pin BA23

1

1

C641

C609

C104

2

2

10U_1206_6.3V6M

10U_1206_6.3V6M

1

2

0.47U_0603_10V7K

Place near pin BA15

CFG[2:0]

CFG5

CFG7

CFG9

CFG6

PSB 4X CLK Enable 1 = Calistoga

CFG[13:12]

CFG16

0.1U_0402_16V4Z

CFG10 CFG18

CFG19

SDVO_CTRLDATA

1

1

C84

C128

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

CFG20

(PCIE/SDVO select)

1

+

C599

2

330U_V_2.5VK_R9

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

(Default)

*

(Default)

0 = Reserved

*

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

10 = 1.05V
01 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R48 2.2K_0402_5%@

CFG5<7>

R54 2.2K_0402_5%@

CFG7<7>

R51 2.2K_0402_5%@

CFG9<7>
CFG11<7>
CFG12<7>
CFG13<7>
CFG16<7>

CFG18<7>
CFG19<7>
CFG20<7>

R47 2.2K_0402_5%@
R49 2.2K_0402_5%@
R50 2.2K_0402_5%@
R53 2.2K_0402_5%@

R74 1K_0402_5%@
R82 1K_0402_5%@
R87 1K_0402_5%@

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

*

*

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (5/6)

LA-2841

1

1.0

of

11 60F r ida y, D ec em be r 1 6, 2005

5

4

3

2

1

U31I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U31J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Calistoga (6/6)

LA-2841

1

1.0

of

12 60F r ida y, D ec em be r 1 6, 2005

5

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..13]<8>

D D

Layout Note:
Place near JP41

+1.8V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

C642

5

C129

1

2

0.1U_0402_16V4Z

1

2

RP25

1 4
2 3

RP24

56_0404_4P2R_5%

1 4
2 3

RP6

56_0404_4P2R_5%

1 4
2 3

RP23

56_0404_4P2R_5%

1 4
2 3

RP22

56_0404_4P2R_5%

1 4
2 3

RP21

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

2.2U_0805_16V4Z

C640

C131

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C639

+0.9VS

C206

C204

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C175

C192

RP27 56_0404_4P2R_5%

14
23

RP15 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP9 56_0404_4P2R_5%

14
23

RP3 56_0404_4P2R_5%

14
23

RP18 56_0404_4P2R_5%

14
23

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C130

1

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C643

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C180

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C166

C630

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

1

2

0.1U_0402_16V4Z

C143

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

C629

4

0.1U_0402_16V4Z
C187

C193

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C145

C158

Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"

4

1

2

C136

3

+1.8V

JP21

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA<7>

DDR_A_BS#2<8>

DDR_A_BS#0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

0.1U_0402_16V4Z

1

2

C628

DDR_CS1_DIMMA#<7>

M_ODT1<7>

CLK_SMBDATA<14,15>

CLK_SMBCLK<14,15>

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C80

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM A

REVERSE

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A7
A6

A4
A2
A0

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R35

R33

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C368

1

2

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

PM_EXTTS#0 <7,14>

DDR_CKE1_DIMMA <7>

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

1

0.1U_0402_16V4Z

1

2

V_DDR_MCH_REF <7,14>

C369

Top side

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-2841

1

1.0

of

13 60Thursday, December 15, 2005

5

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..13]<8>

D D

C C

B B

A A

Layout Note:
Place near JP42

+1.8V

1

2

C202

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

+0.9VS

2.2U_0805_16V4Z

C159

0.1U_0402_16V4Z

C179

RP16 56_0404_4P2R_5%

RP17 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

RP14 56_0404_4P2R_5%

RP11 56_0404_4P2R_5%

RP2 56_0404_4P2R_5%

RP19

56_0404_4P2R_5%

2.2U_0805_16V4Z
C132

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C156

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_BS#1
DDR_B_MA0

DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C146

RP10

RP7

RP8

RP5

RP4

RP1

C214

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

5

2.2U_0805_16V4Z
C205

1

2

0.1U_0402_16V4Z

1

2

C137

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C157

1

2

1

2

C170

14
23

14
23

14
23

14
23

14
23

14
23

14
23

0.1U_0402_16V4Z
C169

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C165

DDR_B_MA9
DDR_B_MA12

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C142

1

2

0.1U_0402_16V4Z

1

2

C144

C147

0.1U_0402_16V4Z

C141

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C191

C133

Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"

4

C140

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C168

C176

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

JP24

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<7>

DDR_B_BS#2<8>

DDR_B_BS#0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<7>

M_ODT3<7>

CLK_SMBDATA<13,15>

CLK_SMBCLK<13,15>

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C79

0.1U_0402_16V4Z

2005/03/10 2006/03/10

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

2

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

10K_0402_5%

12

R34

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C366

2

2

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

PM_EXTTS#0 <7,13>

DDR_CKE3_DIMMB <7>

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2 <7>

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

R32

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-2841

1

V_DDR_MCH_REF <7,13>

C367

1

1.0

of

14 60Thursday, December 15, 2005

5

PCI

SRC

CPU

CLKSEL1

0

1

FSLA

CLKSEL0

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

1000

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.31

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

ICH_SMBDATA<29,34,37>

ICH_SMBCLK<29,34,37>

FSLC1FSLB

CLKSEL2

0

Table : ICS954306

D D

FSB Frequency Selet:

CPU Driven

(Default)

*

533MHz

667MHz

CLK_Re

+VCCP

R232

@

R237

8.2K_0402_5%

C C

B B

A A

FSA

CLKREF1

1 2

R231

0_0402_5%

CLK_Ra

FSB

1 2

R191

0_0402_5%

CLK_Rb

R205

8.2K_0402_5%

1 2

R177

0_0402_5%

CLK_Rc

10K_0402_5%

CLK_ENABLE#

CPU_BSEL0<5>

CPU_BSEL1<5>

CPU_BSEL2<5>

56_0402_5%

CLK_Rd

1 2

12

1 2

R227

1K_0402_5%

12

R228
1K_0402_5%@

+VCCP

R201
1K_0402_5%@

1 2

1 2

R200

1K_0402_5%

12

R199

@

0_0402_5%

CLK_Re

+VCCP

R202
1K_0402_5%@

1 2

12

1 2

R184

R235

1K_0402_5%

12

R183

@

0_0402_5%

CLK_Rf

+3VS

12

5

MCH_CLKSEL0 <7> CLK_48M_CB<32>

MCH_CLKSEL1 <7>

+3VS

12

R589
100K_0402_5%

PCI_PCM

CLK_MCH_DREFCLK<7>

CLK_MCH_DREFCLK#<7>

MCH_CLKSEL2 <7>

LCD clock select

+3VS +3VS

12

R233

10K_0402_5%@

PCI_ICH PCI_MINI

12

R238
10K_0402_5%

High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz Low:Pin44/45 = CPUCLK2_ITP

4

2.2K_0402_5%
Q12
2N7002_SOT23

D

1 3

+3VS

CLK_48M_ICH<29>

CLK_14M_ICH<29>

H_STP_CPU#<29>

H_STP_PCI#<29>

CLK_ENABLE#<53>

CLK_PCI_ICH<27>

CLK_PCI_MINI<36>

CLK_PCI_EC<44>

CLK_PCI_SIO<42>

CLK_PCI_PCM<32>

CLK_SMBDATA<13,14>

CLK_SMBCLK<13,14>

2

2

1 3

D

2N7002_SOT23

Q15

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

Pin44/45 function select

High:Pin44/45 = CLKREQ

**

4

+3VS

R299

S

G

G

S

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CLK_48M_ICH
CLK_48M_CB

CLK_14M_ICH

H_STP_CPU#
H_STP_PCI#
CLK_ENABLE#

CLK_PCI_ICH PCI_ICH

CLK_SMBDATA
CLK_SMBCLK

1 2

R246 10_0402_5%UMA@

1 2

R253 10_0402_5%UMA@

C424

C425

R236 12_0402_5%

R243 12_0402_5%

R230 33_0402_5%

1 2

12

R312
10K_0402_5%

12

R308

10K_0402_5%@

R323

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

+CK_VDD_48

1

2

1

2

+CK_VDD_REF

R2662.4K_0402_1%

R229

33_0402_5%

R20633_0402_5%

12

R21610K_0402_5%

12

R21533_0402_5%

12

R22533_0402_5%@

12

R22433_0402_5%

12

MCH_DREFCLK
MCH_DREFCLK#

+CK_VDD_MAIN1

12
12

12

12

3

+CK_VDD_MAIN1

1 2

+3VS

FSA
FSB
CLKREF1

CLKIREF

PCI_MINI

PCI_EC
PCI_SIO
PCI_PCM

+3VS

16
10

24
33
41
50
55

11
15
59

46
61

60
62

54
53

13
14

12
17
58
47
25
40
32

R324 0_0805_5%

R174 0_0805_5%

5

8
9
7

1
2
3
6

4

1 2

U13

VDD
VDD48
VDDPCI
VDDSRC
VDDSATA
VDDSRC
VDDCPU
VDDREF

FSLA/USB_48MHz
FSLB/TEST_MODE
FSLC/TEST_SEL/REF1

IREF
CPU_STOP#
PCI/SRC_STOP#
Vtt_PwrGd#/PD
**SEL_LCDCLK#/PCICLK_F1

REF0/PCICLK1
*REQ_SEL/PCICLK2
*SEL_PCI1/PCICLK3
**SEL_SATA1/PCICLK4
**SEL_SATA2/PCICLK5
PCICLK6

SDATA
SCLK

DOTT_96MHz
DOTC_96MHz

GND
GND
GND
GND
GNDCPU
GNDSRC
GNDSRC
GNDSATA

ICS954306_TSSOP64

1

C456
10U_0805_10V4Z

2

+CK_VDD_MAIN2

1

C416
10U_0805_10V4Z

2

LCDCLK_SST/SRCCLKT0
LCDCLK_SSC/SRCCLKC0

*CPUCLKT2_ITP/CLKREQC#

*CPUCLKC2_ITP/CLKREQD#

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C422

0.1U_0402_16V4Z

2

1

C418

0.1U_0402_16V4Z

2

X1
X2

SATACLKT

SATACLKC

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

*CLKREQA#

SRCCLKT2

SRCCLKC2

SATA1/SRCCLKT4
SATA1/SRCCLKC4

*CLKREQB#

SRCCLKT1

SRCCLKC1

SRCCLKT3

SRCCLKC3

SATA2/SRCCLKT5
SATA2/SRCCLKC5

SRCCLKT6

SRCCLKC6

SRCCLKT8

SRCCLKC8

SRCCLKT7

SRCCLKC7

2005/03/10 2006/03/10

1

C431

0.1U_0402_16V4Z

2

1

C417

0.1U_0402_16V4Z

2

C419 22P_0402_50V8J

12

Y2

CLK_XTAL_IN

57

CLK_XTAL_OUT

56

28

1 2

R305 0_0402_5%9LP@

29

1 2

R311 0_0402_5%9LP@

CPU_BCLK

52

CPU_BCLK#

51

MCH_BCLK

49

MCH_BCLK#

48

64

SSCDREFCLK

18

SSCDREFCLK#

19

PCIE_MCARD

22

PCIE_MCARD#

23

PCIE_SATA

30

PCIE_SATA#

31

63

PCIE_VGA CLK_PCIE_VGA

20
21

MCH_3GPLL

26

MCH_3GPLL#

27

35
34

CPU_XDP

45
37

PCIE_NC1#

36

43
42

CPU_XDP# CLK_CPU_XDP#

44
39
38

14.31818MHZ_20P_1BX14318BE1A

C421 22P_0402_50V8J

1 2

R239 10_0402_5%

1 2

R247 10_0402_5%

1 2

R254 10_0402_5%

1 2

R258 10_0402_5%

R218 10K_0402_5%@

1 2

R257 10_0402_5%UMA@

1 2

R270 10_0402_5%UMA@

1 2

R282 10_0402_5%

1 2

R284 10_0402_5%

1 2

R297 10_0402_5%

1 2

R304 10_0402_5%
R226 10K_0402_5%@

1 2

R268 10_0402_5%G71@

1 2

R276 10_0402_5%G71@

1 2

R288 10_0402_5%

1 2

R292 10_0402_5%

1 2

R294 10_0402_5%

1 2

R301 10_0402_5%

R273 10K_0402_5%

1 2

R278 10_0402_5%@

1 2

R285 10_0402_5%17@

1 2

R289 10_0402_5%17@

R277 10K_0402_5%

1 2

R271 10_0402_5%@

1 2

R309 10_0402_5%15.4@

1 2

R310 10_0402_5%15.4@

Compal Secret Data

Deciphered Date

2

1

C440

0.1U_0402_16V4Z

2

1 2

R188

1_0805_1%

1 2

R187

2.2_0805_1%

12

12

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

12

CLKREQA#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD#

CLK_PCIE_SATA

CLK_PCIE_SATA#

12

CLKREQB#

CLK_PCIE_VGA#PCIE_VGA#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICHPCIE_ICH

CLK_PCIE_ICH#PCIE_ICH#

CLKREQC#

12

CLK_CPU_XDP

CLK_PCIE_NC1PCIE_NC1

CLK_PCIE_NC1#

CLKREQD#

12

CLK_PCIE_NC2PCIE_NC2

CLK_PCIE_NC2#PCIE_NC2#

2

1

C450

0.1U_0402_16V4Z

2

+CK_VDD_REF

+CK_VDD_48

1

1

C441

0.1U_0402_16V4Z

2

Place crystal within
500 mils of CK410

1

C430

0.1U_0402_16V4Z

2

Place near U54

Place these components
near each pin within 40
mils.

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

+3VS

CLKREQA# <37>
MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>

CLK_PCIE_MCARD <37>
CLK_PCIE_MCARD# <37>

CLK_PCIE_SATA <28>
CLK_PCIE_SATA# <28>

+3VS

CLKREQB# <7>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <29>
CLK_PCIE_ICH# <29>

CLKREQC# <34>

CLK_PCIE_NC1 <34>
CLK_PCIE_NC1# <34>

CLKREQD# <34>

CLK_PCIE_NC2 <34>
CLK_PCIE_NC2# <34>

Title

Size Document Number Rev

Date: Sheet

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

CLK_PCIE_MCARD

CLK_PCIE_MCARD#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_ICH

CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_CPU_XDP

CLK_CPU_XDP#

CLK_PCIE_NC1

CLK_PCIE_NC1#

CLK_PCIE_NC2

CLK_PCIE_NC2#

CLKREQA#
CLKREQB#
CLKREQC#
CLKREQD#

R240 49.9_0402_1%@
R248 49.9_0402_1%@

R255 49.9_0402_1%@
R259 49.9_0402_1%@

R256 49.9_0402_1%@
R269 49.9_0402_1%@

R281 49.9_0402_1%@
R283 49.9_0402_1%@
R287 49.9_0402_1%@

R291 49.9_0402_1%@
R267 49.9_0402_1%@
R275 49.9_0402_1%@

R295 49.9_0402_1%@

R302 49.9_0402_1%@
R245 49.9_0402_1%@
R252 49.9_0402_1%@

R296 49.9_0402_1%@

R303 49.9_0402_1%@

R279 49.9_0402_1% @

R272 49.9_0402_1%@
R286 49.9_0402_1%@
R290 49.9_0402_1%@

R318 49.9_0402_1%@

R319 49.9_0402_1%@

C802 1000P_0402_50V7K

1 2

C803 1000P_0402_50V7K

1 2

C804 1000P_0402_50V7K

1 2

C805 1000P_0402_50V7K

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

Compal Electronics, Inc.

Clock generator

LA-2841

1

12
12

12
12

12
12
12
12

1.0

of

15 60Thursday, December 15, 2005

A

B

C

D

E

F

G

H

LCD Panel & inverter Connector

1 1

2 2

+3VS

R434

1 2

10K_0402_5%

R435

1 2

10K_0402_5%

EDID_CLK_LCD

EDID_DAT_LCD

WL_LED#<37,42>

INVT_PWM<44>
DAC_BRIG<44>

EDID_CLK_LCD<9>
EDID_DAT_LCD<9>

LCD_I2C_CLK_C< 18>
LCD_I2C_DAT_C<18>

+LCDVDD

+5VS
+3VS

+LCDVDD

+5VS
+3VS

WL_LED#

EDID_CLK_LCD
EDID_DAT_LCD

INVPWR_B+

WL_LED#
DISPOFF#
INVT_PWM
DAC_BRIG

LCD_I2C_CLK_C
LCD_I2C_DAT_C

INVPWR_B+

DISPOFF#
INVT_PWM
DAC_BRIG

JP2

UMA

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

8

5

6

3

4

1

2

ACES_88107-4000G

JP1

Discrete

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

8

5

6

3

4

1

2

ACES_88107-4000G

LVDSAC+
LVDSAC-

LVDSA1­LVDSA1+

LVDSBC+
LVDSBC-

LVDSB1­LVDSB1+
LVDSB0+
LVDSB0­LVDSB2+
LVDSB2-

LVDSA0­LVDSA0+
LVDSA2­LVDSA2+

LVDS_AC­LVDS_AC+

LVDS_A2+
LVDS_A2­LVDS_A1+
LVDS_A1­LVDS_A0+
LVDS_A0-

LVDS_B1­LVDS_B1+
LVDS_B2+
LVDS_B2­LVDS_B0+
LVDS_B0-

LVDS_BC+
LVDS_BC-

LVDSAC+ <9>

LVDSAC- <9>

LVDSA1- <9>

LVDSA1+ <9>

LVDSBC+ <9>

LVDSBC- <9>

LVDSB1- <9>
LVDSB1+ <9>
LVDSB0+ <9>

LVDSB0- <9>
LVDSB2+ <9>

LVDSB2- <9>

LVDSA0- <9>
LVDSA0+ <9>
LVDSA2- <9>

LVDSA2+ <9>

LVDS_AC- <18>

LVDS_AC+ <18>
LVDS_A2+ <18>

LVDS_A2- <18>
LVDS_A1+ <18>

LVDS_A1- <18>
LVDS_A0+ <18>

LVDS_A0- <18>

LVDS_B1- <18>
LVDS_B1+ <18>

LVDS_B2+ <18>

LVDS_B2- <18>
LVDS_B0+ <18>

LVDS_B0- <18>
LVDS_BC+ <18>

LVDS_BC- <18>

+3VS

R430

D17

BKOFF#<44>

GMCH_ENBKL<9>

CH751H-40_SC76

D16
CH751H-40_SC76UMA@

R431

100K_0402_5%UMA@

1 2

L25 FBMA-L10-201209-301LMT

1 2

L24 FBMA-L10-201209-301LMT@

1 2

0.1U_0402_16V4Z

4.7K_0402_5%

1 2

21

21

DISPOFF#

INVPWR_B+B+

1

1

C806

C807

2

2

68P_0402_50V8K

3 3

+LCDVDD +5VALW

12

R429

100_0402_1%

2N7002_SOT23

ENVDD

R433

0_0402_5%UMA@

GMCH_LVDDEN<9>

ENVDD<18>

4 4

13

D

Q32

S

12

R428
100K_0402_5%

1 2

2

G

13

2

0.047U_0402_16V4Z

Q31
DTC124EK_SC59

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

1

C572

2

0.1U_0402_16V4Z

+LCDVDD

1

2

C574

Q33
SI2301BDS_SOT23

1 3

D

1

C575

4.7U_0805_10V4Z

2

2005/03/10 2006/03/10

E

+3VS

S

G

2

1

C573

4.7U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

F

Date: Sheet

Compal Electronics, Inc.

LVDS Connector

LA-2841

G

1.0

of

16 60Thursday, December 15, 2005

H

A

R15

M_RED<18>

M_GRN<18>

1 1

R449

CRT_HSYNC<9>

M_HSYNC<18>

2 2

CRT_VSYNC<9>

M_VSYNC<18>

1 2

R450

1 2

R447

1 2

R448

1 2

C580

1 2

0.1U_0402_16V4Z

CRTHSYNC

0_0402_5%UMA@

0_0402_5%G71@

CRTVSYNC

0_0402_5%UMA@

0_0402_5%G71@

M_BLU<18>

CRT_R<9>

CRT_G<9>

CRT_B<9>

+5VS

5

A2Y

3

5

A2Y

3

1 2

0_0402_5%G71@

R11

1 2

0_0402_5%G71@

R8

1 2

0_0402_5%G71@

R13

1 2

0_0402_5%UMA@

R12

1 2

0_0402_5%UMA@

R9

1 2

0_0402_5%UMA@

EMI

1

U29

P

4

OE#

G

1

U28

P

4

OE#

G

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

R14

1 2

75_0402_5%

B

1

2

C29

10P_0402_50V8K

@

CRT_HSYNC_R

CRT_VSYNC_R

R10

1 2

75_0402_5%

C

RB411D_SOT23

CRT CONNECTOR

EMI

L3

CRTR CRTL_R

CRTG

CRTB

1

R7

2

75_0402_5%

C20

10P_0402_50V8K

@

MBK2012800YZF

1 2

L2
MBK2012800YZF

1 2

L1
MBK2012800YZF

1 2

1

2

C9

1 2

10P_0402_50V8K

@

EMI

1

1

2

2

C25

C17

33P_0402_25V8K

33P_0402_25V8K

1 2

L27
FBM-L11-160808-800LMT_0603

1 2

L26
FBM-L11-160808-800LMT_0603

+R_CRT_VCC , +CRTVDD (40mils)

1

2

R16 4.7K_0402_5%

1

2

+CRTVDD

C579 10P_0402_50V8K

+CRTVDD

R443 4.7K_0402_5%

1

2

C46 220P_0402_25V8K

+5VS

+R_CRT_VCC

D1

2 1

1

2

C7

33P_0402_25V8K

CRT_HSYNCRFL

CRT_VSYNCRFL

F1

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

M_SEN#

CRTL_G

CRTL_B

C581

21

C582

1

2

10P_0402_50V8K

D

JP3
ALLTO_C10510-115A5-L_15P-s

6

11

1
7

12

16

2

17

8

13

3
9

14

4
10
15

5

Q1
2N7002_SOT23

D

S

1 3

Q34

2N7002_SOT23

G

2

D

1

2

1 3

C577 220P_0402_25V8K

S

R19

G

2

2.2K_0402_5%

3V_DDCDA

3V_DDCCL

R444

2.2K_0402_5%

+3VS

R20

1 2

R446

1 2

R21

1 2

R445

1 2

E

NZQA5V6AXV5T1_SOT533-5

2

1 5

D46

CLOSE TO JP3

0_0402_5%G71@

0_0402_5%G71@

0_0402_5%UMA@

0_0402_5%UMA@

M_DDCDATA <18>

M_DDCCLK <18>

3VDDCDA <9>

3VDDCCL <9>

43

R25

M_LUMA<18>

M_CRMA<18>

M_COMP<18>

TV_LUMA<9>

3 3

4 4

A

TV_CRMA<9>

TV_COMPS<9>

1 2

R30

1 2

R27

1 2

R24

1 2

R31

1 2

R26

1 2

0_0402_5%G71@

0_0402_5%G71@

0_0402_5%G71@

0_0402_5%UMA@

0_0402_5%UMA@

0_0402_5%UMA@

TVCRMA

TVCOMPS

R28

TVLUMA

12

R29

75_0402_5%

B

TVLUMA
TVCRMA
TVCOMPS

12

R23

75_0402_5%

12

75_0402_5%

C75

270P_0402_50V7K

TVLUMA <46>
TVCRMA <46>
TVCOMPS <46>

1

C77

2

270P_0402_50V7K

TV-Out Connector
S-Video

EMI

L4
MBC1608121YZF_0603

1 2

L6
MBC1608121YZF_0603

1 2

L5
MBC1608121YZF_0603

1 2

1

1

C49

2

2

270P_0402_50V7K

R22

1 2

0_0805_5%

TVGND

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LUMA_CL

CRMA_CL

COMPS_CL

1

C74

2

330P_0402_50V7K

2005/03/10 2006/03/10

1

1

2

C50

C76

2

330P_0402_50V7K

Compal Secret Data

Deciphered Date

330P_0402_50V7K

JP17

1

1

2

2

3

3

4

4

5

5

6

6

GND

7

7

GND

SUYIN_030107FR007G317ZR

D

8
9

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

CRT & TVout Connector

LA-2841

E

1.0

of

17 60Thursday, December 15, 2005

5

PEG_M_TXP0
PEG_M_TXN0
PEG_M_TXP1
PEG_M_TXN1
PEG_M_TXP2
PEG_M_TXN2
PEG_M_TXP3

PEG_M_TXN3
PEG_M_TXP4
PEG_M_TXN4
PEG_M_TXP5
PEG_M_TXN5

OUT

GND

PEG_M_TXP6
PEG_M_TXN6
PEG_M_TXP7
PEG_M_TXN7
PEG_M_TXP8
PEG_M_TXN8
PEG_M_TXP9
PEG_M_TXN9

PEG_M_TXP10

PEG_M_TXN10

PEG_M_TXP11

PEG_M_TXN11

PEG_M_TXP12

PEG_M_TXN12

PEG_M_TXP13

PEG_M_TXN13

PEG_M_TXP14

PEG_M_TXN14

PEG_M_TXP15

PEG_M_TXN15

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLK_PCIE_VGA<15>
CLK_PCIE_VGA#<15>

VGA_RST#<27>

R512 10K_0402_5%128@

1 2

R113 10K_0402_5%128@

1 2

R81 10K_0402_5%

1 2

R57 10K_0402_5%@

1 2

R56 10K_0402_5%@

1 2

R77 10K_0402_5%

1 2

C152

1 2

C161

1 2

3
2

1

C646

128@

22P_0402_50V8J

2

PEG_DTXP0

C1220.1U_0402_16V4Z128@

PEG_DTXN0

C1230.1U_0402_16V4Z128@

PEG_DTXP1

C6260.1U_0402_16V4Z128@

PEG_DTXN1

C6250.1U_0402_16V4Z128@

PEG_DTXP2

C880.1U_0402_16V4Z128@

PEG_DTXN2

C890.1U_0402_16V4Z128@

PEG_DTXP3

C900.1U_0402_16V4Z128@

PEG_DTXN3

C910.1U_0402_16V4Z128@

PEG_DTXP4

C920.1U_0402_16V4Z128@

PEG_DTXN4

C930.1U_0402_16V4Z128@

PEG_DTXP5

C6240.1U_0402_16V4Z128@

PEG_DTXN5

C6230.1U_0402_16V4Z128@

PEG_DTXP6

C940.1U_0402_16V4Z128@

PEG_DTXN6

C950.1U_0402_16V4Z128@

PEG_DTXP7

C960.1U_0402_16V4Z128@

PEG_DTXN7

C970.1U_0402_16V4Z128@

PEG_DTXP8

C6220.1U_0402_16V4Z128@

PEG_DTXN8

C6210.1U_0402_16V4Z128@

PEG_DTXP9

C980.1U_0402_16V4Z128@

PEG_DTXN9

C990.1U_0402_16V4Z128@

PEG_DTXP10

C1000.1U_0402_16V4Z128@

PEG_DTXN10

C1010.1U_0402_16V4Z128@

PEG_DTXP11

C6200.1U_0402_16V4Z128@

PEG_DTXN11

C6190.1U_0402_16V4Z128@

PEG_DTXP12

C1020.1U_0402_16V4Z128@

PEG_DTXN12

C1030.1U_0402_16V4Z128@

PEG_DTXP13

C1260.1U_0402_16V4Z128@

PEG_DTXN13

C1270.1U_0402_16V4Z128@

PEG_DTXP14

C6180.1U_0402_16V4Z128@

PEG_DTXN14

C6170.1U_0402_16V4Z128@

PEG_DTXP15

C1340.1U_0402_16V4Z128@

PEG_DTXN15

C1350.1U_0402_16V4Z128@

CLK_PCIE_VGA
CLK_PCIE_VGA#

VGA_RST#

0.1U_0402_16V4Z128@

0.1U_0402_16V4Z@

XTALIN

XTALOUT

1 2

R492
10K_0402_5%@

D D

PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5

C C

PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

B B

1

2

A A

Y5

4

GND

1

IN

27MHz_16PF_6P27000126128@

C680

128@

22P_0402_50V8J

+3VS

AK13

AK14
AM14
AM15

AL15

AL16
AK16
AK17

AL17

AL18

AM18
AM19

AK19
AK20

AL20

AL21

AM21
AM22

AK22
AK23

AL23

AL24

AM24
AM25

AK25
AK26

AL26

AL27

AM27
AM28

AL28

AL29

AJ15
AK15
AH16
AG16
AG17
AH17
AG18
AH18
AK18

AJ18

AJ19
AH19
AG20
AH20
AG21
AH21
AK21

AJ21

AJ22
AH22
AG23
AH23
AK24

AJ24

AJ25
AH25
AH26
AG26
AK27

AJ27

AJ28
AH27

AH14

AJ14
AH15

AM12
AM11

A26

H2

AJ11
AK12

AL12
AK11

AL13

AM4

AK3

U1
U2

T2

T1

1 2

R496

128@

22_0402_5%

U33A

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_RST_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

TESTMEMCLK
TESTMODE

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_N

IFPAB_VPROBE
IFPCD_VPROBE

XTALIN
XTALOUT

XTALOUTBUFF

XTALSSIN

NV72/73M_BGA820G71@

1 2

Part 1 of 6

OSC_SPREAD <26>
OSC_OUT <26>

R489
10K_0402_5% @

If Spread spectrum not stuff than stuff resistor

DVO / GPIO

MIOA_CLKOUT

MIOA_CLKOUT_N

PCI EXPRESS

MIOB_CLKOUT

MIOB_CLKOUT_N

DACsI2C

TEST

CLK

4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8

MIOAD9
MIOAD10
MIOAD11

MIOA_HSYNC
MIOA_VSYNC

MIOA_DE

MIOA_CTL3

MIOA_CLKIN

MIOA_VREF

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC
MIOB_VSYNC

MIOB_DE

MIOB_CTL3

MIOB_CLKIN

MIOB_VREF

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_IDUMP

DACA_RSET
DACA_VREF

DACC_HSYNC

DACC_VSYNC

DACC_RED

DACC_BLUE

DACC_GREEN

DACC_IDUMP

DACC_RSET
DACC_VREF

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_IDUMP

DACB_RSET
DACB_VREF

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA

K3
H1
K5
G5
E2
J5
G6
K6
E1
D2
H5
F4
E3

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4
L5

R3
R1
P1
P3

M5
R4
P4

L2
AC3

AC1
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
AB4
AA5

AF3
AE3
AD1
AD3

AE4
AD4
AD5

Y2
AF10

AK10
AH11
AH12
AJ12
AG9
AH9

AH10
AG7

AG5
AF6
AE5
AG6
AG4
AF5

AH4
R6

T6
T5
V7
R7

R5
K2

J3
H4
J4
G2
G1
G3
H3

GPIO11

PEX_PLL_TERM
SUB_VENDOR

PEX_CFG0
PEX_CFG1

PEX_CFG2

R115

10K_0402_5%128@

R90 10K_0402_5%128@

M_HSYNC
M_VSYNC
M_RED
M_BLU
M_GRN

R85

DACAVREF

M_CRMA
M_COMP
M_LUMA

DACB_RSET

DACBVREF

M_DDCCLK
M_DDCDATA
DVI_SCLK
DVI_SDATA

I2CH_SCL
I2CH_SDA

ENVDD
NV_ENBKL

THER_ALERT#

12

RAM_CFG0
RAM_CFG1
CRYSTAL_0
PCI_DEVID2
PCI_DEVID0
PCI_DEVID1
CRYSTAL_1
MOBILE_MODE
RAM_CFG2
RAM_CFG3

PCI_DEVID3

12

1 2

124_0402_5%

1 2

C171 0.01U_0402_16V7K128@

C270

LCD_I2C_CLK_C
LCD_I2C_DAT_C

GPIO11

1 2

R101 2K_0402_5%@

1 2

R100 2K_0402_5%@

128@

1 2

0.01U_0402_16V7K128@

2

3

ENVDD <16>
NV_ENBKL <44>

For VDD_CORE voltage select

PEX_PLL_TERM <26>
SUB_VENDOR <26>

PEX_CFG0 <26>
PEX_CFG1 <26>

PEX_CFG2 <26>

MIOA_VDDQ

RAM_CFG0 <26>
RAM_CFG1 <26>
CRYSTAL_0 <26>
PCI_DEVID2 <26>
PCI_DEVID0 <26>
PCI_DEVID1 <26>
CRYSTAL_1 <26>
MOBILE_MODE <26>
RAM_CFG2 <26>
RAM_CFG3 <26>

PCI_DEVID3 <26>

M_HSYNC <17>
M_VSYNC <17>
M_RED <17>
M_BLU <17>
M_GRN <17>

M_CRMA <17>
M_COMP <17>
M_LUMA <17>

M_DDCCLK <17>
M_DDCDATA <17>

LCD_I2C_CLK_C <16>
LCD_I2C_DAT_C <16>

316_0402_1%@

1 2

316_0402_1%@

13

D

Q6

G

S

1 2

2N7002_SOT23@

PEG_RXP[0:15]
PEG_RXN[0:15]
PEG_M_TXP[0..15]
PEG_M_TXN[0..15]

LVDS_AC+<16>
LVDS_AC-<16>
LVDS_A0+<16>
LVDS_A0-<16>
LVDS_A1+<16>
LVDS_A1-<16>
LVDS_A2+<16>
LVDS_A2-<16>

LVDS_BC+<16>
LVDS_BC-<16>
LVDS_B0+<16>
LVDS_B0-<16>
LVDS_B1+<16>
LVDS_B1-<16>
LVDS_B2+<16>
LVDS_B2-<16>

128@

2.2K_0402_5%

D+

1

D-

2

C683

128@

2200P_0402_25V7K

Close to Sensor

R139

R140

R503

124_0402_5%128@

1 2

1 2

+3VS

12

R467

R88 1K_0402_5%@

12

R504
200_0402_5%

128@

R145

1K_0402_5%@

U34

1

VDD

2

D+

3

D-

4

OVERT#

MAX6649MUA_8UMAX128@

12

PEG_RXP[0:15] <9>
PEG_RXN[0:15] <9>
PEG_M_TXP[0..15] <9>
PEG_M_TXN[0..15] <9>

U33D

AK9

IFPA_TXC

AJ9

IFPA_TXC_N

AH6

IFPA_TXD0

AJ6

IFPA_TXD0_N

AH8

IFPA_TXD1

AH7

IFPA_TXD1_N

AJ8

IFPA_TXD2

AK8

IFPA_TXD2_N

AJ5

IFPA_TXD3

AH5

IFPA_TXD3_N

AK4

IFPB_TXC

AL4

IFPB_TXC_N

AM6

IFPB_TXD4

AM5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AK6

IFPB_TXD6

AK5

IFPB_TXD6_N

AK7

IFPB_TXD7

AL8

IFPB_TXD7_N

AL5

IFPAB_RSET

AM2

IFPC_TXC

AM3

IFPC_TXC_N

AE2

IFPC_TXD0

AE1

IFPC_TXD0_N

AF1

IFPC_TXD1

AF2

IFPC_TXD1_N

AG1

IFPC_TXD2

AH1

IFPC_TXD2_N

AG3

IFPD_TXC

AH2

IFPD_TXC_N

AK1

IFPD_TXD4

AJ1

IFPD_TXD4_N

AL2

IFPD_TXD5

AL1

IFPD_TXD5_N

AJ2

IFPD_TXD6

AJ3

IFPD_TXD6_N

AH3

IFPCD_RSET

NV72/73M_BGA820G71@

1

C686

0.1U_0402_16V4Z

2

128@

8

SCLK

7

SDATA

6

ALERT#

5

GND

I2C address
1001 100x

DACB_RSET

12

R146

88.7_0402_1%

@

2

NC

BUFRST_N
MEMSTRAPSEL0
MEMSTRAPSEL1
MEMSTRAPSEL2
MEMSTRAPSEL3

SWAPRDY_A

THERMDN
THERMDP

ROM_SCLK

ROMCS_N

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25

STEREO

STRAP

ROM_SI

ROM_SO

Part 4 of 6

LVDS/TMDS

GENERAL

SERIAL

Thermal sensor

+3VS

LCD_I2C_CLK_C
LCD_I2C_DAT_C

1 2

R501 0_0402_5%128@

12

R499

2.2K_0402_5%

128@

THER_ALERT#

R1178 R1180 are optional

、

trim resistor to provide finer
control of the RSET value

B32
C20
D1
J6
U3
U4
U5
U6
V1
V3
V4
V5
V6
W1
W3
W4
W5
Y5
Y6
Y30
AC26
AG12
AH13
AM8
AM9
AM10

F3
AE26

FAE recommand 6/29

AD26
AH31
AH32
T3
F1
M6
J1
K1

AA7
W2
AA6
AA4

LCD_I2C_DAT_C
LCD_I2C_CLK_C
DVI_SCLK
DVI_SDATA
I2CH_SCL
I2CH_SDA

D­D+

R105

1 2

10K_0402_5%

128@

DVI pull-high close to GPU

R502 2.2K_0402_5%128@

1 2

R500 2.2K_0402_5%128@

1 2

R110 2.2K_0402_5%128@

1 2

R106 2.2K_0402_5%128@

1 2

R130 2.2K_0402_5%128@

1 2

R128 2.2K_0402_5%128@

1 2

1

+3VS

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

18 60Thursday, December 15, 2005

5

FBAD[63..0]

FBAA[12..0]

FBBA[2..5]

DQSA#[7..0]

D D

DQSA[7..0]

DQMA#[7..0]

FBAD[63..0] <22,23>

FBAA[12..0] <22,23>

FBBA[2..5] <23>

DQSA#[7..0] <22,23>

DQSA[7..0] <22,23>

DQMA#[7..0] <22,23>

4

+1.8VS

12

R487

ODTA0

10K_0402_5%@

12

R484

10K_0402_5%128@

3

FBCD[63..0]

FBCA[12..0]

FBDA[2..5]

DQSC#[7..0]

DQSC[7..0]

DQMC#[7..0]

FBCD[63..0] <24,25>

FBCA[12..0] <24,25>

FBDA[2..5] <25>

DQSC#[7..0] <24,25>

DQSC[7..0] <24,25>

DQMC#[7..0] <24,25>

2

+1.8VS

12

R161

ODTC0

10K_0402_5%@

12

R160

10K_0402_5%256@

1

U33C

B7

FBCD0

A7

FBCD1

C7

FBCD2

A2

FBCD3

B2

FBCD4

C4

FBCD5

A5

FBCD6

B5

FBCD7

F9

FBCD8

F10

FBCD9

D12

FBCD10

D9

FBCD11

E12

FBCD12

D11

FBCD13

E8

FBCD14

D8

FBCD15

E7

FBCD16

F7

FBCD17

D6

FBCD18

D5

FBCD19

D3

FBCD20

E4

FBCD21

C3

FBCD22

B4

FBCD23

C10

FBCD24

B10

FBCD25

C8

FBCD26

A10

FBCD27

C11

FBCD28

C12

FBCD29

A11

FBCD30

B11

FBCD31

B28

FBCD32

C27

FBCD33

C26

FBCD34

B26

FBCD35

C30

FBCD36

B31

FBCD37

C29

FBCD38

A31

FBCD39

D28

FBCD40

D27

FBCD41

F26

FBCD42

D24

FBCD43

E23

FBCD44

E26

FBCD45

E24

FBCD46

F23

FBCD47

B23

FBCD48

A23

FBCD49

C25

FBCD50

C23

FBCD51

A22

FBCD52

C22

FBCD53

C21

FBCD54

B22

FBCD55

E22

FBCD56

D22

FBCD57

D21

FBCD58

E21

FBCD59

E18

FBCD60

D19

FBCD61

D18

FBCD62

E19

FBCD63

NV72/73M_BGA820G71@

Part 3 of 6

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

MEMORY INTERFACE B

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

FB_VREF2
FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBC_REFCLK

FBC_REFCLK_N

FBC_DEBUG

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15
B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20

A4
E11
F5
C9
C28
F24
C24
E20

C6
E9
E6
A8
B29
E25
A25
F21

C5
E10
E5
B8
A29
D25
B25
F20

A28
E13

F13
F18
E17
B1
C1
F12

FBCA3
FBCA0
FBCA2
FBCA1
FBDA3
FBDA4
FBDA5
FBCCS1#
FBCCS0#
FBCWE#
FBC_BA0
FBC_CKE

R142

1 2

FBDA2
FBCRAS#

FBCA11
FBCA10
FBC_BA1
FBCA8
FBCA9
FBCA6
FBCA5
FBCA7
FBCA4
FBCCAS#

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

FBA_VREF2
CLKC0

CLKC0#
CLKC1
CLKC1#

1 2

R141 0_0402_5%@

T24

PAD

FBCCS0# <24,25>
FBCWE# <24,25>
FBC_BA0 <24,25>

0_0402_5%256@

FBCRAS# <24,25>

FBC_BA1 <24,25>

FBCCAS# <24,25>

10mil

CLKC0 <24>
CLKC0# <24>
CLKC1 <25>
CLKC1# <25>

12

R135
10K_0402_5%

256@

C355

@

0.1U_0402_16V4Z

FBC_CKE <24,25>

+1.8VS

1

2

12

R138
1K_0402_1%

@

12

R143
1K_0402_1%

@

AD29
AE29
AD28
AC28
AB29
AA30

AB30

AM30

AF30

AJ31
AJ30
AJ32

AK29

AM31

AL30
AE32
AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29
AD27
AF27
AE28

U33B

N27

FBAD0

M27

FBAD1

N28

FBAD2

L29

FBAD3

K27

FBAD4

K28

FBAD5

J29

FBAD6

J28

FBAD7

P30

FBAD8

N31

FBAD9

N30

FBAD10

N32

FBAD11

L31

FBAD12

L30

FBAD13

J30

FBAD14

L32

FBAD15

H30

FBAD16

K30

FBAD17

H31

FBAD18

F30

FBAD19

H32

FBAD20

E31

FBAD21

D30

FBAD22

E30

FBAD23

H28

FBAD24

H29

FBAD25

E29

FBAD26

J27

FBAD27

F27

FBAD28

E27

FBAD29

E28

FBAD30

F28

FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37

Y28

FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

NV72/73M_BGA820G71@

Part 2 of 6

MEMORY INTERFACE A

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

FB_VREF1

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_REFCLK

FBA_REFCLK_N

FBA_DEBUG

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17

C C

FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33 DQMA#5
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49

B B

FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBAA3

P32

FBAA0

U27

FBAA2

P31

FBAA1

U30

FBBA3

Y31

FBBA4

W32

FBBA5

W31

FBACS1#

T32

FBACS0#

V27

FBAWE#

T28

FBA_BA0

T31

FBA_CKE

U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32

M29
M30
G30
F29
AA29
AK30
AC30
AG30

M28
K32
G31
G27
AA28
AL31
AF31
AH29

L28
K31
G32
G28
AB28
AL32
AF32
AH30

E32
P28

R28
Y27
AA27
D32
D31
AC27

R96

1 2

FBBA2
FBAA12 FBCA12
FBARAS#
FBAA11
FBAA10
FBA_BA1
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4

DQMA#6
DQMA#7

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

FBA_VREF1

CLKA0
CLKA0#
CLKA1
CLKA1#

1 2

R94 0_0402_5%@

T21

PAD

FBACS0# <22,23>
FBAWE# <22,23>
FBA_BA0 <22,23>

ODTA0 ODTC0

0_0402_5%128@

FBARAS# <22,23>

FBA_BA1 <22,23>

FBACAS# <22,23>

10mil

CLKA0 <22>
CLKA0# <22>
CLKA1 <23>
CLKA1# <23>

ODTA0 ODTC0

ODTA0 <22,23> ODTC0 <24,25>

12

R97
10K_0402_5%

128@

FBA_CKE <22,23>

C687

0.1U_0402_16V4Z

1

2

10mil

+1.8VS

12

R506
1K_0402_1%

12

R505
1K_0402_1%

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

G72/73VGA Board

LA-2841

1

1.0

of

19 60Thursday, December 15, 2005