Intel 8XC196NP, 80C196NU User Manual

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8XC196NP, 80C196NU Microcontroller

User’ Manual

8XC196NP, 80C196NU Microcontroller User’s Manual

August 2004 Order Number 272479-003

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.

MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.

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*Other brands and names are the property of their respective owners.

Additional copies of this document or other Intel literature may be obtained from:

Intel Corporation

Literature Sales

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

© INTEL CORPORATION, 1996

ii

 

 

CONTENTS

CHAPTER 1

 

GUIDE TO THIS MANUAL

 

1.1

MANUAL CONTENTS ...................................................................................................

1-1

1.2

NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................

1-3

1.3

RELATED DOCUMENTS ..............................................................................................

1-5

1.4

ELECTRONIC SUPPORT SYSTEMS ...........................................................................

1-8

1.4.4

 

World Wide Web .....................................................................................................

1-11

1.5

TECHNICAL SUPPORT ..............................................................................................

1-11

1.6

PRODUCT LITERATURE............................................................................................

1-11

CHAPTER 2

 

ARCHITECTURAL OVERVIEW

 

2.1

TYPICAL APPLICATIONS.............................................................................................

2-1

2.2

DEVICE FEATURES .....................................................................................................

2-2

2.3

BLOCK DIAGRAM.........................................................................................................

2-2

2.3.1

 

CPU Control ..............................................................................................................

2-3

2.3.2

 

Register File ..............................................................................................................

2-3

2.3.3

 

Register Arithmetic-logic Unit (RALU) .......................................................................

2-4

2.3.3.1

Code Execution ....................................................................................................

2-4

2.3.3.2

Instruction Format ................................................................................................

2-5

2.3.4

 

Memory Controller ....................................................................................................

2-5

2.3.5

 

Multiply-accumulate (80C196NU Only) .....................................................................

2-6

2.3.6

 

Interrupt Service ........................................................................................................

2-6

2.4

INTERNAL TIMING........................................................................................................

2-7

2.5

INTERNAL PERIPHERALS.........................................................................................

2-11

2.5.1

 

I/O Ports ..................................................................................................................

2-11

2.5.2

 

Serial I/O (SIO) Port ................................................................................................

2-11

2.5.3 Event Processor Array (EPA) and Timer/Counters .................................................

2-11

2.5.4

 

Pulse-width Modulator (PWM) ................................................................................

2-12

2.6

SPECIAL OPERATING MODES .................................................................................

2-12

2.6.1

 

Reducing Power Consumption ...............................................................................

2-12

2.6.2 Testing the Printed Circuit Board ............................................................................

2-13

2.7

DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS ......

2-13

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8XC196NP, 80C196NU USER’S MANUAL

 

CHAPTER 3

 

ADVANCED MATH FEATURES

 

3.1

ENHANCED MULTIPLICATION INSTRUCTIONS........................................................

3-1

3.2

OPERATING MODES....................................................................................................

3-2

3.2.1

 

Saturation Mode ........................................................................................................

3-2

3.2.2

 

Fractional Mode ........................................................................................................

3-3

3.3

ACCUMULATOR REGISTER (ACC_0x) .......................................................................

3-4

3.4

ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT) .......................

3-5

CHAPTER 4

 

PROGRAMMING CONSIDERATIONS

 

4.1

OVERVIEW OF THE INSTRUCTION SET....................................................................

4-1

4.1.1

 

BIT Operands ............................................................................................................

4-2

4.1.2

BYTE Operands ........................................................................................................

4-2

4.1.3

SHORT-INTEGER Operands ....................................................................................

4-2

4.1.4

 

WORD Operands ......................................................................................................

4-3

4.1.5

INTEGER Operands .................................................................................................

4-3

4.1.6

DOUBLE-WORD Operands ......................................................................................

4-3

4.1.7

LONG-INTEGER Operands ......................................................................................

4-4

4.1.8

QUAD-WORD Operands ..........................................................................................

4-4

4.1.9

 

Converting Operands ................................................................................................

4-4

4.1.10

Conditional Jumps ....................................................................................................

4-4

4.1.11

Floating Point Operations .........................................................................................

4-5

4.1.12

Extended Instructions ...............................................................................................

4-5

4.2

ADDRESSING MODES.................................................................................................

4-6

4.2.1

Direct Addressing ......................................................................................................

4-7

4.2.2

 

Immediate Addressing ..............................................................................................

4-7

4.2.3

 

Indirect Addressing ...................................................................................................

4-7

4.2.3.1

Extended Indirect Addressing ..............................................................................

4-8

4.2.3.2 Indirect Addressing with Autoincrement ...............................................................

4-8

4.2.3.3 Extended Indirect Addressing with Autoincrement ...............................................

4-8

4.2.3.4 Indirect Addressing with the Stack Pointer ...........................................................

4-9

4.2.4

Indexed Addressing ..................................................................................................

4-9

4.2.4.1

Short-indexed Addressing ....................................................................................

4-9

4.2.4.2

Long-indexed Addressing ....................................................................................

4-9

4.2.4.3

Extended Indexed Addressing ...........................................................................

4-10

4.2.4.4

Zero-indexed Addressing ...................................................................................

4-10

4.2.4.5

Extended Zero-indexed Addressing ...................................................................

4-10

4.3

ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS ................................

4-11

4.3.1

Direct Addressing ....................................................................................................

4-11

4.3.2

Indexed Addressing ................................................................................................

4-11

4.3.3

Extended Addressing ..............................................................................................

4-11

4.4

DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES............................................

4-11

4.5

SOFTWARE STANDARDS AND CONVENTIONS .....................................................

4-11

iv

 

 

 

CONTENTS

4.5.1

 

Using Registers .......................................................................................................

4-12

4.5.2

 

Addressing 32-bit Operands ...................................................................................

4-12

4.5.3

 

Addressing 64-bit Operands ...................................................................................

4-12

4.5.4

 

Linking Subroutines ................................................................................................

4-13

4.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES ....................................

4-14

CHAPTER 5

 

MEMORY PARTITIONS

 

5.1

MEMORY MAP OVERVIEW..........................................................................................

5-1

5.2

MEMORY PARTITIONS ................................................................................................

5-3

5.2.1

 

External Memory .......................................................................................................

5-5

5.2.2 Program and Special-purpose Memory ....................................................................

5-5

5.2.2.1 Program Memory in Page FFH ............................................................................

5-5

5.2.2.2

Special-purpose Memory .....................................................................................

5-6

5.2.2.3

Reserved Memory Locations ...............................................................................

5-7

5.2.2.4 Interrupt and PTS Vectors ....................................................................................

5-7

5.2.2.5

Chip Configuration Bytes .....................................................................................

5-7

5.2.3

 

Peripheral Special-function Registers (SFRs) ...........................................................

5-7

5.2.4

 

Register File ..............................................................................................................

5-9

5.2.4.1

General-purpose Register RAM .........................................................................

5-11

5.2.4.2

Stack Pointer (SP) ..............................................................................................

5-11

5.2.4.3

CPU Special-function Registers (SFRs) .............................................................

5-12

5.3

WINDOWING...............................................................................................................

5-13

5.3.1

 

Selecting a Window ................................................................................................

5-14

5.3.2 Addressing a Location Through a Window .............................................................

5-16

5.3.2.1

32-byte Windowing Example ..............................................................................

5-18

5.3.2.2

64-byte Windowing Example ..............................................................................

5-18

5.3.2.3

128-byte Windowing Example ............................................................................

5-18

5.3.2.4 Unsupported Locations Windowing Example (8XC196NP Only) .......................

5-19

5.3.2.5 Using the Linker Locator to Set Up a Window ....................................................

5-19

5.3.3 Windowing and Addressing Modes .........................................................................

5-21

5.4 REMAPPING INTERNAL ROM (83C196NP ONLY) ...................................................

5-22

5.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES..............

5-23

5.5.1

 

Fetching Instructions ...............................................................................................

5-23

5.5.2

 

Accessing Data .......................................................................................................

5-23

5.5.3 Code Fetches in the 1-Mbyte Mode ........................................................................

5-25

5.5.4 Code Fetches in the 64-Kbyte Mode ......................................................................

5-25

5.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes .................................................

5-26

5.6

MEMORY CONFIGURATION EXAMPLES .................................................................

5-27

5.6.1 Example 1: Using the 64-Kbyte Mode ....................................................................

5-27

5.6.2 Example 2: A 64-Kbyte System with Additional Data Storage ................................

5-29

5.6.3 Example 3: Using 1-Mbyte Mode ............................................................................

5-31

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8XC196NP, 80C196NU USER’S MANUAL

 

CHAPTER 6

 

STANDARD AND PTS INTERRUPTS

 

6.1

OVERVIEW OF INTERRUPTS......................................................................................

6-1

6.2

INTERRUPT SIGNALS AND REGISTERS ...................................................................

6-3

6.3

INTERRUPT SOURCES AND PRIORITIES..................................................................

6-4

6.3.1

 

Special Interrupts ......................................................................................................

6-4

6.3.1.1

Unimplemented Opcode ......................................................................................

6-5

6.3.1.2

Software Trap .......................................................................................................

6-5

6.3.1.3

NMI .......................................................................................................................

6-6

6.3.2

 

External Interrupt Pins ..............................................................................................

6-6

6.3.3

 

Multiplexed Interrupt Sources ...................................................................................

6-6

6.3.4

 

End-of-PTS Interrupts ...............................................................................................

6-6

6.4

INTERRUPT LATENCY.................................................................................................

6-7

6.4.1 Situations that Increase Interrupt Latency ................................................................

6-7

6.4.2

Calculating Latency ...................................................................................................

6-8

6.4.2.1

Standard Interrupt Latency ...................................................................................

6-8

6.4.2.2

PTS Interrupt Latency ..........................................................................................

6-9

6.5

PROGRAMMING THE INTERRUPTS.........................................................................

6-10

6.5.1 Programming Considerations for Multiplexed Interrupts .........................................

6-11

6.5.2

 

Modifying Interrupt Priorities ...................................................................................

6-13

6.5.3 Determining the Source of an Interrupt ...................................................................

6-15

6.6

INITIALIZING THE PTS CONTROL BLOCKS.............................................................

6-17

6.6.1

Specifying the PTS Count .......................................................................................

6-18

6.6.2

Selecting the PTS Mode .........................................................................................

6-19

6.6.3

 

Single Transfer Mode ..............................................................................................

6-20

6.6.4

Block Transfer Mode ...............................................................................................

6-23

6.6.5

PWM Modes ...........................................................................................................

6-26

6.6.5.1 PWM Toggle Mode Example .............................................................................

6-27

6.6.5.2

PWM Remap Mode Example .............................................................................

6-32

CHAPTER 7

 

I/O PORTS

 

7.1

I/O PORTS OVERVIEW ................................................................................................

7-1

7.2

BIDIRECTIONAL PORTS 1–4 .......................................................................................

7-1

7.2.1

Bidirectional Port Operation ......................................................................................

7-3

7.2.2 Bidirectional Port Pin Configurations .........................................................................

7-7

7.2.3 Bidirectional Port Pin Configuration Example ...........................................................

7-8

7.2.4

Bidirectional Port Considerations ..............................................................................

7-9

7.2.5 Design Considerations for External Interrupt Inputs ...............................................

7-11

7.3

EPORT ........................................................................................................................

7-11

7.3.1

EPORT Operation ...................................................................................................

7-12

7.3.1.1

Reset ..................................................................................................................

7-14

7.3.1.2

Output Enable ....................................................................................................

7-14

7.3.1.3

Complementary Output Mode ............................................................................

7-14

vi

 

 

 

CONTENTS

7.3.1.4

Open-drain Output Mode ...................................................................................

7-14

7.3.1.5

Input Mode .........................................................................................................

7-16

7.3.2

 

Configuring EPORT Pins ........................................................................................

7-17

7.3.2.1 Configuring EPORT Pins for Extended-address Functions ................................

7-17

7.3.2.2 Configuring EPORT Pins for I/O ........................................................................

7-17

7.3.3

 

EPORT Considerations ...........................................................................................

7-18

7.3.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold .............

7-18

7.3.3.2 EP_REG Settings for Pins Configured as Extended-address Signals ...............

7-18

7.3.3.3 EPORT Status During Instruction Execution ......................................................

7-18

7.3.3.4

Design Considerations .......................................................................................

7-19

CHAPTER 8

 

SERIAL I/O (SIO) PORT

 

8.1

SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW ...................................................

8-1

8.2

SERIAL I/O PORT SIGNALS AND REGISTERS ..........................................................

8-2

8.3

SERIAL PORT MODES.................................................................................................

8-4

8.3.1 Synchronous Mode (Mode 0) ....................................................................................

8-4

8.3.2 Asynchronous Modes (Modes 1, 2, and 3) ...............................................................

8-5

8.3.2.1

Mode 1 .................................................................................................................

8-6

8.3.2.2

Mode 2 .................................................................................................................

8-7

8.3.2.3

Mode 3 .................................................................................................................

8-7

8.3.2.4 Mode 2 and 3 Timings ..........................................................................................

8-7

8.3.2.5

Multiprocessor Communications ..........................................................................

8-8

8.4

PROGRAMMING THE SERIAL PORT ..........................................................................

8-8

8.4.1 Configuring the Serial Port Pins ................................................................................

8-8

8.4.2 Programming the Control Register ............................................................................

8-8

8.4.3 Programming the Baud Rate and Clock Source .......................................................

8-8

8.4.4 Enabling the Serial Port Interrupts ..........................................................................

8-13

8.4.5

 

Determining Serial Port Status ................................................................................

8-13

CHAPTER 9

 

PULSE-WIDTH MODULATOR

 

9.1

PWM FUNCTIONAL OVERVIEW..................................................................................

9-1

9.2

PWM SIGNALS AND REGISTERS ...............................................................................

9-2

9.3

PWM OPERATION........................................................................................................

9-3

9.4

PROGRAMMING THE FREQUENCY AND PERIOD....................................................

9-5

9.5

PROGRAMMING THE DUTY CYCLE...........................................................................

9-7

9.5.1

 

Sample Calculations .................................................................................................

9-9

9.5.2 Enabling the PWM Outputs .......................................................................................

9-9

9.5.3

Generating Analog Outputs ......................................................................................

9-9

CHAPTER 10

 

EVENT PROCESSOR ARRAY (EPA)

 

10.1

EPA FUNCTIONAL OVERVIEW .................................................................................

10-1

vii

8XC196NP, 80C196NU USER’S MANUAL

 

10.2

EPA AND TIMER/COUNTER SIGNALS AND REGISTERS .......................................

10-2

10.3

TIMER/COUNTER FUNCTIONAL OVERVIEW...........................................................

10-5

10.3.1 Cascade Mode (Timer 2 Only) ................................................................................

10-6

10.3.2

Quadrature Clocking Mode .....................................................................................

10-6

10.4

EPA CHANNEL FUNCTIONAL OVERVIEW ...............................................................

10-8

10.4.1

Operating in Capture Mode .....................................................................................

10-9

10.4.1.1

EPA Overruns ..................................................................................................

10-11

10.4.1.2

Preventing EPA Overruns ................................................................................

10-12

10.4.2 Operating in Compare Mode .................................................................................

10-12

10.4.2.1 Generating a Low-speed PWM Output ............................................................

10-12

10.4.2.2 Generating a Medium-speed PWM Output .....................................................

10-13

10.4.2.3 Generating a High-speed PWM Output ...........................................................

10-14

10.4.2.4 Generating the Highest-speed PWM Output ....................................................

10-15

10.5

PROGRAMMING THE EPA AND TIMER/COUNTERS.............................................

10-15

10.5.1 Configuring the EPA and Timer/Counter Port Pins ...............................................

10-15

10.5.2

Programming the Timers .......................................................................................

10-15

10.5.3 Programming the Capture/Compare Channels .....................................................

10-18

10.6

ENABLING THE EPA INTERRUPTS ........................................................................

10-22

10.7

DETERMINING EVENT STATUS..............................................................................

10-22

10.7.1 Using Software to Service the Multiplexed Overrun Interrupts .............................

10-23

10.8

PROGRAMMING EXAMPLES FOR EPA CHANNELS .............................................

10-24

10.8.1

EPA Compare Event Program ..............................................................................

10-24

10.8.2 EPA Capture Event Program ................................................................................

10-25

10.8.3 EPA PWM Output Program ..................................................................................

10-26

CHAPTER 11

 

MINIMUM HARDWARE CONSIDERATIONS

 

11.1

MINIMUM CONNECTIONS .........................................................................................

11-1

11.1.1

Unused Inputs .........................................................................................................

11-2

11.1.2

I/O Port Pin Connections ........................................................................................

11-2

11.2

APPLYING AND REMOVING POWER .......................................................................

11-4

11.3

NOISE PROTECTION TIPS ........................................................................................

11-4

11.4

THE ON-CHIP OSCILLATOR CIRCUITRY .................................................................

11-5

11.5

USING AN EXTERNAL CLOCK SOURCE..................................................................

11-7

11.6

RESETTING THE DEVICE..........................................................................................

11-8

11.6.1 Generating an External Reset .................................................................................

11-9

11.6.2 Issuing the Reset (RST) Instruction ......................................................................

11-11

11.6.3 Issuing an Illegal IDLPD Key Operand .................................................................

11-11

CHAPTER 12

 

SPECIAL OPERATING MODES

 

12.1

SPECIAL OPERATING MODE SIGNALS AND REGISTERS.....................................

12-1

12.2

REDUCING POWER CONSUMPTION .......................................................................

12-3

viii

 

 

 

CONTENTS

12.3

IDLE MODE .................................................................................................................

12-5

12.4

STANDBY MODE (80C196NU ONLY) ........................................................................

12-6

12.4.1 Enabling and Disabling Standby Mode ...................................................................

12-6

12.4.2

Entering Standby Mode ..........................................................................................

12-6

12.4.3

Exiting Standby Mode .............................................................................................

12-7

12.5

POWERDOWN MODE ................................................................................................

12-7

12.5.1 Enabling and Disabling Powerdown Mode ..............................................................

12-7

12.5.2

Entering Powerdown Mode .....................................................................................

12-7

12.5.3

Exiting Powerdown Mode .......................................................................................

12-8

12.5.3.1

Generating a Hardware Reset ...........................................................................

12-8

12.5.3.2 Asserting an External Interrupt Signal ................................................................

12-8

12.5.3.3

Selecting C1 .....................................................................................................

12-10

12.6

ONCE MODE.............................................................................................................

12-12

12.7

RESERVED TEST MODES (80C196NU ONLY).......................................................

12-12

CHAPTER 13

 

INTERFACING WITH EXTERNAL MEMORY

 

13.1

INTERNAL AND EXTERNAL ADDRESSES ...............................................................

13-1

13.2

EXTERNAL MEMORY INTERFACE SIGNALS...........................................................

13-2

13.3

THE CHIP-SELECT UNIT............................................................................................

13-5

13.3.1 Defining Chip-select Address Ranges ....................................................................

13-7

13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing ....................................

13-10

13.3.3

Chip-select Unit Initial Conditions .........................................................................

13-11

13.3.4

Initializing the Chip-select Registers .....................................................................

13-11

13.3.5 Example of a Chip-select Setup ............................................................................

13-12

13.4

CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES .......

13-14

13.5

BUS WIDTH AND MULTIPLEXING...........................................................................

13-18

13.5.1

A 16-bit Example System ......................................................................................

13-21

13.5.2

16-bit Bus Timings ................................................................................................

13-22

13.5.3

8-bit Bus Timings ..................................................................................................

13-24

13.5.4 Comparison of Multiplexed and Demultiplexed Buses ..........................................

13-26

13.6

WAIT STATES (READY CONTROL).........................................................................

13-26

13.7

BUS-HOLD PROTOCOL ...........................................................................................

13-30

13.7.1

Enabling the Bus-hold Protocol .............................................................................

13-32

13.7.2

Disabling the Bus-hold Protocol ............................................................................

13-32

13.7.3

Hold Latency .........................................................................................................

13-32

13.7.4

Regaining Bus Control ..........................................................................................

13-33

13.8

WRITE-CONTROL MODES ......................................................................................

13-33

13.9

SYSTEM BUS AC TIMING SPECIFICATIONS .........................................................

13-36

13.9.1 Deferred Bus-cycle Mode (80C196NU Only) ........................................................

13-40

13.9.2

Explanation of AC Symbols ..................................................................................

13-42

13.9.3

AC Timing Definitions ...........................................................................................

13-42

ix

8XC196NP, 80C196NU USER’S MANUAL

 

APPENDIX A

 

INSTRUCTION SET REFERENCE

 

APPENDIX B

 

SIGNAL DESCRIPTIONS

 

B.1

FUNCTIONAL GROUPINGS OF SIGNALS

................................................................. B-1

B.2

SIGNAL DESCRIPTIONS.............................................................................................

B-6

B.3

DEFAULT CONDITIONS............................................................................................

B-13

APPENDIX C

REGISTERS

GLOSSARY

INDEX

x

 

 

CONTENTS

 

FIGURES

 

Figure

 

Page

2-1

8XC196NP and 80C196NU Block Diagram .................................................................

2-2

2-2

Block Diagram of the Core ...........................................................................................

2-3

2-3

Clock Circuitry (8XC196NP) .........................................................................................

2-7

2-4

Clock Circuitry (80C196NU) .........................................................................................

2-8

2-5

Internal Clock Phases ..................................................................................................

2-9

2-6

Effect of Clock Mode on CLKOUT Frequency............................................................

2-10

3-1

Accumulator (ACC_0x) Register ..................................................................................

3-4

3-2

Accumulator Control and Status (ACC_STAT) Register ..............................................

3-5

5-1

16-Mbyte Address Space .............................................................................................

5-2

5-2

Pages FFH and 00H.....................................................................................................

5-3

5-3

Register File Memory Map .........................................................................................

5-10

5-4

Windowing..................................................................................................................

5-13

5-5

Window Selection (WSR) Register.............................................................................

5-14

5-6

Window Selection 1 (WSR1) Register........................................................................

5-15

5-7

The 24-bit Program Counter.......................................................................................

5-23

5-8

Formation of Extended and Nonextended Addresses................................................

5-24

5-9

A 64-Kbyte System With an 8-bit Bus ........................................................................

5-27

5-10

A 64-Kbyte System with Additional Data Storage ......................................................

5-29

5-11

Example System Using the 1-Mbyte Mode ................................................................

5-31

6-1

Flow Diagram for PTS and Standard Interrupts ...........................................................

6-2

6-2

Standard Interrupt Response Time ..............................................................................

6-9

6-3

PTS Interrupt Response Time......................................................................................

6-9

6-4

PTS Select (PTSSEL) Register ..................................................................................

6-11

6-5

Interrupt Mask (INT_MASK) Register.........................................................................

6-12

6-6

Interrupt Mask 1 (INT_MASK1) Register....................................................................

6-13

6-7

Interrupt Pending (INT_PEND) Register ....................................................................

6-16

6-8

Interrupt Pending 1 (INT_PEND1) Register ...............................................................

6-17

6-9

PTS Control Blocks ....................................................................................................

6-18

6-10

PTS Service (PTSSRV) Register ...............................................................................

6-19

6-11

PTS Mode Selection Bits (PTSCON Bits 7:5) ............................................................

6-20

6-12

PTS Control Block — Single Transfer Mode ..............................................................

6-21

6-13

PTS Control Block — Block Transfer Mode ...............................................................

6-24

6-14

A Generic PWM Waveform ........................................................................................

6-27

6-15

PTS Control Block — PWM Toggle Mode..................................................................

6-29

6-16

EPA and PTS Operations for the PWM Toggle Mode Example.................................

6-31

6-17

PTS Control Block — PWM Remap Mode .................................................................

6-34

6-18

EPA and PTS Operations for the PWM Remap Mode Example ................................

6-36

7-1

Bidirectional Port Structure...........................................................................................

7-5

7-2

EPORT Block Diagram...............................................................................................

7-13

7-3

EPORT Structure .......................................................................................................

7-15

8-1

SIO Block Diagram.......................................................................................................

8-1

8-2

Typical Shift Register Circuit for Mode 0 ......................................................................

8-4

8-3

Mode 0 Timing..............................................................................................................

8-5

8-4

Serial Port Frames for Mode 1 .....................................................................................

8-6

xi

8XC196NP, 80C196NU USER’S MANUAL

FIGURES

Figure

 

Page

8-5

Serial Port Frames in Mode 2 and 3.............................................................................

8-7

8-6

Serial Port Control (SP_CON) Register........................................................................

8-9

8-7

Serial Port Baud Rate (SP_BAUD) Register ..............................................................

8-11

8-8

Serial Port Status (SP_STATUS) Register.................................................................

8-14

9-1

PWM Block Diagram (8XC196NP Only).......................................................................

9-1

9-2

PWM Block Diagram (80C196NU Only).......................................................................

9-2

9-3

PWM Output Waveforms..............................................................................................

9-5

9-4

Control (CON_REG0) Register ....................................................................................

9-7

9-5

PWM Control (PWMx_CONTROL) Register ................................................................

9-8

9-6

D/A Buffer Block Diagram...........................................................................................

9-10

9-7

PWM to Analog Conversion Circuitry .........................................................................

9-10

10-1

EPA Block Diagram ....................................................................................................

10-2

10-2

EPA Timer/Counters ..................................................................................................

10-5

10-3

Quadrature Mode Interface ........................................................................................

10-7

10-4

Quadrature Mode Timing and Count..........................................................................

10-8

10-5

A Single EPA Capture/Compare Channel ..................................................................

10-9

10-6

EPA Simplified Input-capture Structure ....................................................................

10-10

10-7

Valid EPA Input Events ............................................................................................

10-10

10-8

Timer 1 Control (T1CONTROL) Register .................................................................

10-16

10-9

Timer 2 Control (T2CONTROL) Register .................................................................

10-17

10-10

EPA Control (EPAx_CON) Registers .......................................................................

10-19

10-11

EPA Interrupt Mask (EPA_MASK) Register .............................................................

10-22

10-12

EPA Interrupt Pending (EPA_PEND) Register.........................................................

10-23

11-1

Minimum Hardware Connections ...............................................................................

11-3

11-2

Power and Return Connections .................................................................................

11-4

11-3

On-chip Oscillator Circuit............................................................................................

11-5

11-4

External Crystal Connections .....................................................................................

11-6

11-5

External Clock Connections .......................................................................................

11-7

11-6

External Clock Drive Waveforms................................................................................

11-7

11-7

Reset Timing Sequence .............................................................................................

11-8

11-8

Internal Reset Circuitry ...............................................................................................

11-9

11-9

Minimum Reset Circuit .............................................................................................

11-10

11-10

Example System Reset Circuit .................................................................................

11-10

12-1

Clock Control During Power-saving Modes (8XC196NP) ..........................................

12-4

12-2

Clock Control During Power-saving Modes (80C196NU)...........................................

12-5

12-3

Power-up and Powerdown Sequence When Using an External Interrupt..................

12-9

12-4

External RC Circuit.....................................................................................................

12-9

12-5

Typical Voltage on the RPD Pin While Exiting Powerdown.....................................

12-11

13-1

Calculation of a Chip-select Output ............................................................................

13-6

13-2

Address Compare (ADDRCOMx) Register ................................................................

13-7

13-3

Address Mask (ADDRMSKx) Register .......................................................................

13-8

13-4

Bus Control (BUSCONx) Register............................................................................

13-10

13-5

Example System for Setting Up Chip-select Outputs ...............................................

13-13

13-6

Chip Configuration 0 (CCR0) Register .....................................................................

13-15

xii

 

 

CONTENTS

 

FIGURES

 

Figure

 

Page

13-7

Chip Configuration 1 (CCR1) Register .....................................................................

13-16

13-8

Multiplexing and Bus Width Options.........................................................................

13-19

13-9

Bus Activity for Four Types of Buses........................................................................

13-20

13-10

16-bit External Devices in Demultiplexed Mode.......................................................

13-22

13-11

Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP) ...................

13-23

13-12

Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP) .....................

13-25

13-13

READY Timing Diagram — Multi plexed Mode .........................................................

13-28

13-14

READY Timing Diagram — Demultiplexed Mode (8XC196NP) ...............................

13-29

13-15

READY Timing Diagram — Demultiplexed Mode (80C196NU) ...............................

13-30

13-16

HOLD#, HLDA# Timing ............................................................................................

13-31

13-17

Write-control Signal Waveforms...............................................................................

13-34

13-18

Decoding WRL# and WRH#.....................................................................................

13-35

13-19

A System with 8-bit and 16-bit Buses.......................................................................

13-36

13-20

Multiplexed System Bus Timing (8XC196NP) ..........................................................

13-37

13-21

Multiplexed System Bus Timing (80C196NU) ..........................................................

13-38

13-22

Demultiplexed System Bus Timing (8XC196NP) .....................................................

13-39

13-23

Demultiplexed System Bus Timing (80C196NU)......................................................

13-40

13-24

Deferred Bus-cycle Mode Timing Diagram (80C196NU) .........................................

13-41

B-1

8XC196NP 100-lead SQFP Package..........................................................................

B-2

B-2

8XC196NP 100-lead QFP Package ............................................................................

B-3

B-3

80C196NU 100-lead SQFP Package..........................................................................

B-4

B-4

80C196NU 100-lead QFP Package ............................................................................

B-5

xiii

8XC196NP, 80C196NU USER’S MANUAL

TABLES

Table

 

Page

1-1

Handbooks and Product Information ............................................................................

1-6

1-2

Application Notes, Application Briefs, and Article Reprints ..........................................

1-6

1-3

MCS®96 Microcontroller Datasheets (Commercial/Express) ......................................

1-7

1-4

MCS®96 Microcontroller Datasheets (Automotive) .....................................................

1-7

1-5

MCS®96 Microcontroller Quick References ................................................................

1-8

2-1

Features of the 8XC196NP and 80C196NU.................................................................

2-2

2-2

State Times at Various Frequencies ............................................................................

2-9

2-3

Relationships Between Input Frequency, Clock Multiplier, and State Times .............

2-10

3-1

Multiply/Accumulate Example Code.............................................................................

3-2

3-2

Effect of SME and FME Bit Combinations....................................................................

3-6

4-1

Operand Type Definitions.............................................................................................

4-1

4-2

Equivalent Operand Types for Assembly and C Programming Languages .................

4-2

4-3

Definition of Temporary Registers ................................................................................

4-7

5-1

8XC196NP and 80C196NU Memory Map....................................................................

5-4

5-2

Program Memory Access for the 83C196NP ...............................................................

5-5

5-3

8XC196NP and 80C196NU Special-purpose Memory Addresses...............................

5-6

5-4

Special-purpose Memory Access for the 83C196NP ...................................................

5-6

5-5

Peripheral SFRs ...........................................................................................................

5-8

5-6

Register File Memory Addresses ...............................................................................

5-11

5-7

CPU SFRs..................................................................................................................

5-12

5-8

Selecting a Window of Peripheral SFRs.....................................................................

5-15

5-9

Selecting a Window of the Upper Register File ..........................................................

5-15

5-10

Windows.....................................................................................................................

5-17

5-11

Windowed Base Addresses .......................................................................................

5-18

5-12

Memory Map for the System in Figure 5-9 .................................................................

5-28

5-13

Memory Map for the System in Figure 5-10 ...............................................................

5-30

5-14

Memory Map for the System in Figure 5-11 ...............................................................

5-32

6-1

Interrupt Signals ...........................................................................................................

6-3

6-2

Interrupt and PTS Control and Status Registers ..........................................................

6-3

6-3

Interrupt Sources, Vectors, and Priorities.....................................................................

6-5

6-4

Execution Times for PTS Cycles................................................................................

6-10

6-5

Single Transfer Mode PTSCB ....................................................................................

6-23

6-6

Block Transfer Mode PTSCB .....................................................................................

6-23

6-7

Comparison of PWM Modes.......................................................................................

6-26

6-8

PWM Toggle Mode PTSCB........................................................................................

6-28

6-9

PWM Remap Mode PTSCB .......................................................................................

6-33

7-1

Device I/O Ports ...........................................................................................................

7-1

7-2

Bidirectional Port Pins ..................................................................................................

7-2

7-3

Bidirectional Port Control and Status Registers ...........................................................

7-3

7-4

Logic Table for Bidirectional Ports in I/O Mode ............................................................

7-6

7-5

Logic Table for Bidirectional Ports in Special-function Mode .......................................

7-6

7-6

Control Register Values for Each Configuration...........................................................

7-8

7-7

Port Configuration Example .........................................................................................

7-8

7-8

Port Pin States After Reset and After Example Code Execution..................................

7-9

xiv

 

CONTENTS

 

TABLES

 

Table

 

Page

7-9

EPORT Pins ...............................................................................................................

7-11

7-10

EPORT Control and Status Registers ........................................................................

7-12

7-11

Logic Table for EPORT in I/O Mode...........................................................................

7-16

7-12

Logic Table for EPORT in Address Mode ..................................................................

7-16

7-13

Configuration Register Settings for EPORT Pins .......................................................

7-17

8-1

Serial Port Signals........................................................................................................

8-2

8-2

Serial Port Control and Status Registers......................................................................

8-2

8-3

SP_BAUD Values When Using the Internal Clock at 25 MHz....................................

8-12

8-4

SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only) ......

8-13

9-1

PWM Signals ................................................................................................................

9-2

9-2

PWM Control and Status Registers..............................................................................

9-3

9-3

PWM Output Frequencies (8XC196NP).......................................................................

9-6

9-4

PWM Output Frequencies (80C196NU).......................................................................

9-6

9-5

PWM Output Alternate Functions .................................................................................

9-9

10-1

EPA and Timer/Counter Signals.................................................................................

10-2

10-2

EPA Control and Status Registers .............................................................................

10-3

10-3

Quadrature Mode Truth Table....................................................................................

10-7

10-4

Action Taken when a Valid Edge Occurs .................................................................

10-11

10-5

Example Control Register Settings and EPA Operations.........................................

10-18

11-1

Minimum Required Signals.........................................................................................

11-1

11-2

I/O Port Configuration Guide ......................................................................................

11-2

12-1

Operating Mode Control Signals ................................................................................

12-1

12-2

Operating Mode Control and Status Registers...........................................................

12-2

12-3

80C196NU Clock Modes..........................................................................................

12-13

13-1

Example of Internal and External Addresses .............................................................

13-1

13-2

External Memory Interface Signals.............................................................................

13-2

13-3

Chip-select Registers .................................................................................................

13-6

13-4

ADDRCOMx Addresses and Reset Values................................................................

13-7

13-5

ADDRMSKx Addresses and Reset Values ................................................................

13-8

13-6

Base Addresses for Several Sizes of the Address Range .........................................

13-9

13-7

BUSCONx Addresses and Reset Values.................................................................

13-11

13-8

BUSCONx Registers for the Example System .........................................................

13-13

13-9

Results for the Chip-select Example ........................................................................

13-14

13-10

Comparison of AC Timings for Demultiplexed and Multiplexed 16-bit Buses ..........

13-26

13-11

READY Signal Timing Definitions.............................................................................

13-27

13-12

HOLD#, HLDA# Timing Definitions ..........................................................................

13-31

13-13

Maximum Hold Latency ............................................................................................

13-33

13-14

Write Signals for Standard and Write Strobe Modes................................................

13-34

13-15

AC Timing Symbol Definitions..................................................................................

13-42

13-16

AC Timing Definitions...............................................................................................

13-42

A-1

Opcode Map (Left Half) ...............................................................................................

A-2

A-1

Opcode Map (Right Half).............................................................................................

A-3

A-2

Processor Status Word (PSW) Flags ..........................................................................

A-4

A-3

Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions .........

A-5

xv

8XC196NP, 80C196NU USER’S MANUAL

 

TABLES

 

Table

 

Page

A-4

PSW Flag Setting Symbols .........................................................................................

A-5

A-5

Operand Variables ......................................................................................................

A-6

A-6

Instruction Set .............................................................................................................

A-7

A-7

Instruction Opcodes ..................................................................................................

A-47

A-8

Instruction Lengths and Hexadecimal Opcodes ........................................................

A-53

A-9

Instruction Execution Times (in State Times) ............................................................

A-60

B-1

8XC196NP and 80C196NU Signals Arranged by Function.........................................

B-1

B-2

Description of Columns of Table B-3...........................................................................

B-6

B-3

Signal Descriptions......................................................................................................

B-6

B-4

Definition of Status Symbols .....................................................................................

B-13

B-5

8XC196NP and 80C196NU Pin Status .....................................................................

B-13

C-1

Modules and Related Registers ..................................................................................

C-1

C-2

Register Name, Address, and Reset Status................................................................

C-2

C-3

ACC_0x Addresses and Reset Values........................................................................

C-5

C-4

Effect of SME and FME Bit Combinations...................................................................

C-7

C-5

ADDRCOMx Addresses and Reset Values.................................................................

C-8

C-6

ADDRMSKx Addresses and Reset Values .................................................................

C-9

C-7

BUSCONx Addresses and Reset Values..................................................................

C-10

C-8

EPAx_CON Addresses and Reset Values ................................................................

C-23

C-9

EPAx_TIME Addresses and Reset Values................................................................

C-24

C-10

Px_DIR Addresses and Reset Values.......................................................................

C-30

C-11

Px_MODE Addresses and Reset Values ..................................................................

C-31

C-12 Special-function Signals for Ports 1–4.......................................................................

C-31

C-13

Px_PIN Addresses and Reset Values.......................................................................

C-32

C-14

Px_REG Addresses and Reset Values .....................................................................

C-33

C-15

PWMx_CONTROL Addresses and Reset Values .....................................................

C-38

C-16

SP_BAUD Values When Using the Internal Clock at 25 MHz...................................

C-43

C-17

TIMERx Addresses and Reset Values ......................................................................

C-48

C-18 WSR Settings and Direct Addresses for Windowable SFRs.....................................

C-49

C-19

WSR1 Settings and Direct Addresses for Windowable SFRs...................................

C-52

xvi

1

Guide to This Manual

CHAPTER 1

GUIDE TO THIS MANUAL

This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you complete your design.

1.1MANUAL CONTENTS

This manual contains several chapters and appendixes, a glossary, and an index. This chapter, Chapter 1, provides an overview of the manual. This section summarizes the contents of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions and terminology used throughout the manual, provides references to related documentation, describes customer support services, and explains how to access information and assistance.

Chapter 2 — Architectural Overview — provides an overview of the device hardware. It describes the core, internal timing, internal peripherals, and special operating modes.

Chapter 3 — Advanced Math Features — describes the advanced mathematical features of the 80C196NU. The 80C196NU is the first member of the MCS® 96 microcontroller family to incorporate enhanced 16-bit multiplication instructions for performing multiply-accumulate operations and a dedicated, 32-bit accumulator register for storing the results of these operations. The accumulator and the enhanced instructions combine to decrease the amount of time required to perform multiply-accumulate operations. The instructions and accumulator support signed and unsigned integers as well as signed fractional data.

Chapter 4 — Programming Considerations — provides an overview of the instruction set, describes general standards and conventions, and defines the operand types and addressing modes supported by the MCS® 96 microcontroller family. (For additional information about the instruction set, see Appendix A.)

Chapter 5 — Memory Partitions — describes the addressable memory space of the device. It describes the memory partitions, explains how to use windows to increase the amount of memory that can be accessed with direct addressing, and provides examples of memory configurations.

Chapter 6 — Standard and PTS Interrupts — describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It also explains interrupt programming and control.

Chapter 7 — I/O Ports — describes the input/output ports and explains how to configure the ports for input, output, or special functions.

1-1

8XC196NP, 80C196NU USER’S MANUAL

Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO) port and explains how to program it.

Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width modulator (PWM) modules, describes how to program them, and provides sample circuitry for converting the PWM outputs to analog signals.

Chapter 10 — Event Processor Array (EPA) — describes the event processor array, a tim- er/counter-based, high-speed input/output unit. It describes the timer/counters and explains how to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs.

Chapter 11 — Minimum Hardware Considerations — describes options for providing the basic requirements for device operation within a system, discusses other hardware considerations, and describes device reset options.

Chapter 12 — Special Operating Modes — provides an overview of the idle, powerdown, standby, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode.

Chapter 13 — Interfacing with External Memory — lists the external memory signals and describes the registers that control the external memory interface. It discusses the chip selects, multiplexed and demultiplexed bus modes, bus width and memory configurations, the bus-hold protocol, write-control modes, and internal wait states and ready control. Finally, it provides timing information for the system bus.

Appendix A — Instruction Set Reference — provides reference information for the instruction set. It describes each instruction; defines the processor status word (PSW) flags; shows the relationships between instructions and PSW flags; and lists hexadecimal opcodes, instruction lengths, and execution times. (For additional information about the instruction set, see Chapter 4, “Programming Considerations.”)

Appendix B — Signal Descriptions — provides reference information for the device pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments.

Appendix C — Registers — provides a compilation of all device special-function registers (SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the windowed direct addresses for all SFRs in each possible window.

Glossary — defines terms with special meaning used throughout this manual.

Index — lists key topics with page number references.

1-2

GUIDE TO THIS MANUAL

1.2NOTATIONAL CONVENTIONS AND TERMINOLOGY

The following notations and terminology are used throughout this manual. The Glossary defines other terms with special meanings.

#

The pound symbol (#) has either of two meanings, depending on the

 

context. When used with a signal name, the symbol means that the

 

signal is active low. When used in an instruction, the symbol prefixes

 

an immediate value in immediate addressing mode.

addresses

In this manual, both internal and external addresses use the number

 

of hexadecimal digits that correspond with the number of available

 

address lines. For example, the highest possible internal address is

 

shown as FFFFFFH, while the highest possible external address is

 

shown as FFFFFH. When writing code, use the appropriate address

 

conventions for the software tool you are using. (In general,

 

assemblers require a zero preceding an alphabetic hexadecimal

 

character and an “H” following any hexadecimal value, so FFFFFFH

 

must be written as 0FFFFFFH. ANSI ‘C’ compilers require a zero

 

plus an “x” preceding a hexadecimal value, so FFFFFFH must be

 

written as 0xFFFFFF.) Consult the manual for your assembler or

 

compiler to determine its specific requirements.

assert and deassert

The terms assert and deassert refer to the act of making a signal

 

active (enabled) and inactive (disabled), respectively. The active

 

polarity (low or high) is defined by the signal name. Active-low

 

signals are designated by a pound symbol (#) suffix; active-high

 

signals have no suffix. To assert RD# is to drive it low; to assert ALE

 

is to drive it high; to deassert RD# is to drive it high; to deassert ALE

 

is to drive it low.

clear and set

The terms clear and set refer to the value of a bit or the act of giving

 

it a value. If a bit is clear, its value is “0”; clearing a bit gives it a “0”

 

value. If a bit is set, its value is “1”; setting a bit gives it a “1” value.

f

Lowercase “f” represents the internal operating frequency. See

 

“Internal Timing” on page 2-7 for details.

instructions

Instruction mnemonics are shown in upper case to avoid confusion.

 

In general, you may use either upper case or lower case when

 

programming. Consult the manual for your assembler or compiler to

 

determine its specific requirements.

1-3

8XC196NP, 80C196NU USER’S MANUAL

italics

Italics identify variables and introduce new terminology. The context

 

in which italics are used distinguishes between the two possible

 

meanings.

 

Variables in registers and signal names are commonly represented by

 

x and y, where x represents the first variable and y represents the

 

second variable. For example, in register Px_MODE.y, x represents

 

the variable that identifies the specific port associated with the

 

register, and y represents the register bit variable (7:0 or 15:0).

 

Variables must be replaced with the correct values when configuring

 

or programming registers or identifying signals.

numbers

Hexadecimal numbers are represented by a string of hexadecimal

 

digits followed by the character H. Decimal and binary numbers are

 

represented by their customary notations. (That is, 255 is a decimal

 

number and 1111 1111 is a binary number. In some cases, the letter B

 

is appended to binary numbers for clarity.)

register bits

Bit locations are indexed by 7:0 (or 15:0), where bit 0 is the least-

 

significant bit and bit 7 (or 15) is the most-significant bit. An

 

individual bit is represented by the register name, followed by a

 

period and the bit number. For example, WSR.7 is bit 7 of the

 

window selection register. In some discussions, bit names are used.

register names

Register mnemonics are shown in upper case. For example, TIMER2

 

is the timer 2 register; timer 2 is the timer. A register name containing

 

a lowercase italic character represents more than one register. For

 

example, the x in Px_REG indicates that the register name refers to

 

any of the port data registers.

reserved bits

Certain bits are described as reserved bits. In illustrations, reserved

 

bits are indicated with a dash (—). These bits are not used in this

 

device, but they may be used in future implementations. To help

 

ensure that a current software design is compatible with future imple-

 

mentations, reserved bits should be cleared (given a value of “0”) or

 

left in their default states, unless otherwise noted. Do not rely on the

 

values of reserved bits; consider them undefined.

signal names

Signal names are shown in upper case. When several signals share a

 

common name, an individual signal is represented by the signal name

 

followed by a number. For example, the EPA signals are named

 

EPA0, EPA1, EPA2, etc. Port pins are represented by the port abbre-

 

viation, a period, and the pin number (e.g., P1.0, P1.1); a range of

 

pins is represented by Px.y:z (e.g., P1.4:0 represents five port pins:

 

P1.4, P1.3, P1.2, P1.1, P1.0). A pound symbol (#) appended to a

 

signal name identifies an active-low signal.

1-4

 

 

 

 

 

 

 

 

 

 

 

 

 

GUIDE TO THIS MANUAL

t

Lowercase “t” represents the internal operating period. See “Internal

 

Timing” on page 2-7 for details.

 

units of measure

The following abbreviations are used to represent units of measure:

 

A

amps, amperes

 

 

DCV

direct current volts

 

 

Kbytes

kilobytes

 

 

kHz

kilohertz

 

 

kΩ

kilo-ohms

 

 

mA

milliamps, milliamperes

 

 

Mbytes

megabytes

 

 

MHz

megahertz

 

 

ms

milliseconds

 

 

mW

milliwatts

 

 

ns

nanoseconds

 

 

pF

picofarads

 

 

W

watts

 

 

V

volts

 

 

μA

microamps, microamperes

 

 

μF

microfarads

 

 

μs

microseconds

 

 

μW

microwatts

 

X

Uppercase X (no italics) represents

an unknown value or an

 

irrelevant (“don’t care”) state or condition. The value may be either

 

binary

or hexadecimal, depending on

the context. For example,

2XAFH (hex) indicates that bits 11:8 are unknown; 10XXB (binary) indicates that the two least-significant bits are unknown.

1.3RELATED DOCUMENTS

The tables in this section list additional documents that you may find useful in designing systems incorporating MCS 96 microcontrollers. These are not comprehensive lists, but are a representative sample of relevant documents. For a complete list of available printed documents, please order the literature catalog (order number 210621). To order documents, please call the Intel literature center for your area (telephone numbers are listed on page 1-11).

Intel’s ApBUILDER software, hypertext manuals and datasheets, and electronic versions of application notes and code examples are also available from the BBS (see “Bulletin Board System (BBS)” on page 1-9). New information is available first from FaxBack and the BBS. Refer to “Electronic Support Systems” on page 1-8 for details.

1-5

8XC196NP, 80C196NU USER’S MANUAL

Table 1-1. Handbooks and Product Information

Title and Description

Order Number

 

 

Intel Embedded Quick Reference Guide

272439

Solutions for Embedded Applications Guide

240691

Data on Demand fact sheet

240952

Data on Demand annual subscription (6 issues; Windows* version)

240897

Complete set of Intel handbooks on CD-ROM.

 

Handbook Set — handbooks and product overview

231003

Complete set of Intel’s product line handbooks. Contains datasheets, application

 

notes, article reprints and other design information on microprocessors, periph-

 

erals, embedded controllers, memory components, single-board computers,

 

microcommunications, software development tools, and operating systems.

 

Automotive Products

231792

Application notes and article reprints on topics including the MCS 51 and MCS 96

 

microcontrollers. Documents in this handbook discuss hardware and software

 

implementations and present helpful design techniques.

 

Embedded Applications handbook (2 volume set)

270648

Datasheets, architecture descriptions, and application notes on topics including

 

flash memory devices, networking chips, and MCS 51 and MCS 96 microcon-

 

trollers. Documents in this handbook discuss hardware and software implementa-

 

tions and present helpful design techniques.

 

Embedded Microcontrollers

270646

Datasheets and architecture descriptions for Intel’s three industry-standard micro-

 

controllers, the MCS 48, MCS 51, and MCS 96 microcontrollers.

 

Peripheral Components

296467

Comprehensive information on Intel’s peripheral components, including

 

datasheets, application notes, and technical briefs.

 

Flash Memory (2 volume set)

210830

A collection of datasheets and application notes devoted to techniques and

 

information to help design semiconductor memory into an application or system.

 

Packaging

240800

Detailed information on the manufacturing, applications, and attributes of a variety

 

of semiconductor packages.

 

Development Tools Handbook

272326

Information on third-party hardware and software tools that support Intel’s

 

embedded microcontrollers.

 

Included in handbook set (order number 231003)

 

Table 1-2. Application Notes, Application Briefs, and Article Reprints

 

Title

Order Number

 

 

AB-71, Using the SIO on the 8XC196MH (application brief)

272594

AP-125, Design Microcontroller Systems for Electrically Noisy Environments †††

210313

AP-155, Oscillators for Microcontrollers †††

230659

AR-375, Motor Controllers Take the Single-Chip Route (article reprint)

270056

AP-406, MCS®96 Analog Acquisition Primer †††

270365

Included in Automotive Products handbook (order number 231792)

 

††

Included in Embedded Applications handbook (order number 270648)

 

†††

Included in Automotive Products and Embedded Applications handbooks

 

1-6

 

GUIDE TO THIS MANUAL

 

Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)

 

 

 

 

Title

Order Number

 

 

AP-445, 8XC196KR Peripherals: A User’s Point of View

270873

AP-449, A Comparison of the Event Processor Array (EPA) and High Speed

270968

 

Input/Output (HSIO) Unit

 

AP-475, Using the 8XC196NT ††

272315

AP-477, Low Voltage Embedded Design ††

272324

AP-483, Application Examples Using the 8XC196MC/MD Microcontroller

272282

AP-700, Intel Fuzzy Logic Tool Simplifies ABS Design

272595

AP-711, EMI Design Techniques for Microcontrollers in Automotive Applications

272324

AP-715, Interfacing an I2C Serial EEPROM to an MCS®96 Microcontroller

272680

Included in Automotive Products handbook (order number 231792)

 

††

Included in Embedded Applications handbook (order number 270648)

 

†††

Included in Automotive Products and Embedded Applications handbooks

 

 

Table 1-3. MCS® 96 Microcontroller Datasheets (Commercial/Express)

 

Title

Order Number

 

 

8XC196KR/KQ/JR/JQ Commercial/Express CHMOS Microcontroller

270912

8XC196KT Commercial CHMOS Microcontroller

272266

87C196KT/87C196KS 20 MHz Advanced 16-Bit CHMOS Microcontroller

272513

8XC196MC Industrial Motor Control Microcontroller

272323

87C196MD Industrial Motor Control CHMOS Microcontroller

270946

8XC196NP Commercial CHMOS 16-Bit Microcontroller

272459

8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space

272267

80C196NU Commercial CHMOS 16-Bit Microcontroller

272644

Included in Embedded Microcontrollers handbook (order number 270646)

 

Table 1-4. MCS® 96 Microcontroller Datasheets (Automotive)

Title and Description

Order Number

 

 

87C196CA/87C196CB 20 MHz Advanced 16-Bit CHMOS Microcontroller with

272405

Integrated CAN 2.0

 

87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller

272529

87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller

272580

87C196KR/KQ, 87C196JV/JT, 87C196JR/JQ Advanced 16-Bit CHMOS

270827

Microcontroller

 

87C196KT/87C196KS Advanced 16-Bit CHMOS Microcontroller

270999

87C196KT/KS 20 MHz Advanced 16-Bit CHMOS Microcontroller

272513

Included in Automotive Products handbook (order number 231792)

 

1-7

8XC196NP, 80C196NU USER’S MANUAL

Table 1-5. MCS® 96 Microcontroller Quick References

Title and Description

Order Number

 

 

8XC196KR Quick Reference (includes the JQ, JR, KQ, KR)

272113

8XC196KT Quick Reference

272269

8XC196MC Quick Reference

272114

8XC196NP Quick Reference

272466

8XC196NT Quick Reference

272270

1-8

GUIDE TO THIS MANUAL

Page Intentionally Left Blank

1-9

8XC196NP, 80C196NU USER’S MANUAL

Page Intentionally Left Blank

1-10

GUIDE TO THIS MANUAL

1.4.4World Wide Web

We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Select “Embedded Design Products” from the Intel home page.

1.5TECHNICAL SUPPORT

In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S. and Canada, please contact your local distributor.

1-800-628-8686

U.S. and Canada

916-356-7599

U.S. and Canada

916-356-6100 (fax)

U.S. and Canada

1.6PRODUCT LITERATURE

You can order product literature from the following Intel literature centers.

1-800-468-8118, ext. 283

U.S. and Canada

708-296-9333

U.S. (from overseas)

44(0)1793-431155

Europe (U.K.)

44(0)1793-421333

Germany

44(0)1793-421777

France

81(0)120-47-88-32

Japan (fax only)

1-11

2

Architectural

Overview

CHAPTER 2

ARCHITECTURAL OVERVIEW

The 16-bit 8XC196NP and 80C196NU CHMOS microcontrollers are designed to handle highspeed calculations and fast input/output (I/O) operations. They share a common architecture and instruction set with other members of the MCS® 96 microcontroller family. In addition to their 16-bit address/data buses, both microcontrollers have extended addressing ports consisting of 4 external address pins, for a total of 20 address pins. With 20 address pins, these microcontrollers can access up to 1 Mbyte of linear address space. Both devices also have chip-select units that provide a glueless interface to external memory devices. The extended addressing port and chipselect unit enable these microcontrollers to handle larger, more complex programs and to access more external memory at a faster rate than could earlier MCS 96 microcontrollers.

The 8XC196NP and 80C196NU are pin-compatible and have identical cores. However, the 80C196NU can operate at twice the frequency of the 8XC196NP. The 80C196NU also employs an accumulator and enhanced multiplication instructions to support multiply-accumulate operations. The 80C196NU is the first MCS 96 microcontroller with this capability. This chapter provides a high-level overview of the architecture.

2.1TYPICAL APPLICATIONS

MCS 96 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. Automotive customers use MCS 96 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS).

2-1

8XC196NP, 80C196NU USER’S MANUAL

2.2DEVICE FEATURES

Table 2-1 lists the features of the 8XC196NP and 80C196NU.

Table 2-1. Features of the 8XC196NP and 80C196NU

 

 

ROM

Register

I/O Pins

EPA

SIO

PWM

Chip-

External

Device

Pins

RAM

select

Interrupt

(Note 1)

(Note 3)

Pins

Ports

Channels

 

 

(Note 2)

Pins

Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8XC196NP

100

4 K

1024

64

4

1

3

6

4

 

 

 

 

 

 

 

 

 

 

80C196NU

100

0

1024

64

4

1

3

6

4

 

 

 

 

 

 

 

 

 

 

NOTES:

1.Nonvolatile memory is optional for the 8XC196NP, but is not available for the 80C196NU. The second character of the device name indicates the presence and type of nonvolatile memory. 80C196NP = none; 83C196NP = ROM.

2.Register RAM amounts include the 24 bytes allocated to core special-function registers (SFRs) and the stack pointer.

3.I/O pins include address, data, and bus control pins and 32 I/O port pins.

2.3BLOCK DIAGRAM

Figure 2-1 shows the major blocks within the device. The core of the device (Figure 2-2) consists of the central processing unit (CPU) and memory controller. The CPU contains the register file and the register arithmetic-logic unit (RALU). The CPU connects to both the memory controller and an interrupt controller via a 16-bit internal bus. An extension of this bus connects the CPU to the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from the memory controller to the instruction register in the RALU.

Core

 

Optional

 

Interrupt

 

ROM

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock and

 

 

PTS

Power Mgmt.

I/O

SIO

PWM

EPA

A2801-01

Figure 2-1. 8XC196NP and 80C196NU Block Diagram

2-2

ARCHITECTURAL OVERVIEW

 

 

CPU

 

 

Memory Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

Register File

 

 

 

 

RALU

 

 

Prefetch Queue

 

 

 

 

 

 

 

Microcode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Engine

 

 

 

Slave PC

 

 

Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALU

 

 

 

Address Register

 

 

RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master PC

 

 

 

Data Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSW

 

 

 

 

 

 

CPU SFRs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Registers

 

 

 

Bus Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2797-01

Figure 2-2. Block Diagram of the Core

2.3.1CPU Control

The CPU is controlled by the microcode engine, which instructs the RALU to perform operations using bytes, words, or double words from either the 256-byte lower register file or through a window that directly accesses the upper register file. (See Chapter 5, “Me mory Partitions,” for more information about the register file and windowing.) CPU instructions move from the 4-byte (for the 8XC196NP) or 8-byte (for the 80C196NU) prefetch queue in the memory controller into the RALU’s instruction register. The microcode engine decodes the instructions and then generates the sequence of events that cause desired functions to occur.

2.3.2Register File

The register file is divided into an upper and a lower file. In the lower register file, the lowest 24 bytes are allocated to the CPU’s special-function registers (SFRs) and the stack pointer, while the remainder is available as general-purpose register RAM. The upper register file contains only general-purpose register RAM. The register RAM can be accessed as bytes, words, or doublewords.

The RALU accesses the upper and lower register files differently. The lower register file is always directly accessible with direct addressing (see “Addressing Modes” on page 4-6). The upper register file is accessible with direct addressing only when windowing is enabled. Windowing is a technique that maps blocks of the upper register file into a window in the lower register file. See Chapter 5, “Memory Partitions,” for more information about the register file and windowing.

2-3

8XC196NP, 80C196NU USER’S MANUAL

2.3.3Register Arithmetic-logic Unit (RALU)

The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master program counter (PC), the processor status word (PSW), and several registers. The registers in the RALU are the instruction register, a constants register, a bit-select register, a loop counter, and three temporary registers (the upper-word, lower-word, and second-operand registers).

The 24-bit master program counter (PC) provides a linear, nonsegmented 16-Mbyte memory space. Only 20 of the address lines are implemented with external pins, so you can physically address only 1 Mbyte. (For compatibility with earlier devices, the PC can be configured as 16 bits wide.) The master PC contains the address of the next instruction and has a built-in incrementer that automatically loads the next sequential address. However, if a jump, interrupt, call, or return changes the address sequence, the ALU loads the appropriate address into the master PC.

The PSW contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of your program. Appendix A, “Ins truction Set Reference,” provides a detailed description of the PSW.

All registers, except the 3-bit bit-select register and the 6-bit loop counter, are either 16 or 17 bits (16 bits plus a sign extension). Some of these registers can reduce the ALU’s workload by performing simple operations.

The RALU uses the upperand lower-word registers together for the 32-bit instructions and as temporary registers for many instructions. These registers have their own shift logic and are used for operations that require logical shifts, including normalize, multiply, and divide operations. The six-bit loop counter counts repetitive shifts. The second-operand register stores the second operand for two-operand instructions, including the multiplier during multiply operations and the divisor during divide operations. During subtraction operations, the output of this register is complemented before it is moved into the ALU.

The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register so that they are readily available when complementing, incrementing, or decrementing bytes or words. In addition, the constants register generates single-bit masks, based on the bit-select register, for bit-test instructions.

2.3.3.1Code Execution

The RALU performs most calculations for the device, but it does not use an accumulator. Instead it operates directly on the lower register file, which essentially provides 256 accumulators. Because data does not flow through a single accumulator, the device’s code executes faster and more efficiently.

2-4

ARCHITECTURAL OVERVIEW

2.3.3.2Instruction Format

MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand instruction format. This format allows a single instruction to specify two source registers and a separate destination register. For example, the following instruction multiplies two 16-bit variables and stores the 32-bit result in a third variable.

MUL RESULT, FACTOR_1, FACTOR_2

;multiply FACTOR_1 and FACTOR_2

 

;and store answer in RESULT

 

;(RESULT)(FACTOR_1 × FACTOR_2)

An 80C186 device requires four instructions to accomplish the same operation. The following example shows the equivalent code for an 80C186 device.

MOV

AX, FACTOR_1

;move FACTOR_1 into accumulator (AX)

 

 

;(AX)FACTOR1

MUL

FACTOR_2

;multiply FACTOR_2 and AX

 

 

;(DX:AX)(AX)×(FACTOR_2)

MOV

RESULT, AX

;move lower byte into RESULT

 

 

;(RESULT)(AX)

MOV

RESULT+2, DX

;move upper byte into RESULT+2

 

 

;(RESULT+2)(DX)

2.3.4Memory Controller

The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory controller except when windowing is used; see Chapter 5, “Memory Partitions,”) The memory controller contains the prefetch queue, the slave program counter (slave PC), address and data registers, and the bus controller.

The bus controller drives the memory bus, which consists of an internal memory bus and the external address/data bus. The bus controller receives memory-access requests from either the RALU or the prefetch queue; queue requests always have priority. This queue is transparent to the RALU and your software.

NOTE

When using a logic analyzer to debug code, remember that instructions are preloaded into the prefetch queue and are not necessarily executed immediately after they are fetched.

When the bus controller receives a request from the queue, it fetches the code from the address contained in the slave PC. The slave PC increases execution speed because the next instruction byte is available immediately and the processor need not wait for the master PC to send the address to the memory controller. If a jump, interrupt, call, or return changes the address sequence, the master PC loads the new address into the slave PC, then the CPU flushes the queue and continues processing.

2-5

8XC196NP, 80C196NU USER’S MANUAL

The extended program counter (EPC) is an extension of the slave PC. The EPC generates the upper eight address bits for extended code fetches and outputs them on the extended addressing port (EPORT). Because only four EPORT pins are implemented, only the lower four address bits are available. (See Chapter 5, “Memory Partitions,” for additional i nformation.)

The memory controller includes a chip-select unit with six chip-select outputs for selecting an external device during an external bus cycle. During an external memory access, a chip-select output is asserted if the address falls within the address range assigned to that chip-select. The bus width, the number of wait states, and multiplexed or demultiplexed address/data lines are programmed independently for the six chip-selects. The address range of the chip-selects can be programmed for various granularities: 256 bytes, 512 bytes, … 512 Kbytes, or 1 Mbyte. The base address can be any address that is evenly divisible by the selected address range. See Chapter 13, “Interfacing with External Me mory,” for more information.

2.3.5Multiply-accumulate (80C196NU Only)

The 80C196NU is able to process multiply-accumulate operations through the use of a hardware accumulator and enhanced multiplication instructions. The accumulator includes a 16-bit adder, a 3-to-1 multiplexer, a 32-bit accumulator register, and a control register. The multiply-accumu- late function is enabled by any 16-bit multiplication instruction with a destination address that is in the range 00–0FH. The instructions can operate on signed integers, unsigned integers, and signed fractional numbers. The control register allows you to enable saturation mode and fractional mode for signed multiplication. Chapter 3, “Advanced Math Features,” describes the accumulator.

2.3.6Interrupt Service

The device’s flexible interrupt-handling system has two main components: the programmable interrupt controller and the peripheral transaction server (PTS). The programmable interrupt controller has a hardware priority scheme that can be modified by your software. Interrupts that go through the interrupt controller are serviced by interrupt service routines that you provide. The peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides highspeed, low-overhead interrupt handling. You can configure most interrupts (except NMI, trap, and unimplemented opcode) to be serviced by the PTS instead of the interrupt controller.

The PTS can transfer bytes or words, either individually or in blocks, between any memory locations and can generate pulse-width modulated (PWM) signals. PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines. See Chapter 6, “Standard and PTS Interrupts,” for more information.

2-6

ARCHITECTURAL OVERVIEW

2.4INTERNAL TIMING

The clock circuitry of the 8XC196NP (Figure 2-3) is identical to that of earlier MCS 96 microcontrollers. It receives an input clock signal on XTAL1 provided by an external crystal or clock and divides the frequency by two. The clock generators accept the divided input frequency from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high.

Disable Clock Input

(Powerdown)

 

 

FXTAL1

 

 

 

 

 

 

 

 

 

XTAL1

 

Divide-by-two

 

 

 

 

 

 

 

 

 

 

 

Circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable Clocks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL2

 

 

 

 

 

 

 

 

 

(Powerdown)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral Clocks (PH1, PH2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT

 

 

 

 

Disable

Generators

 

 

 

 

 

 

 

 

 

 

Oscillator

 

 

 

 

 

 

 

CPU Clocks (PH1, PH2)

 

 

 

 

 

 

 

 

 

 

(Powerdown)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable Clocks

 

 

 

 

 

 

 

 

 

(Idle, Powerdown)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3161-01

Figure 2-3. Clock Circuitry (8XC196NP)

The 80C196NU’s clock ci rcuitry (Figure 2-4) implements phase-locked loop and clock multiplier circuitry, which can substantially increase the CPU clock rate while using a lower-frequency input clock. The clock circuitry accepts an input clock signal on XTAL1 provided by an external crystal or oscillator. Depending on the values of the PLLEN1 and PLLEN2 pins, this frequency is routed either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. The multiplier circuitry can double or quadruple the input frequency (FXTAL1) before the frequency (f) reaches the divide-by-two circuitry. The clock generators accept the divided input frequency (f/2) from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high.

NOTE

For brevity, this manual uses lowercase “f” to represent the internal clock frequency of both the 8XC196NP and the 80C196NU. For the 8XC196NP, f is

equal to FXTAL1. For the 80C196NU, f is equal to either FXTAL1, 2FXTAL1, or 4FXTAL1, depending on the clock multiplier mode, which is controlled by the

PLLEN1 and PLLEN2 input pins.

2-7

8XC196NP, 80C196NU USER’S MANUAL

 

 

 

 

 

 

Disable

 

 

 

 

 

 

PLL

 

 

 

 

 

 

 

(Powerdown)

 

 

 

 

XTAL1

FXTAL1

 

 

 

 

Phase

Filter

 

 

 

 

 

Comparator

 

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

F

XTAL1

 

 

 

Phase-

 

 

 

 

 

 

 

XTAL2

 

 

 

 

locked

 

 

 

 

 

Oscillator

 

 

 

2F

 

 

 

 

 

 

Disable

XTAL1

Disable Clock Input

Phase-locked Loop

 

Oscillator

(Powerdown)

 

 

 

Clock Multiplier

 

 

4F

 

 

 

(Powerdown)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f Divide-by-two

 

 

 

 

 

 

Circuit

 

 

 

 

PLLEN1

 

f

 

Disable Clocks

 

 

 

2

(Standby, Powerdown)

 

 

PLLEN2

 

 

 

 

Peripheral Clocks (PH1, PH2)

 

 

 

 

 

 

 

 

 

Clock

 

CLKOUT

 

 

 

 

Generators

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU Clocks (PH1, PH2)

 

 

 

 

 

Disable Clocks

 

 

 

 

 

(Idle, Standby, Powerdown)

 

 

 

 

 

 

 

 

A3063-02

 

Figure 2-4.

Clock Circuitry (80C196NU)

 

For both the 8XC196NP and 80C196NU, the rising edges of PH1 and PH2 generate CLKOUT (Figure 2-5). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibility in power management. (“Reducing Power Consumption” on page 12-3 describes the power management modes.) It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay varies with temperature and voltage.

2-8

ARCHITECTURAL OVERVIEW

XTAL1

t

t

1 State Time 1 State Time

PH1

PH2

CLKOUT

Phase 1

Phase 2

Phase 1

Phase 2

A0805-01

Figure 2-5. Internal Clock Phases

The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies.

Table 2-2. State Times at Various Frequencies

f

(Frequency Input to the State Time Divide-by-two Circuit)

12.5 MHz

160 ns

25 MHz

80 ns

 

 

50 MHz

40 ns

The following formulas calculate the frequency of PH1 and PH2, the duration of a state time, and the duration of a clock period (t).

f

PH2

2

1

PH1 (in MHz) = -- =

State Time (in µs) = --

t = --

2

 

f

f

Because the device can operate at many frequencies, this manual defines time requirements (such as instruction execution times) in terms of state times rather than specific measurements. Datasheets list AC characteristics in terms of clock periods (t).

For the 80C196NU, Table 2-3 details the relationships between the input frequency (FXTAL1), the configuration of PLLEN1 and PLLEN2, the operating frequency (f), the clock period (t), and state times. Figure 2-6 illustrates the timing relationships between the input frequency (FXTAL1), the operating frequency (f), and the CLKOUT signal with each of the three valid PLLENx pin configurations. (Since the maximum operating frequency is 50 MHz, only a 12.5 MHz external clock frequency allows all three clock modes.)

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8XC196NP, 80C196NU USER’S MANUAL

Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times

FXTAL1

PLLEN2:1

Multiplier

f

t

State Time

(Frequency

(Input Frequency to

(Clock

on XTAL1)

 

 

the Divide-by-two Circuit)

Period)

 

 

 

 

 

 

 

50 MHz

00

1

50 MHz

20 ns

40 ns

25 MHz

00

1

25 MHz

40 ns

80 ns

10

2

50 MHz

20 ns

40 ns

 

 

00

1

12.5 MHz

80 ns

160 ns

12.5 MHz

10

2

25 MHz

40 ns

80 ns

 

11

4

50 MHz

20 ns

40 ns

Assumes an external clock. The maximum frequency for an external crystal oscillator is 25 MHz.

 

TXHCH

XTAL1

 

(12.5 MHz)

 

f

 

PLLEN2:1=00

t = 80ns

CLKOUT

 

f

 

PLLEN2:1=10

t = 40ns

CLKOUT

 

f

 

PLLEN2:1=11

t = 20ns

 

CLKOUT

 

 

A3160-01

Figure 2-6. Effect of Clock Mode on CLKOUT Frequency

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ARCHITECTURAL OVERVIEW

2.5INTERNAL PERIPHERALS

The internal peripheral modules provide special functions for a variety of applications. This section provides a brief description of the peripherals; subsequent chapters describe them in detail.

2.5.1I/O Ports

The 8XC196NP and 80C196NU have five I/O ports, ports 1–4 and the EPORT. Individual port pins are multiplexed to serve as standard I/O or to carry special-function signals associated with an on-chip peripheral or an off-chip component. If a particular special-function signal is not used in an application, the associated pin can be individually configured to serve as a standard I/O pin. Port 4 has a higher drive capability than the other ports to support pulse-width modulator (PWM) high-drive outputs.

Ports 1–4 are eight-bit, bidirectional, standard I/O ports. Only the lower nibble of port 4 is implemented in current package offerings. Port 1 provides I/O pins for the four event processor array (EPA) modules and the two timers. Port 2 is used for the serial I/O (SIO) port, two external interrupts, and bus hold functions. Port 3 is used for chip-select functions and two external interrupts. Port 4 (functionally only a 4-bit port) provides I/O pins associated with the three on-chip pulsewidth modulators. The EPORT provides address lines A19:16 to support extended addressing. See Chapter 7, “I/O Ports,” for more i nformation.

2.5.2Serial I/O (SIO) Port

The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchronous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three asynchronous modes (modes 1, 2, and 3) for both transmission and reception. The asynchronous modes are full duplex, meaning that they can transmit and receive data simultaneously. The receiver is buffered, so the reception of a second byte can begin before the first byte is read. The transmitter is also buffered, allowing continuous transmissions. See Chapter 8, “Serial I/O (SIO) Port,” for details.

2.5.3Event Processor Array (EPA) and Timer/Counters

The event processor array (EPA) performs high-speed input and output functions associated with its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an event occurs, the EPA records the timer value associated with it. This is a capture event. In the output mode, the EPA monitors a timer until its value matches that of a stored time value. When a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin. This is a compare event. Both capture and compare events can initiate interrupts, which can be serviced by either the interrupt controller or the PTS.

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8XC196NP, 80C196NU USER’S MANUAL

Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or externally. Each timer/counter is called a timer if it is clocked internally and a counter if it is clocked externally. See Chapter 10, “Event Processor Array (EPA),” for additional information on the EPA and timer/counters.

2.5.4Pulse-width Modulator (PWM)

The output waveform from each PWM channel is a variable duty-cycle pulse with a programmable frequency that occurs every 256 or 512 state times (for the 8XC196NP) or every 256, 512, or 1024 state times (for the 80C196NU), as programmed. Several types of motors require a PWM waveform for most efficient operation. When filtered, the PWM waveform produces a DC level that can change in 256 steps by varying the duty cycle. See Chapter 9, “Pulse-width Modulator,” for more information.

2.6SPECIAL OPERATING MODES

In addition to the normal execution mode, the device operates in several special-purpose modes. Idle and powerdown modes conserve power when the device is inactive. An additional power conservation mode, standby, is available on the 80C196NU. On-circuit emulation (ONCE) mode electrically isolates the microcontroller from the system. See Chapter 12, “Special Operating Modes,” for more information about idle, powerdown, standby, and ONCE modes.

2.6.1Reducing Power Consumption

The power saving modes selectively disable internal clocks to reduce power consumption. Figure 2-3 on page 2-7 and Figure 2-4 on page 2-8 illustrate the clock circuitry of the 8XC196NP and 80C196NU, respectively.

In idle mode, the CPU stops executing instructions, but the peripheral clocks remain active. Power consumption drops to about 40% of normal execution mode consumption. Either a hardware reset or any enabled interrupt source will bring the device out of idle mode.

The 80C196NU has an additional power saving mode, standby. In standby mode, all internal clocks are frozen at logic state zero, but the oscillator and phase-locked loop continue to run. Power consumption drops to about 10% of normal execution mode consumption. Either a hardware reset or any enabled external interrupt source will bring the device out of standby mode.

In powerdown mode, all internal clocks are frozen at logic state zero and the oscillator is shut off. The register file and most peripherals retain their data if VCC is maintained. Power consumption drops into the µW range.

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ARCHITECTURAL OVERVIEW

2.6.2Testing the Printed Circuit Board

The on-circuit emulation (ONCE) mode electrically isolates the 8XC196 device from the system. By invoking ONCE mode, you can test the printed circuit board while the device is soldered onto the board.

2.7DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS

This section summarizes differences to consider when converting your design requirements from the 80C196NP to the 80C196NU.

The 80C196NU can achieve an operating frequency of 50 MHz, while the 80C196NP can achieve only 25 MHz.

The 80C196NU is pin-compatible with the 80C196NP. The functions of four pins differ:

— the 80C196NU has PLLEN1 in place of a no-connection pin of the 80C196NP

the 80C196NU has PLLEN2 in place of a V SS pin of the 80C196NP

the 80C196NU has a V CC pin in place of a no-connection pin of the 80C196NP

the 80C196NU has a no-connection pin in place of the EA# pin of the 80C196NP

The 80C196NU requires that you tie the PLLEN1 and PLLEN2 pins either high or low, depending on the clock multiplier mode you select.

The 80C196NU requires that you connect an external capacitor to the RPD pin if your design uses both powerdown mode and a clock multiplier mode.

The 80C196NU has a new, 32-bit accumulator register and an accumulator status register to support its multiply-accumulate functions.

The 80C196NU, since it has no nonvolatile memory, has no REMAP bit in the CCB.

The 80C196NU can window additional memory into the lower register file via a second window selection register (WSR1).

Unlike the 80C196NP, the 80C196NU’s EPORT special-function registers are located in SFR address space, rather than in memory-mapped space, so they can be windowed for direct access.

The 80C196NU has an 8-byte prefetch queue, while the 80C196NP has a 4-byte prefetch queue.

In the 80C196NU, data accesses have a higher priority than instruction queue fetches. In the 80C196NP, the opposite is true (instruction fetches have the highest priority).

The 80C196NU’s serial I/O port has a divide-by-2 prescaler, controlled by the SP_CON register.

The 80C196NU’s EPA has an a dditional prescaler option (divide-by-128), controlled by the timer control register (Tx_CONTROL).

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8XC196NP, 80C196NU USER’S MANUAL

The 80C196NU’s PWM has an additional prescaler option (divide-by-4), controlled by the PWM control register (CON_REG0).

When operating with a demultiplexed bus, the 80C196NU can add an automatic delay in the first cycle following a chip-select change or in a write cycle that follows a read. This mode, called deferred mode, extends the following timing specifications by two clock periods (2t):

TAVDV, TAVWL, TAVRL, TRLDV, TRHDZ, TRHRL, TLHLH, TRHLH, TSLDV, and TWHLH.

The 80C196NU has an additional power-saving mode, standby (IDLPD #3).

The 8XC196NP allows you to change the value of EP_REG to control which memory page a nonextended instruction accesses. However, software tools require that EP_REG be equal to 00H. The 80C196NU forces all nonextended data accesses to page 00H. You cannot use EP_REG to change pages.

After a HOLD request, the 80C196NU’s chip-select channels become inactive before the 80C196NU asserts HLDA#.

In demultiplexed mode, the 80C196NU’s RD# and WR# signals are asserted one clock period (1t) earlier than on the 80C196NP.

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3

Advanced Math

Features

CHAPTER 3

ADVANCED MATH FEATURES

The 80C196NU is the first member of the MCS® 96 microcontroller family to incorporate enhanced 16-bit multiplication instructions for performing multiply-accumulate operations and a dedicated, 32-bit accumulator register for storing the results of these operations. The accumulator and the enhanced instructions combine to decrease the amount of time required to perform mul- tiply-accumulate operations. The instructions and accumulator support signed and unsigned integers as well as signed fractional data. This chapter describes the 80C196NU’s advanced mathematical features.

3.1ENHANCED MULTIPLICATION INSTRUCTIONS

The 16-bit multiplication instructions, MULU and MUL, that exist for all MCS 96 microcontrollers have been enhanced for the 80C196NU. The MULU instruction supports unsigned integers, while the MUL instruction supports signed integers and signed fractionals.

When you execute a 16-bit multiplication instruction with a destination address that is 0FH or below, the 80C196NU automatically stores the result in the accumulator. If bit 3 of the destination address is set (address 08H, 09H, …, 0FH), the 80C196NU clears the accumulator before it stores the result of the current instruction. If bit 3 of the destination address is clear (address 00H, 01H, …, 07H), it adds the result of the current instruction to the existing contents of the accumulator.

This simple example illustrates the results of consecutive multiply-accumulate instructions. The results of the first three instructions are automatically added together in the accumulator, while the last instruction clears the accumulator before the result is stored.

register_1 = 10 decimal (0AH),register_2 = 20 decimal (14H) register_3 = 30 decimal (1EH),register_4 = 40 decimal (28H)

mul 00H,register_1,register_2 ;10×20= 200. Accumulator = 200 decimal. mul 00H,register_3,register_4 ;30×40=1200. Accumulator =1400 decimal. mul 00H,register_2,register_4 ;20×40= 800. Accumulator =2200 decimal. mul 08H,register_2,register_3 ;20×30= 600. Accumulator = 600 decimal.

Table 3-1 compares the instructions required to perform a multiply-accumulate operation for the 8XC196NP and those required for the 80C196NU. The 8XC196NP requires four instructions, while the 80C196NU requires only one to accomplish the same operation. The four 8XC196NP instructions take a total of 32 state times to execute, while the single 80C196NU instruction takes only 16 state times. In addition, the 80C196NU can operate at twice the frequency of the 8XC196NP; therefore, a state time for the 80C196NU is half that of the 8XC196NP. These two factors combine to make the 80C196NU code execute in one-fourth the time required for the 8XC196NP code.

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