Intel 80286, 80287 User Manual

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80286 AND 80287 PROGRAMMER'S REFERENCE MANUAL

1987

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CG·S/26/87

PREFACE

This manual describes the 80286, the most powerful 16-bit microprocessor in the 8086 family, and the 80287 Numeric Processor Extension (NPX).

ORGANIZATION OF THIS MANUAL

This manual is, essentially, two books in one. The first book describes the 80286, the second the 80287 NPX.

80286

The 80286 contains a table of contents, eleven chapters, four appendices, and an index. For more information on the 80286 book's organization, see its first chapter, Chapter 1, "Introduction to the 80286." Section 1.4 in that chapter explains the organization in detail.

80287 NPX

The 80287 NPX contains a preface, table of contents, four chapters, three appendices, and a glossary. For more information on the 80287 NPX book's organization, see its preface.

iii

TABLE OF CONTENTS

 

CHAPTER 1

 

Page

INTRODUCTION TO THE 80286

 

 

General Attributes ... ......................................................

.................................................

1-1

Modes of Operation ........................................................................

...............................

1-2

Advanced Features ........................................................................................................

 

1-2

Memory Management .................................................................................................

 

1-2

Task Management ......................................................................................................

 

1-3

Protection Mechanisms ..............................................................................................

 

1-3

Support for Operating Systems .................................................................................

 

1-4

Organization of This Book .............................................................................................

 

1-4

Related Publications .......................................................................

................................

1-6

CHAPTER 2

 

 

80286 BASE ARCHITECTURE

 

 

Memory Organization and Segmentation ......................................................................

 

2-1

Data Types ........................................................................................................

.............

2-1

Registers .........................................................................................................................

 

2-7

General Registers .......................................................................................................

 

2-7

Memory Segmentation and Segment Registers ..........

, .............................................

2-8

Index, Pointer, and Base Registers ...........................................................................

 

2-9

Status and Control Registers .....................................................................................

 

2-14

Addressing Modes .........................................................................................................

 

2-16

Operands .........................................................................................

...........................

2-16

Register and Immediate Modes ................................................................

.................

2-17

Memory Addressing Modes .......................................................................................

 

2-17

Segment Selection ....................................................................................

..............

2-18

Offset Computation .................................................................................................

 

2-19

Memory Mode .........................................................................................................

 

2-20

Input/Output ...................................................................................................................

 

2-21

I/O Address Space ...................................................................

..................................

2-23

Memory-Mapped I/O ..................................................................................................

 

2-23

Interrupts and Exceptions ..............................................................................................

 

2-24

Hierarchy of Instruction Sets .........................................................................................

 

2-25

CHAPTER 3

 

 

BASIC INSTRUCTION SET

 

 

Data Movement Instructions ..........................................................................................

 

3-1

General-Purpose Data Movement Instructions .........................................................

 

3-1

Stack Manipulation Instructions .................................................................................

 

3-2

Flag Operation with the Basic Instruction Set ...............................................................

 

3-4

Status Flags ................................................................................................................

 

3-4

Control Flags ...............................................................................................................

 

3-4

Arithmetic Instructions ...................................................................................................

 

3-5

Addition Instructions ...................................................................................................

 

3-7

Subtraction Instructions .............................................................................................

 

3-7

Multiplication Instructions ...........................................................................................

 

3-8

Division Instructions ...................................................................................................

 

3-9

Logical Instructions ........................................................................................................

 

3-9

Boolean Operation Instructions .................................................................................

 

3-9

Shift and Rotate Instructions ......................................................................................

 

3-10

Shift Instructions .....................................................................................................

 

3-10

v

TABLE OF CONTENTS

 

 

Page

Rotate Instructions ..................................................................................................

3-13

Type Conversion and No-Operation Instructions ......................................................

3-16

Test and Compare Instructions .....................................................................................

3-16

Control Transfer Instructions .........................................................................................

3-16

Unconditional Transfer Instructions ...........................................................................

3-17

Jump Instruction .....................................................................................................

3-17

Call Instruction ........................................................................................................

3-18

Return and Return from Interrupt Instruction ........................................................

3-19

Conditional Transfer Instructions ...............................................................................

3-19

Conditional Jump Instructions ................................................................................

3-20

Loop Instructions ....................................................................................................

3-20

Executing a Loop or Repeat Zero Times ...............................................................

3.-21

Software-Generated Interrupts ..................................................................................

3-21

Software Interrupt Instruction .................................................................................

3-21

Character Translation and String Instructions ..............................................................

3-22

Translate Instruction ...................................................................................................

3-22

String Manipulation Instructions and Repeat Prefixes ..............................................

3-22

String Movement Instructions ................................................................................

3-23

Other String Operations ..........................................................................................

3-23

Address Manipulation Instructions ................................................................................

3-24

Flag Control Instructions ................................................................................................

3-25

Carry Flag Control Instructions ..................................................................................

3-25

Direction Flag Control Instructions ............................................................................

3-25

Flag Transfer Instructions ..........................................................................................

3-26

Binary-Coded Decimal Arithmetic Instructions .............................................................

3-27

Packed BCD Adjustment Instructions ........................................................................

3-27

Unpacked BCD Adjustment Instructions ...................................................................

3-27

Trusted Instructions ... ....................................................................................................

3-28

Trusted and Privileged Restrictions on POPF and IRET ..........................................

3-28

Machine State Instructions .........................................................................................

3-28

Input and Output Instructions ....................................................................................

3-29

Processor Extension Instructions ..................................................................................

3-29

Processor Extension Synchronization Instructions ..................................................

3-30

Numeric Data Processor Instructions ........................................................................

3-30

Arithmetic Instructions ............................................................................................

3-30

Comparison Instructions .........................................................................................

3-30

Transcendental Instructions ...................................................................................

3-30

Data Transfer Instructions ......................................................................................

3-31

Constant Instructions ..............................................................................................

3-31

CHAPTER 4

 

EXTENDED INSTRUCTION SET

 

Block I/O Instructions ......................................................................................................

4-1

High-Level Instructions ....................................................................................................

4-2

CHAPTER 5

 

REAL ADDRESS MODE

 

Addressing and Segmentation .......................................................................................

5-1

Interrupt Handling ...........................................................................................................

5-3

Interrupt Vector Table .................................................................................................

5-3

Interrupt Priorities ...................................................................................................

5-4

Interrupt Procedures ...................................................................................................

5-5

vi

TABLE OF CONTENTS

 

Page

Reserved and Dedicated Interrupt Vectors ...............................................................

5-5

System Initialization ........................................................................................................

5-7

CHAPTER 6

 

MEMORY MANAGEMENT AND VIRTUAL ADDRESSING

 

Memory Management Overview ....................................................................................

6-1

Virtual Addresses ...........................................................................................................

6-2

Descriptor Tables ...........................................................................................................

6-4

Virtual-to-Physical Address Translation ........................................................................

6-6

Segments and Segment Descriptors .............................................................................

6-7

Memory Management Registers ...................................................................................

6-9

Segment Address Translation Registers ...................................................................

6-9

System Address Registers .........................................................................................

6-12

CHAPTER 7

 

PROTECTION

 

Introduction .....................................................................................................................

7-1

Types of Protection ....................................................................................................

7-1

Protection Implementation .........................................................................................

7-2

Memory Management and Protection ...........................................................................

7-4

Separation of Address Spaces ..................................................................................

7-5

LDT and GDT Access Checks ...................................................................................

7-5

Type Validation ...........................................................................................................

7-6

Privilege Levels and Protection .....................................................................................

7-8

Example of Using Four Privilege Levels ....................................................................

7-8

Privilege Usage ...........................................................................................................

7-9

Segment Descriptor .......................................................................................................

7-10

Data Accesses ............................................................................................................

7-12

Code Segment Access ...............................................................................................

7-13

Data Access Restriction by Privilege Level ...............................................................

7-13

POinter Privilege Stamping via ARPL .........................................................................

7-14

Control Transfers ...........................................................................................................

7-15

Gates ...........................................................................................................................

7-16

Call Gates ................................................................................................................

7-17

Intra-Level Transfers via Call Gate .........................................................................

7-18

Inter-Level Control Transfer via Call Gates ............................................................

7-19

Stack Changes Caused by Call Gates ...................................................................

7-20

Inter-Level Returns .....................................................................................................

7-20

CHAPTERS

 

TASKS AND STATE TRANSITIONS

 

Introduction .....................................................................................................................

8-1

Task State Segments and Descriptors ..........................................................................

8-1

Task State Segment Descriptors ...............................................................................

8-3

Task Switching ...............................................................................................................

8·4

Task Linking ...................................................................................................................

8-7

Task Gates .....................................................................................................................

8-8

CHAPTER 9

 

INTERRUPTS AND EXCEPTIONS

 

Interrupt Descriptor Table ..............................................................................................

9-1

Hardware Initiated Interrupts .........................................................................................

9-2

vii

TABLE OF CONTENTS

 

 

 

 

Page

Software Initiated Interrupts ..........................................................................................

 

9-3

Interrupt Gates and Trap Gates .....................................................................................

 

9-3

Task Gates and Interrupt Tasks ....................................................................................

 

9-7

Scheduling Considerations ................................................................

.........................

9-8

Deciding Between Task, Trap, and Interrupt Gates ................................

..................

9-8

Protection Exceptions and Reserved Vectors ..............................................................

 

9-9

Invalid OP-Code (Interrupt 6) ......................................................................................

 

9-10

Double Fault (Interrupt 8) ............................................................................................

 

9-10

Processor Extension Segment Overrun (Interrupt 9) ................................................

 

9-10

Invalid Task State Segment (Interrupt 10) .................................................................

 

9-11

Not Present (Interrupt 11) ...........................................................................................

 

9-11

Stack Fault (Interrupt 12) ............................................................................................

 

9-12

General Protection Fault (Interrupt 13) ......................................................................

 

9-13

Additional Exceptions and Interrupts ............................................................................

 

9-13

Single Step Interrupt (Interrupt 1) ..............................................................................

 

9-14

CHAPTER 10

 

 

SYSTEM CONTROL AND INITIALIZATION

 

 

System Flags and Registers ............................................................................

............

10-1

Descriptor Table Registers .......................................................................................

 

10-1

System Control Instructions ........................................................................................

 

10-3

Machine Status Word ...............................................................................................

 

10-4

Other Instructions .....................................................................................................

 

10-5

Privileged and Trusted Instructions .............................................................................

 

10-5

Initialization ...................................................................................................................

 

10-6

Real Address Mode ..................................................................................................

 

10-7

Protected Mode ........................................................................................................

 

10-7

CHAPTER 11

 

 

ADVANCED TOPICS

 

 

Virtual Memory Management ..............................................................................

.........

11-1

Special Segment Attributes ...................................... ....................................................

 

11-1

Conforming Code Segments ....................................................................................

 

11-1

Expand-Down Data Segments .........................................................................

........

11-2

Pointer Validation .........................................................................................................

 

11-3

Descriptor Validation ................................................................................................

 

11-4

Pointer Integrity: RPL and the "Trojan Horse Problem" ........................................

 

11-4

NPX Context Switching ................................................................................................

 

11-5

Multiprocessor Considerations .............................................................

.......................

11-5

Shutdown .............................................................................................

;........................

11-7

APPENDIX A

80286 SYSTEM INITIALIZATION

APPENDIX B

THE 80286 INSTRUCTION SET

APPENDIX C

8086/8088 COMPATIBILITY CONSIDERATIONS

APPENDIX D

80286/80386 SOFTWARE COMPATIBILITY CONSIDERATIONS

INDEX

viii

TABLE OF CONTENTS

Figures

Figure

 

Title

 

 

 

Page

1-1

Four Privilege Levels

.....................................

........................

..............

....................

1-4

2-1

Segmented Virtual Memory ..........................................

.................

..........................

 

2-2

2-2

Bytes and Words in Memory...................................................................................

 

 

 

2-3

2-3

80286/80287 Supported Data Types ............................

..............

............................

 

2-5

2-4

80286 Base Architecture Register Set ...................................................................

 

 

 

2-7

2-5

Real Address Mode Segment Selector Interpretation ...........................................

 

 

2-9

2-6

Protected Mode Segment Selector Interpretation .................................................

 

 

2-10

2-7

80286 Stack .............................................................................................................

 

 

 

 

2-11

2-8

Stack Operation .......................................................................................................

 

 

 

 

2-12

2-9

BP Usage as a Stack Frame Base Pointer .............................................................

 

 

 

2-13

2-10

Flags Register ..........................................................................................................

 

 

 

 

2-15

2-11

Two-Component Address .......................................................................................

 

 

 

2-18

2-12

Use of Memory Segmentation ......................

:.........................................................

 

 

2-20

2-13

Complex Addressing Modes ...................................................................................

 

 

 

2-22

2-14

Memory-Mapped I/O

................................................................................................

 

 

 

2-24

2-15

Hierarchy of Instructions .........................................................................................

 

 

 

2-27

3-1

PUSH .......................

:...............................................................................................

 

 

 

3-2

3-2

PUSHA......................................................

....................

........................

...................

 

3-3

3-3

POP ..........................................................................................................................

 

 

 

 

3-4

3-4

POPA ........................................................................................................................

 

 

 

 

3-5

3-5

Flag Word Contents ..................................

.......................................

 

........................

 

3-6

3-6

SAL and SHL ...........................................................................................................

 

 

 

 

3-11

3-7

SHR ..........................................................................................................................

 

 

 

 

3-12

3-8

SAR ..........................................................................................................................

 

 

 

 

3-12

3-9

ROL ..........................................................................................................................

 

 

 

 

3-13

3-10

ROR .........................................................................................................................

 

 

 

 

3-14

3-11

RCL ..........................................................................................................................

 

 

 

 

3-15

3-12

RCR ..........................................................................................................................

 

 

 

 

3-15

3-13

LAHF and SAHF ......................................................................................................

 

 

 

 

3-26

3-14

PUSHF and POPF ...................................................................................................

 

 

 

 

3-27

4-1

Formal Definition of the ENTER Instruction ...........................................................

 

 

 

4-3

4-2

Variable Access in Nested Procedures ..................................................................

 

 

 

4-4

4-2a

Stack Frame for MAIN at Level 1 ............................................................................

 

 

 

4-4

4-2b

Stack Frame for Procedure A .....................................

..................

..........................

 

4-5

4-2c

Stack Frame for Procedure B at Level 3 Called from A ....... ................................

:

 

4-5

4-2d

Stack Frame for Procedure C at Level 3 Called from B ........................................

 

 

4-6

5-1 a

Forming the Segment Base Address ..........................

........................

....................

 

5-2

5-1 b

Forming the 20-Bit Physical Address in the Real Address Mode .........................

 

5-2

5-2

Overlapping Segments to Save Physical Memory ........................

.........................

 

5-3

5-3

Interrupt Vector Table for Real Address Mode ......................................................

 

 

5-4

5-4

Stack Structure after Interrupt (Real Address Mode) .......................................

....

:

5-5

6-1

Format of the Segment Selector Component

........................................................

 

 

6-2

6-2

Address Spaces and Task Isolation .......................................................................

 

 

 

6-3

6-3

Segment Descriptor (S = 1) ..............................

............................

...........................

 

6-5

6-4

Special Purpose Descriptors or System Segment Descriptors (S=O) .................

 

6-6

6-5

LDT Descriptor ........................................................................................................

 

 

 

 

6-7

6-6

Virtual-to-Physical Address Translation ............

........................

.............................

 

6-8

6-7

Segment Descriptor Access Bytes .........................................................................

 

 

 

6-9

6-8

Memory Management Registers .............................................................................

 

 

 

6-10

6-9

Descriptor Loading ..................................................................................................

 

 

 

 

6-11

ix

 

TABLE OF CONTENTS

 

 

Figure

Title

 

Page

7-1

Addressing Segments of a Module within a Task ..................................................

 

7-3

7-2

Descriptor Cache Registers .............................................................

'"....................

7-4

7-3

80286 Virtual Address Space ........................................................

..........................

7-6

7-4

Local and Global Descriptor Table Definitions .......................................................

 

7-7

7-5

Error Code Format (on the stack) ...........................................................................

 

7-7

7-6

Code and Data Segments Assigned to a Privilege Level ...............

........................

7-9

7-7

Selector Fields .........................................................................................................

 

7-11

7-8

Access Byte Examples ..............................................................................................

 

7-12

7-9

Pointer Privilege Stamping ......................................................................................

 

7-15

7-10

Gate Descriptor Format ...........................................................................................

 

7-17

7-11

Call Gate ..................................................................................................................

 

7-19

7-12

Stack Contents after an Inter-Level Call .................................................................

 

7-21

8-1

Task State Segment and TSS Registers ................................................................

 

8-2

8-2

TSS Descriptor ............................................................................................

............

8-4

8-3

Task Gate Descriptor ..............................................................................................

 

8-8

8-4

Task Switch Through a Task Gate .........................................................................

 

8-9

9-1

Interrupt Descriptor Table Definition ......................................................................

 

9-1

9-2

IDT Selector Error Code ..........................................................................................

 

9-2

9-3

Trap/Interrupt Gate Descriptors .............................................................................

 

9-4

9-4

Stack Layout after an Exception with an Error Code ..................

..........................

9-5

10-1

Local and Global Descriptor Table Definition .........................................................

 

10-2

10-2

Interrupt Descriptor Table Definition ......................................................................

 

10-2

10-3

Data Type for Global Descriptor Table and Interrupt Descriptor Table ................

10-3

11-1

Expand-Down Segment .....................................................................

.....................

11-2

11-2

Dynamic Segment Relocation and Expansion of Segment Limit

..........................

11-3

11-3

Example of NPX Context Switching .......................................................................

 

11-6

B-1

In Instruction Byte Format ......................................................................................

 

B-2

B-2

Ir Instruction Byte Format .......................................................................................

 

B-4

 

Tables

 

 

Table

Title

 

Page

2-1

Implied Segment Usage by Index, Pointer, and Base Registers ...........................

 

2-14

2-2

Segment Register Selection Rules ..................................................

.......................

2-19

2-3

Memory Operand Addressing Modes ....................................................................

 

2-21

2-4

80286 Interrupt Vector Assignments (Real Address Mode) ..................................

 

2-26

3-1

Status Flags'Functions ...........................................................................................

 

3-6

3-2

Control Flags'Functions .........................................................................................

 

3-7

3-3

Interpretation of Conditional Transfers ..................................................................

 

3-20

5-1

Interrupt Processing Order .....................................................................................

 

5-4

5-2

Dedicated and Reserved Interrupt Vectors in Real Address Mode ......................

5-6

5-3

Processor State after RESET ......................................................

:..........................

5-7

7-1

Segment Access Rights Byte Format '"..............................................

....................

7-11

7-2

Allowed Segment Types in Segment Registers ..........................

;..........................

7-12

7-3

Call Gate Checks .....................................................................................................

 

7-18

7-4

Inter-Level Return Checks ......................................................................................

 

7-22

8-1

Checks Made during a Task Switch .......................................................................

 

8-6

8-2

Effect of a Task Switch on BUSY and NT Bits and the Link Word .......................

8-7

9-1

Trap and Interrupt Gate Checks .............................................................................

 

9-6

9-2

Interrupt and Gate Interactions ...............................................................................

 

9-7

x

 

TABLE OF CONTENTS

 

Table

Title

Page

9-3

Reserved Exceptions and Interrupts ......................................................................

9-9

9-4

Interrupt Processing Order ... ..................................................................................

9-9

9-5

Conditions That Invalidate the TSS ........................................................................

9-12

10-1

MSW 8it Functions ..................................................................................................

10-4

10-2

Recommended MSW Encodings for Processor Extension Control......................

10-5

11-1

NPXContextSwitching ...........................................................................................

11-7

8-1

ModRM Values ........................................................................................................

8-3

8-2

Protection Exceptions of the 80286 .............. ....................... ....................... ............

8-8

8-3

Hexadecimal Values for the Access Rights 8yte ...................................................

8-14

C-1

New 80286 Interrupts ..............................................................................................

C-1

xi

inter

CUSTOMER SUPPORT

CUSTOMER SUPPORT

Customer Support is Intel's complete support service that provides Intel customers with hardware support, software support, customer training, and consulting services. For more information contact your local sales offices.

After a customer purchases any system hardware or software product, service and support become major factors in determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. As you might expect, Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices providing hardware repair services, software support services, customer training classes, and consulting services.

HARDWARE SUPPORT SERVICES

Intel is committed to providing an international service support package through a wide variety of service offerings available from Intel Hardware Support.

SOFfWARE SUPPORT SERVICES

Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and SUbscription service (product-specific troubleshooting guides and COMMENTS Magazine). Basic support includes updates and the SUbscription service. Contracts are sold in environments which represent product groupings (Le., iRMX environment).

CONSULTING SERVICES

Intel provides field systems engineering services for any phase of your development or support effort. You can use our systems engineers in a variety of ways ranging from assistance in using a new product, developing an application, personalizing training, and customizing or tailoring an Intel product to providing technical and management consulting. Systems Engineers are welJ versed in technical areas such as microcommunications, real-time applications, embedded microcontrolJers, and network services. You know your application needs; we know our products. Working together we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING

Intel offers a wide range of instructional programs covering various aspects of system design and implementation. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course categories include: architecture and assembly language, programming and operating systems, bitbus and LAN applications.

Introduction to the 80286

1

CHAPTER 1

INTRODUCTION TO THE 80286

The 80286 is the most powerful 16-bit processor in the 8086 series of microprocessors, which includes the 8086, the 8088, the 80186, the 80188, and the 80286. It is designed for applications that require very high performance. It is also an excellent choice for sophisticated "high end" applications that will benefit from its advanced architectural features: memory management, protection mechanisms, task management, and virtual memory support. The 80286 provides, on a single VLSI chip, computational and architectural characteristics normally associated with much larger minicomputers.

Sections 1.1, 1.2, and 1.3 of this chapter provide an overview of the 80286 architecture. Because the 80286 represents an extension of the 8086 architecture, some of this overview material may be new and unfamiliar to previous users of the 8086 and similar microprocessors. But the 80286 is also an evolutionary development, with the new architecture superimposed upon the industry standard 8086 in such a way as to affect only the design and programming of operating systems and other such system softwar~. Section 1.4 of this chapter provides a guide to the organization of this manual, suggesting which chapters are relevant to the needs of particular readers.

1.1 GENERAL ATTRIBUTES

The 80286 base architecture has many features in common with the architecture of other members of the 8086 family, such as byte addressable memory, I/O interfacing hardware, interrupt vectoring, and support for both multiprocessing and processor extensions. The entire family has a common set of addressing modes and basic instructions. The 80286 base architecture also includes a number of extensions which add to the versatility of the computer.

The 80286 processor can function in two modes of operation (see section 1.2 of this chapter, Modes of Operation). In one of these modes only the base architecture is available to programmers, whereas in the other mode a number of very powerful advanced features have been added, including support for virtual memory, multitasking, and a sophisticated protection mechanism. These advanced features are described in section 1.3 of this chapter.

The 80286 base architecture was designed to support programming in high-level languages, such as Pascal, C or PL/M. The register set and instructions are well suited to compiler-generated code. The addressing modes (see section 2.6.3 in Chapter 2) allow efficient addressing of complex data structures, such as static and dynamic arrays, records, and arrays within records, which are commonly supported by high-level languages. The data types supported by the architecture include, along with bytes and words, high level language constructs such as strings, BCD, and floating point.

The memory architecture of the 80286 was designed to support modular programming techniques. Memory is divided into segments, which may be of arbitrary size, that can be used to contain procedures and data structures. Segmentation has several advantages over more conventional linear memory architectures. It supports structured software, since segments can contain meaningful program units and data, and more compact code, since references within a segment can be shorter (and locality of reference usually insures that the next few references will be within the same segment). Segmentation also lends itself to efficient implementation of sophisticated memory management, virtual memory, and memory protection.

In addition, new instructions have been added to the base architecture to give hardware support for procedure invocations, parameter passing, and array bounds checking.

1-1

INTRODUCTION TO THE 80286

1.2 MODES OF OPERATION

The 80286 can be operated in either of two different modes: Real Address Mode or Protected Virtual Address Mode (also referred to as Protected Mode). In either mode of operation, the 80286 represents an upwardly compatible addition to the 8086 family of processors.

In Real Address Mode, the 80286 operates essentially as a very high-performance 8086. Programs written for the 8086 or the 80186 can be executed in this mode without any modification (the few exceptions are described in Appendix C, "Compatibility Considerations"). Such upward compatibility extends even to the object code level; for example, an 8086 program stored in read-only memory will execute successfully in 80286 Real Address Mode. An 80286 operating in Real Address Mode provides a number of instructions not found on the 8086. These additional instructions, also present with the 80186, allow for efficient subroutine linkage, parameter validation, index calculations, and block 1/0 transfers.

The advanced architectural features and full capabilities of the 80286 are realized in its native Protected Mode. Among these features are sophisticated mechanisms to support data protection, system integrity, task concurrency, and memory management, including virtual storage. Nevertheless, even in Protected Mode, the 80286 remains upwardly compatible with most 8086 and 80186 application programs. Most 8086 applications programs can be re-compiled or re-assembled and executed on the 80286 in Protected Mode.

1.3 ADVANCED FEATURES

The architectural features described in section 1.1 of this chaper are common to both operating modes of the processor. In addition to these common features, Protected Mode provides a number of advanced features, including a greatly extended physical and logical address space, new instructions, and support for additional hardware-recognized data structures. The Protected Mode 80286 includes a sophisticated memory management and multilevel protection mechanism. Full hardware support is included for multitasking and task switching operations.

1.3.1 Memory Management

The memory architecture of the Protected Mode 80286 represents a significant advance over that of the 8086. The physical address space has been increased froml megabyte to 16 megabytes (224 byies), while the virtual address space (i.e., the address space visible to a program) has been increased from 1 megabyte to 1 gigabyte (230 bytes). Moreover, separate virtual address spaces are provided for each task in a multi-tasking system (see the next section, 1.3.2, "Task Management").

The 80286 supports on-chip memory management instead of relying on an external memory management unit. The one-chip solution is preferable because no software is required to manage an external memory management unit, performance is much better, and hardware designs are significantly simpler.

Mechanisms have been included in the 80286 architecture to allow the efficient implementation of virtual memory systems. (In virtual memory systems, the user regards the combination of main and external storage as a single large memory. The user can write large programs without worrying about the physical memory limitations of the system. To accomplish this, the operating system places some of the user programs and data in external storage and brings them into main memory only as they are needed.) All instructions that can cause a segment-riot-present fault are fully restartable. Thus, a notpresent segment can be loaded from external storage, and the task can be restarted at the point where the fault occurred.

1-2

INTRODUCTION TO THE 80286

The 80286, like all members of the 8086 series, supports a segmented memory architecture. The 80286 also fully integrates memory segmentation into a comprehensive protection scheme. This protection scheme includes hardware-enforced length and type checking to protect segments from inadvertent misuse.

1.3.2 Task Management

The 80286 is designed to support multi-tasking systems. The architecture provides direct support for the concept of a task. For example, task state segments (see section 8.2 in Chapter 8) are hardwarerecognized and hardware-manipulated structures that contain information on the current state of all tasks in the system.

Very efficient context-switching (task-switching) can be invoked with a single instruction. Separate logical address spaces are provided for each task in the system. Finally, mechanisms exist to support intertask communication, synchronization, memory sharing, and task scheduling. Task Management is described in Chapter 8.

1.3.3 Protection Mechanisms

The 80286 allows the system designer to define a comprehensive protection policy to be applied, uniformly and continuously, to all ongoing operations of the system. Such a policy may be desirable to ensure system reliability, privacy of data, rapid error recovery, and separation of multiple users.

The 80286 protection mechanisms are based on the notion of a "hierarchy of trust." Four privilege levels are distinguished, ranging from Level 0 (most trusted) to Level 3 (least trusted). Level 0 is usually reserved for the operating system kernel. The four levels may be visualized as concentric rings, with the most privileged level in the center (see figure 1-1).

This four-level scheme offers system reliability, flexibility, and design options not possible with the typical two-level (supervisorluser) separation provided by other processors. A four-level division is capable of separating kernel, executive, system services, and application software, each with different privileges.

At anyone time, a task executes at one of the four levels. Moreover, all data segments and code segments are also assigned to privilege levels. A task executing at one level cannot access data at a more privileged level, nor can it call a procedure at a less privileged level (i.e., trust a less privileged procedure to do work for it). Thus, both access to data and transfer of control are restricted in appropriate ways.

A complete separation can exist between the logical address spaces local to different tasks, providing users with automatic protection against accidental or malicious interference by other users. The hardware also provides immediate detection of a number of fault and error conditions, a feature that can be useful in the development and maintenance of software.

Finally, these protection mechanisms require relatively little system overhead because they are integrated into the memory management and protection hardware of the processor itself.

1-3

INTRODUCTION TO THE 80286

LEAST TRUSTED

MOST TRUSTED

G30108

Figure 1-1. Four Privilege Levels

1.3.4 Support for Operating Systems

Most operating systems involve some degree of concurrency, with multiple tasks vying for system resources. The task management mechanisms described above provide the 80286 with inherent support for such multi-tasking systems. Moreover, the advanced memory management features of the 80286 allow the implementation of sophisticated virtual memory systems.

Operating system implementors have found that a multi-level approach to system services provides better security and more reliable systems. For example, a very secure kernel might implement critical functions such as task scheduling and resource aiiocation, while less fundamenlal [ulictions (such as I/O) are built around the kernel. This layered approach also makes program development and enhancement simpler and facilitates error detection and debugging. The 80286 supports the layered approach through its four-level privilege scheme.

1.4 ORGANIZATION OF THIS BOOK

To facilitate the use of this book both as an introduction to the 80286 architecture and as a reference guide, the remaining chapters are divided into three major parts.

Part I, comprising chapters 2 through 4, should be read by all those who wish to acquire a basic familiarity with the 80286 architecture. These chapters provide detailed information on memory segmentation, registers, addressing modes and the general (application level) 80286 instruction set. In conjunction with the 80286 Assembly Language Reference Manual, these chapters provide sufficient information for an assembly language programmer to design and write application programs.

1-4

INTRODUCTION TO THE 80286

The chapters in Part I are:

Chapter 2, "Architectural Features." This chapter discusses those features of the 80286 architecture that are significant for application programmers. The information presented can also function as an introduction to the machine for system programmers. Memory organization and segmentation, processor registers, addressing modes, and instruction formats are all discussed.

Chapter 3, "Basic Instruction Set." This chapter presents the core instructions of the 8086 family.

Chapter 4, "Extended Instruction Set." This chapter presents the extended instructions shared by the 80186 and 80286 processors.

Part II of the book consists of a single chapter:

Chapter 5, "Real Address Mode." This chapter presents the system programmer's view of the 80286 when the processor is operated in Real Address Mode.

Part III of the book comprises chapters 6 through 11. Aimed primarily at system programmers, these chapters discuss the more advanced architectural features of the 80286, which are available when the processor is. in Protected Mode. Details on memory management, protection mechanisms, and task switching are provided.

The chapters in Part III are:

Chapter 6, "Virtual Memory." This chapter describes the 80286 address translation mechanisms that support virtual memory. Segment descriptors, global and local descriptor tables, and descriptor caches are discussed.

Chapter 7, "Protection." This chapter describes the protection features of the 80286. Privilege levels, segment attributes, access restrictions, and call gates are discussed.

Chapter 8, "Tasks and State Transitions." This chapter describes the 80286 mechanisms that support concurrent tasks. Context-switching, task state segments, task gates, and interrupt tasks are discussed.

Chapter 9, "Interrupts, Traps and Faults." This chapter describes interrupt and trap handling. Special attention is paid to the exception traps, or faults, which may occur in Protected Mode. Interrupt gates, trap gates, and the interrupt descriptor table are discussed.

Chapter 10, "System Control and Initialization." This chapter describes the actual instructions used to implement the memory management, protection, and task support features of the 80286. System registers, privileged instructions, and the initial machine state are discussed.

Chapter 11, "Advanced Topics." This chapter completes Part III with a description of several advanced topics, including special segment attributes and pointer validation.

1.5 RELATED PUBLICATIONS

The following manuals also contain information of interest to programmers of 80287 systems:

Introduction to the 80286, order number 210308

ASM286 Assembly Language Reference Manual, order number 121924

80286 Operating System Writer's Guide, order number 121960

1-5

inter

INTRODUCTION TO THE 80286

80286 Hardware Reference Manual, order number 210760

Microprocessor and Peripheral Handbook, order number 230843

PL/M-286 User's Guide, order number 121945

80287 Support Library Reference Manual, order number 122129

8086 Software Toolbox Manual, order number 122203 (includes information about 80287 Emulator Software)

1-6

80286 Base Architecture

2

CHAPTER 2

80286 BASE ARCHITECTURE

This chapter describes the 80286 application programming environment as seen by assembly language programmers. It is intended to introduce the programmer to those features of the 80286 architecture that directly affect the design and implementation of 80286 application programs.

2.1 MEMORY ORGANIZATION AND SEGMENTATION

The main memory of an 80286 system makes up its physical address space. This address space is organized as a sequence of 8-bit quantities, called bytes. Each byte is assigned a unique address ranging from 0 up to a maximum of 220 (1 megabyte) in Real Address Mode, and up to 224 (16 megabytes) in Protected Mode. .

A virtual address space is the organization of memory as viewed by a program. Virtual address space is also organized in units of bytes. (Other addressable units such as words, strings, and BCD digits are described below in section 2.2, "Data Types.") In Real Address Mode, as with the 8086 itself, programs view physical memory directly, inasmuch as they manipulate pure physical addresses. Thus, the virtual address space is identical to the physical address space (1 megabyte).

In Protected Mode, however, programs have no direct access to physical addresses. Instead, memory is viewed as a much larger virtual address space of 230 bytes (1 gigabyte). This 1 gigabyte virtual address is mapped onto the Protected Mode's 16-megabyte physical address space by the address translation mechanisms described in Chapter 6.

The programmer views the virtual address space on the 80286 as a collection of up to sixteen thousand linear subspaces, each with a specified size or length. Each of these linear address spaces is called a segment. A segment is a logical unit of contiguous memory. Segment sizes may range from one byte up to 64K (65,536) bytes.

80286 memory segmentation supports the logical structure of programs and data iq memory. Programs are not written as single linear sequences of instructions and data, but rather as modules of code and data. For example, program code may include a main routine and several separate procedures. Data may also be organized into various data structures, some private and some shared with other programs in the system. Run-time stacks constitute yet another data requirement. Each of these several modules of code and data, moreover, may be very different in size or vary dynamically with program execution.

Segmentation supports this logical structure (see figure 2-1). Each meaningful module of a program may be separately contained in individual segments. The degree of modularization, of course, depends on the requirements of a particular application. Use of segmentation benefits almost all applications. Programs execute faster and require less space. Segmentation also simplifies the design of structured software.

2.2 DATA TYPES

Bytes and words are the fundamental units in which the 80286 manipulates data, i.e., the fundamental data types.

2-1

80286 BASE ARCHITECTURE

r--------

,

 

20000 CS

8000 r-----..,

 

MAIN

8600 r-----.,

PROCEDURE

PROCEDURE

A

 

0 _____...

 

_____I

0'"-____..1

 

7253051

DATA (B)

 

DATA (A)

0 _____...

L..-__-- I

0 I..____--1

2000 ~----..,

 

 

o ___ ...

 

 

O~""';""';_ __I

L _______ ...J

CURRENTLY

ACCESSIBLE

G3010B

Figure 2-1. Segmented Virtual Memory

A byte is 8 contiguous bits starting on an addressable byte boundary. The bits are numbered 0 through 7, starting from the right. Bit 7 is the most significant bit:

o

I I i

BYTE

,I

A word is defined as two contiguous bytes starting on an arbitrary byte boundary; a word thus contains 16 bits. The bits are numbered 0 through 15, starting from the right. Bit 15 is the most significant bit. The byte containing bit 0 of the word is called the low byte; the byte containing bit 15 is called the high byte.

15

0

I : :~IGH:B+: : I : :+W:BY+: : I

LOCATION N+1

LOCATION N

2-2

80286 BASE ARCHITECTURE

Each byte within a word has its own particular address, and the smaller of the two addresses is used as the address of the word. The byte at this lower address contains the eight least significant bits of the word, while the byte at the higher address contains the eight most significant bits. The arrangement of bytes within words is illustrated in figure 2-2.

Note that a word need not be aligned at an even-numbered byte address. This allows maximum flexibility in data structures (e.g., records containing mixed byte and word entries) and efficiency in memory utilization. Although actual transfers of data between the processor and memory take place at physically aligned word boundaries, the 80286 converts requests for unaligned words into the appropriate sequences of requests acceptable to the memory interface. Such odd aligned word transfers, however, may impact performance by requiring t'Yo memory cycles to transfer the word rather than one. Data structures (e.g., stacks) should therefore be designed in such a way that word operands are aligned on word boundaries whenever possible for maximum system performance. Due to instruction prefetching and queueing within the CPU, there is no requirement for instructions to be aligned on word boundaries and no performance loss if they are not.

Although bytes and words are the fundamental data types of operands, the processor also supports additional interpretations on these bytes or words. Depending on the instruction referencing the operand, the following additional data types can be recognized:

Integer:

A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All operations assume a 2's complement representation. (Signed 32and 64-bit integers are supported using the 80287 Numeric Data Processor.)

BYTE

MEMORY

 

ADDRESS'

VALUES

 

'r

 

"

E

 

 

D

 

 

C

FE

WORD AT ADDRESS B

 

 

B

06

CONTAINS FE06

I

A

 

 

 

 

BYTE AT ADDRESS 9

9

1F

) CONTAINS 1F

8

 

 

7

23

WORD AT ADDRESS 6

 

 

6

OB

CONTAINS 230B

I

5

 

 

4

 

 

3

74

WORD AT ADDRESS 2

 

31

 

I

 

 

CONTAINS 74CB

2

CB

IWORD AT ADDRESS 1

 

 

CONTAINS CB31

o

 

'NOTE:

 

 

ALL VALUES IN HEXADECIMAL

G30108

Figure 2-2. Bytes and Words in Memory

2-3

80286 BASE ARCHITECTURE

Ordinal:

An unsigned binary numeric value contained in an 8-bit byte or 16-bit word.

Pointer:

A 32-bit address quantity composed of a segment selector component and an offset component. Each component is a 16-bit word.

String:

A contiguous sequence of bytes or words. A string may contain from 1 byte to 64K bytes.

ASCII:

A byte representation of alphanumeric and control characters using the. ASCII standard of character representation.

BCD:

A byte (unpacked) representation of the decimal digits (0-9).

Packed BCD:

A byte (packed) representation of two decimal digits (0-9). One digit is stored in each nibble of the byte.

Floating Point:

A signed 32-, 64-, or 80-bit real number representation. (Floating operands are supported using the 80287 Numeric Processor Configuration.)

Figure 2-3 graphically represents the data types supported by the 80286. 80286 arithmetic operations may be performed on five types of numbers: unsigned binary, signed binary (integers), unsigned pflcked decimal, unsigned unpacked decimal, and floating point. Binary numbers may be 8 or 16 bits long. Decimal numbers are stored in bytes; two digits per byte for packed decimal, one digit per byte for unpacked decimal. The processor always assumes that the operands specified in arithmetic instructions contain data that represent valid numbers for the type of instruction being performed. Invalid data may produce unpredictable results.

Unsigned binary numbers may be either 8 or 16 bits long; all bits are considered in determining a number's magnitude. The value range of an 8-bit unsigned binary number is 0-255; 16 bits can represent values from 0 through 65,535. Addition, subtraction, multiplication and division operations are available for unsigned binary numbers.

Signed binary numbers (integers) may be either 8 or 16 bits long. The high-order (leftmost) bit is interpreted as the number's sign: O=positive and 1= negative. Negative numbers are represented in standard two's complement notation. Since the high-order bit is used for a sign, the range of an 8-bit integer is -128 through +127; 16-bit integers may range from -.32,768 through +32,767. The value zero has a positive sign.

2-4

80286 BASE ARCHITECTURE

7

 

I I I1 I I

0

 

 

SI~~~~ II

I

 

 

SIGN BIT -lj

 

I

 

 

 

MAGNITUDE

 

 

UNSI~~~~ I7

I I I I I II

0I

 

 

ILMSB

I

 

 

MAGNITUDE

 

 

 

1514 + 1 87

0

0

s~~~g II

Ii II II

IIi I IIi

I I

SIGN BIT -I j

L- MSB

 

 

1

MAGNITUDE

31

+3

 

+2

 

1615

+ 1

 

 

0

0

 

 

SIGNED D~~~~ 11"

II II

II

I I II I I I Ii

I III

I II II

III I I

 

 

SIGN BIT ...I

IL MSB

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

MAGNITUDE

 

 

 

 

 

 

 

+7

+6

 

+5

+4

+3

+2

 

+1

0

 

 

 

63

 

4847

 

3231

 

 

1615

 

0

 

 

SIGNED QUAD II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WORD'

 

 

I

 

 

I

 

 

 

I

 

I

 

 

SIGN BIT JIL MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAGNITUDE

 

 

 

 

 

 

 

~

+1

 

0

 

0

 

 

 

 

 

 

 

 

UNS~~~g 1:1 I II 11I1 I II

1I 1I

 

 

 

 

 

 

 

 

I

MSB

 

 

 

I

 

 

 

 

 

 

 

 

 

 

MAGNITUDE

 

 

 

 

 

 

 

 

 

 

7

+N

0

 

 

7

+1

07

0

0

 

 

~~~~61'iiliijl

 

 

II ill Iii 11111"1

I

 

 

DECIMAL I..___-'.

 

 

 

 

 

 

 

 

 

 

 

(BCD)

DI~7~N

 

 

 

BCD

 

BCD

 

 

 

 

 

 

 

 

 

DIGIT 1

 

DIGIT 0

 

 

 

7

+N

0

 

 

7

+1

07

0

0

 

 

ASCIIIIIIIIIII

 

 

lilllllIlllIlllIl

 

 

 

ASCII

 

 

 

 

 

ASCII

ASCII

 

 

 

 

CHARACTERN

 

 

CHARACTER,

CHARACTERO

 

 

7

+N

0

 

 

7

+1

07

0

0

 

 

PAC~~g II

I I II I I

I

 

 

Ii Ii

Iii

i

II I I

I" i

I

 

 

MOST

 

 

 

 

 

 

 

 

 

LEAST

 

 

SIGNIFICANT DIGIT

 

 

 

SIGNIFICANT DIGIT

 

 

7/15+ N

0

 

 

7/15+ 1

07/15

0

0

 

 

STRING II II II III

 

 

I I I I III

I II I I III I I

 

 

BYTE/WORD N

 

 

BYTE/WORD 1

BYTE/WORD 0

 

 

31

+3

 

+2

1615

+ 1

 

 

0

0

 

 

POINTER I I i I II I I II

I I II I I II I I II i

I II I I I 1 I I I

 

 

I

 

SELECTOR

 

 

 

OFFSET

 

I

 

 

 

 

 

 

 

 

 

 

'SUPPORTED BY

79 +9

+8

+7

+6 +5

 

+4

+3

+2

+1 0

0

FLOATING II

 

 

 

 

 

 

 

 

 

 

 

 

80287

 

 

 

 

 

 

 

 

 

 

 

 

I

NUMERIC DATA

POINT'

 

 

 

 

 

 

 

 

 

 

 

 

CONFIGURATIONPROCESSOR

SIGN BIT ...II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXPONENT

 

 

 

 

MAGNITUDE

 

 

G30108

Figure 2·3. 80286/80287 Supported Data Types

2-5

80286 BASE ARCHITECTURE

Separate multiplication and division operations are provided for both signed and unsigned binary numbers. The same addition and subtraction instructions are used with signed or unsigned binary values. Conditional jump instructions, as well as an "interrupt on overflow" instruction, can be used following an unsigned operation on an integer to detect overflow into the sign bit.

Unpacked decimal numbers are stored as unsigned byte quantities. One digit is stored in each byte. The magnitude of the number is determined from the low-order half-byte; hexadecimal values 0-9 are valid and are interpreted as decimal numbers. The high-order half-byte must be zero for multiplication and division; it may contain any value for addition and subtraction.

Arithmetic on unpacked decimal numbers is performed in two steps. The unsigned binary addition, subtraction and multiplication operations are used to produce an intermediate result. An adjustment instruction then changes the value to a final correct unpacked decimal number. Division is performed similarly, except that the adjustment is carried out on the two digit numerator operand in register AX first, followed by an unsigned binary division instruction that produces a correct result.

Unpacked decimal numbers are similar to the ASCII character representations of the digits 0-9. Note, however, that the high-order half-byte of an ASCII numeral is always 3. Unpacked decimal arithmetic may be performed on ASCII numeric characters under the following conditions:

the high-order half-byte of an ASCII numeral must be set to OR prior to multiplication or division.

unpacked decimal arithmetic leaves the high-order half-byte set to OR; it must be set to 3 to produce a valid ASCII numeral.

Packed decimal numbers are stored as unsigned byte quantities. The byte is treated as having one decimal digit in each half-byte (nibble); the digit in the high-order half-byte is the most significant. Values 0-9 are valid in each half-byte, and the range of a packed decimal number is 0-99. Additions and subtractions are performed in two steps. First, an addition or subtraction instruction is used to produce an intermediate result. Then, an adjustment operation is performed which changes the intermediate value to a final correct packed decimal result. Multiplication and division adjustments are only available for unpacked decimal numbers.

Pointers and addresses are described below in section 2.3.3, "Index, Pointer, and Base Registers," and in section 3.8, "Address Manipulation Instructions."

Strings are contiguous bytes or words from 1 to 64K bytes in length. They generaiiy coniain ASCII Of other character data representations. The 80286 provides string manipulation instructions to move, examine, or modify a string (see section 3.7, "Character Translation and String Instructions").

If the 80287 numeric processor extension (NPX) is present in the system -

see the 80287 NPX

book-the 80286 architecture also supports floating point numbers, 32and

64-bit integers, and

18-digit BCD data types.

 

The 80287 Numeric Data Processor supports and stores real numbers in a three-field binary format as required by IEEE standard 754 for floating point numerics (see figure 2-3). The number's significant digits are held in the significand field, the exponent field locates the binary point within the significant digits (and therefore determines the number's magnitude), and the sign field indicates whether the number is positive or negative. (The exponent and significand are analogous to the terms "characteristic" and "mantissa," typically used to describe floating point numbers on some computers.) This format is used by the 80287 with various length significands and exponents to support single precision, double precision and extended (80-bit) precision floating point data types. Negative numbers differ from positive numbers only in their sign bits.

2-6

inter

80286 BASE ARCHITECTURE

2.3 REGISTERS

The 80286 contains a total of fourteen registers that are of interest to the application programmer. (Five additional registers used by system programmers are covered in section 10.1.) As shown in figure 2-4, these registers may be grouped into four basic categories:

General registers. These eight 16-bit general-purpos~ registers are used primarily to contain operands for arithmetic and logical operations.

Segment registers. These four special-purpose registers determine, at any given time, which segments of memory are currently addressable.

Status and Control registers. These three special-purpose registers are used to record and alter certain aspects of the 80286 processor state.

2.3.1 General Registers

The general registers of the 80286 are the 16-bit registers AX, BX, CX, DX, SP, BP, SI, and DI. These registers are used interchangeably to contain the operands of logical and arithmetic operations.

Some instructions and addressing modes (see section 2.4), however, dedicate certain general registers to specific uses. BX and BP are often used to contain the base address of data structures in memory (for example, the starting address of an array); for this reason, they are often referred to as the base registers. Similarly, SI and D1 are often used to contain an index value that will be incremented to step through a data structure; these two registers are called the index registers. Finally, SP and BP are used for stack manipulation. Both SP and BP normally contain offsets into the current stack. SP generally contains the offset of the top of the stack and BP contains the offset or base address of the current

 

16-BIT

 

 

 

SPECIAL

 

 

 

(S-BIT REGISTER

 

 

 

REGISTER

 

 

 

 

NAME

 

 

 

FUNCTIONS

 

 

 

,~

 

 

07

o

 

 

15

o

AX

AH

AL

 

 

CS

 

CODE SEGMENT SELECTOR

ADDRESSABLE

 

 

 

MULTIPLYI DIVIDE

 

1 ------- 1

OX

DH

DL

1/0 INSTRUCTIONS

OS

 

DATA SEGMENT SELECTOR

 

1

 

 

REGISTER

CX

CH

CL

LOOP ISHIFTI

SS

 

STACK SEGMENT SELECTOR

NAMES

REPEAT COUNT

 

 

 

 

 

t ------- f

SHOWN)

 

 

 

 

 

 

BX

BH

BL

}BASE REGISTERS

ES

 

EXTRA SEGMENT SELECTOR

 

BP

 

 

 

SEGMENT REGISTERS

 

 

SI

 

 

 

 

 

15

0

 

 

 

 

 

 

 

 

01

 

 

}) INDEX REGISTERS

 

 

 

 

 

 

 

 

F§FLAGS

 

 

 

 

 

 

 

SP

 

 

STACK POINTER

IP

 

INSTRUCTION POINTER

 

15

 

 

o

 

MSW·

MACHINE STATUS WORD

 

 

 

GENERAL

 

 

 

 

 

REGISTERS

STATUS AND CONTROL

 

REGISTERS

 

G3010B

Figure 2-4. 80286 Base Architecture Register Set

2-7

80286 BASE ARCHITECTURE

stack frame. The use of these general-purpose registers for operand addressing is discussed in section 2.3.3, "Index, Pointer, and Base Registers." Register usage for individual instructions is discussed in chapters 3 and 4.

As shown in figure 2-4, eight byte registers overlap four of the 16-bit general registers. These registers are named AH, BH, CH, and DH (high bytes); and AL, BL, CL, and DL (low bytes); they overlap AX, BX, CX, and DX. These registers can be used either in their entirety or as individual 8-bit registers. This dual interpretation simplifies the handling of both 8- and 16-bit data elements.

2.3.2 Memory Segmentation and Segment Registers

Complete programs generally consist of many different code modules (or segments), and different types of data segments. However, at any given time during program execution, only a small subset of a program's segments are actually in use. Generally, this subset will include code, data, and possibly a stack. The 80286 architecture takes advantage of this by providing mechanisms to support direct access to the working set of a program's execution environment and access to additional segments on demand.

At any given instant, four segments of memory are immediately accessible to an executing 80286 program. The segment registers DS, ES, SS, and CS are used to identify these four current segments. Each of these registers specifies a particular kind of segment, as characterized by the associated mnemonics ("code," "stack," "data," or "extra") shown in figure 2-4.

An executing program is provided with concurrent access to the four individual segments of memory- a code segment, a stack segment, and two data segments-by means of the four segment registers. Each may be said to select a segment, since it uniquely determines the one particular segment from among the numerous segments in memory, which is to be immediately accessible at highest speed. Thus, the 16-bit contents of a segment register is called a segment selector.

Once a segment is selected, a base address is associated with it. To address an element within a segment, a 16-bit offset from the segment's base address must be supplied. The 16-bit segment selector and the 16-bit offset taken together form the high and low order halves, respectively, of a 32-bit virtual address pointer. Once a segment is selected, only the lower 16-bits of the pointer, called the offset, generally need to be specified by an instruction. Simple rules define which segment register is used to form an address when only a 16-bit offset is specified.

An executing program requires, first of all, that its instructions reside somewhere in memory. The segment of memory containing the currently executing sequence of instructions is known as the current code segment; it is specified by means of the CS register. All instructions are fetched from this code segment, using as an offset the contents of the instruction pointer (IP). The CS:IP register combination therefore forms the full 32-bit pointer for the next sequential program instruction. The CS register is manipulated indirectly. Transitions from one code segment to another (e.g., a procedure call) are effected implicitly as the result of control-transfer instructions, interrupts, and trap operations.

Stacks playa fundamental role in the 80286 architecture; subroutine calls, for example, involve a number of implicit stack operations. Thus, an executing program will generally require a region of memory for its stack. The segment containing this region is known as the current stack segment, and it is specified by means of the SS register. All stack operations are performed within this segment, usually in terms of address offsets contained in the stack pointer (SP) and stack frame base (BP) registers. Unlike CS, the SS register can be loaded explicitly for dynamic stack definition.

2-8

80286 BASE ARCHITECTURE

Beyond their code and stack requirements, most programs must also fetch and store data in memory. The DS and ES registers allow the specification of two data segments, each addressable by the currently executing program. Accessibility to two separate data areas supports differentiation and access requirements like local procedure data and global process data. An operand within a data segment is addressed by specifying its offset either directly in an instruction or indirectly via index and/or base registers (described in the next subsection).

Depending on the data structure (e.g., the way data is parceled into one or more segments), a program may require access to multiple data segments. To access additional segments, the DS and ES registers can be loaded under program control during the course of a program's execution. This simply requires loading the appropriate data pointer prior to accessing the data.

The interpretation of segment selector values depends on the operating mode of the processor. In Real Address Mode, a segment selector is a physical address (figure 2-5). In Protected Mode, a segment selector selects a segment of the user's virtual address space (figure 2-6). An intervening level of logical- to-physical address translation converts the logical address to a physical memory address. Chapter 6, "Memory Management," provides a detailed discussion of Protected Mode addressing. In general, considerations of selector formats and the details of memory mapping need not concern the application programmer.

2.3.3 Index, Pointer, and Base Registers

Five of the general-purpose registers are available for offset address calculations. These five registers, shown in figure 2-4, are SP, BP, BX, SI, and DL SP is called a pointer register; BP and BX are called base registers; SI and DI are called index registers.

 

64K

{

SEG 1

1 MEGABYTE PHYSICAL

SEGMENT

BYTES

 

ADDRESS SPACE

 

 

I BASE ADDRESS

ISELECTOR I0000 I

NOTES: 1. THE SELECTOR IDENTIFIES A SEGMENT IN PHYSICAL MEMORY.

2.A SELECTOR SPECIFIES THE SEGMENTS BASE ADDRESS, MODULO 16, WITHIN THE 1 MEGABYTE ADDRESS SPACE.

3.THE SELECTOR IS THE 16 MOST SIGNIFICANT BITS OF A SEGMENTS PHYSICAL BASE ADDRESS.

4.THE VALUES OF SELECTORS DETERMINES THE AMOUNT THEY OVERLAP IN REAL MEMORY.

5.SEGMENTS MAY OVERLAP BY INCREMENTS OF*16 BYTES. OVERLAP RANGES FROM COMPLETE (SEG 1 ~ SEG 1) TO NONE (SEG 1 SEG 2 64K)±

G3010a

Figure 2-5. Real Address Mode Segment Selector Interpretation

2-9

inl:el®

80286 BASE ARCHITECTURE

 

SEG 3FFF

 

SEG 3FFE

 

SEG 3FFD

 

SEG 3FFC

,

SEG 3FFB

1 GIGABYTE

 

VIRTUAL ADDRESS

 

SPACE

I

SELECTOR

I

SEG 4

SEG 3

1 TO 64K BYTES {

SEG 2

 

SEG 1

 

SEG 0

NOTES: 1. A SELECTOR UNIQUELY IDENTIFIES (NAMES) ONE OF 16K POSSIBLE SEGMENTS IN THE

TASK'SVIRTUAL ADDRESS SPACE.

2.THE SELECTOR VALUE DOES NOT SPECIFY THE SEGMENT'SLOCATION IN PHYSICAL MEMORY.

3.THE SELECTOR DOES NOT IMPLY ANY OVERLAP WITH OTHER SEGMENTS (THIS DEPENDS ON THE BASE ADDRESS OF THE SEGMENT AS SPECIFIED VIA THE MEMORY MANAGEMENT AND PROTECTION INFORMATION).

G3010B

Figure 2-6. Protected Mode Segment Selector Interpretation

As described in the previous section, segment registers define the set of four segments currently addressable by a program. A pointer, base, or index register may contain an offset value relative to the start of one of these segments; it thereby points to a particular operand's location within that segment. To allow for efficient computations of effective address offsets, all base and index registers may participate interchangeably as operands in most arithmetical operations.

Stack operations are facililattd by the stack pointer (SP) ~nd stack frame base (BP) register~_ By specifying offsets into the current stack segment, each of these registers provides access to data on the stack. The SP register is the customary top-of-stack pointer, addressing the uppermost datum on a push-down stack. It is referenced implicitly by PUSH and POP operations, subroutine calls, and interrupt operations. The BP register provides yet another offset into the stack segment. The existence of this stack relative base register, in conjunction with certain addressing modes described in section 2.6.3, is particularly useful for accessing data structures, variables and dynamically allocated work space within the stack.

Stacks in the 80286 are implemented in memory and are located by the stack segment register (SS) and the stack pointer register (SP). A system may have an unlimited number of stacks, and a stack may be up to 64K bytes long, the maximum length of a segment.

One stack is directly addressable at a time; this is the current stack, often referred to simply as "the" stack. SP contains the current top of the stack (TOS). In other words, SP contains the offset to the top of the push down stack from the stack segment's base address. Note, however, that the stack's base address (contained in SS) is not the "bottom" of the stack (figure 2-7).

2-10

inter

80286 BASE ARCHITECTURE

-

l

+

LOGICAL

BOTTOM OF STACK (initial SP value)

POP-UP

LOGICAL

TOP OF STACK

PUSH-DOWN

I

SS I SP

I

STACK SEGMENT BASE ADDRESS

G3010B

Figure 2-7_ 80286 Stack

80286 stack entries are 16 bits wide. Instructions operate on the stack by adding and removing stack items one word at a time, An item is pushed onto the stack (see figure 2-8) by decrementing SP by 2 and writing the item at the new TOS. An item is popped off the stack by copying it from TOS and then incrementing SP by 2. In other words, the stack grows down in memory toward its base address. Stack operations never move items on the stack; nor do they erase them. The top of the stack changes only as a result of updating the stack pointer.

The stack frame base pointer (BP) is often used to access elements on the stack relative to a fixed point on the stack rather than relative to the current TOS. It typically identifies the base address of the current stack frame established for the current procedure (figure 2-9). If an index register is used relative to BP (e.g., base + index addressing mode using BP as the base), the offset will be calculated automatically in the current stack segment.

Accessing data structures in data segments is facilitated by the BX register, which has the same function in addressing operands within data segments that BP does for stack segments. They are called base registers because they may contain an offset to the base of a data structure. The similar usage of these two registers is especially important when discussing addressing modes (see section 2.4, "Addressing Modes").

Operations on data are also facilitated by the SI and DI registers. By specifying an offset relative to the start of the currently addressable data segment, an index register can be used to address an operand in the segment. If an index register is used in conjunction with the BX base register (i.e., base + index addressing) to form an offset address, the data is also assumed to reside in the current data segment. As a rule, data referenced through an index register or BX is presumed to reside in the current data segment. That is, if an instruction invokes addressing for one of its operands using either BX, DI, SI, or BX with SI or DI, the contents of the register(s) (BX, DI, or SI) implicitly specify an offset in the current data segment. As previously mentioned, data referenced via SP, BP or BP with SI or DI implicitly specify an operand in the current stack segment (refer to table 2-1).

2-11

80286 BASE ARCHITECTURE

STACK OPERATION FOR CODE SEQUENCE:

 

 

 

STACK

 

 

 

 

 

 

PUSH AX

 

 

 

 

SEGMENT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

POP AX

 

 

 

 

 

 

 

 

 

 

 

 

 

POPBX

 

 

 

1062

0

0

0

0

 

1"~~

 

 

 

 

 

 

105A

4

4

4

4

 

 

 

 

 

 

 

1060

 

 

 

 

 

 

 

 

 

 

 

 

 

lOSE

2

2

2

2

 

 

 

 

 

 

 

 

 

105C

3

3

3

3

 

OF STACK

 

 

 

 

 

 

 

 

 

 

 

 

I

 

1058

5

5

5

5

 

 

 

 

 

SS

 

 

1056

6

6

6

6

 

 

 

 

 

 

SP

1054

7

7

 

7

 

NOT PRESENTLV

I SELECTOR

I OFFSET

I

1052

8

8

8

8

 

USED

 

 

 

 

 

 

 

 

I

 

 

 

1050

9

9

9

9

 

 

 

 

 

 

 

 

00001

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

EXISTING STACK BEFORE PUSH

 

 

 

 

 

 

 

 

 

 

 

 

 

STACK

 

 

 

 

 

 

 

 

 

 

 

SEGMENT

 

 

 

 

 

 

 

 

 

1062

0

0

0

0

 

 

 

 

 

 

 

 

 

1060

1

 

 

 

 

 

 

 

 

 

 

 

 

lOSE

2

2

2

 

 

 

 

 

 

 

 

 

 

105C

3

3

3

3

 

 

 

 

 

 

 

 

 

105A

4

4

4

4

 

 

 

 

 

 

 

 

 

1058

5

5

5

5

 

 

PUSH AX

 

 

 

I

 

1056

A

A

A

A-4 A

A

A

A

SS

 

SP

1054

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I SELECTOR

I

I

1052

8

8

8

8

 

 

 

 

 

OFFSET

1050

9

9

9

9

I

 

 

 

 

 

 

 

 

00001

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STACK

 

 

 

 

 

 

 

 

 

 

 

 

SEGMENT

 

 

 

 

 

 

 

 

 

1062

0

0

0

0

 

 

 

 

 

 

 

 

 

1060

 

 

 

 

 

 

 

 

 

 

 

 

 

lOSE

 

2

2

2

 

 

POP BX

 

 

 

 

 

 

 

 

 

:3

 

 

 

 

 

 

 

105C

3

3

3

 

15

5

5

5

 

 

 

 

105A

4

4

4

4

 

 

 

I

 

 

 

j

 

 

 

 

 

1058

5

5

5

5

 

 

 

 

 

 

 

 

 

 

J

 

 

SS

 

 

SP

1056

A

A

A

A

 

 

 

 

 

I SELECTOR

I OFFSET

I

1054

7

7

7

7

 

I A

 

 

A I

1052

8

8

8

8

 

A

A

 

 

 

 

1050

9

9

9

9

 

 

POP AX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00001

 

 

 

I

 

 

 

G30108

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2-8. Stack Operation

2-12

80286 BASE ARCHITECTURE

BP IS A CONSTANT POINTER TO STACK BASED VARIABLES AND WORK SPACE, ALL REFERENCES USE BP AND ARE INDEPENDENT OF SP, WHICH MAY VARY DURING A ROUTINE EXECUTION,

PROC N

 

 

 

PUSH AX

 

 

 

PUSH ARRALSIZE

 

 

 

CALL PROC_N+1

-----.....~ PROC_N+1:

 

 

 

PUSH BP

 

 

 

PUSH CX

 

 

 

MOV BP, SP

 

 

 

SUB SP, WORK_SPACE

 

 

"PROCEDURE BODY"

 

 

 

MOV SP, BP

 

 

 

POP CX

 

 

 

POP BP

 

 

 

RET

 

 

'['

r

 

BOTTOMOF

t

 

 

S TACK

PARAMETERS

 

 

 

RETURN ADDR

1"'--'

.-

REGISTERS

I

BP I

 

L __ ..I

WORK_SPACE

PARAMETERS

RETURN ADDR

REGISTERS

WORK_SPACE

PROCEDURE N STACK FRAME

IPROCEDURE N+ 1 STACK FRAME

DYNAMICALLY ALLOCATED ON DEMAND RATHER THAN STATICALLY

---

TOP OF STACK

 

 

STACK SEGMENT BASE

G30108

Figure 2-9. BP Usage as a Stack Frame Base Pointer

2-13

80286 BASE ARCHITECTURE

Table 2-1. Implied Segment Usage by Index, Pointer, and Base Registers

Register

Implied Segment

SP

55

BP

SS

BX

OS

SI

OS

01

OS, ES for String Operations

BP + 51, 01

SS

BX + SI, 01

OS

NOTE:

All implied Segment usage, except SP to SS and 01 to ES for String Operations, may be explicitly specified with a segment override prefix for any of the four segments. The prefix precedes the instruction for which explicit reference is desired.

There are two exceptions to the rules listed above. The first concerns the operation of certain 80286 string instructions. For the most flexibility, these instructions assume that the DI register addresses destination strings not in the data segment, but rather in the extra segment (ES register). This allows movement of strings between different segments. This has led to the descriptive names "source index" and "destination index." In all cases other than string instructions, however, the SI and DI registers may be used interchangeably to reference either source or destination operands.

A second more general override capability allows the programmer complete control of which segment is used for a specific operation. Segment-override prefixes, discussed in section 2.4.3, allow the index and base registers to address data in any of the four currently addressable segments.

2.3.4 Status and Control Registers

Two status and control registers are of immediate concern to applications programmers: the instruction pointer and the FLAGS registers.

The instruction pointer register (IP) contains the offset address, relative to the start of the current code segment, of the next sequential instruction to be executed. Together, the CS:IP registers thus define a 32-bit program-counter. The instmction pointer is not directly visible to the programmer; it is controlled implicitly, by interrupts, traps, and control-transfer operations.

The FLAGS register encompasses eleven flag fields, mostly one-bit wide, as shown in figure 2-10. Six of the flags are status flags that record processor status information. The status flags are affected by the execution of arithmetic and logical instructions. The carry flag is also modifiable with instructions that will clear, set or complement this flag bit. See Chapters 3 and 4.

The carry flag (CF) generally indicates a carry or borrow out of the most significant bit of an 8- or 16-bit operand after performing an arithmetic operation; this flag is also useful for bit manipuiation operations involving the shift and rotate instructions. The effect on the remaining status flags, when defined for a particular instruction, is generally as follows: the zero flag (ZF) indicates a zero result when set; the sign flag (SF) indicates whether the result was negative (SF= 1) or positive (SF=O); when set, the overflow flag (OF) indicates whether an operation results in a carry into the high order bit of the result but not a carry out of the high-order bit, or vice versa; the parity flag (PF) indicates whether the modulo 2 sum of the low-order eight bits of the operation is even (PF=O) or odd (PF= 1) parity. The auxiliary carry flag (AF) represents a carry out of or borrow into the least significant 4-bit digit when performing binary coded decimal (BCD) arithmetic.

2-14

80286 BASE ARCHITECTURE

STATUS FLAGS:

 

 

 

 

 

 

 

 

 

CARRY--------

____________________________--

,

PARITY --------

 

 

___________________--,

 

AUXILIARY CARRY ___________________-'-..,

 

 

ZERO

 

 

 

____-,

 

 

I

 

SIGN -------------

 

 

 

 

 

 

OVERFLOW

 

 

12 ~11 10

 

I

 

 

 

 

o

15

14

13

9

B 7

6

5

4

3 2 1

FLAGS: _

NT

10rL

OF I OF

IF

I TF I SF

I ZF

_

AF

_

 

 

 

 

 

)1

::7~;~"

 

 

 

 

 

 

 

 

 

INTERRUPT ENABLE

 

 

 

 

 

'

---------

 

DIRECTION FLAG

 

 

 

 

 

 

 

 

 

SPECIAL FIELDS:

 

 

 

 

 

' --------------

 

 

1/0 PRIVILEGE LEVEL

 

 

 

' --------------------

 

 

 

 

NESTED TASK FLAG

 

 

_ INTEL RESERVED

G30108

Figure 2-10. Flags Register

The FLAGS register also contains three control flags that are used, under program control, to direct certain processor operations. The interrupt-enable flag (IF), if set, enables external interrupts; other· wise, interrupts are disabled. The trap flag (TF), if set, puts the processor into a single-step mode for debugging purposes where the target program is automatically interrupted to a user supplied debug routine after the execution of each target program instruction. The direction flag (DF) controls the forward or backward direction of string operations: 0 = forward or auto increment the address registeres) (SI, DI or SI and DI), 1 = backward or auto·decrement the address register(s) (SI, DI or SI and DI).

In general, the interrupt enable flag may be set or reset with special instructions (STI = set, CLI = clear) or by placing the flags on the stack, modifying the stack, and returning the flag image from the stack to the flag register. If operating in Protected Mode, the ability to alter the IF bit is subject to protection checks to prevent non·privileged programs from effecting the interrupt state of the CPU. This applies to both instruction and stack options for modifying the IF bit.

The TF flag may only be modified by copying the flag register to the stack, setting the TF bit in the stack image, and returning the modified stack image to the flag register. The trap interrupt occurs on completion of the next instruction. Entry to the single step routine saves the flag register on the stack with the TF bit set, and resets the TF bit in the register. After completion of the single step routine, the TF bit is automatically set on return to the program being single stepped to interrupt the program again arkr completion of the next instruction. Use of TF is not inhibited by the protection mechanism in Proteckd Mode.

2-15

80286 BASE ARCHITECTURE

The DF flag, like the IF flag, is controlled by instructions (CLD = clear, STD = set) or flag register modification through the stack. Typically, routines that use string instructions will save the flags on the stack, modify DF as necessary via the instructions provided, and restore DF to its original state by restoring the Flag register from the stack before returning. Access or control of the DF flag is not inhibited by the protection mechanism in Protected Mode.

The Special Fields bits are only relevant in Protected Mode. Real Address Mode programs should treat these bits as don't-care's, making no assumption about their status. Attempts to modify the 10PL and NT fields are subject to protection checking in Protected Mode. In general, the application's programmer will not be able to and should not attempt to modify these bits. (See section 10.3, "Privileged and Trusted Instructions" for more details.)

2.4 ADDRESSING MODES

The information encoded in an 80286 instruction includes a specification of the operation to be performed, the type of the operands to be manipulated, and the location of these operands. If an operand is located in memory, the instruction must also select, explicitly or implicitly, which of the currently addressable segments contains the operand. This section covers the operand addressing mechanisms; 80286 operators are discussed in Chapter 3.

The five elements of a general in~truction are briefly described below. The exact format of 80286 instructions is specified in Appendix B.

The opcode is present in all instructions; in fact, it is the only required element. Its principal function is the specification of the operation performed by the instruction.

A register specifier.

The addressing mode specifier, when present, is used to specify the addressing mode of an operand for referencing data or performing indirect calls or jumps.

The displacement, when present, is used to compute the effective address of an operand in memory.

The immediate operand, when present, directly specifies one operand of the instruction.

Of the four elements, only one, the opcode, is always present. The other elements mayor may not be present, depending on the particular operation involved and on the location and type of the operands.

2.4.1 Operands

Generally speaking, an instruction is an operation performed on zero, one, or two operands, which are the data manipulated by the instruction. An operand can be located either in a register (AX, BX, ex, ox, SI, DI, SP, or BP in the case of 16-bii operands; AR, AL, BR, BL, CR, CL, DIl, or DL in the case of 8-bit operands; the FLAG register for flag operations in the instruction itself (as an immediate operand», or in memory or an I/O port. Immediate operands and operands in registers can be accessed more rapidly than operands in memory since memory operands must be fetched from memory while immediate and register operands are available in the processor.

An 80286 instruction can reference zero, one, or two operands. The three forms are as follows:

Zero-operand instructions, such as RET, NOP, and HLT. Consult Appendix B.

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80286 BASE ARCHITECTURE

One-operand instructions, such as INC or DEC. The location of the single operand can be specified implicitly, as in AAM (where the register AX contains the operand), or explicitly, as in INC (where the operand can be in any register or memory location). Explicitly specified operands are accessed via one of the addressing modes described in section 2.4.2.

Two operand instructions such as MOV, ADD, XOR, etc., generally overwrite one of the two participating operands with the result. A distinction can thus be made between the source operand (the one left unaffected by the operation) and the destination operand (the one overwritten by the result). Like one-operand instructions, two-operand instructions can specify the location of operands either explicitly or implicitly. If an instruction contains two explicitly specified operands, only one of them-either the source or the destination-can be in a register or memory location. The other operand must be in a register or be an immediate source operand. Special cases of two-operand instructions are the string instructions and stack manipulation. Both operands of some string instructions are in memory and are explicitly specified. Push and pop stack operations allow transfer between memory operands and the memory based stack.

Thus, the two-operand instructions of the 80286 permit operations of the following sort:

Register-to-register

Register-to-memory

Memory-to-register

Immediate-to-register

Immediate-to-memory

Memory-to-memory

Instructions can specify the location of their operands by means of eight addressing modes, which are described in sections 2.4.2 and 2.4.3.

2.4.2 Register and Immediate Modes

Two addressing modes are used to reference operands contained in registers and instr.uctions:

Register Operand Mode. The operand is located in one of the 16-bit registers (AX, BX, CX, DX, sr, DI, SP, or BP) or in one of the 8-bit general registers (AR, BR, CR, DR, AL, BL, CL, or DL).

Special instructions are also included for referencing the CS, DS, ES, SS, and Flag registers as operands also.

Immediate Operand Mode. The operand is part of the instruction itself (the immediate operand element).

2.4.3 Memory Addressing Modes

Six modes are used to access operands in memory. Memory operands are accessed by means of a pointer consisting of a segment selector (see section 2.3.2) and an offset, which specifies the operand's displacement in bytes from the beginning of the segment in which it resides. Both the segment selector component and the offset component are 16-bit values. (See section 2.1 for a discussion of segmentation.) Only some instructions use a full 32-bit address.

2-17

80286 BASE ARCHITECTURE

Most memory references do not require the instruction to specify a full 32-bit pointer address. Operands that are located within one of the currently addressable segments, as determined by the four segment registers (see section 2.3.2, "Segment Registers"), can be referenced very efficiently simply by means of the 16-bit offset. This form of address is called by short address. The choice of segment (CS, DS, ES, or SS) is either implicit within the instruction itself or explicitly specified by means of a segment override prefix (see below).

See figure 2-11 for a diagram of the addressing process.

2.4.3.1 SEGMENT SELECTION

All instructions that address operands in memory must specify the segment and the offset. For speed and compact instruction encoding, segment selectors are usually stored in the high speed segment registers. An instruction need specify only the desired segment register and an offset in order to address a memory operand.

Most instructions need not explicitly specify which segment register is used. The correct segment register is automatically chosen according to the rules of table 2-1 and table 2-2. These rules follow the way programs are written (see figure 2-12) as independent modules that require areas for code and data, a stack, and access to external data areas.

There is a close connection between the type of memory reference and the segment in which that operand resides (see the next section for a discussion of how memory addressing mode calculations are performed). As a rule, a memory reference implies the current data segment (Le., the implicit segment selector is in DS) unless the BP register is involved in the address specification, in which case the current stack segment is implied (i.e, SS contains the selector).

 

POINTER

 

 

I SEGMENT

 

 

OFFSET

 

-----~--r~~------~ SEGMENT

31

16

15

0

 

 

 

 

OPERAND

 

 

 

 

SELECTED

SELECTED

 

 

 

1MEMORY

1

G3010B

Figure 2-11. Two-Component Address

2-18

80286 eASE ARCHITECTURE

Table 2-2. Segment Register Selection Rules

Memory

Segment Register

Implicit Segment

Reference Needed

Used

Selection Rule

Instructions

Code (CS)

Automatic with instruction prefetch.

Stack

Stack (SS)

All stack pushes and pops. Any memory refer-

 

 

ence which uses BP as a base register.

Local Data

Data (OS)

All data references except when relative to stack

 

 

or string destination.

External (Global) Data

Extra (ES)

Alternate data segment and destination of string

 

 

operation.

The 80286 instruction set defines special instruction prefix elements (see Appendix B). One of these is SEG, the segment-override prefix. Segment-override prefixes allow an explicit segment selection. Only in two special cases-namely, the use of DI to reference destination strings in the ES segment, and the use of SP to reference stack locations in the SS segment-is there an implied segment selection which cannot be overridden. The format of segment override prefixes is shown in Appendix B.

2.4.3.2 OFFSET COMPUTATION

The offset within the desired segment is calculated in accordance with the desired addressing mode. The offset is calculated by taking the sum of up to three components:

the displacement element in the instruction

the base (contents of BX or BP-a base register) the index (contents of SI or DI-an index register)

Each of the three components of an offset may be either a positive or negative value. Offsets are calculated modulo 216.

The six memory addressing modes are generated using various combinations of these three components. The six modes are used for accessing different types of data stored in memory:

addressing mode

offset calculation

direct address

displacement alone

register indirect

base or index alone

based

base + displacement

indexed

index + displacement

based indexed

base + index

based indexed with

base + index + disp

displacement

 

In all six modes, the operand is located at the specified offset within the selected segment. All displacements, except direct address mode, are optionally 8- or 16-bit values. 8-bit displacements are automatically sign-extended to 16 bits. The six addressing modes are described and demonstrated in the following section on memory addressing modes.

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80286 BASE ARCHITECTURE

r---...,

 

I

I

 

 

ODE

 

MODULE A

~

 

 

 

 

 

DATA

 

 

 

CODE

 

CPU

 

 

 

MODULE B

 

L I-

 

 

DATA

CODE

 

I

I

DATA

 

I

I

 

 

 

 

STACK

PROCESS

 

- I-

EXTRA

STACK

 

 

 

 

SEGMENT

 

I

I

REGISTERS

 

 

 

I

I

 

PROCESS [l

DATA

BLOCK 1

PRog~~~D

BLOCK 2

I I

L ___ .J

MEMORY

G301uo

Figure 2-12. Use of Memory Segmentation

2.4.3.3 MEMORY MODE

Two modes are !.!sed for simple scalar operands located in memory:

Direct Address Mode. The offset of the operand is contained in the instruction as the displacement element. The offset is a 16-bit quantity.

Register Indirect Mode. The offset of the operand is in one of the registers SI, DI, or BX. (BP is excluded; if BP is used as a stack frame base, it requires an index or displacement component to reference either parameters passed on the stack or temporary variables allocated on the stack. The instruction level bit encoding for the BP only address mode is used to specify Direct Address mode. See Chapter 12 for more details.)

2-20

80286 BASE ARCHITECTURE

The following four modes are used for accessing complex data structures in memory (see figure 2-13):

Based Mode. The operand is located within the selected segment at an offset computed as the sum of the displacement and the contents of a base register (BX or BP). Based mode is often used to access the same field in different copies of a structure (often called a record). The base register points to the base of the structure (hence the term "base" register), and the displacement selects a particular field. Corresponding fields within a collection of structures can be accessed simply by changing the base register. (See figure 2-13, example 1.)

Indexed Mode. The operand is located within the selected segment at an offset computed as the sum of the displacement and the contents of an index register (SI or DI). Indexed mode is often used to access elements in a static array (e.g., an array whose starting location is fixed at translation time). The displacement locates the beginning of the array, and the value of the index register selects one element. Since all array elements are the same length, simple arithmetic on the index register will select any element. (See figure 2-13, example 2.)

Based Indexed Mode. The operand is located within the selected segment at an offset computed asthe sum of the base register's contents and an index register's contents. Based Indexed mode is often used to access elements of a dynamic array (i.e., an array whose base address can change during execution). The base register points to the base of the array, and the value of the index register is used to select one element. (See figure 2-13, example 3.)

Based Indexed Mode with Displacement. The operand is located with the selected segment at an offset computed as the sum of a base register's contents, an index register's contents, and the displacement. This mode is often used to access elements of an array within a structure. For example, the structure could be an activation record (i.e., a region of the stack containing the register contents, parameters, and variables associated with one instance of a procedure); and one variable could be an array. The base register points to the start of the activation record, the displacement expresses the distance from the start of the record to the beginning of the array variable, and the index register selects a particular element of the array. (See figure 2-13, example 4.)

Table 2-3 gives a summary of all memory operand addressing options.

2.5 INPUT/OUTPUT

The 80286 allows input/output to be performed in either of two ways: by means of a separate I/0 address space (using specific I/O instructions) or by means of memory-mapped I/O (using generalpurpose operand manipulation instructions).

Table 2-3. Memory Operand A'ddressingModes

Addressing Mode

Offset Calculation

Direct

16-bit Displacement in the instruction

Register Indirect

BX, 51, 01

Based

(BX or BP) + Displacement"

Indexed

(51 or 01) + Displacement"

Based Indexed

(BX or BP) + (51 or 01)

Based Indexed + Displacement

(BX or BP) + (SI or 01) + Displacement"

" The displacement can be a 0, 8 or 16-bit value.

 

2-21

80286 BASE ARCHITECTURE

 

 

,

1. BASED MODE

 

 

MOV AX, [BP + DATE-CODE]

 

 

ADD [BX + BALANCE], CX

 

~ OPERAND

I

DISPL

L

+

 

BASE

 

I

+

 

SEGMENT

 

2. INDEXED MODE

 

r

MOV ID [SI], DX

 

 

SUB BX, DATA_TBL[SI]

 

 

I

INDEX

~ OPERAND

I

+

 

DISPL

 

 

+

 

L

SEGMENT

J

3. BASED INDEXED

 

'I'

MOV DX, [BP][ill]

 

 

AND [aX + S~, 3FFH

 

~ OPERAND

I

INDEX

 

+

 

1

BASE

 

 

+

 

1 SEGMENT

'r

I

r

FIXED ) ARRAY

, IBASED ARRAY

MOV CX, [ap][si + CNT]

SHR [ax + 01 + MASK]

BASED

STRUCTURE

CONTAINING

ARRAY

G3010B

Figure 2-13. Complex Addressing Modes

2-22

80286 BASE ARCHITECTURE

2.5.1 1/0 Address Space

The 80286 provides a separate I/O address space, distinct from physical memory, to address the input/ output ports that are used for external devices. The I/0 address space consists of 216 (64K) individually addressable 8-bit ports. Any two consecutive 8-bit ports can be treated as a 16-bit port. Thus, the I/0 address space can accommodate up to 64K 8-bit ports or up to 32K 16-bit ports. I/0 port addresses 00F8H to OOFFH are reserved by Intel.

The 80286 can transfer either 8 or 16 bits at a time to a device located in the I/O space. Like words in memory, 16-bit ports should be aligned at even-numbered addresses so that the 16 bits will be transferred in a single access. An 8-bit port may be located at either an even or odd address. The internal registers in a given peripheral controller device should be assigned addresses as shown below.

Port Register

Port Addresses

Example

16-bit

even word addresses

OUT

FE,AX

a-bit; device on lower half

even byte addresses

IN

AL,FE

of 16-bit data bus

 

 

 

a-bit; device on upper half

odd byte addresses

OUT

FF,AL

of 16-bit data bus

 

 

 

The I/0 instructions IN and OUT (described in section 3.11.3) are provided to move data between I/0 ports and the AX (l6-bit I/O) or AL (8-bit I/O) general registers. The block I/O instructions INS and OUTS (described in section 4.1) move blocks of data between I/0 ports and memory space (as shown below). In Protected Mode, an operating system may prevent a program from executing these I/0 instructions. Otherwise, the function of the I/0 instructions and the structure of the I/0 space are identical for both modes of operation.

INS es:byte ptr [dil, DX

OUTS DX, byte ptr [sil

IN and OUT instructions address I/O with either a direct address to one of up to 256 port addresses, or indirectly via the DX register to one of up to 64K port addresses. Block I/0 uses the DX register to specify the I/0 address and either SI or DI to designate the source or destination memory address. For each transfer, SI or DI are either incremented or decremented as specified by the direction bit in the flag word while DX is constant to select the I/0 device.

2.5.2 Memory-Mapped 1/0

I/0 devices also may be placed in the 80286 memory address space. So long as the devices respond like memory components, they are indistinguishable to the processor.

Memory-mapped I/0 provides additional programming flexibility. Any instruction that references memory may be used to access an I/0 port located in the memory space. For example, the MOY instruction can transfer data between any register and a port; and the AND, OR, and TEST instructions may be used to manipulate bits in the internal registers of a device (see figure 2-14). Memorymapped I/0 performed via the full instruction set maintains the full complement of addressing modes for selecting the desired I/0 device.

Memory-mapped I/O, like any other memory reference, is subject to access protection and control when executing in protected mode.

2-23

80286 BASE ARCHITECTURE

MEMORY

 

ADDRESS SPACE

110 DEVICE 1

INTERNAL REGISTER

1-------11-- =====~I....___.....

110 DEVICE 2

INTERNAL REGISTER

1 ------- 1 ======~I....___.....

G30108

Figure 2-14. Memory-Mapped 1/0

2.6 INTERRUPTS AND EXCEPTIONS

The 80286 architecture supports several mechanisms for interrupting program execution. Internal interrupts are synchronous events that are the responses of the CPU to certain events detected during the execution of an instruction. External interrupts are asynchronous events typically triggered by external devices needing attention. The 80286 supports both maskable (controlled by the IF flag) and non-maskable interrupts. They cause the processor to temporarily suspend its present program execution in order to service the requesting device. The major distinction between these two kinds of inter- rupts is their origin; art internal interrupt is always repioducible by re-executing \vith the program and data that caused the interrupt, whereas an external interrupt is generally independent of the currently executing task.

Interrupts 0-31 are reserved by Intel.

Application programmers will normally not be concerned with servicing external interrupts. More information on external interrupts for system programmers may be found in Chapter 5, section 5.2, "Interrupt Handling for Real Address Mode," and in Chapter 9, "Interrupts, Traps and Faults for Protected Virtual Address Mode."

In Real Address Mode, the application programmer is affected by two kinds of internal interrupts. (Internal interrupts are the result of executing an instruction which causes the interrupt.) One type of interrupt is called an exception because the interrupt only occurs if a particular fault condition exists. The other type of interrupt generates the interrupt every time the instruction is executed.

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