Fairchild Semiconductor 100351SCX, 100351SC, 100351QIX, 100351QI, 100351QCX Datasheet

© 2000 Fairchild Semiconductor Corporation DS009885 www.fairchildsemi.com

July 1988
Revised August 2000

100351 Low Power Hex D-Type Flip-Flop

100351
Low Power Hex D-Type Flip-Flop

General Description

The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and compl emen t outputs , a pair of
common Clock inputs (CP

a

and CPb) and common Master

Reset (MR) input. Data enters a master when both CP

a

and CPb are LOW and transfers to the slave when CPa and
CP

b

(or both) go HIGH. The MR input override s all other

inputs and makes the Q outputs LOW. All inputs have
50 k

Ω pull-down resistors.

Features

■ 40% power reduction of the 100151

■ 2000V ESD protection

■ Pin/function compatible with 100151

■ Voltage compensated operating range:

−4.2V to −5.7V

■ Available to industrial grade temperature range

Ordering Code:

Devises also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PLCC

Order Number Package Number Package Description

100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (

−40°C to +85°C)

Pin Names Description

D

0–D5

Data Inputs

CP

a

, CP

b

Common Clock Inputs
MR Asynchronous Master Reset Input
Q

0–Q5

Data Outputs
Q

0–Q5

Complementary Data Outputs

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100351

Truth Tables

(Each Flip-flop)

Synchronous Operation

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

t = Time before CP positive transition

t+1 = Time after CP positive transiti on



= LOW-to-HIGH transition

Asynchronous Operati on

Logic Diagram

Inputs Outputs

D

n

CP

a

CP

b

MR Qn(t+1)

L



LL L

H



LL H

LL



LL

HL



LH

XH



LQ

n

(t)

X



HL Q

n

(t)

XL LL Q

n

(t)

Inputs Outputs

D

n

CP

a

CP

b

MR Qn(t+1)

XXXH L

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100351

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are those value s beyond which

the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version
DC Electrical Characteristics

(Note 3)

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND, T

C

= 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasin g the al l owable syste m opera ti ng ran ge s. Cond it i ons fo r t estin g sho w n in the tabl es are cho­sen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

V

EE

= −4.2V to −5.7V, VCC = V

CCA

= GND

Storage Temperature (T

STG

) −65°C to +150°C

Maximum Junction Temperature (T

J

) +150°C

V

EE

Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current (DC Output HIGH)

−50 mA

ESD (Note 2)

≥2000V

Case Temperature (T

C

)

Commercial 0

°C to +85°C

Industrial

−40°C to +85°C

Supply Voltage (V

EE

) −5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

V

OH

Output HIGH Voltage −1025 −955 −870

mV

VIN =VIH (Max) Loading with

V

OL

Output LOW Voltage −1830 −1705 −1620 or VIL (Min) 50Ω to −2.0V

V

OHC

Output HIGH Voltage −1035

mV

VIN = VIH (Min) Loading with

V

OLC

Output LOW Voltage −1610 or VIL (Max) 50Ω to −2.0V

V

IH

Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

V

IL

Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

I

IL

Input LOW Current 0.50 µAVIN = VIL (Min)

I

IH

Input HIGH Current

MR 350

D

0–D5

240 µAVIN = VIH (Max)

CP

a

, CP

b

350

I

EE

Power Supply Current −129 −62 mA Inputs OPEN

Symbol Parameter

TC = 0°CT

C

= +25°CT

C

= +85°C

Units Conditions

Min Max Min Max Min Max

f

MAX

Toggle Frequency 375 375 375 MHz Figures 2, 3

t

PLH

Propagation Delay

0.80 2.00 0.80 2.0 0.90 2.10 ns Figures 1, 3

t

PHL

CPa, CPb to Output

t

PLH

Propagation Delay

1.10 2.30 1.10 2.30 1.20 2.40 ns Figures 1, 4

t

PHL

MR to Output

t

TLH

Transition Time

0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 3

t

THL

20% to 80%, 80% to 20%

t

S

Setup Time
D0–D

5

0.40 0.40 0.40 ns Figure 5

MR (Release Time) 1.60 1.60 1.60 Figure 4

t

H

Hold Time

0.80 0.80 0.80 ns Figure 5

D0–D

5

tPW(H) Pulse Width HIGH

2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR