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1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
ClockWorks™
SY10E111
SY100E111
FEATURES
■ Low skew
■ Extended 100E VEE range of –4.2V to –5.5V
■ Guaranteed skew limits
■ Differential design
■ VBB output
■ Enable input
■ Fully compatible with industry standard 10KH, 100K
I/O levels
■ 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E111
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
IN
Q4
DESCRIPTION
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or
single-ended input, with VBB used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
The VBB output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using VBB for this purpose, it is
recommended that VBB is decoupled to VCC via a 0.01µF
capacitor.
V
IN
EN
BB
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Rev.: B Amendment: /2
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Issue Date: February, 1998
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Micrel
IN
t
r
IN
EN
Q
Q
50%
ClockWorks™
SY10E111
SY100E111
PIN CONFIGURATION
0
0
1
Q
Q
Q
24 23 22 21 20 19
25
V
EE
26
EN
V
V
NC
IN
CC
IN
BB
27
28
1
2
3
4
567891011
TOP VIEW
8
8
Q
Q
PLCC
J28-1
7
Q
CCO
V
CCO
V
2
2
1
Q
Q
Q
Q
18
17
16
15
14
13
12
6Q6
7
Q
Q
3
Q
3
Q
4
V
CCO
Q
4
Q
5
Q
5
PIN NAMES
Pin Function
IN, IN Differential Input Pair
EN Enable Input
Q0, Q0 — Q8, Q8 Differential Outputs
VBB VBB Output
CCO VCC to Output
V
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
V
BB Output Reference V —
Voltage 10E –1.38 —–1.27 –1.35 —–1.25 –1.31 —–1.19
100E –1.38 —–1.26 –1.38 —–1.26 –1.38 —–1.26
IIH Input HIGH Current ——150 ——150 ——150 µA —
EE Power Supply mA —
I
Current 10E — 48 60 — 48 60 — 48 60
100E — 48 60 — 48 60 — 55 69
TIMING DIAGRAMS
IN
IN
t
s
50%
EN
75 mV
Q
Q
75 mV
Figure 1. Set-up Time
IN
IN
EN
Q
Q
Figure 2. Hold Time
t
h
50%
75 mV
75 mV
Figure 3. Release Time
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ClockWorks™
SY10E111
Micrel
SY100E111
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
tPLH Propagation Delay to Output ps
t
PHL IN (differential) 430 — 630 430 — 630 430 — 630 1
IN (single-ended) 330 — 730 330 — 730 330 — 730 2
Enable 450 — 850 450 — 850 450 — 850 3
Disable 450 — 850 450 — 850 450 — 850 3
tSKEW Within-Device Skew — 25 50 — 25 50 — 25 50 ps 4
tS Set-up Time, EN to IN 200 0 — 200 0 — 200 0 — ps 5
tH Hold Time, IN to EN 0 –200 — 0 –200 — 0 –200 — ps 6
tR Release Time, EN to IN 300 100 — 300 100 — 300 100 — ps 7
VPP Minimum Input Swing 250 ——250 ——250 ——mV 8
VCMR Common Mode Range –1.6 —–0.4 –1.6 —–0.4 –1.6 —–0.4 V 9
r Rise/Fall Times 275 375 600 275 375 600 275 375 600 ps —
t
tf 20% to 80%
NOTES:
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential
output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q (or a negative
transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the 50% point of a negative transition
on Q (or a positive transition on Q).
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. The set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75mV to
that IN/IN transition (see Figure 1).
6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response greater
than ±75mV to that IN/IN transition (see Figure 2).
7. The release time is the minimum time that EN must be de-asserted prior to the next IN/IN transition to ensure an output response that meets the specified
IN to Q propagation delay and output transition times (see Figure 3).
8. VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min.) is AC limited for the
E111, as a differential input as low as 50mV will still produce full ECL levels at the output.
9. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be
such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.).
(1-9)
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E111JC J28-1 Commercial
SY10E111JCTR J28-1 Commercial
SY100E111JC J28-1 Commercial
SY100E111JCTR J28-1 Commercial
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Micrel
28 LEAD PLCC (J28-1)
ClockWorks™
SY10E111
SY100E111
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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