Datasheet SY100S336A Datasheet (MICREL)

ENHANCED 4-STAGE

R

COUNTER/SHIFT REGISTER

SY100S336A

FEATURES

■ Max. shift frequency of 700MHz

■ Clock to Q delay max. of 1100ps

■ S

n to TC speed improved by 50%

■ Sn set-up and hold time reduced by more than 50%

■ IEE min. of –170mA

■ Industry standard 100K ECL levels

■ Internal 75KΩ input pull-down resistors

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved

noise immunity

■ 50% faster than Fairchild 300K at lower power

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

PIN CONFIGURATIONS

3

3

3

P1P2P

P

0

12

CP

13

V

EE

14

V

EES

15

MR

16
17

0

S
S

1

1911201021922823724

2

S

EES

V

Top View

PLCC
J28-1

EES

CEP

/CET

V

0

D

D

Q3Q

6

0

Q

TC

S2

CEP

D0/CET

TC
Q0
Q

25

5

Q

2

4
3

Q

2

V

CCA

2
1

V

CC

V

CC

28
27

Q

1

2618

0

Q

0

1

Q

S1

S0

M

1
2
3

Top View

Flatpack

4
5
6

F24-1

7248239221021112012

Q1

VCC

VEE

VCCA

CP

19

Q2Q1Q2

P0

18
17
16
15
14
13

P1
P2
P3
D3
Q3
Q3

DESCRIPTION

The SY100S336A is functionally the same as the

SY100S336, but has S

n to TC speed and Sn set-up and

hold times significantly improved, allowing for higher clock
frequency when used as a cascaded multi-stage counter.

The SY100S336A functions either as a modulo-16 up/
down counter or as a 4-bit bidirectional shift register and is
designed for use in high-performance ECL systems. Three
Select inputs (Sn) are provided for determining the mode of
operation. The Function Table lists the available modes of
operation. In order to allow cascading for multistage
counters, two Count Enable controls (CEP, CET) are
provided. The CET input also functions as the Serial Data
input (S0) for a shift-up operation, while the D3 input serves
as the Serial Data input for the shift-down operation.

When the device is in the counting mode, the Terminal
Count (TC) goes to a logical LOW when the count reaches
15 for count-up or reaches 0 for count-down. When in the
shift mode, the TC output simply repeats the Q3 output.

The flexiblity provided by the TC/Q3 output and the D0/
CET input allows these signals to be interconnected from
one stage to the next higher stage for multistage counting
or shift-up operations. The individual Presets (Pn) allow
initialization of the counter by entering data in parallel to
preset the counter. A logic HIGH on the Master Reset (MR)
overrides all other inputs and asynchronously clears the
flip-flops. An additional synchronous Clear is provided, as
well as a complement function which synchronously inverts
the contents of the flip-flops. All inputs have 75KΩ pull­down resistors.

PIN NAMES

Pin Function

CP Clock Pulse Input
CEP Count Enable Parallel Input (Active LOW)
D

0/CET Serial Data Input/Count Enable Trickle

Input (Active LOW)
S0 — S2 Select Inputs
MR Master Reset Input
VEES VEE Substrate
VCCA VCCO for ECL Outputs
P0 – P3 Preset Inputs
D3 Serial Data Input
TC Terminal Count Output
Q0 — Q3 Data Outputs

0 — Q3 Complementary Data Outputs

Q

Rev.: G Amendment: /0

1

Issue Date: July, 1999

Micrel

BLOCK DIAGRAM

S

0

S

1

S

2

SY100S336A

D3

D0/CET

CEP

CP

MR

Q

0

T
T

Q

0

R

T

C

R

Q

1

T

Q

1

R
T

TT

2

Q

T
T

2

Q

R
T

TCTC

P0 Q0 Q0 P1 Q1 Q1 P2 Q2 Q2

T

Q

3

T
T

T
R

Q

3

T

TC

P3 Q3 Q3

TC

2

Micrel

SY100S336A

TRUTH TABLE

(1)

Inputs Outputs

MR S2 S1 S0 CEP D0/CET D3 CP Q0 Q1 Q2 Q3 TC Mode

LLLL X X X uP0 P1 P2 P3 L Preset (Parallel Load)
LLLH X X X uQ0 Q1 Q2 Q3 L Invert
LLHL X X X uQ1 Q2 Q3 D3 D3 Shift Left
LLHH X X X uD0 Q0 Q1 Q2 Q3* Shift Right
LHLL L L X u (Q
LHLL H L X XQ

0–3) minus 1 ① Count Down

0 Q1 Q2 Q3 ① Count Down with CEP

Not Active

LHLL X H X XQ0 Q1 Q2 Q3 H Count Down with CET

Not Active
LHLH X X X uLLLLHClear
LHHL L L X u (Q
LHHL H L X XQ

0–3) plus 1 ≠ Count Up

0 Q1 Q2 Q3 ≠ Count Up with CEP

Not Active
LHHL X H X XQ0 Q1 Q2 Q3 H Count Up with CET

Not Active
LHHH X X X XQ0 Q1 Q2 Q3 H Hold
HLLL X X X XLLLLLAsynchronous Master

HLLHX X X XLLLLLReset
HLHL X X X XLLLLL
HLHHX X X XLLLLL
HHLL X L X XLLLLL
HHLL X H X XLLLLH
HHLHX X X XLLLLH
HHHL X X X XLLLLH
HHHH X X X XLLLLH

NOTE:

1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
u = LOW-to-HIGH Transition
① = L if Q0 – Q3 = LLLL

H if Q0 – Q3 ≠ LLLL

≠ = L if Q0 – Q3 = HHHH

H if Q0 – Q3 ≠ HHHH

* Before the clock, TC is Q3; after the clock, TC is Q2

DC ELECTRICAL CHARACTERISTICS

VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND

Symbol Parameter Min. Typ. Max. Unit Condition

IIH Input HIGH Current, All Inputs ——200 µAVIN = VIH (Max.)

EE Power Supply Current –170 –120 –60 mA Inputs Open

I

3

Micrel

SY100S336A

AC ELECTRICAL CHARACTERISTICS

CERPACK

VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND

TA = 0°CTA = +25°CTA = +85°C

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition

fshift Shift Frequency 700 — 700 — 700 — MHz

PLH Propagation Delay 450 1200 450 1200 450 1200 ps

t
tPHL CP to Qn, Qn

tPLH Propagation Delay 600 1900 600 1900 600 1900 ps
tPHL CP to TC

t

PLH Propagation Delay 500 1400 500 1400 500 1400 ps

tPHL MR to Qn, Qn
tPLH Propagation Delay 600 1900 600 1900 600 1900 ps

tPHL MR to TC

PLH Propagation Delay 400 1200 400 1200 400 1200 ps

t
tPHL D0/CET to TC

PLH Propagation Delay 400 1500 400 1500 400 1500 ps

t
tPHL Sn to TC

TLH Transition Time 300 900 300 900 300 900 ps

t
tTHL 20% to 80%, 80% to 20%

S Set-up Time ps

t

D3 800 — 800 — 800 —
Pn 800 — 800 — 800 —
D0/CET to CEP 700 — 700 — 700 —
Sn 1000 — 1000 — 1000 —
MR (Release Time) 900 — 900 — 900 —

t

H Hold Time ps

D3 200 — 200 — 200 —
Pn 200 — 200 — 200 —
D0/CET to CEP 200 — 200 — 200 —
Sn -200 — -200 — -200 —

pw (H) Pulse Width HIGH, CP, MR — 800 — 800 — 800 ps

t

4

Micrel

SY100S336A

AC ELECTRICAL CHARACTERISTICS

PLCC

VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND

A = 0°CTA = +25°CTA = +85°C

T

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition

fshift Shift Frequency 700 — 700 — 700 — MHz

PLH Propagation Delay 450 1100 450 1100 450 1100 ps

t
tPHL CP to Qn, Qn

tPLH Propagation Delay 600 1800 600 1800 600 1800 ps
tPHL CP to TC

PLH Propagation Delay 500 1300 500 1300 500 1300 ps

t
tPHL MR to Qn, Qn

tPLH Propagation Delay 600 1800 600 1800 600 1800 ps
tPHL MR to TC

PLH Propagation Delay 400 1100 400 1100 400 1100 ps

t
tPHL D0/CET to TC

PLH Propagation Delay 400 1500 400 1500 400 1500 ps

t
tPHL Sn to TC

TLH Transition Time300 900 300 900 300 900 ps

t
tTHL 20% to 80%, 80% to 20%

S Set-up Time ps

t

D3 800 — 800 — 800 —
Pn 800 — 800 — 800 —
D0/CET to CEP 700 — 700 — 700 —
Sn 1000 — 1000 — 1000 —
MR (Release Time) 900 — 900 — 900 —

H Hold Time ps

t

D3 200 — 200 — 200 —
Pn 200 — 200 — 200 —
D0/CET to CEP 200 — 200 — 200 —
Sn -200 — -200 — -200 —

t

pw (H) Pulse Width HIGH, CP, MR — 800 — 800 — 800 ps

5

Micrel

A

K

K

TIMING DIAGRAMS

DAT

CLOC

t

PHL

1/fshift tpw (H)

t

PLH

SY100S336A

0.7 ± 0.1 ns0.7 ± 0.1 ns
–0.95V

80%

50%

20%

–1.69V

OUTPUT

OUTPUT

MR

CLOC

t

PLH

t

PHL

t

TLH

t

THL

Propagation Delay (Clock) and Transition Times

0.7 ± 0.1 ns0.7 ± 0.1 ns

80%

50%

20%

tpw (H)

50%

–0.95V

–1.69V

tS (RELEASE TIME)

50%

t

OUTPUT

PHL

t

PLH

50%

t

PLH

t

PHL

80%

OUTPUT

50%

20%

Propagation Delay (Reset)

6

Micrel

K

–

n

–

–

–

–

–

TIMING DIAGRAMS

SY100S336A

INPUT

OUTPUT

CEP

t

PHL

t

TLH

0.7 ± 0.1 ns0.7 ± 0.1 ns

80%

50%

20%

50%

20%

t

PLH

80%

t

THL

–0.95V

–1.69V

Propagation Delay (Serial Data, Selects)

INHIBIT COUNT

50%

ENABLE COUNT

t

H

t

S

0.95V

1.69V

0.95V

D3, Pn, S

t

H

t

S

CLOC

50%

Set-up and Hold Time

NOTES:

1. VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND.

2. tS is the minimum time before the transition of the clock that information
must be present at the data input.

3. tH is the minimum time after the transition of the clock that information must
remain unchanged at the data input.

50%

1.69V

0.95V

1.69V

PRODUCT ORDERING CODE

Ordering Package Operating

Code Type Range

SY100S336AFC F24-1 Commercial
SY100S336AJC J28-1 Commercial
SY100S336AJCTR J28-1 Commercial

7

Micrel

24 LEAD CERPACK (F24-1)

SY100S336A

Rev. 03

8

Micrel

28 LEAD PLCC (J28-1)

SY100S336A

Rev. 03

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA

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© 2000 Micrel Incorporated

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