Local Control On/Off, Bend Range)
Tuning Control:440Hz ± 100 cents
Terminals:Headphone Jack [Output Impedance: 100 Ω, Output Voltage: 1.7 V(rms)
MAX], Assignable Jack, MIDI Jacks (IN, OUT), AC Adaptor Jack (12V)
Built-In Speakers:12 cm dia. 1.1W Input Rating: 2 pcs.
Power Source:2-way AC or DC source
AC: AC adaptor AD-12
DC: 6 D size dry batteries
Battery life: Approx. 5 hours by manganese batteries R20P(SUM-1)
Approx. 5 hours by alkaline batteries LR20(AM1)
Auto Power Off:Approximately 6 minutes after the last operation
Power Consumption:18 W
Dimentions:141 x 968 x 411 mm (HWD)
(5-11/16 x 38-1/16 x 16-5/16 inches) (HWD)
Weight:7.0 kg (15.5 lbs) excluding batteries
Standard Accessory:Music stand
— 1 —
Electrical
Current Drain with 12V DC:
No Sound Output390 mA ± 20%
Maximum Volume1700 mA ± 20%
with white keys D2 to D3 pressed in Synth-Bass-2 tone
and in Latin Fusion rhythm at initial setup tempo
Volume; maximum, Touch: maximum
Line Output Level (Vrms with 47 KΩ load each cannel):
with key D4 pressed in FSynth-Bass-2 tone on L-ch850 mV ± 20%
with key G4 pressed in FSynth-Bass-2 tone on R-ch800 mV ± 20%
Phone Output Level (Vrms with 8 Ω load each channel):
with key D4 pressed in FSynth-Bass-2 tone on L-ch280 mV ± 20%
with key G4 pressed in FSynth-Bass-2 tone on R-ch260 mV ± 20%
Speaker Input Level:
with key D4 pressed in FSynth-Bass-2 tone on L-ch5200 mV ± 20%
with key G4 pressed in FSynth-Bass-2 tone on R-ch5600 mV ± 20%
Minimum Operating Voltage:5.5 V
REPLACING THE DSP (HG51A115A01FD)
Note: To increase productivity ,the DSP HG51A115A01FD is sticked on the main PCB with a double-side
adhesive tape, then its leads are soldered.
Remove the DSP according to the following procedures.
1. Prepare isopropyl alcohol and a flat IC desoldering machine (Spot Heater HS-600).
2. Apply plenty of the alcohol to the adhesive tape from the reverse side of the main PCB. (Fig. 1)
There is a hole on the PCB just under the LSI, and the adhesive tape can be seen through the hole.
3. Leave it more than one minute so that the alcohol weaken adhesive power fully.
4. Using a proper size of nozzle, apply heat to leads of the LSI with the desoldering machine.
5. Grasp the LSI with tweezers, and using gentle force vibrate the tweezers to feel melting solder. (Fig.2)
6. Remove the LSI after meltingsolder at every leads wholly.
Initial reset
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
The CPU then initializes its internal circuit and clears data in the working strage RAM.
Power ON reset
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU first raises
APO signal to +5V to generat DVDD voltage, then raises RESET signal to +5V. During this period the
gate array, the DSP and the key touch LSI initializes their internal circuit.
CPU (HD6433298A18P)
The 16-bit CPU contains a 32k-bit ROM, a 1k-bit RAM, seven 8-bit I/O ports, an A/D convertor and serial
interfaces. The CPU accesses to the working strage RAM, the DSP and the key touch LSI. The CPU also
controls buttons, LEDs, bender input and MIDI input/output.
Pin No.TerminalIn/OutFunction
1P40Out KO signal data output
2P41Out Clock for KO signal data
3P42Out APO (Auto Power Off) signal output. ON: High, OFF: Low
4P43Out Read enable signal output
5P44Out Write enable signal output
6P45 Not used.
7P46Out 10MHz clock output
8P47In Wait signal input. Connected to +5V.
9TXDOut MIDI signal output
10RXDIn MIDI signal input
11P52Out Reset signal output
12-RESETIn Reset signal input
13-NMIIn Power ON signal input.
14VCCIn +5V source
15-STBYIn Standby signal input. Connected to +5V.
16VSSIn Ground (0V) source
17XTALIn 20MHz clock input
21AVSSIn Ground (0V) source for internal DAC
22AN0In Analog input. Connected to the bender volume.
23 ~ 29 P71 ~ P77In Button input signal input
30AVCCIn +5V source for internal DAC
31 ~ 38 P60 ~ P67Out LED segment signal output
39VCCIn +5V source
40 ~ 56 P27 ~ P10Out Address bus
48VSSIn Ground (0V) source
57 ~ 64 P30 ~ P37Ijn/Out Data bus
— 6 —
Gate Array (UPD65005C-578)
Functions of the gate array are;
(1) To decode chip select signals for the working strage RAM, the DSP and the key touch LSI.
(2) To hold the following signals on "Low" during power off.
Read/write enable signals for the DSP and the key touch LSI
10MHz clock for the key touch LSI
(3) To generate button scan / LED drive signals.
The following table shows the pin functions of the gate array.
Pin No.TerminalIn/OutFunction
1-RESETIn Reset signal input
2-RDAPOOut Read enable signal output
3-WRAPOOut Write enable signal output
4-LSISOut Chip select signal for the DSP
5-HGOut Chip select signal for the key touch LSI
6PHAPOOut 10MHz clock for the key touch LSI
7-SRAMOut Chip select signal for the working strage RAM
8 ~ 9KO8 ~ KO9 Not used.
10 ~ 17KO7 ~ KO0Out Button scan / LED drive signal output
18 ~ 20 Not used.
21GNDIn Ground (0V) source
22PHAIn 10MHz clock input
23-WRIn Write enable signal input
24-RDIn Read enable signal input
25-APOIn APO (Auto Power Off) signal input
26KOCIn KO signal data input
27KODIn Clock for KO signal data
28 ~ 39A15 ~ A4In Address bus
40, 41D0, D1In Data bus
42VDDIn +5V source
A4 ~ A15
D0, D1
RD
WR
PHA
APO
KOD
KOC
RESET
Address decoder
Controller
Shift register
LSIS
HG
SRAM
RDAPO
WRAPO
PHAPO
KO0 ~ KO7
— 7 —
(Chip select sigal for the DSP)
(Chip select signal for the key touch LSI)
(Chip select signal for the working strage RAM)
(Read enable signal controlled by APO)
(Write enable signal controlled by APO)
(10MHz clock for the key touchLSI.
Controlled by APO)
(Button scan / LED drive signal)
Digital Signal Processor (HG51A115A01FD)
Upon receipt of note numbers and their velocities, the DSP reads sound and velocity data from the sound
source ROM in accordance with the selected tone; the DSP can read rhythm data simultaneously when a
rythm pattern is selected. Then it provides 16-bit serial signals containing data of the melody, chord, bass,
and percussion to the DAC. The DSP also adds the selected effect to the sound data using a 256k-bit
RAM.
The following table shows the pin functions of the DSP.
18, 19XT0, XT1In/Out 16.384MHz clock input/output. Connected to a crystal oscillator.
20SGLIn System control terminal. Single chip system: Open
21CCSBIn Chip select signal input
22 ~ 25CA0 ~ CA3In Addess bus
26CE0In Not used. Connected to ground.
27CWRBIn Write enable signal
28CRDBIn Read enable signal
29 ~ 32 Not used.
33RESBIn Reset signal input
34TESBIn Not used. Connected to +5V.
35 ~ 39 Not used.
40 ~ 49
52 ~ 57
RD0 ~ RD15In Data bus for the sound source ROM
58RA23Out Not used.
59RA22Out Chip select signal for the sound source ROM
60, 61RA20, RA21Out Not used.
62 ~ 73
75 ~ 82
RA0 ~ RA19Out Data bus for the sound source ROM
74GND5In Ground (0V) source
83WOK2Out Word clock output. Not used.
84VCC3In +5V source
85GND3In Ground (0V) source
86WOK1Out Word clock for the DAC
87SOLMOut Serial data output. Not used.
88SOLPOut Serial data output for the DAC
89BOKOut Bit clock output for the DAC
90 ~ 92 Not used.
— 8 —
Pin No.TerminalIn/OutFunction
93VCC5In +5V source
94, 95
97 ~ 105
107,109
EA0 ~ EA14Out Address bus for the effect RAM
110, 112
96EWEBOut Write enable signal output for the effect RAM
106EOEBOut Read enable signal output for the effect RAM
108VCC7In +5V source
111ECEBOut Chip select signal output for the effect RAM
113 ~ 117 Not used.
118VCC4In +5V source
119GND4In Ground (0V) source
120 ~ 122 Not sued.
123 ~ 130ED0 ~ ED7In/Out Data bus for the effect RAM
131GND5In Ground (0V) source
132 ~ 134 Not used. Connected to ground.
135, 136 Not used.
Block diagram of DSP and DAC circuit
Sound Source ROM
TC5316200CP-C081
CE
A0 ~ A19D0 ~ D15
RA22
RA0 ~
RA19
D0 ~ D7
A0 ~ A3
HG51A115A01FD
LSIS
RDAPO
WRAPO
RESET
ECEB EOEB
OE
CS
PG
16.384MHz
RD0 ~
RD15
DSP
EWEB
WE
ED0 ~
ED15
D0 ~ D15
EA0 ~
EA14
A0 ~ A14
Effect RAM (256K-bit)
HM65256BLP
SOLP: Sound data
BOK: Bit clock
WOK1: Word clock
DAC
SOLP
BOK
WOK1
SI
CLK
LRCK
UPD6376CX
ROUT
LOUT
— 9 —
DAC (UPD6376CX)
RESB
CCSB
CWRB
CRDB
CKI
CD0
CD7
CA0 ~ CA2
First contact
Second contact
KC0
KC7
FI0
FI7
SI0
SI7
Key input signal
Key scan signal
~
Data bus
Address bus
Reset signal from the CPU
Chip select signal from the gate array
Read enable signal from the gate array
Write enable signal from the gate array
Clock from the gate array
Key touch LSI
HG52E35P
Keyboard
FI
SI
KC
UPD6376CX is a two-channel 16-bit Digital to Analog Convertor consisting of resistor string, output
amplifier and zero offset circuit.
Pin No.TerminalIn/OutFunction
1SELIn Mode selection terminal. Connected to ground.
2D.GNDIn Ground (0V) source for internal digital circuit
3NC Not used.
4DVDDIn +5V source for internal digital circuit
5A.GNDIn Ground (0V) source for internal analog circuit
6R.OUTOut Sound waveform output
7A.VDDIn +5V source for internal analog circuit
8A.VDDIn +5V source for internal analog circuit
9R.REFIn Reference voltage terminal. Connected to a capacitor.
10L.REFIn Reference voltage terminal. Connected to a capacitor.
11L.OUTOut Left channel sound waveform output
12A.GNDIn Ground (0V) source for internal analog circuit
13LRCKIn Word clock (L/R separation signal) input.
14LRSELIn Not used. Connected to ground.
15SIIn Sound data input
16CLKIn Bit clock input
Key Touch LSI (HG52E35P)
By counting the time between first-key input signal FI and second-key SI from the keyboard unit, the key
touch LSI detects key velocity of 256-step. Then the LSI sends the CPU the note number and its velocity
data.
— 10 —
The following table shows the pin functions of the key touch LSI.
Pin No.TerminalIn/OutFunction
1REQBOut Interrupt request. Not used.
2, 3FI10, SI10In Key input signal
4VCCIn +5V source
5CRDBIn Read enable signal
6CWRBIn Write enable signal
7CCBBIn Chip select signal
8, 9T, STBYIn Not used. Connected to +5V.
10RESBIn Reset signal
11WIn Not used. Connected to +5V.
12CKIIn 10 MHz clock input
13, 14TMD, TSTIn Not used. Connected to ground.
15CKOOut Not used.
16GNDIn Ground (0V) source
17XINIn Not used. Connected to ground.
18XOUTOut Not used.
19TRESIn Not used. Connected to ground.
20 ~ 23, 25 ~ 28CD0 ~ CD7In/Out Data bus
24GNDIn Ground (0V) source
29 ~ 31CR0 ~ CR2In Address bus
32VCCIn +5V source
33 ~ 39, 41 ~ 43
53 ~ 55, 57 ~ 63
FI0 ~ FI9,
SI0 ~ SI9
In Key input signal
40VCCIn +5V source
44 ~ 47, 49 ~ 52KC0 ~ KC7Out Key scan signal
48, 56GNDIn Ground (0V) source
64VCCIn +5V source
Filter Block
Since the sound signals from the DAC are stepped waveforms, the filter block is added to smooth the
waveforms.
10V22µ
To main volume
M5218APR
+
-
C104(H)
1K
C182(H)
AG
— 11 —
2SC1740SQ
1K1K
C152(H)
AG
AVDD
1K
AG
AVEE
10K
10V22µ
From the DAC
Power Amplifier (LA4620)
The power amplifier is a two-channel balanced amplifier with standby switch. The following figure shows
the internal diagram of the amplifier.
Internal Diagram of LA4620
Boot11
19
20
21
22
23
1
18
17
15
14
12
OUT11
PoGND1
OUT12
Boot21
VCC1
Boot21
OUT21
PoGND2
OUT22
Boot22
IN11+
IN11-
IN12-
PriGND
IN21+
IN21-
IN22-
3
5
4
6
9
7
8
+
Input
Amp.
-
Input
Amp.
+
Terminal
Protection
Circuit
+
Input
Amp.
-
Input
Amp.
+
Pre-drive
Amp.
RL Short
Protector
Pre-drive
Amp.
Ripple
Filter
Pre-drive
Amp.
RL Short
Protector
Pre-drive
Amp.
Power
Amp.
Power
Amp.
Pop Noise
Prevention
Circuit
Power
Amp.
Power
Amp.
16
NCDCMUTEVCC2ADJ
2
10
11
13
Power Supply Circuit
The power supply circuit generates six voltages as shown in the following table. VDD voltage is always
generated. The others are controlled by APO signal from the CPU.
2606 1141 Carbon film resistorR-20-1K-J-T23-T 16 202C A
2606 1148 Carbon film resistorR-20-220-J-T23-T 4 202C A
2606 1155 Carbon film resistorR-20-330-J-T23-T 1 202C A
2606 1162 Carbon film resistorR-20-10-J-T23-T 5 202CA
2606 1169 Carbon film resistorR-20-100-J-T23-T 33 202C A
2606 1176 Carbon film resistorR-20-100K-J-T23-T 9 202C A
2606 1183 Carbon film resistorR-20-10K-J-T23-T 7 202CA
2606 1197 Carbon film resistorR-20-22-J-T23-T 8 202CA
2606 1232 Carbon film resistorR-20-82-J-T23-T 2 202CA
2606 1253 Carbon film resistorR-20-4.7K-J-T23-T 2 202CA
2606 1302 Carbon film resistorR-20-270-J-T23-T 1 202C A
2606 1309 Carbon film resistorR-20-470-J-T23-T 36 202C A
2606 1323 Carbon film resistorR-20-56K-J-T23-T 22 202C A
2606 1330 Carbon film resistorR-20-68K-J-T23-T 1 202CA
2606 1337 Carbon film resistorR-20-1M-J-T23-T 1 202C A
2606 1358 Carbon film resistorR-20-3.3K-J-T23-T 3 202CA
2606 1372 Carbon film resistorR-20-33K-J-T23-T 11 202C A
2606 1428 Carbon film resistorR-20-5.6K-J-T23-T 2 202CA
2606 1435 Carbon film resistorR-20-560-J-T23-T 1 202C A
2606 1491 Carbon film resistorR-20-6.8K-J-T23-T 1 202CA
2606 1694 Carbon film resistorR-20-68-J-T23-T 2 202CA
2606 1708 Carbon film resistorR-20-47-J-T23-T 4 202CA
N2606 1722 Carbon film resistorR-20-2.2-J-T23-T 4 202C A
N2606 1757 Carbon film resistorR-20-6.8-J-T23-T 4 202C A
16920 7581 TR white key set CEGBM111223A-151180CC
26920 7591 TR white key set DFASM111222A-111180CC
36920 7601 TR white key set DFAM111221A-141160CB
46920 7611 TR black key set 10PM111220A-121230C C
56920 7621 TR black key set 5PM111220A-211150CB
66920 7560 PET-TAC-TR29M111224-111350C D
76920 7570 PET-TAC-TR32M111225-111370C D
86921 8610 KB chassis HTRASK61GDM111547-111650C G
96921 8621 Upper stopper HTRASKM412168A-111130CB