R
(with price)
CTK-650
CTK-650
ELECTRONIC KEYBOARD
CONTENTS |
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SPECIFICATIONS .................................................................................................... |
1 |
BLOCK DIAGRAM ................................................................................................... |
2 |
CIRCUIT DESCRIPTION |
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CPU (HD6433298A16P : H8/329) ..................................................................... |
3 |
DIGITAL SIGNAL PROCESSOR, LSI-S (HG51A115A01FD) .......................... |
4 |
KEY TOUCH LSI (HG52E35P) .......................................................................... |
5 |
POWER AMPLIFIER (LA4598) ......................................................................... |
6 |
BUTTON MATRIX ............................................................................................. |
7 |
KEY MATRIX ..................................................................................................... |
8 |
WIRING DIAGRAM ................................................................................................... |
9 |
IC LEAD IDENTIFICATION AND INTERNAL CIRCUIT .......................................... |
10 |
PCB VIEW AND MAJOR WAVEFORMS ................................................................. |
12 |
SCHEMATIC DIAGRAM ........................................................................................... |
13 |
PARTS LIST ............................................................................................................. |
15 |
EXPLODED VIEW .................................................................................................... |
19 |
SPECIFICATION
Number of keys: |
61 |
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Polyphony: |
32-note(max.) |
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Preset tones: |
128 |
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Magical preset: |
BREAK BEAT |
16 |
MELODYCOMP |
8 |
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SHADOW DRUM |
4 |
FREE SESSION |
32 |
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TONE STACK |
40 |
KEY SPLIT |
12 |
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HYPERACTIVE |
16 |
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Auto-accompaniment: |
Rhythm patterns |
128 |
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Tempo |
Adjustable(40 - 255) |
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Chords |
Three system: CASIO CHORD, FINGERD, |
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FULL-RANGE CHORD |
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Other |
Variation pattern, fill-in pattern, intro/ending pattern for each |
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rhythm. |
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Song memory: |
song:one |
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System:Real-time recording |
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Memory capacity:Up to 1,300 notes |
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Registration memory: |
4 setups |
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Sound control pads: |
Phrases |
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10 |
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Drums |
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10 |
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SE/Percussion |
10 |
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Controller |
2 |
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Digital effects: |
REVERB 1, REVERB 2, REVERB 3, CHORUS, TREMOLO, PHASE |
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SHIFTER, ORGAN SP, ENHANCER, FLANGER, EQLOUNDNESS |
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DEMO tunes: |
3 tunes |
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Other functions: |
Transpose (F# ~ C ~ F : half-note) |
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Tuning adjustable A4 = 440KHz 50 cents increments |
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Volume control (Main /Accompaniment) |
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Speakers: |
12cm diameter X 2 (Output:2W+2W) |
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I/O terminals: |
Power supply |
9V DC jack |
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Headphones |
Stereo mini jack |
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Output impedance:100 ohm |
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Output voltage:4.5V(RMS. max) |
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Assignable jack |
Standard jack |
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MIDI |
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IN, OUT |
Power supply: |
3-way AC/DC power sources; |
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Batteries |
Six D-size |
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Battry life |
Approximately 5 hours on R20P(SUM-1) |
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AC |
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Required optional AD-5 AC adaptor |
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Car battery |
Required optional CA-5 car adaptor |
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Auto power off: |
Approximately 6 minutes after the last operation |
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Power consumption: |
7.7W |
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Dimensions: |
942 X 367 X 135 mm(HWD) |
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31 7/16" X 14 1/2" X 4 3/8" inches(HWD) |
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Weight: |
5.2kg(11.7lbs) excluding batteries |
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Accessory: |
Score stand |
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— 1 —
BLOCK DIAGRAM |
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7-Segment |
LO0~LO4 |
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LED |
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RAM-1(64K) |
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La |
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LED driver |
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MN4464-08L-1 |
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~Lp |
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BA612 |
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KO0~4 |
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KC0~KC7 |
Key Touch |
D0~D7 |
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CPU |
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KO0~KO5 |
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LSI |
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HD6433298A16P |
Buttons |
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Address Bus |
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Keyboard |
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(H8/329) |
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KI1~KI7 |
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HG52E35P |
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SI0~SI7 |
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FI0~FI7 |
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VDD |
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MIDI |
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100K |
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OUT |
IN |
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Power Switch |
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RA0~RA19 |
LSI-S |
EA0~EA12 |
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RAM-2(64K) |
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ROM(16M) |
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TC5316200CP-C079 |
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HG51A115A01FD |
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MN4464-08L-2 |
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RD0~RD15 |
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ED0~ED7 |
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WCK1 SLOP BCK
D/A Converter
µPD6376CX
Filter Filter
Main |
Output |
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Volume |
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Power Amplifier
Speakers
LA4598
— 2 —
CIRCUIT DESCRIPTION
CPU(HD6433298A16P : H8/329)
The 16-bit CPU contains a 32K-byte ROM, a 1K-byte RAM, an 8-bit A/D converter, timers and I/O ports. The CPU accesses to the DSP, Key Touch LSI, RAM, buttons and LEDs. But the CPU directly receives MIDI and pedal signals.
Pin No. |
Terminal |
In/Out |
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Function |
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1 |
P40/IRQ2 |
In |
KO signal data. |
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2 |
P41/IRQ1 |
In |
Timing signal for KO signal. |
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3 |
P42/IRQ0 |
In |
APO signal output. |
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4 |
P43/-RD |
Out |
Read signal outpt. |
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5 |
P44/-WR |
Out |
Write signal output. |
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7 |
P46/PHI |
Out |
System clock output. |
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8 |
P47/-WAIT |
In |
Wait signal input |
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9 |
P50/Txd |
Out |
MIDI signal output. |
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10 |
P51/Rxd |
In |
MII signal input. |
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11 |
P52/SCK |
Out |
Reset signal output. |
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12 |
-RESET |
In |
Reset signal input. |
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13 |
-NMI |
In |
Power on signal input.(Low active) |
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14 |
Vcc |
In |
+5V source. |
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15 |
-STBY |
In |
Standby signal input. Connected to +5V. |
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16 |
Vss |
In |
Ground(0V) source. |
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17,18 |
XTAL,EXTAL |
In/Out |
20MHz clock pulse input/output. Connected to crystal. |
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19,20 |
MD1,MD0 |
In |
Selection for system. |
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MD1 |
MD0 |
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MODE |
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0 |
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1 |
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MODE-1 : Internal ROM mode |
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1 |
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0 |
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MODE-2 : Non internal ROM mode |
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1 |
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1 |
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MODE-3 : Single chip mode |
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21 |
AVss |
In |
Analog ground source. |
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22 |
P70/AN0 |
In |
Connected to ground. |
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23~29 |
P71/AN0~P77/AN7 |
In |
KI signal input. |
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30 |
AVcc |
In |
+5V source. |
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31~38 |
P60/FTCI~P67/TMO1 |
Out |
Control signal for 7-segment LED. |
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39 |
Vcc |
In |
+5V source. |
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41~56 |
P26/A14~P10/A0 |
Out |
Address bus. |
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48 |
Vss |
In |
Ground(0V) source. |
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57~64 |
P30/D0~P37/D7 |
In/Out |
Data bus. |
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— 3 —
DIGITAL SIGNAL PROCESSOR, LSI-S (HG51A115A01FD)
The LSI-S is a 16-bit DSP(Digital Signal Processor) and accessable to 16M-bit sound source ROM and to 64Kbit RAM. The DSP can read data of 32 polyphonic note from the ROM and provides two 16-bit serial dat with timing signals to each channel's D/A converter.
Pin No. |
Terminal |
In/Out |
Function |
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1~7 |
D7~D0 |
I/O |
Data bus. |
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11 |
GND7 |
In |
Ground(0V) source. |
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12 |
CK16 |
Out |
16.384MHz clock pulse output. |
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13 |
VCC6 |
In |
+5V source |
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14 |
CK0 |
In |
Clock pulse input. Connected to terinal CK16. |
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16 |
VCC1 |
In |
+5V source. |
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17 |
GND1 |
In |
Ground(0V) source. |
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18,19 |
XTI, XTO |
In/Out |
16.384MHz clock pulse input/output. Connected to crystal. |
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21 |
CCSB |
I |
Chip select signal input. |
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22~25 |
CA0~CA3 |
In |
Address bus. |
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26 |
CE0 |
In |
Connected to ground.(ROM interface ontrol terminal) |
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27 |
CWRB |
In |
Write enable signal. |
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28 |
CRDB |
In |
Read enebla signal. |
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33 |
RESB |
In |
Reset sna iput |
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34 |
TESB |
In |
Connected to +5V. |
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40~49 |
RD0~RD15 |
In |
Data bus for sound source ROM. |
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52~57 |
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50 |
VCC2 |
In |
+5V source. |
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51 |
GND2 |
In |
Ground(0V) source. |
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59 |
RA22 |
Out |
Chip enable signal output for ROM. |
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62~73 |
RA0~RA19 |
Out |
Address bus for sound source ROM. |
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75~82 |
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74 |
GND5 |
In |
Ground(0V) source. |
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84 |
VCC3 |
In |
+5V source. |
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85 |
GND3 |
In |
Ground source. |
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86 |
WOK1 |
Out |
Ward clock for DAC. |
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88 |
SOLP |
Out |
16-bit serial data for L-channel DAC. |
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89 |
BOK |
Out |
Bit clock for DAC. |
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93 |
VCC5 |
In |
+5V source. |
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95,97 |
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99~105 |
EA0~EA12 |
Out |
Address bus for RAM. |
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107,109 |
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110,112 |
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96 |
EWEB |
Out |
Write enable signal for RAM. |
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106 |
EOEB |
Out |
Read enable signal for RAM. |
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108 |
VCC7 |
In |
+5V source. |
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111 |
ECEB |
Out |
Chip eneble signal for RAM. |
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118 |
VCC4 |
In |
+5V source. |
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119 |
GND4 |
In |
Ground(0V) source. |
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123~130 |
ED0~ED7 |
In/Out |
Data bus for RAM. |
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131 |
GND6 |
In |
Connected to Ground. |
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132 |
SSI |
In |
Connected to Ground. |
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133 |
SBCK |
In |
Connected to Ground. |
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134 |
SWCK |
In |
Connected to Ground. |
— 4 —
KEY TOUCH LSI(HG52E35P)
By counting the time between the first key input signal FI and the second SI from the keyboard unit, the key touch LSI detects key velocity of 256-step. Then the LSI sends the CPU note numbers and their velocities.
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Key Touch LSI |
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CPU |
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HG52E35P |
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HD6433298A16P |
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RESB |
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P52/SCK |
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CCSB |
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A12 |
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A14 |
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KC0~KC7 |
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P44/-WR |
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CWRB |
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P42/IRQ0 |
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Keyboard |
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CRDB |
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P43/-RD |
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FI0~FI9 |
CKI |
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P46/PHI |
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SI0~SI9 |
P30/D0~P37/D7 |
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D0~D7 |
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CD0~CD7 |
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P12/A2~P10/A0 |
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A0~A2 |
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CA0~CA2 |
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Pin No. |
Terminal |
In/Out |
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Function |
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1 |
REQB |
Out |
Interrupt request. Not used. |
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2,3 |
FI10,SI10 |
In |
Connected to +5V. |
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4 |
VCC |
In |
+5V source. |
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5 |
CRDB |
In |
Read enable signal. |
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6 |
CWRB |
In |
Write enable signal. |
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7 |
CCBB |
In |
Chip select signal. |
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8 |
T |
In |
Test terminal. Connected to +5V. |
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9 |
STYB |
In |
Standby terminal. Connected to +5V. |
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10 |
RESB |
In |
Reset signal. |
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11 |
W |
In |
Test terminal. Connected to +5V. |
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12 |
CKI |
In |
External clock input. |
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13 |
TMD |
In |
Test terminal. Connected to ground. |
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14 |
TST |
In |
Test terminal. Connected to ground. |
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15 |
CKO |
Out |
External clock output. Not used. |
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16 |
GND |
In |
Ground(0V) source. |
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17 |
XIN |
In |
Clock pulse input. Connected to ground. |
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18 |
XOUT |
Out |
Clock pulse output. Not used. |
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19 |
TRES |
In |
Test terminal. Connected to ground. |
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20~28 |
CD0~CD7 |
In/Out |
Data bus. |
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24 |
GND |
In |
Ground(0V) source. |
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29~31 |
CA0~CA2 |
Out |
Address bus. |
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32 |
VCC |
In |
+5V source. |
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33~43 |
FI0~FI9 |
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53~55 |
In |
Key input signal. |
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SI0~SI9 |
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57~63 |
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40 |
VCC |
In |
+5V source. |
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44~53 |
KC0~KC7 |
Out |
Key scan signal. |
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48,56 |
GND |
In |
Ground(0V) source. |
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54 |
VCC |
In |
+5V source. |
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— 5 —
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