Apple K22 Schematics

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

K22

1 OF 110

0000774858

A

051-7845

A.0.0

1 OF 110

PRODUCTION RELEASED

2009-08-21

LAST_MODIFIED=Wed Aug 26 13:27:43 2009

K51

MCP CURRENT AND VOLTAGE SENSE

45

54

12/08/2008

MASTER

CPU/MXM CURRENT AND VOLTAGE SENSE

44

53

N/A

MASTER

SMBUS CONNECTIONS

43

52

N/A

MASTER

LPC+SPI Debug Connector

42

51

N/A

MASTER

SMC Support

41

50

N/A

MASTER

SMC40

49

N/A

MASTER

Internal USB Connections

39

47

MASTER

EXTERNAL USB CONNECTORS

38

46

N/A

MASTER

SATA Connectors

37

45

N/A

MASTER

FIREWIRE CONNECTOR

36

43

N/A

MASTER

FW: 1394B MISC

35

42

N/A

MASTER

FireWire LLC/PHY (XIO2213B)

34

41

N/A

MASTER

ETHERNET CONNECTOR

33

39

N/A

MASTER

Ethernet Support

32

38

N/A

K51

Ethernet PHY (RTL8211CL)

31

37

12/08/2008

MASTER

PCI-E Wireless Connector

30

34

N/A

K51

DDR3 SUPPORT AND BITSWAPS

29

33

10/13/2008

MASTER

DDR3 SO-DIMM CONNECTOR B

28

32

N/A

MASTER

DDR3 SO-DIMMs 0 & 2

27

31

N/A

MASTER

MEMORY CAPS

26

30

N/A

MASTER

FSB/DDR3 Vref Margining

25

29

MASTER

SB Misc24

28

N/A

MASTER

MCP Graphics Support

23

26

N/A

K51

22

25

12/08/2008

MASTER

21

22

N/A

MASTER

MCP HDA & MISC

20

21

N/A

MASTER

MCP SATA & USB

19

20

N/A

MASTER

MCP PCI & LPC

18

19

N/A

MASTER

MCP Ethernet & Graphics

17

18

N/A

MASTER

16

17

N/A

MASTER

MCP MEMORY CNTRL & MISC

15

16

N/A

MASTER

MCP Memory Interface

14

15

N/A

MASTER

13

14

N/A

MASTER

eXtended Debug Port (XDP)

12

13

N/A

MASTER

CPU POWER, GND, DECAPS

11

12

N/A

MASTER

CPU TEST & MISC.

10

11

N/A

MASTER

CPU FSB9

N/A

MASTER

SIGNAL ALIASES

8

9

N/A

MASTER

UNUSED SIGNAL ALIAS

7

8

N/A

MASTER

HOLES & STANDOFFS

6

7

N/A

MASTER

Power Conn / Alias

5

6

N/A

MASTER

BOM Configuration

4

N/A

MASTER

Power Block Diagram

3

N/A

MASTER

System Block Diagram

2

N/A

K22/K23 ICT/FCT

87

110

MASTER

N/A

K22/K23 RULE DEFINITIONS

86

109

MASTER

N/A

K22/K23 SPECIFIC CONSTRAINTS

85

108

MASTER

N/A

GRAPHICS CONSTRAINTS

84

107

MASTER

N/A

SMC Constraints

83

106

MASTER

N/A

FireWire Constraints

82

105

MASTER

N/A

Ethernet Constraints

81

104

MASTER

N/A

MCP Constraints 2

80

103

MASTER

N/A

MCP Constraints 1

79

102

MASTER

N/A

Memory Constraints

78

101

MASTER

N/A

CPU/FSB Constraints

77

100

MASTER

N/A

DisplayPort Connector

76

94

MASTER

N/A

DISPLAYPORT SUPPORT

75

93

MASTER

N/A

DP MUX SUPPORT

74

91

MASTER

N/A

INTERNAL DISPLAY

73

90

MASTER

LCD MUX & CHOKES

72

89

MASTER

MXM ALIASES

71

87

MASTER

N/A

MXM PCIE CAPS

70

86

MASTER

N/A

MXM I/O69

85

K51

10/31/2008

MXM PCIe, DP & Power

84

K51

10/31/2008

1V8 POWER SUPPLY

67

80

MASTER

N/A

1V1 S5 POWER SUPPLY

66

79

K51

10/31/2008

S3 & S0 FETs

65

78

MASTER

N/A

FSB VTT/3.3V S5 SUPPLIES

64

76

MASTER

N/A

1.5V DDR SUPPLY

63

75

MASTER

N/A

MCP CORE REGULATOR

62

74

MASTER

N/A

5V_S3 REGULATOR

61

73

MASTER

N/A

VREG: PPVCORE_S0_CPU

60

72

MASTER

N/A

VREG: PPVCORE_S0_CPU

59

71

MASTER

N/A

PGOOD and Power Sequencing

58

70

MASTER

N/A

57

69

K51

12/08/2008

AUDIO: Mikey

56

68

SKIPAUDIO

06/01/2009

AUDIO: Detects/Grounding

55

67

SKIPAUDIO

06/01/2009

Audio: MLB to I/O Conn.

54

66

SKIPAUDIO

06/01/2009

AUDIO: SPEAKER AMP

53

65

SKIPAUDIO

06/01/2009

AUDIO: SPEAKER AMP

52

64

SKIPAUDIO

06/01/2009

AUDIO: FILTER/BUFFER

51

63

SKIPAUDIO

06/01/2009

AUDIO: CODEC/REGULATOR

50

62

SKIPAUDIO

06/01/2009

SPI ROM49

61

K51

12/08/2008

CPU FAN48

57

MASTER

N/A

HD AND OD FAN

47

56

MASTER

N/A

(.csa)

Date

Contents

SyncPage

Thermal Sensors

46

55

MASTER

N/A

ABBREV=DRAWING

TITLE=K22

MASTER

Table of Contents

1

N/A

Page

(.csa)

Date

Sync

Contents

SCH,K22,MLB

POWER SEQUENCING BLOCK DIAGRAM

MCP Standard Decoupling

MCP Power & Ground

MCP PCIe Interfaces

MCP CPU Interface

10

68

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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Apple Inc.

PAGE

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B

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8 7 5 4 2 1

INTERNAL

J9410

PORT CONN

FW643

MXM CONNECTOR

64-Bit

XDP CONN

PG 10

MEMORY

PG 15

LPC+SPI CONN

PG 56,57

PG 51

PG 53

PG 55

U4900

J3100, J3200

PG 31,32

PG 61

PG 49

J4780

PG 47

PG 20

2 7

11

J4720

PG 21

SATA-A0

LVDS OUT

U3900

PG 39

PG 37

PG 17

Mini PCI-E

Conn

AirPort

J3400

U4100

PG 43

PG 41

GPIOs

PG 34

PG 18

DP OUT

DVI OUT

RGB OUT

TMDS OUT

J8400

HDMI OUT

65 841 3

CLK

PG 13

SYNTH

J5100

Ser Prt

ADC

SMC

BSBB,0

SPI

U1000

U1300

PG 13

PG 20

SATA-A1

E-NET

MAGNETICS

Conn

FireWire

J4300

CPU DIE

CPU HEATSINK

MXM - GPU DIE

TEMP SENSORS

J5600, J5601, J5700

PG 19

Boot ROM

PG 21

Port80,serial

PG 21

Bluetooth

PWR

U1400

CTRL

PG 84

PG 45

J4510

HD

SATA

1.05V/3GHZ.

Conn

SATA

ODD

Conn

PG 45

J4520

PG 94

DISPLAY

J9002

PG 90

DISP

INTEL CPU

LCD TEMP

LPC

DDR3-1067MHZ

MAIN

3.X GHZ

LGA775 - WOLFDALE

PG 10-12

4 SO-DIMMs

MCP7A

PG 47

IR

J4700

PG 47

CAMERA

PG 47

J47xx

WHICH PORT?

EXTERNAL

J4610,4620,4630,4640

Connectors

USB

PG 47

SD CARD

SPI

U6100

Misc

PG 24

USB

(UP TO 12 DEVICES)

9

10

Fan

MCP DIE

AMBIENT INTAKE

HARD DRIVE

OPTICAL DRIVE

MCP HEATSINK

FAN CONN AND CONTROL

POWER SENSE

FSB INTERFACE

GPU HEATSINK

TEMP, CURRENT SENSE

POWER SUPPLY

1333 MHZ

FSB

DIMM

NVIDIA

SATA

UP TO 20 LANES3

X16 PCI-E

T3900

PG 39

Conns

Audio

U3700

Audio

U6201

Mikey

U6806

Codec

PG 19

PCI

0

RGMII

PCI-E

SMB

MIKEY

HDA

(UP TO FOUR PORTS)

DIMM’s

PG 18

E-NET

Speaker

Amps

U6400, U6500

GB

RTL8211CLGR

Line In

Int/Ext Mics

Headphones

J6600,J6601,J6602,J6603

051-7845

A.0.0

2 OF 110

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

System Block Diagram

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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8 7 5 4 2 1

PAGE 6

MXM 20" INVERTER

CPU_CORE

PAGE 76

PPVTT_S0_FSB

PM_SLP_S3

CPU_AVDD

DDR3 MAIN MEMORY

PPVCORE_CPU

PAGE 71-72

PAGE 74

MCP, CPU FSB (VTT)

MCP_PLL

CPU_VCCP

PP1V8_S0_REG

MCP

PP1V1_S5

SMBUS

PAGE 78

PPDDR_S3_REG

PP5V_S3_REG

CAMERA

MEM_VTT

AP PCIE

AUDIO

20" PANEL

24" PANEL

FANS

MCP_ENET

FW

AP

ETHERNET

PAGE 78

USB

PP12V_S0

MCP

PAGE 76

BT

HDD

20" PANEL

PP12V_S5

CLOCK

PAGE 38

PP1V2_S3

PAGE 75

PP1V5_S0

PP0V75_S0

ENET

PAGE 75

PM_SLP_S3_OD

12V_S5

MAIN MEMORY

MCP79 MEM

TEMP SENSOR

CONTROL

PP12V_S0_INV

PP12V_S0_HDD

HARD DRIVE

PAGE 79

PP5V_S0

IR

BOOT ROM

AC/DC POWER SUPPLY

PAGE 76

MCP_CORE

DCM/FCM

PAGE 80

OPTICAL

MCP_VDD_AUXC

MXM

PAGE 74

P5VS0_EN

FIREWIRE PORTS

AUDIO

PPMCPCORE_S0_REG

MXM

FW

PP3V3_S3

P3V3S3_EN

P3V3S0_EN

PP3V3_S0

PAGE 78

AUDIO

PAGE 42

PP1V_S5

SMC

PP3V3_S5_REG

3 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

Power Block Diagram

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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345678

D

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8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

CPUS

BOM Variants

(338S0563 - BLNK)

K22 PARTS

COMMON

MCP -J SKU HAS INTEGRATED GPU

GROUND

7

6

5

4

BOTTOM

SIGNAL

POWER

GROUND

2 3

TOP

SIGNAL

POWER

BOARD STACK-UP

SIGNAL

MCP -D SKU DOES NOT

ALTERNATES

BOM GROUPS

4 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

K22,3P06GHZ_CPU,BASIC,MXM,K22_MXM

K22,3P16GHZ_CPU,BASIC,IG

630-9878

PCBA,3.06 GHZ CPU,IG,K22(Investigation)

PCBA,MLB,3.06GHZ,MXM,K22

PCBA,MLB,3.16GHZ,IG,K22

PCBA,MLB,3.16GHZ,MXM,K22

PCBA,MLB,3.33GHZ,IG,K22

PCBA,MLB,3.33GHZ,MXM,K22

PCBA,MLB,DEV,K22

CRITICAL 3P33GHZ_CPU

2P93GHZ_CPU

3P06GHZ_CPU

CPU

WLF,SLB9L,PRQ,3.33G,65W,1333,E0,6M,LGA

WLF,SLB9K,PRQ,3.16G,65W,1333,E0,6M,LGA

WLF,SLB9J,PRQ,3.0G,65W,1333,E0,6M,LGA

WLF,SLB9J,PRQ,2.83G,65W,1333,E0,6M,LGA

WLF,QXXX,QS,2.80G,65W,1066,R0,3M,LGA

CRITICAL

3P0GHZ_CPU

630-9768

639-0036

COMMON,ALTERNATE,MCP7A,XDP,BETTER,MCP_ISL9563A,MLB_PNL_PWR,PRODUCTION

WLF,SLGU9,PRQ,2.80G,65W,1066,R0,2M,LGA

337S3807

337S3766

337S3745

337S3742

337S3726

337S3715

337S3727

WLF,SLB9L,PRQ,2.93G,65W,1333,E0,6M,LGA

WLF,SLB9L,PRQ,3.06G,65W,1333,E0,6M,LGA

CPU

K22,2P80GHZ_CPU,BASIC,MXM,K22_MXM

PCBA,2.8 GHZ CPU,MXM,K22

2P80GHZ_2M_CPU337S3804 CRITICAL

1

CPU

1

CRITICAL

CPU

CRITICAL

3P16GHZ_CPU

CRITICAL

K22,2P80GHZ_CPU,BASIC,IG

SYNC_MASTER=MASTER

SYNC_DATE=N/A

BOM Configuration

PCBA,MLB,GOOD,K22

825-7122 MLB LABEL,48.0X4.8

X14

CRITICAL

1

CRITICAL12P80GHZ_CPU

2P83GHZ_CPU

1

CPU

DEV_GROUP

XDP_CONN,LPCPLUS,VREFMRGN,MCP_PWR_SENSE,MCP_CPU_TDIODE,PECI_SMB,MOJOMUX

1

U4900 CRITICAL341T0168 IC,SMC,K22

K22

IC,XIO2211ZAY,1394B,167BGA

338S0765 U4100

1

CRITICAL

IC,MCP,MCP7A-DA,B03,35X35MM,BGA1437,DT

1

MXM

338S0732 U1400

127S0060 C6211127S0111 AUDIO, NEED QUAL

CPU

1

PCBF,K22,MLB MLB1

1

820-2494

K22

U3700 CRITICAL

1

IC,RTL8251CA,GIGE TRANSCEIVER, 48P TQFP

338S0694

341T0170

1

CRITICALU6100IC,EFI BOOTROM,K22/K23

IC,GMCP,MCP7A-JA,B03,35X35MM,BGA1437,DT

1

338S0731 IGU1400

SCH,K22,MLB SCH1051-7845

1

K22

BOOT_MODE_USER,MEMRESET_HW,MEMRESET_MCP

MCP7A

BASIC

CRITICAL

1

CPU

CRITICAL

1

K22,2P80GHZ_2M_CPU,BASIC,IG

PCBA,2.8 GHZ-2M CPU,IG,K22

639-0392

K22,2P80GHZ_2M_CPU,BASIC,MXM,K22_MXMPCBA,2.8 GHZ-2M CPU,MXM,K22

639-0393

639-0184

PCBA,2.93 GHZ CPU,IG,K22 K22,2P93GHZ_CPU,BASIC,IG

K22,2P93GHZ_CPU,BASIC,MXM,K22_MXM

PCBA,2.93 GHZ CPU,MXM,K22

639-0186

PCBA,3.0 GHZ CPU,IG,K22

639-0037

K22,3P0GHZ_CPU,BASIC,IG

PCBA,MLB,CTO,K22

K22,3P0GHZ_CPU,BASIC,MXM,K22_MXM

639-0183 K22,3P06GHZ_CPU,BASIC,IG

639-0511

639-0510

639-0324

K22,3P16GHZ_CPU,BASIC,MXM,K22_MXM

K22,3P33GHZ_CPU,BASIC,IG639-0206

639-0207

K22,3P33GHZ_CPU,BASIC,MXM,K22_MXM

DEVELOPMENT,DEV_GROUP

607-4426

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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345678

D

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8 7 5 4 2 1

5 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

BLANK PAGE

IN

G

S

D

G

S

D

IN

G

S

D

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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8 7 5 4 2 1

ON IN RUN AND SLEEP

SILKSCREEN:4

518-0352

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

PLACE AT J600.

"S5" RAILS

GND RAILS

SILKSCREEN:2

SILKSCREEN:1

ONLY ON IN RUN

EMC: C600,C626,C627,C628,C629,C630,C631

SILKSCREEN:3

"S0" RAILS "S3" RAILS

6 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

9

8

7

6

5

4

3

2

14

13

12

11

10

1

J600

2

1

C631

2

1

C630

2

1

C623

2

1

C600

2

1

3

Q610

2

1

C626

2

1

C624

2

1

C627

2

1

3

Q602

2

1

LED602

2

1

R602

2

1

3

Q604

2

1

LED604

2

1

R604

2

1

LED603

2

1

R603

2

1

LED605

2

1

R600

2

1

LED601

2

1

R601

=PP1V05_S0_MCP_PEX_DVDD

PP3V3_S3

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAX_NECK_LENGTH=3 MM

VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_S3_MINI

=PP1V05_S0_MCP_HDMI_VDD_R

=PP5V_S3_1V8

=PP5V_S3_MCPREG =PP5V_S3_CAMERA =PP5V_S3_IR

=PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET =PPDDR_S3_S0FET

PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM

=PP3V3_S0_VRD

=PPSPD_S0_MEM_B

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

PPVTT_S0_FSB_REG

MIN_LINE_WIDTH=0.6 mm

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE VOLTAGE=1.2V

=PPVTT_S0_FSB_CPU

PPMCPCORE_S0_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

=PP1V05_S0_MCP_PLL_UF

PM_ACDC_PS_ON

=PP5V_S3_PWRCTL

=PP5V_S3_VTTCLAMP

=PP1V5_S3_MEM_A

PP3V3_S5_REG

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL =PP3V3_S5_S3FET =PP3V3_S5_S0FET =PP3V3_S5_ENET_FET

LCD_PWM

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_MCPREG

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

PPVTT_S0_DDR_LDO

MAKE_BASE=TRUE VOLTAGE=0.75V MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_MCP =PP3V3_S5_MCP_GPIO

=PP0V75_S0_MEM_VTT_A

=SMB_ACDC_SDA

PP12V_S5

=PP5V_S3_S0FET

PP1V1_S5_REG

MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.1V

=PP1V1_S5_ENET_FET

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S5_ROM =PP3V3_S5_RTC_D

=PP3V3_S5_SMC

=PP3V3_S5_LPCPLUS

=PP3V3_S5_MEMRESET

ITS_ALIVE

PP3V3_S5_REG

=PP5V_S5_AVREF

=PP3V3_S5_SMCUSBMUX

MXM_GOOD

PP3V3_S3

CORE_VOLTAGES_ON

ITS_PLUGGED_IN

LCD_SHOULD_ON

PP3V3_S3

GPU_PRESENT_R

=PP12V_S5_PWRCTL

PPDDR_S3_REG

NET_SPACING_TYPE=PPDDR_MEM MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.5V MIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_P1V1S5

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.1V MIN_LINE_WIDTH=0.6MM

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR

=PP3V3_S5_SMBUS_SMC_BSA

PM_SLPS3_BUF2_L

=PPDDR_S3_PGCMP

CORE_VOLTAGES_ON_R

LCD_BKL_ON

=PPVTT_S0_CPU

=PP3V3_S3_VREFMRGN

PP5V_S5_LDO

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

MAX_NECK_LENGTH=3 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

=PP12V_S5_FW =PPVIN_S5_DDRREG =PPVIN_S5_P3V3S5 =PPVIN_S5_P5VS3 =PP12V_S5_REG

PP12V_S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE VOLTAGE=12V

=PP5V_S0_SATA

=SMB_ACDC_SCL

GPU_PRESENT_DRAIN

PP5V_LCD_CONN

ALL_SYS_PWRGD_R

PP3V3_S0

=PP5V_S0_VRD

=PP5V_S0_MXM

=PP5V_S0_LCD

=PP5V_S0_ISENSE

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_AUDIO

=PPSPD_S0_MEM_A

=PP3V3_S0_XDP

=PP3V3_S0_VIDEO

=PP3V3_S0_TSENS

=PP3V3_S0_SMC_LS

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_MGMT

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SATALED

=PP3V3_S0_PWRCTL

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCPTHMSNS

=PP3V3_S0_FAN

=PP3V3_S0_DPCONN

=PP3V3_S0_AUDIO =PP3V3R1V5_S0_MCP_HDA

=PPV_S0_MXM_PWR =PPVIN_S0_PPVTT_FSB

=PPVIN_S0_MCPCORE

=PP12V_S0_VRD

=PP1V05_S0_MCP_AVDD_UF

=PPVTT_S0_XDP =PP1V05_S0_MCP_FSB

=PP3V3R1V8_S0_MCP_IFP_VDD_R =PP1V8_S0_PGCMP

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MXM

=PP3V3_S0_ODD

=PP5V_S0_SATA

=PP5V_S0_PWRCTL

=PP12V_S0_FAN =PP12V_S0_AUDIO_SPKRAMP

PP12V_S0

MAX_NECK_LENGTH=3 MM

VOLTAGE=12V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

PP1V8_S0_REG

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.1 MM

VOLTAGE=1.8V

=PP1V05_S0_MCP_SATA_DVDD0

PP12V_S0

=PPVTT_S3_DDR_BUF

=PP3V3_S3_BT

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_SDCARD

=PP3V3_S3_SMC

=PP5V_S3_USB

=PP5V_S3_DDRREG

PP5V_S3_REG

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

VOLTAGE=5V MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PPVCORE_S0_MCP

=PPVCORE_S0_CPU

=PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP

=PP1V5_S0_AUD_DIG

=PP1V5_S0_CPU_VCCPLL

=PP1V5_FWRS0_FWXIO

PP1V5_S0

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE VOLTAGE=1.5V

NET_SPACING_TYPE=PWR

=PP3V3_FW_FWPHY

PP5V_S0

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

VOLTAGE=5.0V MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

=PP5V_S0_LPCPLUS

=PP3V3_FWRS0_FWXIO

PP3V3_S0

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR

VOLTAGE=3.3V MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.30MM

MAX_NECK_LENGTH=4.1 MM

MAKE_BASE=TRUE

GND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

Power Conn / Alias

SYNC_MASTER=MASTER

SYNC_DATE=N/A

70

2N7002

SOT23-HF1

2.0X1.25MM-SM

GREEN-3.6MCD

1/16W

1K

5% MF-LF

402

9

2N7002

SOT23-HF1

MXM

2.0X1.25MM-SM

GREEN-3.6MCD

MF-LF

5% 1/16W

1K

402

MXM

2.0X1.25MM-SM

GREEN-3.6MCD

5% MF-LF

1/16W

1.5K

402

GREEN-3.6MCD

DEVELOPMENT

2.0X1.25MM-SM

DEVELOPMENT

1K

5% 1/16W MF-LF 402

MF-LF 402

5% 1/16W

1K

GREEN-3.6MCD

2.0X1.25MM-SM

CRITICAL

76833-0100

M-RT-TH

0.001UF

402

10% X7R

50V 50V

X7R

0.001UF

10%

402

10UF

20% 10V X5R 805

0.001UF

50V X7R 402

10%

2N7002

SOT23-HF1

402

10% X7R

50V

0.001UF

10% 16V

1210

10UF

X5R-CERM

70 50 49 9

0.001UF

402

50V X7R

10%

28 25

110 78 6 34

26

80

74

47

108 32 30

33

78

75

71

32

21 19 18

26

25 22 21

30 25 16

76

12 11

74 54

25

70

78

108 31 30

76 6

70

78

38

90

52

74

75

25 22

20 18

31

52

6

78

79

38

25 22

61 51

28

50 49

51

33

76 6

50

46

110 78 6

78 70 38

75

79

72 71

52

70 90 89

71 55 50 10

29

76

43

75

76

73

76

6

45 6

52

90

78 6

71

84

90

53

93

68 62

31

13

90 89

55

55 50

54 53 50

52

45

70

25

55

57 56

94

68 67 66 65 64 62

25 21

53

76

74

71 70

25

13

25 22 14

26

70

52

85 84

45

45 6

80

57 56

67

70 6

80

28 20

70 6

29

47

21

47

46

75 30

110 73

25 22

12

32

78

62

12

41

54

43 42 41

110 78 51

41

78 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BACKER PLATE NUTS

REAR COVER STANDOFFS

4 MM PLATED HOLES FOR CPU HEATSINK

DIMM CONNECTOR NUTS

998-0850

870-1125 FOR MCP HEATSINK

7 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

1

SDF0717

1

SDF0716

1

SDF0715

1

SDF0714

1

SDF0750

1

SDF0751

1

SDF0752

1

SDF0753

1

SDF0703

1

SDF0702

1

SDF0701

1

SDF0700

1

SDF0713

1

SC0701

1

SC0700

1

ZH0703

1

ZH0702

1

ZH0701

1

ZH0700

HOLES & STANDOFFS

SYNC_MASTER=MASTER

SYNC_DATE=N/A

CRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICALCRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICALCRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

STDOFF-6.8OD15.0H-1.56-TH

CRITICAL

CLIP-SM1

CRITICAL

EMI-SPRING

CLIP-SM1

EMI-SPRING

CRITICAL

OMIT

4P75R4

OMIT

4P75R44P75R4

OMITOMIT

4P75R4

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

NC ON UNUSED ALIASES

MCP HAS INTERNAL 15K PULL-DOWNS

UNUSED MEMORY SIGNALS

UNUSED GMUX JTAG FROM MCP

8 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_PE4_CLKREQ_L NC_PE4_CLKREQ_L

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_ENET_PWRDWN_L

USB_MINI_N

NC_USB_MINI_N

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_USB_10P

TP_USB_10N

NC_USB_MINI_P

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_MINI_P

NO_TEST=TRUE

NC_USB_EXCARD_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_P

USB_EXCARD_N

MAKE_BASE=TRUE

NC_ENET_INTR_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_KBDRSTIN_L

TP_PCIE_PE4_D2RN

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_P

NO_TEST=TRUE

NC_MCP_PCI_GNT0_L

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCI_AD<8>

NO_TEST=TRUE

NC_PCI_AD<8>

MAKE_BASE=TRUE

TP_PCI_AD<12..10>

NO_TEST=TRUE

NC_PCI_AD<12..10>

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

ODD_PWR_EN_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ODD_PWR_EN_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_10P

NO_TEST=TRUE

NC_USB_10N

MAKE_BASE=TRUE

TP_SB_A20GATE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_A20GATE

TP_PE4_PRSNT_L

NO_TEST=TRUE

NC_PE4_PRSNT_L

MAKE_BASE=TRUE

PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

NC_PCIE_EXCARD_PRSNT_L

NO_TEST=TRUE

TP_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P

TP_PCI_PAR

TP_PCI_INTZ_L

TP_PCI_INTW_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_FRAME_L

TP_PCI_CLK1

TP_PCI_CLK0

TP_PCI_C_BE_L<3>

PCIE_EXCARD_D2R_N

TP_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_PE4_R2D_CP

PCIE_EXCARD_D2R_P

NO_TEST=TRUE

NC_USB_TPAD_P

MAKE_BASE=TRUE

TP_PCIE_PE4_D2RP

NC_PCIE_PE4_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_PE4_D2RP

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

NC_MEM_A_CLK2P

NO_TEST=TRUE

GMUX_JTAG_TMS

NC_MCP_BUF_SIO_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_IRDY_L

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

CRT_IG_G_Y_Y

TP_PCI_AD<31..15>

NC_PCI_FRAME_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ENET_PWDWN_L

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_CLK0

NC_PCI_CLK1

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_TPAD_N

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_AD<31..15>

NC_PCI_PERR_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_GPIO_18

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_INTW_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_INTY_L

NO_TEST=TRUE

NC_PCI_INTZ_L

MAKE_BASE=TRUE

MCP_TV_DAC_RSET

MCP_CLK27M_XTALOUT

TP_PCI_IRDY_L

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_PCI_C_BE_L<1..0>

TP_ENET_INTR_L

TP_MCP_KBDRSTIN_L

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MCP_BUF_SIO_CLK

MAKE_BASE=TRUE

NC_LPC_DRQ0_L

NO_TEST=TRUE

TP_LPC_DRQ0_L

TP_PCI_PERR_L

MAKE_BASE=TRUE

NC_MEM_A_CLK2N

NO_TEST=TRUE

NC_MEM_A_CLK5P

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_MEM_A_CLK5P

NC_MEM_A_CLK5N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TCK_L

NO_TEST=TRUE

MAKE_BASE=TRUE

GMUX_JTAG_TCK_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TDO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TDI

GMUX_JTAG_TDI

MAKE_BASE=TRUE

NC_GMUX_JTAG_TMS

NO_TEST=TRUE

NC_PCI_C_BE_L<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

CRT_IG_VSYNC

NO_TEST=TRUE

NC_MEM_B_CLK2P

MAKE_BASE=TRUE

TP_MEM_B_CLK2P

NO_TEST=TRUE

NC_MEM_B_CLK2N

MAKE_BASE=TRUE

TP_MEM_B_CLK2N

NO_TEST=TRUE

NC_MEM_B_CLK5P

MAKE_BASE=TRUE

TP_PCI_INTY_L

NC_MLB_RAM_SIZE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MEM_B_CLK5P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_VSYNC

TP_PCI_DEVSEL_L

TP_PCI_SERR_L NC_PCI_SERR_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_DEVSEL_L

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MEM_A_CLK5N

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

PCIE_EXCARD_R2D_C_N

TP_PCI_RESET1_L

TP_PCI_STOP_L

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TP_PCI_TRDY_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4N

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

NC_PCI_TRDY_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_GNT1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_STOP_L

TP_MEM_B_CLK5N

NO_TEST=TRUE

NC_PCI_INTX_L

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MLB_RAM_SIZE

TP_MCP_GPIO_18

NC_MEM_B_CLK5N

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_PE4_R2D_CP

GMUX_JTAG_TDO

USB_TPAD_P

NC_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_N

NO_TEST=TRUE

NC_USB_TPAD_N

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCI_INTX_L

NO_TEST=TRUE

NC_PCI_PAR

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_RESET1_L

MAKE_BASE=TRUE

SYNC_MASTER=MASTER

SYNC_DATE=N/A

UNUSED SIGNAL ALIAS

17

18

20

17

19

17

21

17

19

17

19

18

19

20

18

19

18

19

18

21

19

16

17

19

18

15

19

16

19

16

17

19

15

16

21

17

20

19

OUT

IN

OUT

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB PORT 2 AND 3 (C AND D) SHARE OVER-CURRENT WITH PORT 2 PREVIOUSLY, PORT 3 HAD ITS OWN BUT EFI MAPS THAT TO EXPRESSCARD SEE RDAR://6250424

K22/K23 Use one GPIO for both ports 2&3 OC

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

MCP_CPUVDD_EN WILL ASSERT AFTER MCP_PS_PWRGD IS UP

Audio Mux aliasing

K23 Uses this to control the DP audio mux. K22 does not need this signal

K23 uses a mux between the DP audio source and the audio in port

this alias connects spdif directly from the I/O port to the codec

SIGNAL ALIAS

(P50 HAS A 100K TO GROUND)

MCP79 PCIe PRSNT# Straps

DisplayPort / TMDS Support

PEG Slot Support

9 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R993

2

1

R912

21

R911

21

R910

21

R930

2

1

R955

21

R983

21

R981

21

R992

21

R990

21

R991

21

R971

2

1

C973

21

R925

21

R972

21

R926

21

R929

21

R900

PCIE_RESET_L

PCA9557D_RESET_L

LPC_RESET_L

PM_CLK32K_SUSCLK

PM_CLK32K_SUSCLK_R

LPC_CLK33M_SMC

PEG_RESET_L

MINI_RESET_L

MCP_MII_NU

MAKE_BASE=TRUE

LPC_CLK33M_SMC_R

=MCP_MII_CRS

LPC_CLK33M_LPCPLUS

SMC_LRESET_L

FW_RESET_L

=MCP_MII_COL

=MCP_MII_RXER

DEBUG_RESET_L

MEM_VTT_EN_R

DDRVTT_EN

CARDREADER_PLT_RST_L

MCP_CPUVDD_EN

MCP_CPU_VLD

AUD_SPDIF_IN_CODEC

TP_AUD_MUX_CNTRL

MAKE_BASE=TRUE

AUD_SPDIF_IN

AUD_MUX_CNTRL

PM_SLPS3_BUF1_L

MAKE_BASE=TRUE

PM_SLP_S3_L

MAKE_BASE=TRUE

PM_SLPS3_BUF2_L

PCIE_FW_PRSNT_L

PCIE_MINI_PRSNT_L

GPU_CLK100M_PCIE_P

MAKE_BASE=TRUE

GPU_CLK100M_PCIE_N

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

MXM_DETECT_L

MAKE_BASE=TRUE

DP_IG_ML_P<3>

MAKE_BASE=TRUE

DP_IG_ML_N<3> DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

MAKE_BASE=TRUE

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_DATA DP_IG_HPD

MAKE_BASE=TRUE

HPLUG_DET2

MAKE_BASE=TRUE

=DVI_HPD_GMUX_INT

PEG_CLK100M_P

PEG_CLK100M_N =PEG_R2D_C_P<0..15> =PEG_R2D_C_N<0..15> =PEG_D2R_P<0..15> =PEG_D2R_N<0..15>

PEG_PRSNT_L

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

TP_MLB_RAM_VENDOR

MXM_GOOD

MAKE_BASE=TRUE

USB_EXTD_OC_L

MAKE_BASE=TRUE

USB_EXTC_OC_L

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SIGNAL ALIASES

47

5%

402

MF-LF

0

1/16W

62

62 103 66

402

100K

5% 1/16W MF-LF

402

MF-LF

1/16W

5%

15

5%

1/16W

402

MF-LF

15

21

PLACEMENT_NOTE=Place close to U1400

22

1/16W

5%

MF-LF

402

21

1/16W

47K

402

MF-LF

5%

51

49

41

34

90 87

29

78 75

103 49

103 51

103 49

402

1/16W

5%

MF-LF

33

PLACEMENT_NOTE=Place close to U1400

MF-LF

1/16W

5%

33

402

PLACEMENT_NOTE=Place close to U1400

103 19

402

0

5% 1/16W MF-LF

402

0

5% MF-LF

1/16W

0

MF-LF

5%

402

1/16W

0

MF-LF

5%

402

0.47UF

6.3V CERM-X5R

10%

402

NO STUFF

402

33

PLACEMENT_NOTE=Place close to U1400

5% 1/16W MF-LF

402

MF-LF

33

1/16W

5%

402

5% 1/16W MF-LF

33

PLACEMENT_NOTE=Place close to U1400

1/16W

5%

MF-LF

22

402

PLACEMENT_NOTE=Place close to U1400

17

19

103 19

103 21

1/16W

5%

20K

MF-LF

402

17 85

17

18

91

93

107 91

102 87

102 87 17

17

102 86

17

17 102 86

102 86

18

94 73

102 21 70 50 49 6

18

21 6

46

46 20

BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

BI

IN

A_34* A_35*

REQ_4*

A_7*

DBSY*

INIT*

A_20*

A20M*

ADS*

ADSTB_0*

ADSTB_1*

A_3* A_4*

A_6*

A_8*

A_10*

A_14* A_15* A_16*

A_17* A_18* A_19*

A_21* A_22* A_23* A_24* A_25* A_26* A_27* A_28* A_29* A_30* A_31* A_32* A_33*

BCLK_0 BCLK_1

BNR*

BPRI*

BR_0*

DEFER*

DRDY*

FERR_PBE*

IERR*

IGNNE*

LINT0 LINT1

REQ_0* REQ_1*

REQ_3*

RS_0* RS_1* RS_2*

SMI*

STPCLK*

REQ_2*

A_13*

A_12*

A_11*

A_9*

A_5*

LOCK*

RESET*

TRDY*

HIT*

HITM*

CONTROL

ADDR GROUP0

(1 OF 7)

CLK

SB

ADDR GROUP1

IN

OUT

IN

IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI

D_11*

D_10*

D_9*

D_1* D_2*

D_8*

D_7*

D_6*

DBI_0*

DBI_1*

DBI_2*

DBI_3*

DSTBN_0*

DSTBN_1*

DSTBN_2*

DSTBN_3*

DSTBP_0

DSTBP_1

DSTBP_2

DSTBP_3

D_0*

D_3* D_4* D_5*

D_12* D_13* D_14* D_15*

D_16* D_17* D_18* D_19* D_20* D_21* D_22* D_23* D_24* D_25* D_26* D_27* D_28* D_29* D_30* D_31*

D_32* D_33* D_34* D_35* D_36* D_37* D_38* D_39* D_40* D_41* D_42* D_43* D_44* D_45* D_46* D_47*

D_48* D_49* D_50* D_51* D_52* D_53* D_54* D_55* D_56* D_57* D_58* D_59* D_60* D_61* D_62* D_63*

(2 OF 7)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE W/ A TESTPOINT W/ A GND NEARBY

CPU GTLREF

(63.5% OF 1.2V) = 0.762V

GTLREF VOLTAGE SHOULD BE 0.635 * VTT

10 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1044

2

1

R1043

2

1

R1001

2

1

C1042

21

R1045

2

1

C1043

2

1

R1041

2

1

C1040

2

1

R1040

2

1

C1041

21

R1042

C17

G19

E12

B9

A16

G20

G12

C8

C20

D19

G11

A8

A11

A10

A7

B22

A22

A19

B19

B7

B21

C21

B18

A17

B16

C18

B15

C14

C15

A14

B6

D17

D20

G22

D22

E22

G21

F21

E21

F20

E19

A5

E18

F18

F17

G17

G18

E16

E15

G16

G15

F15

C6

G14

F14

G13

E13

D13

F12

F11

D10

E10

D7

A4

E9

F9

F8

G9

D11

C12

B12

D8

C11

B10

C5

B4

J1000

E3

M3

P2

A3

F5

B3

G23

J6

K6

M6

J5

K4

C3

L1

K1

P3

N2

AB2

E4

D4

R3

C1

G7

B2

F3

G8

C2

G28

F28

AD5

R6

D2

T5

R4

M4

L4

M5

P6

AJ6

AJ5

AH5

AH4

AG5

AG4

L5

AG6

AF4

AF5

AB4

AC5

AB5

AA5

AD6

AA4

Y4

Y6

W6

AB6

W5

V4

V5

U4

U5

T4

U6

K3

J1000

2

1

R1004

2

1

R1003

2

1

R1000

PPCPU_VTT_OUT_LEFT

FSB_BPRI_L

FSB_DEFER_L

FSB_DBSY_L

FSB_BREQ0_L

CPU_FERR_L

PPCPU_VTT_OUT_RIGHT

CPU_STPCLK_L

CPU_NMI

FSB_HIT_L FSB_HITM_L

FSB_CPURST_L

CPU_IERR_L CPU_INIT_L

FSB_RS_L<0> FSB_RS_L<1>

PPCPU_VTT_OUT_RIGHT

FSB_RS_L<2>

FSB_TRDY_L

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_D_L<27>

CPU_GTLREF1

FSB_BNR_L

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_DINV_L<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<25>

FSB_DSTB_L_P<0>

FSB_DINV_L<0>

FSB_D_L<13>

FSB_D_L<11>

FSB_ADS_L

=PPVTT_S0_CPU

CPU_IGNNE_L

FSB_DSTB_L_N<0>

FSB_D_L<12>

FSB_D_L<9>

FSB_LOCK_L

FSB_A_L<3>

FSB_D_L<10>

FSB_D_L<1> FSB_D_L<2>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_DINV_L<2>

FSB_DINV_L<3>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_D_L<0>

FSB_D_L<3> FSB_D_L<4> FSB_D_L<5>

FSB_D_L<14> FSB_D_L<15>

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26>

FSB_D_L<30> FSB_D_L<31>

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

PPCPU_VTT_OUT_LEFT

CPU_GTLREF0

CPU_GTLREF_DIV0

FSB_REQ_L<4>

FSB_A_L<7>

CPU_A20M_L

FSB_ADSTB_L<0>

FSB_A_L<4>

FSB_A_L<6>

FSB_A_L<10>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30>

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_DRDY_L

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<3>

CPU_SMI_L

FSB_REQ_L<2>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<5>

FSB_A_L<31>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_INTR

FSB_A_L<8>

PPCPU_VTT_OUT_LEFT

CPU_GTLREF_DIV1

SYNC_MASTER=MASTER

CPU FSB

SYNC_DATE=N/A

100

1% 1/16W MF-LF 402

MF-LF

57.6

402

1% 1/16W

MF-LF

5%

402

62

1/16W

1UF

6.3V CERM 402

10%

MF-LF

402

1%

10

1/16W

X7R-CERM

NOSTUFF

220PF

10%

402

50V

1% 1/16W MF-LF

100

402

CERM

10%

6.3V

1UF

402

1/16W

57.6

402

MF-LF

1%

10%

402

X7R-CERM

50V

220PF

NOSTUFF

1/16W

10

1%

MF-LF

402

CPU

CRITICAL

WOLFDALE-SKT-1

BGA-NOHSK

100 14

CPU

CRITICAL

WOLFDALE-SKT-1

BGA-NOHSK

200

1/16W 402

5% MF-LF

402

62

MF-LF

5% 1/16W

MF-LF

5%

402

62

1/16W

100 14

100 14 13

100 14

12 11 10

100

12 11 10

100 29 11

71 55 50 6

12 11 10

100 29 11

12 11 10

IN IN

OUT

IN IN

BI BI

BI

IN

BI

TESTHI_0

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5*

DBR*

FC3

FC8 FC10 FC15 FC18 FC23 FC26

FC27/BPMB0*

FC28/TDO_M

FC29 FC30 FC31 FC32 FC33 FC34 FC35 FC36 FC37 FC39 FC40

FC41/BPMB1*

ITPCLK_0 ITPCLK_1

RSVD_A20

RSVD_AC4 RSVD_AE4

RSVD_AE6

RSVD_AH2

RSVD_D1

RSVD_D14

RSVD_D16

RSVD_E5

RSVD_E6

RSVD_E7

RSVD_E23 RSVD_F23

RSVD_F29

RSVD_G6

RSVD_J3

RSVD_N4

RSVD_N5

RSVD_P5

RSVD_V2

TCK TDI TDO

TESTHI_1 TESTHI_2 TESTHI_3 TESTHI_4 TESTHI_5 TESTHI_6 TESTHI_7

TESTHI_8/BPMB3*

TESTHI_9/BPMB2*

TESTHI_10

TESTHI_12/TDI_M

TMS TRST*

(4 OF 7)

RESERVED

TEST JTAG

XDP/ITP

PROCHOT* THERMTRIP*

GTLREF1 GTLREF0

THERMDC

FC5/GTLREF2

BOOTSELECT

BSEL_0 BSEL_1 BSEL_2

COMP_0 COMP_1 COMP_2 COMP_3 COMP_8

DPRSTP*

DPSLP*

IMPSEL

MSID_0

MSID_1

PECI

PSI*

PWRGOOD

SKTOCC*

SLP*

THERMDA

VRDSEL

FC38/GTLREF3

(3 OF 7)

THERMAL

PWR MGMT

BI

BI BI

BI BI BI BI

OUT OUT OUT

IN OUT OUT OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(TDI)

WITHIN 38MM (1.5IN) OF THE CPU

FROM 975X PDG: IMPSEL 0 - 51 PD TO GND

IPU

NC

NC NC NC

PLACE TMS/TMI/TCK TERMINATION

(TMS)

(TCK)

NC

(ALSO WRITTEN AS BPM2)

CPU BPMB TERM

KENTSFIELD CPU SUPPORT

CPU BPM TERM

(SELECTS 50 OHM SYSTEM IMPEDANCE)

11 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1150

2

1

R1120

2

1

R1121

2

1

R1122

2

1

R1123

2

1

R1128

2

1

R1151

2

1

R1109

2

1

R1129

2

1

R1180

2

1

R1181

2

1

R1182

2

1

R1183

2

1

R1130

2

1

R1133

2

1

R1132

2

1

R1135

AL3

M2

AK1

AL1

L2

AE8

N1

Y3

AL2

G5

V1 W1

F6

H2 H1 F2

G10

P1

T2

B13

R1

G2

T1

A13

G30

H30

G29

Y1

J1000

AG1

AC1

G4 G3

F24

G24

G26

G27

G25

F25

W2

H5

W3

F26

AF1

AD1

AE1

V2

P5

N5

N4

J3

G6

F29

F23

E7

E6 E5

E23

D16

D14

D1

AH2

AE6

AE4

AC4

A20

AJ3

AK3

AK6

C9

AM6

AA2

AB3

AD3

H4

J17

H16

H15

J16

U3

J2

U2

U1

G1

E29

A24

AE3

H29

E24

AC2

AG3

AF2

AG2

AD2

AJ1

AJ2

J1000

2

1

R1191

2

1

R1195

2

1

R1190

2

1

R1192

2

1

R1193

2

1

R1194

21

R1102

21

R1101

21

R1100

CPU_PWRGD

CPU_DPRSTP_L

CPU_DPSLP_L

CPU_PROCHOT_L

PPCPU_VTT_OUT_RIGHT

CPU_GTLREF1

CPU_BOOT

CPU_BSEL<0> CPU_BSEL<1>

CPU_PSI_L

FSB_CPUSLP_L

CPU_BSEL<2>

CPU_THERMD_N

CPU_THERMD_P

CPU_PECI_L

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<0>

CPU_GTLREF0

CPU_COMP<0>

CPU_COMP<1>

CPU_COMP<8>

CPU_COMP<2>

CPU_COMP<3>

=PPVTT_S0_FSB_CPU

PPCPU_VTT_OUT_LEFT

CPU_XDP_BPM_L<3> CPU_XDP_BPM_L<4> CPU_XDP_BPM_L<5>

CPU_XDP_BPM_L<1> CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<0>

PPCPU_VTT_OUT_RIGHT

CPU_XDP_TCK CPU_XDP_TDI

CPU_XDP_TMS

CPU_TESTHI_M

CPU_TESTHI_2_7

PPCPU_VTT_OUT_RIGHT

PPCPU_VTT_OUT_LEFT

CPU_TESTHI_0 CPU_TESTHI_1

CPU_TESTHI_10

PM_PGOOD_PVCORE_CPU

CPU_XDP_BPMB<0> CPU_XDP_BPMB<1>

CPU_XDP_BPMB<3>

CPU_XDP_BPMB<2>

CPU_XDP_BPMB<0>

CPU_XDP_BPMB<1>

CPU_XDP_TDO

CPU_XDP_TRST_L

CPU_XDP_BPM_L<0> CPU_XDP_BPM_L<1> CPU_XDP_BPM_L<2> CPU_XDP_BPM_L<3> CPU_XDP_BPM_L<4> CPU_XDP_BPM_L<5>

CPU_XDP_BPMB<2>

CPU_XDP_BPMB<3>

XDP_DBRESET_L

PM_THRMTRIP_L

CPU_COMP<1>

CPU_COMP<8> CPU_PD_IMPSEL

SYNC_DATE=N/A

SYNC_MASTER=MASTER

CPU TEST & MISC.

71 70

100 50 14

71

100 14

100 14 13

100 14

402

1/16W MF-LF

130

1%

NOSTUFF

MF-LF

1/16W 402

1%

49.9

402

MF-LF

49.9

1% 1/16W 1/16W

1%

402

MF-LF

49.9 49.9

1% 1/16W MF-LF 402

1%

402

MF-LF

1/16W

24.9

402

5% 1/16W MF-LF

51

108 55

51

402

1/16W

5% MF-LF

100 14

MF-LF

51

1/16W

5%

402

100 13 11

5% 1/16W

402

MF-LF

51

5% 1/16W

402

51

MF-LF

5%

402

MF-LF

1/16W

51

5% 1/16W MF-LF 402

51

100 13 11

MF-LF

402

51

1/16W

5%

MF-LF

402

1/16W

5%

51 51

1/16W

5%

402

MF-LF MF-LF

51

5%

402

1/16W

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

BGA-NOHSK

WOLFDALE-SKT-1

CRITICAL

CPU

1/16W

5% MF-LF

402

51

MF-LF

51

1/16W

5%

402402

1/16W

51

MF-LF

5%

51

402

MF-LF

1/16W

5%

51

402

MF-LF

1/16W

5%

51

1/16W

5% MF-LF

402

100 13 11

51

5%

402

1/16W MF-LF

5%

51

402

MF-LF

1/16W

5%

51

402

1/16W MF-LF

28 13

100 13 11

100 13

12 11 10

100 29 10

100 11

100 29 10

100 11

12 6

12 11 10

100 13 11

12 11 10

100 11

OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

VCCP

VTT_C29 VTT_C30 VTT_D25 VTT_D26 VTT_D27 VTT_D28 VTT_D29 VTT_D30

VTT_OUT_RIGHT VTT_OUT_LEFT VTT_SEL

VTT_C28

VTT_C27

VTT_C26

VTT_C25

VTT_B29

VTT_B28

VTT_B27

VTT_B26

VTT_B25

VTT_A30

VTT_A29

VTT_A28

VTT_A27

VTT_A26

VTT_A25

VTT_B30

VCCA

VCCIOPLL

VCCP

VCCPLL

VCC_MB_REGULATION

VCC_SENSE

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

VID_SELECT

VSSA

VSS_MB_REGULATION

VSS_SENSE

VCCP

(7 OF 7)

OUT

GND GND

(5 OF 7)

GNDGND

(6 OF 7)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

POWER

GND

VCC PLL DECOUPLING

(SEE VREG PAGE)

VCCP CORE DECOUPLING

~125MA CURRENT

THIS IS FOR OLDER CPU SUPPORT

GND

WILL PLACE FILTER BUT NOT CONNECT FOR WOLFDALE

VID PULLUPS WITH VREG

FSB VTT DECOUPLING

12 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1200

V25

E20

R7

V27

R5

V28 V29

R2

V30

V26

E26

P7

P4

N7

N6

N3

M7

M1

L7

L6

C13

V7

B8

B5

B1

D3 D5

R30

D6

C4

D9

E2

H6

T7

Y2

H3

AN24 AN27 AN28

E27

H12

B11

K7

B14

C22

K2

C24

D12

C10

C19

AN2

D18

F7

D21

E11

Y5

L28

E14

H7 H8

H28

H9

AN23

AN20

J4

K5

J7

L25

D24

E28

F10 F13 F16

F22

F4

E17

F19

C16

H13 H14 H17 H18 H19 H20 H21 H22

H10

H23 H24 H25

B17

H26

B20

E8

H27

L3

B24

L23 L24

H11

L26 L27

Y7

D15

L29

L30

C7

P23

W7

P25

W4

P26 P27

V6

P28 P29

V3

P30

R23 R24

U7

R25 R26 R27 R28 R29

E25

T6

V23 V24

T3

P24

J1000

AN10

AA24 AA25 AA26 AA27

AN13

AA28

AM4

AA29

AA30

AB23 AB24 AB25

AN16

AB26

AB1

AB27

AN17

AB28 AB29 AB30

AK24

AJ27

AH1

AE26

AJ4

A9

A6

A2

A18

AF13

AE10

AF16 AF17

AG24

AF23 AF24 AF25 AF26 AF27

AL7 AJ7

AH7

AK7

AF7

AK23

AL10

AF28

AE16

AN1

AF29

AL17

AL13

AM1

AM27

AK20

AK16

AL20

AK13

AL24

AL16

AM24

AE24

AF10

AE30

AE29

AF30

AE28

A12

AL23

AK30

AG7

AE13

AJ23

AM10

AK10

AH3

AJ17

AK29

AF6

AG10

AE17

AJ16

AK5

AF3

AJ10

AJ30

AH24

AM13

AE7

AH23

AE5

AH20

AH17

AK17

AH16

AD7

AH13

AJ28

AE27

AG13

AE25

AM16

AH6

AC7

AC6

AC3

AM17

AG16

AJ24

AB7

AA6

AG17

AA7

AA3

AM20

AK28

AK27

AJ29

AE2

A21

AH10

A15

AM23

AG20

AD4

AL27

AG23

AJ20

AJ13

AM28

AF20

AK2

AL28

AA23

AE20

J1000

F27

AA1

J1

D30

D29

D28

D27

D26

D25

C30

C29

C28

C27

C26

C25

B30

B29

B28

B27

B26

B25

A30

A29

A28

A27

A26

A25

B23

AN4 AN6

AN7

AM7

AM5

AL4

AK4

AL6

AM3

AL5

AM2

D23

AM15

AD23

AF11

AK15

AG27

J21

J18

J26

AL15

AF18

AD29

AH15

AN9

AG26

AJ15

J10

AK26

AG11

AN29

AK22

AF22

AL29

AF9

N26

AG9

AN12

AK8

T27

AJ19

U26

AJ8

AN15

AG8

AL22

AH12

N28

T26

AM8

AL19

K23

P8

K25

J11

AA8

J29

AH9

AJ25

AL30

N29

AG14

AK11

AJ9

AL12

AH25

AG18

AN30

AL14

K30

AJ11

AL11

AM11

AJ21

AG30

AK21

AK14

J30

Y24

AF21

AD30

AL9

AG19

J27

J12

W28

T28

J13

AF14

J24

AM12

AL26

AG28

AH27

AH29

AH19

J15

AL8

AE11 AE12

AM26

K29

AG22

AJ14

AB8

AM19

AM18

AC27

J23

U24

M29

AC29

Y26

AD28

AH11

AN14

Y30

W30

AC25

AL18

Y28

T25

W25

W24

W23

AK9

M27

Y25

Y27

AN18

AN11

AN25

AN26

Y23

AC23

AC24

U29

M28

W29

N23

AE14

AC8

AF15

AM9

T30

J28

J8

AC26

AF12

W26

AE18

N25

AC28

T8

AN21

M24

K27

M30

AE15

N8

AC30

AE19

AM30

AE21

K8

V8

AN19

AE22 AE23

AD24

AF19

K28

U28

AM22

N27

AG29

M23

U23

AD27

AJ12

Y8

K26

U25

L8

M26

M25

AM29

AJ26

AD26

N30

M8

AD25

J14

AM21

AG21

T24

J22

AG15

AK19

AK25

Y29AE9

AM25

AN22

AM14

T29

AH22

AK12

AH21

AH28

K24

AD8

AK18

U8

N24

R8 T23

AH14

AN8

AL25

W27

AH26

AH18

J20

AJ22

AH8

AG12

AH30

J19

AJ18

AG25

AL21

U30

J25

AF8

W8

J9

U27

C23

A23

AN3 AN5

J1000

2

1

C1200

2

1

C1201

2

1

C1281

2

1

C1280

2

1

C1210

2

1

C1213

2

1

C1211

2

1

C1212

21

R1211

21

R1210

21

L1210

2

1

C1238

2

1

C1237

2

1

C1236

2

1

C1235

2

1

C1234

2

1

C1226

CPU_VCC_PKG_SENSE_P

CPU_VCC_SENSE

CPU_VID_SELECT

PPCPU_VTT_OUT_RIGHT

=PPVCORE_S0_CPU

PPCPU_VTT_OUT_RIGHT

MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.2V

CPU_VID_SELECT

=PPVTT_S0_FSB_CPU

TP_CPU_VSS_SENSE

=PPVTT_S0_FSB_CPU

CPU_VID<4>

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.2V

CPU_VCCIOPLL

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.2V

CPU_VCCA

CPU_VID<3>

=PP1V5_S0_CPU_VCCPLL

VOLTAGE=1.2V

PPCPU_VTT_OUT_LEFT

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPCPU_VTT_OUT_LEFT

=PP1V5_S0_CPU_VCCPLL

CPU_VCCA_FLT

CPU_VID<0>

CPU_VSSA

CPU_VID<6>

CPU_VID<5>

CPU_VID<2>

CPU_VCCIOPLL

CPU_VCCA

PPCPU_VTT_OUT_RIGHT

TP_VTT_SEL

CPU_VID<1>

CPU_VCC_PKG_SENSE_N

CPU_VID<7>

=PPVTT_S0_FSB_CPU

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPU_VSSA

VOLTAGE=0V

SYNC_MASTER=MASTER

SYNC_DATE=N/A

CPU POWER, GND, DECAPS

CERM 402

20%

0.1UF

10V

20% 402

10V CERM

0.1UF

CERM

10V 402

20%

0.1UF

402

10V

20% CERM

0.1UF

402

0.1UF

10V

20% CERM

10V

20%

0.1UF

CERM 402

MF-LF

1/16W

5%

680

402

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

100 71

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

20%

0.1UF

10V CERM 402

0.1UF

CERM 402

20% 10V

0.01UF

CERM

10% 16V

402

20%

10UF

X5R

6.3V 603

22UF

20%

6.3V CERM-X5R 805-3

20%

603

10uF

X5R

6.3V

6.3V CERM

402

10%

1UF

NOSTUFF

402

CERM

10%

1UF

6.3V

NOSTUFF

0

5% 1/10W MF-LF

603

1/10W

0

603

5% MF-LF

CONROE

0603

FERR-120-OHM-0.2A

100 71

108 53

100 71

12

12 11 10

6

12

11 10

12

12 11 6

12

12 6

12

11 10

12 11 10

12 6

12

12 11 10

12 11 6

12

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

IN IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PWRGD/HOOK0

OBSDATA_A3

OBSDATA_A2

TRSTn

DBR#/HOOK7

RESET#/HOOK6

OBSFN_D1

OBSFN_D0

OBSDATA_C1

OBSDATA_C0

OBSFN_C1

OBSFN_C0

OBSDATA_C2 OBSDATA_C3

OBSDATA_B3

OBSDATA_D1

OBSDATA_A1

MCP79-specific pinout

OBSFN_A1

HOOK3

OBSFN_B1

OBSDATA_B2

TDO

TDI

XDP_PRESENT#

TMS

TCK0

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_B0

OBSFN_A0

HOOK1

OBSDATA_D0

VCC_OBS_CD

OBSDATA_A0

OBSFN_B0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_D2

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

HOOK2

VCC_OBS_AB

13 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1301

2

1

R1316

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1300

21

R1303

2

1

C1301

2

1

C1300

2

1

R1315

21

R1399

TP_XDP_OBSFN_B0

FSB_CLK_ITP_P

CPU_XDP_TDO

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TDI JTAG_MCP_TMS

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

JTAG_MCP_TRST_L

JTAG_MCP_TDO

=PP3V3_S0_XDP

CPU_XDP_BPMB<1>

CPU_XDP_BPMB<3>

MCP_DEBUG<4> MCP_DEBUG<5>

CPU_XDP_BPM_L<0>

CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<1>

CPU_XDP_BPM_L<4>

CPU_XDP_TMS

CPU_XDP_TDI

MCP_DEBUG<6>

FSB_CPURST_L

MCP_DEBUG<7>

CPU_XDP_BPM_L<5>

CPU_PWRGD

CPU_XDP_BPM_L<3>

=PPVTT_S0_XDP

TP_XDP_OBSFN_B1

XDP_DBRESET_L

XDP_PWRGD

JTAG_MCP_TCK

PM_LATRIGGER_L

SMBUS_MCP_0_CLK

CPU_XDP_TRST_L

CPU_XDP_TCK

SMBUS_MCP_0_DATA

XDP_OBS20

CPU_XDP_BPMB<0>

CPU_XDP_BPMB<2>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

eXtended Debug Port (XDP)

51

402

5%

XDP

1/16W MF-LF

100 11

MF-LF

1/16W

XDP

62

5%

402

19

28 11

100 11

100 14

21

19

21

100 11

LTH-030-01-G-D-A-TR

XDP_CONN

CRITICAL

F-ST-SM

5%

1/16W

XDP

1K

402

PLACEMENT_NOTE=Place close to CPU to minimize stub.

MF-LF

100 14 10

100 11

X5R

16V

402

10%

0.1uF

XDP

16V

402

X5R

10%

0.1uF

XDP

MF-LF

1/16W

1%

54.9

402

106 52 21

XDP

1/16W

5%

MF-LF

1K

402

100 14 11

100

6

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT

IN

BI BI

CPU_ADSTB0*

CPU_BPRI*

CPU_A25*

CPU_A24*

CPU_D4*

BCLK_OUT_CPU_N

BCLK_VML_COMP_GND

BCLK_VML_COMP_VDD

CPU_A14* CPU_A15*

CPU_A10* CPU_A11*

CPU_A13*

CPU_A12*

CPU_A16*

CPU_A31*

CPU_A18*

CPU_A30*

CPU_A26*

CPU_A33*

CPU_A21*

CPU_A20*

CPU_A23*

CPU_A19*

CPU_A22*

CPU_A28* CPU_A29*

CPU_A7*

CPU_A17*

CPU_A27*

CPU_A35*

CPU_A34*

CPU_A32*

CPU_REQ2*

CPU_A9*

CPU_REQ3*

CPU_A4*

CPU_A8*

CPU_A3*

CPU_ADSTB1*

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

CPU_COMP_GND

CPU_COMP_VCC

CPU_D1*

CPU_D3*

CPU_D15*

CPU_D11*

CPU_D10*

CPU_D8*

CPU_D13*

CPU_D9*

CPU_D23*

CPU_D19*

CPU_D21* CPU_D22*

CPU_D2*

CPU_D18*

CPU_D20*

CPU_D17*

CPU_D31*

CPU_D28*

CPU_D27*

CPU_D25* CPU_D26*

CPU_D24*

CPU_D7*

CPU_D30*

CPU_D29*

CPU_D38*

CPU_D33*

CPU_D32*

CPU_D39*

CPU_D37*

CPU_D36*

CPU_D5*

CPU_D42*

CPU_D44*

CPU_D43*

CPU_D40* CPU_D41*

CPU_D45*

CPU_D49*

CPU_D55*

CPU_D6*

CPU_D50*

CPU_D53*

CPU_D52*

CPU_D51*

CPU_D48*

CPU_D54*

CPU_D59*

CPU_D57*

CPU_D62*

CPU_D58*

CPU_D0*

CPU_D61*

CPU_D60*

CPU_D63*

CPU_D56*

CPU_D14*

CPU_D12*

CPU_DBI1*

CPU_DBI2*

CPU_DPRSTP*

CPU_DPSLP*

CPU_DPWR*

CPU_DSTBN0*

CPU_DSTBN2*

CPU_DSTBN3*

CPU_DSTBP0*

CPU_DSTBP1*

CPU_DSTBP2*

CPU_DSTBP3*

CPU_FERR*

CPU_HIT*

CPU_LOCK*

CPU_NMI

CPU_PECI CPU_PROCHOT*

CPU_REQ0* CPU_REQ1*

CPU_A6*

CPU_RESET*

CPU_RS0* CPU_RS1* CPU_RS2*

CPU_SLP*

CPU_SMI*

CPU_THERMTRIP*

CPU_TRDY*

V1P1_DLLDLCELL_AVDD

V1P1_PLL_CPU

V1P1_PLL_FSB

V1P1_PLL_MCLK

CPU_D16*

CPU_D47*

CPU_D46*

CPU_A5*

CPU_DBI3*

CPU_D35*

CPU_D34*

BCLK_OUT_ITP_N

CPU_DEFER*

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P

BCLK_IN_N

BCLK_OUT_NB_N

BCLK_OUT_NB_P

CPU_INIT*

BCLK_IN_P

CPU_A20M*

CPU_IGNNE*

CPU_INTR

CPU_PWRGD

CPU_STPCLK*

CPU_BR0* CPU_BR1* CPU_DBSY* CPU_DRDY*

CPU_HITM*

CPU_BNR*

CPU_ADS*

CPU_REQ4*

CPU_DBI0*

CPU_DSTBN1*

FSB

(1 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

20 mA 29 mA 15 mA

206 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Loop-back clock for delay matching.

270 mA (A01)

NC

14 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1420

2

1

R1421

2

1

R1422

AH27 AG28 AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC39

AC37

AE38

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

T43

T41

W41

H39

H43

K41

J40

V42

H41

H42

L41

M43

M42

K42

N41

N40

M40

P41

Y39

L42

H40

J39

J38

J37

L39

L38

L37

N38

N36

Y42

R39

N33

R37

R38

N34

P35

R34

R35

U38

R33

W42

U37

U36

U35

U34

U33

W38

W35

W34

W33

AA34

Y40

AA37

AA36

AA35

AA38

R42

P42

R41

U41

T39

T42

Y43

Y41

AM43 AM42

F42 D42 F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AE34

AE35

AC34

AC35

AC33

AE37

AN34

AR39

AN36

AN35

AN38

AL33

AB35

AN37

AL34

AL35

AJ33

AL38

AL39

AJ36

AL37

AJ35

AF41

AJ37

AJ38

AG33

AJ34

AG34

AG35

AF35

AG37

AG38

AE33

AG39

AM39 AM40

AL41 AK42

AL43 AL42

G42 G41

AJ40

AK41

U1400

2

1

R1416

2

1

R1440

2

1

R1410

2

1

R1435

2

1

R1430

2

1

R1431

2

1

R1436

=PP1V05_S0_MCP_FSB

CPU_FERR_L

=PP1V05_S0_MCP_FSB

FSB_ADSTB_L<0>

FSB_DEFER_L

FSB_BPRI_L

FSB_A_L<25>

FSB_D_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_MCP_N

FSB_CLK_MCP_P

FSB_A_L<14>

FSB_A_L<11>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<16>

FSB_A_L<31>

FSB_A_L<18>

CPU_A20M_L

FSB_A_L<26>

FSB_A_L<33>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<28>

FSB_A_L<7>

FSB_A_L<27>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<32>

FSB_REQ_L<2>

FSB_A_L<9>

FSB_REQ_L<3>

FSB_A_L<4>

FSB_A_L<8>

FSB_A_L<3>

FSB_ADS_L

FSB_ADSTB_L<1>

FSB_BNR_L FSB_BREQ0_L

FSB_D_L<1>

FSB_D_L<3>

FSB_D_L<15>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<8>

FSB_D_L<13>

FSB_D_L<9>

FSB_D_L<23>

FSB_D_L<19>

FSB_D_L<21> FSB_D_L<22>

FSB_D_L<2>

FSB_D_L<18>

FSB_D_L<20>

FSB_D_L<17>

FSB_D_L<31>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<25> FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<7>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<35>

FSB_D_L<38>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<34>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<5>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<40> FSB_D_L<41>

FSB_D_L<49>

FSB_D_L<55>

FSB_D_L<6>

FSB_D_L<50>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<48>

FSB_D_L<54>

FSB_D_L<59>

FSB_D_L<57>

FSB_D_L<62>

FSB_D_L<58>

FSB_D_L<0>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<63>

FSB_D_L<56>

FSB_D_L<14>

FSB_D_L<12>

FSB_DINV_L<0>

FSB_DINV_L<1>

FSB_DINV_L<2>

FSB_DBSY_L

CPU_DPRSTP_L

FSB_DRDY_L

FSB_DSTB_L_N<0>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>

FSB_DSTB_L_P<1>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_HITM_L FSB_LOCK_L

CPU_PECI_MCP

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<4>

FSB_A_L<6>

FSB_CPURST_L

FSB_RS_L<0>

CPU_STPCLK_L

FSB_D_L<16>

FSB_D_L<47>

FSB_D_L<46>

FSB_A_L<5>

FSB_DINV_L<3>

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<17>

FSB_A_L<23>

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_IGNNE_L

FSB_D_L<45>

FSB_D_L<42>

FSB_A_L<24>

MCP_CPU_COMP_GND

MCP_BCLK_VML_COMP_GND

MCP_BCLK_VML_COMP_VDD

FSB_CPUSLP_L CPU_DPSLP_L

MCP_CPU_COMP_VCC

PP1V05_S0_MCP_PLL_FSB

FSB_RS_L<2>

FSB_RS_L<1>

FSB_HIT_L

CPU_BSEL<2> CPU_BSEL<1> CPU_BSEL<0>

FSB_A_L<21> FSB_A_L<22>

FSB_A_L<29> FSB_A_L<30>

PM_THRMTRIP_L

CPU_PROCHOT_L

FSB_TRDY_L

FSB_BREQ1_L

CPU_INIT_L

MCP CPU Interface

SYNC_MASTER=MASTER

SYNC_DATE=N/A

402

470

MF-LF

1/16W

5%

1/16W MF-LF

5%

470

402

1/16W MF-LF

5%

470

402

OMIT

BGA

MCP7A

5%

62

MF-LF 402

1/16W

5%

MF-LF 402

1/16W

150

NO STUFF

1/16W MF-LF

402

62

5%

MF-LF 402

1% 1/16W

49.9

1/16W

1%

402

MF-LF

49.9

MF-LF

402

1%

1/16W

MF-LF 402

1% 1/16W

49.9

100 10

100 50 11

108 55

100 11

100 10

100 11

100 13 11

100 10

100 13

100 10

100 13 10

100 10

100 11

25 22 14 6

100

25

100

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

MDQ0_1

MDQ0_2

MCLK0A_1_N

MCLK0A_0_P

MCS0A_0*

MDQ0_63 MDQ0_62 MDQ0_61

MDQS0_1_P

MDQS0_0_P

MDQ0_57

MDQ0_41 MDQ0_40

MDQ0_28

MDQ0_42

MDQ0_43

MDQ0_44

MDQ0_45

MDQ0_46

MDQ0_47

MDQ0_48

MDQ0_49

MDQ0_38

MA0_0

MA0_1

MA0_10

MA0_11

MA0_12

MA0_13

MA0_14

MA0_2

MA0_4

MA0_5

MA0_6

MA0_7

MA0_8

MA0_9

MBA0_0

MBA0_1

MBA0_2

MCAS0*

MCKE0A_0

MCKE0A_1

MCLK0A_0_N

MCLK0A_1_P

MCLK0A_2_N

MCLK0A_2_P

MCS0A_1*

MDQ0_0

MDQ0_10

MDQ0_11

MDQ0_12

MDQ0_13

MDQ0_14

MDQ0_15

MDQ0_16

MDQ0_17

MDQ0_18

MDQ0_20

MDQ0_21

MDQ0_22

MDQ0_23

MDQ0_24

MDQ0_25

MDQ0_26

MDQ0_27

MDQ0_29

MDQ0_3

MDQ0_30

MDQ0_31

MDQ0_32

MDQ0_33

MDQ0_34

MDQ0_35

MDQ0_36

MDQ0_37

MDQ0_39

MDQ0_4

MDQ0_5

MDQ0_55

MDQ0_56

MDQ0_58

MDQ0_59

MDQ0_6

MDQ0_60

MDQ0_7

MDQ0_9

MDQM0_0

MDQM0_1

MDQM0_2

MDQM0_3

MDQM0_4

MDQM0_5

MDQM0_6

MDQM0_7

MDQS0_0_N

MDQS0_1_N

MDQS0_2_N

MDQS0_2_P

MDQS0_3_N

MDQS0_3_P

MDQS0_4_N

MDQS0_4_P

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MODT0A_0

MODT0A_1

MRAS0*

MWE0*

MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50

MA0_3

MDQ0_19

MDQ0_8

0A

MEMORY

CONTROL

MEMORY PARTITION 0

(2 OF 11)

MDQ1_43

MA1_0

MA1_1

MA1_10

MA1_11

MA1_12

MA1_13

MA1_14

MA1_2

MA1_3

MA1_4

MA1_5

MA1_6

MA1_7

MA1_8

MA1_9

MBA1_0

MBA1_1

MBA1_2

MCAS1*

MCKE1A_0

MCS1A_0*

MDQ1_0

MDQ1_1

MDQ1_10

MDQ1_11

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_16

MDQ1_17

MDQ1_18

MDQ1_19

MDQ1_2

MDQ1_20

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_25

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_3

MDQ1_30

MDQ1_31

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_4

MDQ1_40

MDQ1_41

MDQ1_42

MDQ1_44

MDQ1_45

MDQ1_46

MDQ1_47

MDQ1_48

MDQ1_49

MDQ1_5

MDQ1_50

MDQ1_51

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_55

MDQ1_56

MDQ1_57

MDQ1_58

MDQ1_59

MDQ1_6

MDQ1_61

MDQ1_62

MDQ1_63

MDQ1_7

MDQ1_8

MDQ1_9

MDQM1_0

MDQM1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQS1_0_N

MDQS1_0_P

MDQS1_1_N

MDQS1_1_P

MDQS1_2_P

MDQS1_3_N

MDQS1_3_P

MDQS1_4_N

MDQS1_4_P

MDQS1_5_N

MDQS1_5_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_7_P

MODT1A_1

MRAS1*

MWE1*

MDQ1_60

MDQS1_2_N

MCLK1A_2_P MCLK1A_2_N

MCLK1A_1_P MCLK1A_1_N

MCLK1A_0_P MCLK1A_0_N

MCS1A_1*

MODT1A_0

MCKE1A_1

MEMORY

CONTROL

1A

MEMORY PARTITION 1

(3 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

15 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BA16

AW16

BB13 AY15

AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

AT5 BA2

AY7 BA11 BB34 BB38 AY43 AR42

AW42 AW41 AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9 BB10 BB12 AW12

BB8

BB9 AY12 BA12 BC32 AW32

AU40

BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40

AU41

BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40

AR41 AP42

BB14 BB16

BA42 BB42

BB22 BA22

BA19 AY19

AY31 BB30

BA15

BB29 BB18 BB17

BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25

BA29 BA14 AW28 BC28 BA17

BB25 BA18

U1400

AR17

AV17

AP15 AV15

AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

AN5

AU5 AR10 AN13 AN27 AW29 AV35 AR34

AT37 AU37 AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5 AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9 AP11

AW6

AY5

AU9

AV9

AR38

AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25

AV38

AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31

AW38

AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31

AR35 AP35

AT15 AR18

AW33 AV33

BA24 AY24

BB20 BC20

AU23 AT23

AP17

AP23 AP19 AW17

AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19

AR23 AU15 AN23 AW21 AN19

AT19 AR19

U1400

MEM_A_DQ<9> MEM_A_DQ<8>

MEM_A_ODT<1>

MEM_B_DQ<43>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_DQ<1>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<2>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<3>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<4>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<5>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<6>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_ODT<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQ<60>

MEM_B_DQS_N<2>

TP_MEM_B_CLK2P TP_MEM_B_CLK2N

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_A_DQ<55>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CS_L<0>

MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<57>

MEM_A_DQ<41> MEM_A_DQ<40>

MEM_A_DQ<28>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<38>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CAS_L

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_CS_L<1>

MEM_A_DQ<0>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<3>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<39>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<56>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<6>

MEM_A_DQ<60>

MEM_A_DQ<7>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_ODT<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50>

MEM_A_A<3>

MEM_A_DQ<19>

MEM_B_DQ<0>

MEM_B_ODT<0>

MEM_B_CKE<0>

MCP Memory Interface

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP7A

OMIT

BGA

OMIT

BGA

MCP7A

101 33

101 32

101 33

101 32

101 33

101 31

101 33

101 31

101 33

8

8 8

8

MRESET0*

MCLK0B_0_P

MCLK0B_1_P MCLK1B_1_P

MCLK1B_2_P

GND

MCKE1B_0 MCKE1B_1

MCLK0B_2_N

MCLK0B_2_P

MCLK1B_0_N

MCLK1B_0_P

MCLK1B_1_N

MCS0B_0* MCS1B_0*

MCS1B_1*

MODT0B_1 MODT1B_1

V1P1_PLL_DP

V1P8_MEM_VDDP

GND

MEM_COMP_1P8V

MEM_COMP_GND

V1P1_PLL_XREF_XS

V1P1_PLL_CORE

V1P1_PLL_V

MCKE0B_1

MODT0B_0

MCLK0B_0_N

MCLK0B_1_N

MODT1B_0

MCLK1B_2_N

MCS0B_1*

MCKE0B_0

MEMORY CONTROL 1B

MEMORY CONTROL 0B

(4 OF 11)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER SIZE

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A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA 39 mA

TP or NC for DDR2.

87 mA (A01)

16 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

AR16

AV16

AP24

AP20

AN22

BC29

AN16

AM29

AM27

AM25

AP16

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AT17

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AN24

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AN20

AM17

T27

T28 U28 U27

AY32

BC13

AY16

AN15

AN17

AM41 AN41

BA13

BC16

AR15

AU17

BA41 BB41

AY23 BA23

BA20 AY20

AU33 AU34

BB24 BC24

BA21 BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

2

1

R1611

2

1

R1610

MCP_MEM_RESET_L

MEM_B_CKE<3>

MEM_A_CLK_P<3>

MEM_A_CLK_P<4> MEM_B_CLK_P<4>

TP_MEM_B_CLK5P

MEM_B_CKE<2>

TP_MEM_A_CLK5P

MEM_B_CLK_N<4>

MEM_B_CS_L<3>

MEM_A_ODT<3> MEM_B_ODT<3>

MEM_A_CKE<3>

MEM_A_CLK_N<3>

MEM_B_ODT<2>

TP_MEM_B_CLK5N

MEM_A_CS_L<3>

MEM_A_CKE<2>

=PP1V8R1V5_S0_MCP_MEM

MEM_A_CS_L<2>

MEM_A_ODT<2>

MEM_A_CLK_N<4>

TP_MEM_A_CLK5N

PP1V05_S0_MCP_PLL_CORE

=PP1V8R1V5_S0_MCP_MEM

MEM_B_CLK_P<3> MEM_B_CLK_N<3>

MEM_B_CS_L<2>

MCP_MEM_COMP_VDD

MCP_MEM_COMP_GND

SYNC_DATE=N/A

SYNC_MASTER=MASTER

MCP MEMORY CNTRL & MISC

33

40.2

MF-LF

1%

1/16W

402

1%

40.2

1/16W

402

MF-LF

MCP7A

BGA

OMIT

101 32

101 33

101 33 101 33

8

101 32

8

101 33

101 32

101 31 101 32

101 31

101 33

101 32

8

101 31

30 25 16 6

101 31

101 33

8

25

30 25 16 6

101 33

101 32

101

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

PEB_CLKREQ*/GPIO_49 PEB_PRSNT*

PE0_RX13_N PE0_RX14_P

PEE_CLKREQ*/GPIO_16

V1P1_PEX_AVDD0

V1P1_PEX_AVDD1

V1P1_PEX_DVDD0

V1P1_PEX_DVDD1

V1P1_PLL_PEX

PE_WAKE*

PE0_PRSNT_16*

PE0_REFCLK_N

PE0_REFCLK_P

PE0_RX0_N

PE0_RX0_P

PE0_RX1_N

PE0_RX1_P

PE0_RX10_N

PE0_RX10_P

PE0_RX11_N

PE0_RX11_P

PE0_RX12_N

PE0_RX12_P

PE0_RX13_P

PE0_RX14_N

PE0_RX15_N

PE0_RX15_P

PE0_RX2_N

PE0_RX2_P

PE0_RX3_N

PE0_RX3_P

PE0_RX4_P

PE0_RX6_N

PE0_RX6_P

PE0_RX7_N

PE0_RX7_P

PE0_RX8_N

PE0_RX8_P

PE0_RX9_N

PE0_RX9_P

PE0_TX0_N

PE0_TX0_P

PE0_TX1_N

PE0_TX1_P

PE0_TX10_P

PE0_TX11_N

PE0_TX11_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_N

PE0_TX13_P

PE0_TX14_N

PE0_TX14_P

PE0_TX15_N

PE0_TX15_P

PE0_TX2_N

PE0_TX2_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_N

PE0_TX4_P

PE0_TX5_N

PE0_TX5_P

PE0_TX6_N

PE0_TX6_P

PE0_TX7_N

PE0_TX7_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_N

PE0_TX9_P

PE1_REFCLK_N

PE1_REFCLK_P

PE1_RX0_N

PE1_RX0_P

PE1_RX1_N

PE1_RX1_P

PE1_RX2_N

PE1_RX2_P

PE1_RX3_N

PE1_RX3_P

PE1_TX0_N

PE1_TX0_P

PE1_TX1_N

PE1_TX1_P

PE1_TX2_N

PE1_TX2_P

PE1_TX3_N

PE1_TX3_P

PE3_REFCLK_N

PE3_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_N

PE6_REFCLK_P

PEC_CLKREQ*/GPIO_50 PEC_PRSNT*

PED_CLKREQ*/GPIO_51 PED_PRSNT*

PEE_PRSNT*/GPIO_46

PEF_CLKREQ*/GPIO_17 PEF_PRSNT*/GPIO_47

PEX_CLK_COMP

PEX_RST0*

PE0_RX5_P PE0_RX5_N

PE0_RX4_N

PE0_TX10_N

PE2_REFCLK_N

PE2_REFCLK_P

PEG_PRSNT*/GPIO_48

PEG_CLKREQ*/GPIO_18

PCI EXPRESS

(5 OF 11)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

84 mA (A01)

Int PU

Minimum 1.025V for Gen2 support

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Int PU

57 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

Int PU

17 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

R12

P12

M12

AB12

AA12

W12

V12

AD12

U12

T12

N12

AC12

Y12

K11

A11

M19

M17

M18

M16

L18

L16

B10

M15

C10

E8

D9

D5

F17

N14 M14

L14 K14

J13 H13

G13 F13

J11 J10

B6 C6

A7 B7

B8 A8

D8 C8

H7 G7

F9 E9

H9 G9

K9 J9

G11 F11

H3 H2

G3 H4

F3 F4

E2 F2

D2 E1

C1 D1

B3 B2

A4 A3

C4 B4

M2 M1

M4 M3

L4 L3

K2 K3

J2 J3

H1 J1

C5 D4

L11 L10

J5 J4

J7 J6

G5 H5

C3 D3

E4 E3

E5 F5

E6 F6

D7 C7

N5 N4

N7 N6

N9 P9

N11 N10

L7 L6

L9 L8

F7 E7

E11 D11

C9

U1400

2

1

R1710

PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N

=PEG_R2D_C_N<10>

=PEG_D2R_N<4>

=PEG_D2R_N<5>

=PEG_D2R_P<5>

PCIE_RESET_L

TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N

PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N

TP_PCIE_PE4_D2RP

PCIE_EXCARD_D2R_P

PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N

=PEG_R2D_C_P<9> =PEG_R2D_C_N<9>

=PEG_R2D_C_P<8> =PEG_R2D_C_N<8>

=PEG_R2D_C_P<7> =PEG_R2D_C_N<7>

=PEG_R2D_C_P<6> =PEG_R2D_C_N<6>

=PEG_R2D_C_P<5> =PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<15> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<14> =PEG_R2D_C_N<14>

=PEG_R2D_C_P<13> =PEG_R2D_C_N<13>

=PEG_R2D_C_P<12> =PEG_R2D_C_N<12>

=PEG_R2D_C_P<11> =PEG_R2D_C_N<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_P<0> =PEG_R2D_C_N<0>

=PEG_D2R_P<9> =PEG_D2R_N<9>

=PEG_D2R_P<8> =PEG_D2R_N<8>

=PEG_D2R_P<7> =PEG_D2R_N<7>

=PEG_D2R_P<6> =PEG_D2R_N<6>

=PEG_D2R_P<4>

=PEG_D2R_P<3> =PEG_D2R_N<3>

=PEG_D2R_P<2> =PEG_D2R_N<2>

=PEG_D2R_N<14>

=PEG_D2R_P<13>

=PEG_D2R_P<12> =PEG_D2R_N<12>

=PEG_D2R_P<11> =PEG_D2R_N<11>

=PEG_D2R_P<10> =PEG_D2R_N<10>

=PEG_D2R_P<1> =PEG_D2R_N<1>

=PEG_D2R_N<0>

PEG_CLK100M_P PEG_CLK100M_N

=PP1V05_S0_MCP_PEX_AVDD1

=PEG_D2R_P<14>

=PEG_D2R_N<13>

PCIE_MINI_PRSNT_L

=PP1V05_S0_MCP_PEX_AVDD0

=PEG_D2R_P<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2> =PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

MCP_PEX_CLK_COMP

PP1V05_S0_MCP_PLL_PEX

=PP1V05_S0_MCP_PEX_DVDD1

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_D2RN

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_MINI_D2R_N

GMUX_JTAG_TDO

TP_PE4_CLKREQ_L

PCIE_FW_PRSNT_L

=PEG_D2R_P<15> =PEG_D2R_N<15>

PEG_PRSNT_L

MINI_CLKREQ_L

FW_CLKREQ_L

EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L

PCIE_WAKE_L

PCIE_MINI_D2R_P

=PP1V05_S0_MCP_PEX_DVDD0

TP_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L

CARDREADER_RESET

MCP PCIe Interfaces

SYNC_MASTER=MASTER

SYNC_DATE=N/A

47

MCP7A

BGA

OMIT

67

8

9

2.37K

402

MF-LF

1% 1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

9

8

102 34

8

102 41

102 34

8

9

34

8

102 41

34

42

9

102 34

9

8

28

28 25

102

25

28

8

28 25

8

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

IN OUT

IN IN IN

BI

XTALIN_TV

RGB_DAC_RSET

MII_COMP_GND

MII_COMP_VDD

V1P1_DUAL_MACPLL

MII_COL/GPIO_20/MSMB_DATA

BUF_25MHZ

DDC_CLK0

DDC_CLK2/GPIO_23

DDC_CLK3

DDC_DATA0

DDC_DATA2/GPIO_24

DDC_DATA3

DP_AUX_CH0_N

DP_AUX_CH0_P

GPIO_6/FERR*/IGPU_GPIO6 GPIO_7/NFERR*/IGPU_GPIO7

HDMI_RSET

HDMI_TXC_N/ML0_LANE3_N

HDMI_TXC_P/ML0_LANE3_P

HDMI_TXD0_N/ML0_LANE2_N

HDMI_TXD0_P/ML0_LANE2_P

HDMI_TXD1_N/ML0_LANE1_N

HDMI_TXD1_P/ML0_LANE1_P

HDMI_TXD2_N/ML0_LANE0_N

HDMI_TXD2_P/ML0_LANE0_P

HDMI_VPROBE

HPLUG_DET2/GPIO_22 HPLUG_DET3

IFPA_TXC_N

IFPA_TXC_P

IFPA_TXD0_N

IFPA_TXD0_P

IFPA_TXD1_N

IFPA_TXD2_N

IFPA_TXD2_P

IFPA_TXD3_N

IFPA_TXD3_P

IFPAB_RSET

IFPAB_VPROBE

IFPB_TXC_N

IFPB_TXC_P

IFPB_TXD4_N

IFPB_TXD4_P

IFPB_TXD5_N

IFPB_TXD5_P

IFPB_TXD6_N

IFPB_TXD6_P

IFPB_TXD7_N

IFPB_TXD7_P

LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58

MII_RESET*

MII_RXER/GPIO_36

MII_VREF

V3P3_DUAL_RMGT0 V3P3_DUAL_RMGT1

V1P0_DUAL_RMGT_0 V1P0_DUAL_RMGT_1

V3P3_PLL_HDMI

V3P3_PLL_IFPAB

V3P3_RGBDAC_VDD

V3P3_TVDAC_VDD

V1P1_HDMI_VDD

V1P8_IFPA_VDD V1P8_IFPB_VDD

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB_DAC_RED

RGB_DAC_VREF

RGB_DAC_VSYNC

MII_MDC

MII_MDIO

MII_PWRDWN/GPIO_37

MII_RXCLK MII_RXDV

MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3

MII_TXD0 MII_TXD1 MII_TXD2

TV_DAC_BLUE

TV_DAC_GREEN

TV_DAC_HSYNC/GPIO_44

TV_DAC_RED

TV_DAC_RSET TV_DAC_VREF

TV_DAC_VSYNC/GPIO_45

XTALOUT_TV

MII_TXEN

MII_TXCLK

MII_TXD3

RGB_DAC_GREEN

IFPA_TXD1_P

MII_CRS/GPIO_21/MSMB_CLK

MII_INTR/GPIO_35

DACS

LAN

FLAT PANEL

(6 OF 11)

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: HDMI port requires level-shifting. IFP interface can

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

TP_DP_IG_AUX_CHP/N

TMDS_IG_HPD

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0> =MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

be used to provide HDMI or dual-channel TMDS without

DP_IG_DDC_DATA

DP_IG_DDC_CLK

Interface Mode

level-shifters.

DP_IG_AUX_CH_P/N

NOTE: 20K pull-down required on DP_HPD_DET.

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

TMDS_IG_DDC_DATA

MCP Signal

=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD

8 mA 8 mA

16 mA (A01)

95 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_ML_P/N<0>

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

18 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

D38

C38

K32

J32

M28 M29

K24

J24

M26

M27

T25

T23

V23

U23

C37

A35

E36

A36

D36

B36 C36

A41

B38

C39

B39

A40

A39 B40

E28

C26

D25

C25

C24

B24

D24F23

C22

A24

E24

B23

C23

A23

J23

G23

C21

D21

J22

B22

C27 B27

B26

F40

E37

G39

N30 M30

L30 K30

L29 K29

J29 H29

L31 K31

G31

E32

B34 C34

D33 C33

D32 C32

B32 A32

B35 C35

F31

C31

J30

J33 H33

F33 G33

G35 F35

D35 E35

J31

B15

E16

D43 C43

E31

B30

A31

D31

C30

B31

E23

U1400

2

1

R1820

2

1

R1860

2

1

R1861

2

1

R1850

2

1

R1811

2

1

R1810

MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN

TP_MCP_RGB_DAC_RSET

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

PP1V05_ENET_MCP_PLL_MAC

=MCP_MII_COL

MCP_CLK25M_BUF0_R

MCP_DDC_CLK0

LVDS_IG_DDC_CLK

=MCP_HDMI_DDC_CLK

MCP_DDC_DATA0

LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_DATA

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

LPCPLUS_GPIO DP_IG_CA_DET

MCP_HDMI_RSET

=MCP_HDMI_TXC_N

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXD_P<2>

MCP_HDMI_VPROBE

=DVI_HPD_GMUX_INT =MCP_HDMI_HPD

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<3>

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

ENET_RESET_L

=MCP_MII_RXER

MCP_MII_VREF

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_RMGT

PP3V3_S0_MCP_VPLL

PP3V3_S0_MCP_DAC

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_RED

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_VSYNC

ENET_MDC ENET_MDIO

TP_ENET_PWRDWN_L

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2>

CRT_IG_B_COMP_PB

CRT_IG_G_Y_Y

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_TV_DAC_RSET

CRT_IG_VSYNC

MCP_CLK27M_XTALOUT

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

TP_MCP_RGB_GREEN

LVDS_IG_A_DATA_P<1>

=MCP_MII_CRS

TP_ENET_INTR_L

=PP3V3_S5_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<3>

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP Ethernet & Graphics

104 37

102 26

104 37

102 26

9

89

107 89

104 37

107 89

104 37

107 89

104 37

MCP7A

BGA

OMIT

5%

47K

402

MF-LF

1/16W

51

402

MF-LF

5%

1/16W

100K

402

5%

100K

1/16W MF-LF

10K

402

1/16W

5%

MF-LF

9

8

93

MF-LF

49.9

402

1%

1/16W

1% 1/16W MF-LF

402

49.9

8

107 26

9

107 93

9

89

8

37

104 37

104 38

104 37

25

104

25

38 25 18

38 25

26

8

20 6

38 25 18

21 19 6

OUT

BI BI BI BI

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

(7 OF 11)

PCI

GND

LPC

PCI_AD28

PCI_REQ4*/GPIO_52/RS232_SIN*

PCI_REQ2*/GPIO_40/RS232_DSR*

PCI_AD31

LPC_PWRDWN*/GPIO_54/EXT_NMI*

LPC_RESET0*

LPC_AD1 LPC_AD2 LPC_AD3

LPC_CLK0

LPC_FRAME*

PCI_TRDY*

PCI_STOP*

PCI_SERR*

PCI_RESET1*

PCI_RESET0*

PCI_REQ3*/GPIO_38/RS232_CTS*

PCI_REQ1*/FANRPM2

PCI_REQ0*

PCI_PME*/GPIO_30

PCI_PERR*/GPIO_43/RS232_DCD*

PCI_PAR

PCI_IRDY*

PCI_INTZ*

PCI_INTY*

PCI_INTX*

PCI_INTW*

PCI_GNT4*/GPIO_53/RS232_SOUT*

PCI_GNT3*/GPIO_39/RS232_RTS*

PCI_GNT2*/GPIO_41/RS232_DTR*

PCI_GNT1*/FANCTL2

PCI_GNT0*

PCI_FRAME*

PCI_DEVSEL*

PCI_CLKRUN*/GPIO_42

PCI_CLKIN

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CBE3*

PCI_CBE2*

PCI_CBE1*

PCI_CBE0*

PCI_AD30

PCI_AD29

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

PCI_AD22

PCI_AD21

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD0

LPC_SERIRQ

LPC_DRQ0*

LPC_AD0

GND GND

LPC_DRQ1*/GPIO_19

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

19 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2 AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

21

R1953

21

R1952

21

R1951

21

R1950

21

R1960

2

1

R1961

21

R1992

21

R1994

21

R1990

21

R1991

21

R1989

2

1

R1910

TP_PCI_AD<26>

PCI_CLK33M_MCP

TP_PCI_GNT0_L

TP_PCI_AD<28>

MCP_RS232_SIN_L

CRTMUX_SEL_TV_L

TP_PCI_AD<31>

LPC_PWRDWN_L

LPC_RESET_L

LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

TP_PCI_TRDY_L

TP_PCI_STOP_L

TP_PCI_SERR_L

TP_PCI_RESET1_L

MEM_VTT_EN_R

AUD_IPHS_SWITCH_EN

PCI_REQ1_L

PCI_REQ0_L

PM_LATRIGGER_L

TP_PCI_PERR_L

TP_PCI_PAR

TP_PCI_IRDY_L

TP_PCI_INTZ_L

TP_PCI_INTY_L

TP_PCI_INTX_L

TP_PCI_INTW_L

MCP_RS232_SOUT_L

GMUX_JTAG_TDI

GMUX_JTAG_TMS

TP_PCI_GNT1_L

TP_PCI_FRAME_L

TP_PCI_DEVSEL_L

PM_CLKRUN_L

PCI_CLK33M_MCP_R

TP_PCI_CLK1

TP_PCI_CLK0

TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<0>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<27>

TP_PCI_AD<25>

TP_PCI_AD<24>

TP_PCI_AD<23>

TP_PCI_AD<22>

TP_PCI_AD<21>

TP_PCI_AD<20>

TP_PCI_AD<19>

TP_PCI_AD<18>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<15>

TP_PCI_AD<14>

TP_PCI_AD<13>

TP_PCI_AD<12>

TP_PCI_AD<11>

TP_PCI_AD<10>

TP_PCI_AD<9>

TP_PCI_AD<8>

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

MCP_DEBUG<4>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

LPC_SERIRQ

TP_LPC_DRQ0_L

LPC_AD_R<0>

FW_PME_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

LPC_AD<0>

LPC_FRAME_L

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

MCP_RS232_SOUT_L

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L

MCP PCI & LPC

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP7A

BGA

OMIT

8

68

13

19

42

9

402

MF-LF1/16W

5%

22

5%

1/16W MF-LF

402

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

1/16W MF-LF

402

22

5%

MF-LF 402

1/16W

5%

10K

19

8.2K

5%

1/16W MF-LF

402 402

MF-LF1/16W

8.2K

5%

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

PLACEMENT_NOTE=Place close to pin R8

MF-LF 402

1/16W

5%

22

51 49

103 9 51 49

51 49

103 51 49

103 9

103 51 49

8

103

8

103

8

103 19

8

103

8

103

21 18 6

19

103 19

19

BI BI

IN IN IN

OUT OUT

IN

OUT OUT

IN IN

USB9_P USB9_N

USB8_P USB8_N

USB7_P USB7_N

USB6_P USB6_N

USB5_P USB5_N

USB4_P USB4_N

USB3_P USB3_N

USB2_P USB2_N

USB11_P USB11_N

USB10_P USB10_N

USB1_P USB1_N

USB0_P

USB_RBIAS_GND

USB_OC3*/GPIO_28/MGPIO

USB_OC2*/GPIO_27/MGPIO

USB_OC1*/GPIO_26

USB_OC0*/GPIO_25

SATA_TERMP

SATA_C1_RX_P

SATA_C1_RX_N

SATA_C0_TX_P SATA_C0_TX_N

SATA_C0_RX_P

SATA_C0_RX_N

SATA_B1_TX_P SATA_B1_TX_N

SATA_B1_RX_P

SATA_B1_RX_N

SATA_B0_TX_P SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_RX_N

SATA_A1_TX_P SATA_A1_TX_N

SATA_A1_RX_P

SATA_A1_RX_N

SATA_A0_TX_N

SATA_A0_RX_N

V3P3_PLL_USB

V1P1_SATA_DVDD1

V1P1_SATA_DVDD0

V1P1_SATA_AVDD1

V1P1_SATA_AVDD0

GND

SATA_A0_TX_P

SATA_C1_TX_N

SATA_C1_TX_P

SATA_LED*

V1P1_PLL_SATA

USB0_N

SATA_A0_RX_P

USB

SATA

(8 OF 11)

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

19 mA (A01)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

External D

External A

Camera

Bluetooth

IR

External B

External C

Minimum 1.025V for Gen2 support

43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

Minimum 1.025V for Gen2 support

ExpressCard

20 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

L28

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AE16

A27

H21

J21

K21

L21

H25 J25

K25 L25

D27 E27

F27 G27

J26 J27

K27 L27

F29 G29

A28 B28

C28 D28

K23 L23

F25 G25

C29 D29

AE3

E12

AP3 AP2

AN2

AN3

AN1 AM1

AM3

AM2

AM4 AL3

AK3

AL4

AK2 AJ3

AJ1

AJ2

AJ11 AJ10

AK9

AJ9

AJ7 AJ6

AJ4

AJ5

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

U1400

2

1

R2050

2

1

R2051

2

1

R2052

2

1

R2053

2

1

R2060

2

1

R2010

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L

EXCARD_OC_L

PP3V3_S0_MCP_PLL_USB

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

SATA_HDD_D2R_P

USB_EXTA_N

PP1V05_S0_MCP_PLL_SATA

TP_MCP_SATALED_L

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

SATA_HDD_R2D_C_P

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RN TP_SATA_F_D2RP

MCP_SATA_TERMP

MCP_USB_RBIAS_GND

USB_EXTA_P

USB_MINI_N

USB_MINI_P

TP_USB_10P

USB_EXTD_N

USB_EXTD_P

USB_CAMERA_N

USB_CAMERA_P

USB_IR_N

USB_IR_P

USB_TPAD_P

USB_BT_N

USB_EXTB_P

USB_EXCARD_N

USB_EXCARD_P

USB_EXTC_N

USB_EXTC_P

SATA_ODD_D2R_N

TP_SATA_D_D2RN

USB_EXTB_N

USB_SDCARD_N

USB_SDCARD_P

TP_USB_10N

MCP SATA & USB

SYNC_MASTER=MASTER

SYNC_DATE=N/A

103 47

MCP7A

BGA

OMIT

102 45

402

1/16W MF-LF

5%

8.2K

5%

8.2K

1/16W

402

MF-LF

402

1/16W MF-LF

5%

8.2K

5%

8.2K

MF-LF

1/16W

402

806

MF-LF

1%

1/16W

402

MF-LF

1% 1/16W

402

2.49K

46 9

46

103 46

8

103 46

103 47

8

103 47

103 46

8

103 46

25

18 6

25

45

28

28 6

28

102

103

8

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

IN

OUT

IN

OUT

IN

EXT_SMI*/GPIO_32

V1P1_PLL_NV_H

A20GATE

BUF_SIO_CLK

CPU_DPRSLPVR

CPU_VLD

CPUVDD_EN

FANCTL0/GPIO_61

FANCTL1/GPIO_62

FANRPM0/GPIO_60

FANRPM1/GPIO_63

GPIO_1/PWRDN_OK/SPI_CS1 GPIO_12/SUS_STAT*/ACCLMTR_EXT_TRIG

HDA_BITCLK

HDA_RESET*

HDA_SDATA_IN0

GPIO_2/HDA_SDATA_IN1/PS2_KB_CLK

GPIO_3/HDA_SDATA_IN2/PS2_KB_DATA

HDA_SDATA_OUT

HDA_SYNC

INTRUDER*

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST*

KBRDRSTIN*

LID* LLB*

GPIO_13/MCP_VID0 GPIO_14/MCP_VID1 GPIO_15/MCP_VID2

V3P3_DUAL_HDA_0 V3P3_DUAL_HDA_1

V1P1_PLL_SP_SPREF

PKG_TEST

PS_PWRGD

PWRBTN*

PWRGD_SB

RSTBTN*

RTC_RST*

SIO_PME*

SLP_RMGT*

SLP_S3*

SMB_ALERT*/GPIO_64

SMB_CLK0

SMB_CLK1/MSMB_CLK

SMB_DATA0

SMB_DATA1/MSMB_DATA

GPIO_11/SPI_CLK

GPIO_10/SPI_CS0

GPIO_8/SPI_DI GPIO_9/SPI_DO

SPKR

SUS_CLK/GPIO_34

TEST_MODE_EN

THERM_DIODE_N

THERM_DIODE_P

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

SLP_S5*

GPIO_5/HDA_DOCK_RST*/PS2_MS_DATA

GPIO_4/HDA_DOCK_EN*/PS2_MS_CLK

HDA_PULLDN_COMP

HDA

MISC

(9 OF 11)

OUT

IN

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLK

SPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

SAFE mode: For ROMSIP recovery

USER mode: Normal

Connects to SMC for

(MXM_OK for MXM systems)

automatic recovery.

Int PU

NC

21 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

B19

B16

A19

A16

K16

J16

AE17

AE18

B11 C11

K22

B18

C13

F21

K19 G21

L19

M23

H17

G17 J17

C19

C20

D16

D20

C16

E20

L22

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15G15

K15

A15

E15

B14

C15

L17

K17

J15

J14

L24

M21

M20

L20

L26

D13

C14

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

2

1

R2140

2

1

R2143

1

2

R2154

2

1

R2151

2

1

R2155

2

1

R2156

2

1

R2157

2

1

R2141

2

1

R2142

2

1

R2147

2

1

C2172

2

1

C2170

2

1

C2173

2

1

C2171

2

1

R2150

2

1

R2110

21

R2172

2

1

R2181

2

1

R2180

2

1

R2160

2

1

R2163

21

R2173

21

R2171

21

R2170

2

1

R2190

2

1

R2120

2

1

R2121

MCP_PS_PWRGD

SMC_RUNTIME_SCI_L

PP1V05_S0_MCP_PLL_NV

TP_SB_A20GATE

MCP_CPUVDD_EN

ODD_PWR_EN_L

MEM_EVENT_L

SMC_IG_THROTTLE_L

=SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDIN0

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

HDA_SDOUT_R

HDA_SYNC_R

SM_INTRUDER_L

JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS

TP_MCP_KBDRSTIN_L

TP_MCP_LID_L PM_BATLOW_L

MCP_VID<0> MCP_VID<1>

=PP3V3R1V5_S0_MCP_HDA

PM_RSMRST_L

PM_SYSRST_DEBOUNCE_L

SMC_WAKE_SCI_L

PM_SLP_RMGT_L

PM_SLP_S3_L

SMBUS_MCP_0_CLK

SMBUS_MCP_1_CLK

SPI_CLK_R

SPI_CS0_R_L

SPI_MISO SPI_MOSI_R

MCP_SPKR

PM_CLK32K_SUSCLK_R

MCP_TEST_MODE_EN

MCP_THMDIODE_N

MCP_THMDIODE_P

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

PM_SLP_S4_L

AUD_I2C_INT_L

MCP_GPIO_4

MCP_HDA_PULLDN_COMP

AP_PWR_EN

AUD_I2C_INT_L

MCP_GPIO_4

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V3_G3_RTC

=PP3V3R1V5_S0_MCP_HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

ARB_DETECT

HDA_SYNC

MEM_EVENT_L SMC_IG_THROTTLE_L

=PP3V3_S0_MCP

TP_MCP_BUF_SIO_CLK

=PP3V3_S3_MCP_GPIO

MCP_CPU_VLD

PM_PWRBTN_L

MCP_VID<2>

MCP_VID<1>

MCP_VID<0>

=PP3V3_S0_MCP_GPIO

JTAG_MCP_TRST_L JTAG_MCP_TCK

ARB_DETECT

AP_PWR_EN

SMBUS_MCP_1_DATA

SMBUS_MCP_0_DATA

MCP_VID<2>

RTC_RST_L

MCP HDA & MISC

SYNC_MASTER=MASTER

SYNC_DATE=N/A

103 51

103 61 51

28

49

70

103 28

MCP7A

BGA

OMIT

50 21

50

10K

5%

MF-LF

1/16W

402

MF-LF 402

1/16W

5%

10K

1/16W MF-LF

5%

100K

402

MF-LF

5% 1/16W

100K

402

1/16W

22K

5%

MF-LF

22K

5%

MF-LF

1/16W

402

22K

5%

MF-LF

1/16W

402

1/16W MF-LF

5%

10K 10K

5% 1/16W

402

MF-LF

402

1/16W MF-LF

5%

100K

55 49 32 31 21

50 49

9 9

68 21

8

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

10PF

50V

5%

402

CERM

13

402

1/16W MF-LF

5%

10K

49.9

MF-LF

1/16W

1%

402

51

402

5%

22

1/16W MF-LF

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

MF-LF

8.2K

5% 1/16W

402

MF-LF 402

5%

10K

1/16W

5%

22

MF-LF

1/16W

402

MF-LF

5%

1/16W

402

22

MF-LF

402

5%

22

1/16W

49

103 9

402

MF-LF

1K

1% 1/16W

1%

49.9K

MF-LF

402

1/16W

MF-LF

1/16W

1%

402

49.9K

103 62

49

70

108 55

21

74 21

108 55

74 21

52

106 52 13

52

106 52 13

102 70

102 9

103 61 51

25

8

103 21

8

9

103 21

8

25 21 6

21

103

21

68 21

21

28 22

25 21 6

103 21

21

55 49 32 31 21

50 21

25 22 6

8

6

74 21

19 18 6

21

V1P0_CORE_VDD

V3P3

V3P3_DUAL_USB

V3P3_DUAL

V3P3_VBAT

V1P0_VDD_AUXC

V1P2_CPU_VTT

V1P2_CPUCLK_VTT

(10 OF 11)(11 OF 11)

GNDGND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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8 7 5 4 2 1

23065 mA (A01, 1.2V)

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

1182 mA (A01)

450 mA (A01)

22 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

AG32

AL31

AD32

AK32

AK31

W32

V32

AJ32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

AH32

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

AE32

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

AF32

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

P31

R32

V21

U21

T21

AC21

AA16

AC20

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AC19

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AC18

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AC17

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AC16

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AA28

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

AA27

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AA26

AA25

U1400

=PP1V05_S5_MCP_VDD_AUXC

PP3V3_G3_RTC

=PP3V3_S5_MCP

=PP3V3_S0_MCP

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

MCP Power & Ground

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP7A

OMIT

BGA

OMIT

BGA

MCP7A

25 6

28 21

25 6

25 21 6

25 6 25 14 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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A

B

C

345678

D

B

8 7 5 4 2 1

23 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=MASTER

SYNC_DATE=N/A

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

24 OF 110

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BLANK PAGE

SYNC_DATE=12/08/2008

SYNC_MASTER=K51

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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8 7 5 4 2 1

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTIONPART#

TABLE_5_ITEM

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP SATA (DVDD) Power

NV: 1X 4.7UF 0402, 2X 1UF 0402, 2X 0.1UF 0402 (6.9UF)

84 mA (A01)

270 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

19 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

5 mA (A01)

87 mA (A01)

562 mA (A01)

84 mA (A01)

BALLS FOR AVDD0 SO 80% OF CAPACITANCE ON AVDD0

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

450 mA (A01)

57 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

83 mA (A01)

131 mA (A01)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

MCP 3.3V Ethernet Power

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

4771 mA (A01, DDR3)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 1.05V AUX Power

105 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

MCP PCIE (DVDD) Power

APPLE: 4X 4.7UF 0402, 4X 1UF 0402, 6X 0.1UF 0402 (23.4 UF)

MCP Core Power

DIFFERENT THAN ON T18

PEX_AVDD RAIL SPLIT BASED ON IG VS. EG. 12 OUT OF 15

PEX_DVDD RAIL SPLIT BASED ON IG VS. EG. 8 OUT OF 10

CAPACITANCE ON DVDD0

BALLS FOR DVDD0 SO 80% OF

Apple: 7x 2.2uF 0402 (15.4 uF)

43 mA (A01)

333 mA (A01)

MCP 1.05V RMGT Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

K50: 2X 2.2UF 0402, 2X 1UF 0402, (6.4 UF)

25 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C2597

2

1

C2528

2

1

C2529

2

1

C2596

2

1

C2587

2

1

C2585

2

1

C2583

2

1

C2581

2

1

C2518

2

1

C2521

2

1

R2591

2

1

C2591

2

1

R2590

21

L2595

2

1

C2595

2

1

C2590

2

1

C2589

2

1

C2560

2

1

C2525

2

1

C2526

21

L2580

2

1

C2501

2

1

C2500

21

L2555

21

L2586

21

L2588

21

L2584

21

L2582

21

L2575

21

L2570

2

1

C2580

2

1

C2564

2

1

C2562

2

1

C2540

2

1

C2541

2

1

C2542

2

1

C2543

2

1

C2544

2

1

C2545

2

1

C2546

2

1

C2547

2

1

C2548

2

1

C2549

2

1

C2550

2

1

C2551

2

1

C2552

2

1

C2553

2

1

C2575

2

1

C2576

2

1

C2573

2

1

C2574

2

1

C2570

2

1

C2520

2

1

C2571

2

1

C2572

2

1

C2515

2

1

C2516

2

1

C2517

2

1

C2530

2

1

C2531

2

1

C2532

2

1

C2533

2

1

C2534

2

1

C2535

2

1

C2536

2

1

C2512

2

1

C2513

2

1

C2508

2

1

C2509

2

1

C2510

2

1

C2511

2

1

C2504

2

1

C2505

2

1

C2506

2

1

C2507

2

1

C2502

2

1

C2555

2

1

C2586

2

1

C2584

2

1

C2588

2

1

C2582

2

1

C2503

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP

=PP1V05_S0_MCP_AVDD_UF

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

=PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP1V05_S0_MCP_PEX_AVDD0

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP

=PP3V3R1V5_S0_MCP_HDA

MCP_MII_VREF

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_PLL_MAC

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_FSB

=PP1V05_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

=PPVCORE_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_PEX_DVDD0

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

MCP Standard Decoupling

C2574,C2518

2

IGRES,0,5%,0402116S0004

4.7UF

X5R 402

20%

4V

4.7UF

20%

402

X5R

20%

402

X5R

4V

4.7uF

10V

20%

402

0.1uF

CERM

4.7UF

X5R

4V

20%

402

4.7UF

4V X5R

20%

402

4.7UF

X5R

4V

20%

402

4.7UF

20% 4V X5R 402

20% 4V

4.7UF

402

X5R

MXM

402-LF

6.3V CERM

20%

2.2UF

0.1uF

20% 10V

402

CERM

18

402

1.47K

1/16W

1%

MF-LF

402

10V

20%

CERM

0.1UF

402

MF-LF

1%

1/16W

1.47K

0402

30-OHM-1.7A

402

X5R

4V

4.7UF

20%

402

20%

2.2UF

X5R

4V

4.7UF

402

20% 4V X5R

CERM 402-LF

20%

2.2UF

6.3V

402

10V

0.1uF

20% CERM

402

10V

0.1uF

20% CERM

30-OHM-1.7A

0402

402

X5R

20%

4.7UF

4V

4.7UF

402

X5R

20%

4V

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

30-OHM-5A

0603

30-OHM-5A

0603

4.7UF

20% X5R

402

4V

6.3V

2.2UF

20%

402-LF

CERM

20%

2.2UF

6.3V 402-LF

4V

402

X5R

4.7UF

20%

402

10V

20% CERM

0.1UF

402

CERM

10V

0.1UF

20%

0.1UF

CERM 402

10V

20%

402

10V CERM

20%

0.1UF

402

CERM

10V

20%

0.1UF 0.1UF

CERM 402

20% 10V

402

10V CERM

20%

0.1UF

402

10V CERM

20%

0.1UF

402

10V CERM

20%

0.1UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

6.3V

2.2UF

402-LF

20%

2.2UF

6.3V CERM CERM

402-LF

20%

6.3V

2.2UF

402-LF

2.2UF

CERM

20%

6.3V

2.2UF

6.3V

20%

402-LF

CERM

MXM

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

20%

402-LF

CERM

6.3V

MXM

20%

2.2UF

6.3V CERM 402-LF

X5R

4.7UF

4V

20%

402

MXM

6.3V

2.2UF

20%

402-LF

CERM

MXM

6.3V

20%

402-LF

CERM

2.2UF

20%

CERM

6.3V

MXM

402-LF

2.2UF

10V X5R 402-1

1UF

10%

X5R

MXM

10V

10%

1UF

402-1

6.3V

2.2UF

20%

402-LF

CERM

2.2UF

CERM

6.3V

20%

402-LF

CERM 402-LF

20%

2.2UF

6.3V 402-LF

CERM

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

6.3V CERM 402-LF

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

1UF

402-1

10% X5R

10V 10V

X5R 402-1

1UF

10%

4.7UF

402

X5R

20%

4V

CERM

20%

6.3V

2.2UF

402-LF

402

X5R

20%

4.7UF

4V

402

X5R

4V

20%

4.7UF

402

X5R

4V

4.7UF

20%

402

X5R

20%

4.7UF

4V

14

6 22 21 6

6

28

16

6

20

21

28 17

38 25 18 22 6

21 6

38 25 18

38 18

17

20

22 6

22 14 6

38 18

28 28

22 6

30 16 6

28 6 28 17

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

190 mA (A01, 1.8V)

95 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Apple: ???

16 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R2680

21

R2690

21

R2650

2

1

C2616

2

1

C2641

21

L2640

2

1

C2640

2

1

C2615

2

1

C2630

2

1

R2630

2

1

C2620

2

1

C2610

2

1

R2620

MCP_HDMI_VPROBE

MCP_HDMI_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_HDMI_VDD

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_VPLL

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_DAC

MAKE_BASE=TRUE

POWER_MCP_DAC

=PP3V3_S0_MCP_VPLL_UF

MCP_IFPAB_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD

MXM

C2641

1

RES,0,5%,402116S0004

1

116S0004 RES,0,5%,402

MXM

C2610

116S0004

1

RES,0,5%,402 C2616

MXM

SYNC_DATE=N/A

SYNC_MASTER=MASTER

MCP Graphics Support

CERM

20%

6.3V 402-LF

2.2UF

IG

MF-LF

1% 1/16W

402

1K

IG

1/16W MF-LF

5%

0

402

MF-LF

IG

0

402

5%

1/16W

1/16W MF-LF

5%

402

0

0.1UF

CERM

IG

20%

402

10V

IG

CERM

20% 10V

402

0.1uF

IG

0402

30-OHM-1.7A

4.7UF

20%

6.3V

IG

X5R-CERM

402

X5R 402

IG

4.7UF

20%

4V

402

CERM

10V

20%

0.1UF

NO STUFF

1%

1K

402

1/16W MF-LF

0.1UF

402

CERM

10V

20%

NO STUFF

107 18

6

18

102 18

18

6

102 18

18

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

27 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=12/08/2008

SYNC_MASTER=K51

BLANK PAGE

IN

OUT

NCNC

IN

OUT

IN

OUT

NCNC

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

10K pull-up to 3.3V S0 inside MCP

RTC Power Sources

Reset Button

Coin-Cell Holder

IMAC

PEG POWER ALIAS/OPTION TO GND UNUSED POWER PIN

UNPOWER PEG INTERFACE WHEN IG IS USED

DVDD DOES NOT NEED FILTER

AVDD IS FILTERED ON P25

UNPOWER PEG INTERFACE WHEN IG IS USED

SATA ALIAS/GROUNDING UNUSED DVDD1 AND AVDD1

PLACE AT LEAST 1 CAP NEAR MCP PIN A20

511S0054

fault protection for RTC battery.

NOTE: R2800 and D2800 form the double-

RTC Crystal

MCP 25MHz Crystal

28 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

Y2815

41

Y2810

21

R2882

21

R2880

2

1

R2898

2

1

C2899

21

R2899

2

1

R2816

21

R2815

21

C2816

21

C2815

2

1

C2801

2

1

C2802

1

2

J2800

2

5

3

6

4

1

D2800

21

R2896

2

1

R2811

21

R2810

21

C2811

21

C2810

12

R2800

2

1

C2800

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PPVBATT_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PPVBATT_G3_RTC_R

VOLTAGE=3.3V

PM_SYSRST_DEBOUNCE_L

=PP1V05_S0_MCP_SATA_DVDD0

PP3V3_G3_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PM_SYSRST_L

=PP3V3_S5_RTC_D

XDP_DBRESET_L

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

PP1V05_S0_MCP_PEX_DVDD0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE VOLTAGE=1.05V

=PP1V05_S0_MCP_PEX_DVDD1

PP1V05_S0_MCP_PEX_AVDD0

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_DVDD

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALIN

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

SYNC_DATE=N/A

SYNC_MASTER=MASTER

SB Misc

6.3V

1UF

10%

CERM

402

25.0000M

SM-3-LF

CRITICAL

32.768K-12.5PF

SM-HF

CRITICAL

5% 1/16W MF-LF

402

0

MXM

0

5%

402

1/16W MF-LF

MXM

SILK_PART=RESET_BTN

603

1/10W

NO STUFF

MF-LF

5%

0

49

NO STUFF

X5R

10%

1UF

10V

402

33

MF-LF

1/16W

402

5%

103 21

NO STUFF

10M

1/16W

402

MF-LF

5%

402

0

MF-LF

5%

1/16W

20PF

5%

402

CERM

50V

20PF

402

CERM

50V

5%

0.1UF

20%

402

CERM

10V

402

10V

0.1UF

20% CERM

103 21

SM

CRITICAL

BB10201-C1403-7H

BAT54DW-X-G

SOT-363

XDP

5%

1/16W

0

402

MF-LF

10M

1/16W MF-LF

402

5%

MF-LF

402

0

5%

1/16W

5%

402

CERM

12pF

50V

12pF

402

5%

50V

CERM

1/16W MF-LF

1K

402

5%

21 13 11

20 6

22 21 6

25 17

17

25 17

20

25

17

25

25 6

20

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

OUT

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Place close to J3200.1

PRODUCTION

- =I2C_VREFDACS_SCL

Signal aliases required by this page:

- =PPVTT_S3_DDR_BUF

Required zero ohm resistors when no VREF margining circuit stuffed

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

DAC channel A B A B C

ADDR=0x30(WR)/0x31(RD)

MEM B VREF DQ

Min DAC code 0x00 0x00 0x00 0x00 0x00 Max DAC code 0x87 0x87 0x87 0x87 0x55 Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

CPU FSB VREF

MEM B VREF CA

Power aliases required by this page:

Page Notes

MEM A VREF DQ MEM A VREF CA

(per DAC LSB)

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

BOM options provided by this page: VREFMRGN

10mA max load

PLACE CLOSE TO U1000

Place close to J3200.126

Place close to J3100.1

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

Place close to J3100.126

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

PLACE CLOSE TO U1000

ADDR=0x98(WR)/0x99(RD)

29 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

B4

B1

A4

A1

A2

A3

U2904

21

R2913

21

R2914

21

R2903

21

R2905

21

R2909

21

R2911

B4

B1

A4

A1

A2

A3

U2902

B4

B1

C4

C1

C2

C3

U2902

B4

B1

A4

A1

A2

A3

U2903

B4

B1

C4

C1

C2

C3

U2904

21

R2912

21

R2916

21

R2910

21

R2906

21

R2904

B4

B1

C4

C1

C2

C3

U2903

21

R2915

2

1

C2905

2

1

C2900

2

1

C2901

5

4

2

1

8

7

6

3

10

9

U2900

21

R2908

2

1

C2904

21

R2907

21

R2901

21

R2902

2

1

C2902

2

1

C2903

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2901

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CPUFSB_EN0

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

TP_PCA9557_P7

TP_PCA9557_P6

=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN1

VREFMRGN_CPUFSB_EN0

PCA9557D_RESET_L

VREFMRGN_CPUFSB1

=PPVTT_S3_DDR_BUF

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm

=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA

CPU_GTLREF0

VREFMRGN_CPUFSB_EN1

VREFMRGN_DQ_SODIMMA_EN

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMM

=PP3V3_S3_VREFMRGN

VREFMRGN_CPUFSB0

CPU_GTLREF1

VREFMRGN_CPUFSB_BUF1

VREFMRGN_CPUFSB_BUF0

CRITICAL

R2903

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

PRODUCTION

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

1

CRITICAL

R2905 PRODUCTION

RES,MTL FILM,0,5%,0402,SM,LF

R2909

116S0004 CRITICAL1PRODUCTION

VREFMRGN

RES,MTL FILM,200,1%,0402,SM,LF

114S0149

1

CRITICAL

R2911

1

114S0149

RES,MTL FILM,200,1%,0402,SM,LF

VREFMRGN

R2909

CRITICAL

RES,MTL FILM,0,5%,0402,SM,LF

R2911

116S0004

1

CRITICAL

PRODUCTION

CRITICAL

1

114S0149 VREFMRGN

R2905

RES,MTL FILM,200,1%,0402,SM,LF

CRITICAL

R2903

1

114S0149

RES,MTL FILM,200,1%,0402,SM,LF

VREFMRGN

FSB/DDR3 Vref Margining

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

100 11 10

0.1UF

20%

402

10V CERM

VREFMRGN

100K

VREFMRGN

MF-LF

402

5%

1/16W

20% CERM

402

10V

VREFMRGN

0.1UF

6.3V

2.2UF

CERM

20%

VREFMRGN

402-LF

10V

VREFMRGN

20% CERM

402

0.1UF

52

MSOP

VREFMRGN

DAC5574

52

9

402

100K

MF-LF

5%

1/16W

VREFMRGN

402

VREFMRGN

20%

0.1UF

10V CERM

QFN

PCA9557

VREFMRGN

1/16W MF-LF

402

5%

100K

VREFMRGN

5%

VREFMRGN

MF-LF

402

100K

1/16W

MF-LF

1/16W

100K

402

5%

VREFMRGN

MAX4253

VREFMRGN

UCSP

VREFMRGN

1/16W

100K

5%

402

MF-LF

FSB_VREFMRGN

1% 1/16W MF-LF

402

100

100 11 10

OMIT

402

MF-LF

1/16W

200

1%

OMIT

200

402

1/16W

1%

MF-LF

OMIT

402

1/16W

200

1%

MF-LF

200

OMIT

402

MF-LF

1/16W

1%

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

VREFMRGN

UCSP

MAX4253

VREFMRGN

0.1UF

20% 10V

402

CERM

MAX4253

VREFMRGN

UCSP

402

1/16W

VREFMRGN

1%

MF-LF

100

FSB_VREFMRGN

1/16W

1% MF-LF

402

100

VREFMRGN

100

1% 1/16W MF-LF

402

VREFMRGN

1/16W

100

1%

402

MF-LF

VREFMRGN

1% 1/16W

100

MF-LF

402

UCSP

MAX4253

VREFMRGN

29

32

29

6

31

29

31

29

6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

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A

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

EXTRA DECOUPLING CAPS FOR MCP MEM RAIL

CAPS TO COUPLE PP5V_S3 UNDER DIMM CONNECTORS

DIMM B (CLOSER TO MCP)

CAPS TO COUPLE MCP 1V5_S0_MEM

DIMM A (FURTHER FROM MCP)

4771 mA (A01, DDR3)

DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR

DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

30 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

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C3046

=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

=PP1V8R1V5_S0_MCP_MEM

=PP5V_S3_DDRREG

SYNC_DATE=N/A

SYNC_MASTER=MASTER

MEMORY CAPS

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

10V CERM

0.1UF

20%20%

0.1UF

CERM

10V 402

0.1UF

10V CERM 402

20%20%

0.1UF

CERM

10V 402

CERM

20% 10V

402

0.1UF

402

20%

0.1UF

CERM

10V

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20% 10V CERM 402

20%

0.1UF

402

10V CERM

0.1UF

20% 10V CERM

0.1UF

20%

402402

CERM

0.1UF

20% 10V

402

10V CERM

20%

0.1UF

402

10V CERM

20%

0.1UF0.1UF

402

20% 10V CERMCERM

20%

0.1UF

10V 402

0.1UF

402

10V

20% CERM

402

20% 10V CERM

0.1UF 0.1UF

402

10V CERM

20%

402

10V CERM

20%

0.1UF

402

CERM

10%

1UF

6.3V

402

CERM

6.3V

1UF

10%

402

10% CERM

6.3V

1UF

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402 402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V 6.3V

1UF

10% CERM

402

CERM

6.3V

1UF

10%

402

10% CERM

6.3V

1UF

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402 402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

1UF

10% CERM

402

CERM

1UF

6.3V

10%

402

CERM

10%

1UF

6.3V 6.3V 402

CERM

10%

1UF

402

CERM

10%

1UF

6.3V 6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

10% CERM

6.3V

1UF

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402 402

CERM

10%

1UF

6.3V

20%

6.3V X5R 603

10UF

603

10UF

6.3V X5R

20%

402

10% CERM

1UF

6.3V

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

603

20%

6.3V X5R

10UF

603

10UF

6.3V

X5R

20%

402

10% CERM

1UF

6.3V

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

30 25

16 6

30 25 16 6

108 31 6

108 32 6

30 25 16 6

75 30 6

Apple K22 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual