Apple K22 Schematics

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

K22

1 OF 110

0000774858

A

051-7845

A.0.0

1 OF 110

PRODUCTION RELEASED

2009-08-21

LAST_MODIFIED=Wed Aug 26 13:27:43 2009

K51

MCP CURRENT AND VOLTAGE SENSE

45

54

12/08/2008

MASTER

CPU/MXM CURRENT AND VOLTAGE SENSE

44

53

N/A

MASTER

SMBUS CONNECTIONS

43

52

N/A

MASTER

LPC+SPI Debug Connector

42

51

N/A

MASTER

SMC Support

41

50

N/A

MASTER

SMC40

49

N/A

MASTER

Internal USB Connections

39

47

MASTER

EXTERNAL USB CONNECTORS

38

46

N/A

MASTER

SATA Connectors

37

45

N/A

MASTER

FIREWIRE CONNECTOR

36

43

N/A

MASTER

FW: 1394B MISC

35

42

N/A

MASTER

FireWire LLC/PHY (XIO2213B)

34

41

N/A

MASTER

ETHERNET CONNECTOR

33

39

N/A

MASTER

Ethernet Support

32

38

N/A

K51

Ethernet PHY (RTL8211CL)

31

37

12/08/2008

MASTER

PCI-E Wireless Connector

30

34

N/A

K51

DDR3 SUPPORT AND BITSWAPS

29

33

10/13/2008

MASTER

DDR3 SO-DIMM CONNECTOR B

28

32

N/A

MASTER

DDR3 SO-DIMMs 0 & 2

27

31

N/A

MASTER

MEMORY CAPS

26

30

N/A

MASTER

FSB/DDR3 Vref Margining

25

29

MASTER

SB Misc24

28

N/A

MASTER

MCP Graphics Support

23

26

N/A

K51

22

25

12/08/2008

MASTER

21

22

N/A

MASTER

MCP HDA & MISC

20

21

N/A

MASTER

MCP SATA & USB

19

20

N/A

MASTER

MCP PCI & LPC

18

19

N/A

MASTER

MCP Ethernet & Graphics

17

18

N/A

MASTER

16

17

N/A

MASTER

MCP MEMORY CNTRL & MISC

15

16

N/A

MASTER

MCP Memory Interface

14

15

N/A

MASTER

13

14

N/A

MASTER

eXtended Debug Port (XDP)

12

13

N/A

MASTER

CPU POWER, GND, DECAPS

11

12

N/A

MASTER

CPU TEST & MISC.

10

11

N/A

MASTER

CPU FSB9

N/A

MASTER

SIGNAL ALIASES

8

9

N/A

MASTER

UNUSED SIGNAL ALIAS

7

8

N/A

MASTER

HOLES & STANDOFFS

6

7

N/A

MASTER

Power Conn / Alias

5

6

N/A

MASTER

BOM Configuration

4

N/A

MASTER

Power Block Diagram

3

N/A

MASTER

System Block Diagram

2

N/A

K22/K23 ICT/FCT

87

110

MASTER

N/A

K22/K23 RULE DEFINITIONS

86

109

MASTER

N/A

K22/K23 SPECIFIC CONSTRAINTS

85

108

MASTER

N/A

GRAPHICS CONSTRAINTS

84

107

MASTER

N/A

SMC Constraints

83

106

MASTER

N/A

FireWire Constraints

82

105

MASTER

N/A

Ethernet Constraints

81

104

MASTER

N/A

MCP Constraints 2

80

103

MASTER

N/A

MCP Constraints 1

79

102

MASTER

N/A

Memory Constraints

78

101

MASTER

N/A

CPU/FSB Constraints

77

100

MASTER

N/A

DisplayPort Connector

76

94

MASTER

N/A

DISPLAYPORT SUPPORT

75

93

MASTER

N/A

DP MUX SUPPORT

74

91

MASTER

N/A

INTERNAL DISPLAY

73

90

MASTER

LCD MUX & CHOKES

72

89

MASTER

MXM ALIASES

71

87

MASTER

N/A

MXM PCIE CAPS

70

86

MASTER

N/A

MXM I/O69

85

K51

10/31/2008

MXM PCIe, DP & Power

84

K51

10/31/2008

1V8 POWER SUPPLY

67

80

MASTER

N/A

1V1 S5 POWER SUPPLY

66

79

K51

10/31/2008

S3 & S0 FETs

65

78

MASTER

N/A

FSB VTT/3.3V S5 SUPPLIES

64

76

MASTER

N/A

1.5V DDR SUPPLY

63

75

MASTER

N/A

MCP CORE REGULATOR

62

74

MASTER

N/A

5V_S3 REGULATOR

61

73

MASTER

N/A

VREG: PPVCORE_S0_CPU

60

72

MASTER

N/A

VREG: PPVCORE_S0_CPU

59

71

MASTER

N/A

PGOOD and Power Sequencing

58

70

MASTER

N/A

57

69

K51

12/08/2008

AUDIO: Mikey

56

68

SKIPAUDIO

06/01/2009

AUDIO: Detects/Grounding

55

67

SKIPAUDIO

06/01/2009

Audio: MLB to I/O Conn.

54

66

SKIPAUDIO

06/01/2009

AUDIO: SPEAKER AMP

53

65

SKIPAUDIO

06/01/2009

AUDIO: SPEAKER AMP

52

64

SKIPAUDIO

06/01/2009

AUDIO: FILTER/BUFFER

51

63

SKIPAUDIO

06/01/2009

AUDIO: CODEC/REGULATOR

50

62

SKIPAUDIO

06/01/2009

SPI ROM49

61

K51

12/08/2008

CPU FAN48

57

MASTER

N/A

HD AND OD FAN

47

56

MASTER

N/A

(.csa)

Date

Contents

SyncPage

Thermal Sensors

46

55

MASTER

N/A

ABBREV=DRAWING

TITLE=K22

MASTER

Table of Contents

1

N/A

Page

(.csa)

Date

Sync

Contents

SCH,K22,MLB

POWER SEQUENCING BLOCK DIAGRAM

MCP Standard Decoupling

MCP Power & Ground

MCP PCIe Interfaces

MCP CPU Interface

10

68

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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Apple Inc.

PAGE

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B

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8 7 5 4 2 1

INTERNAL

J9410

PORT CONN

FW643

MXM CONNECTOR

64-Bit

XDP CONN

PG 10

MEMORY

PG 15

LPC+SPI CONN

PG 56,57

PG 51

PG 53

PG 55

U4900

J3100, J3200

PG 31,32

PG 61

PG 49

J4780

PG 47

PG 20

2 7

11

J4720

PG 21

SATA-A0

LVDS OUT

U3900

PG 39

PG 37

PG 17

Mini PCI-E

Conn

AirPort

J3400

U4100

PG 43

PG 41

GPIOs

PG 34

PG 18

DP OUT

DVI OUT

RGB OUT

TMDS OUT

J8400

HDMI OUT

65 841 3

CLK

PG 13

SYNTH

J5100

Ser Prt

ADC

SMC

BSBB,0

SPI

U1000

U1300

PG 13

PG 20

SATA-A1

E-NET

MAGNETICS

Conn

FireWire

J4300

CPU DIE

CPU HEATSINK

MXM - GPU DIE

TEMP SENSORS

J5600, J5601, J5700

PG 19

Boot ROM

PG 21

Port80,serial

PG 21

Bluetooth

PWR

U1400

CTRL

PG 84

PG 45

J4510

HD

SATA

1.05V/3GHZ.

Conn

SATA

ODD

Conn

PG 45

J4520

PG 94

DISPLAY

J9002

PG 90

DISP

INTEL CPU

LCD TEMP

LPC

DDR3-1067MHZ

MAIN

3.X GHZ

LGA775 - WOLFDALE

PG 10-12

4 SO-DIMMs

MCP7A

PG 47

IR

J4700

PG 47

CAMERA

PG 47

J47xx

WHICH PORT?

EXTERNAL

J4610,4620,4630,4640

Connectors

USB

PG 47

SD CARD

SPI

U6100

Misc

PG 24

USB

(UP TO 12 DEVICES)

9

10

Fan

MCP DIE

AMBIENT INTAKE

HARD DRIVE

OPTICAL DRIVE

MCP HEATSINK

FAN CONN AND CONTROL

POWER SENSE

FSB INTERFACE

GPU HEATSINK

TEMP, CURRENT SENSE

POWER SUPPLY

1333 MHZ

FSB

DIMM

NVIDIA

SATA

UP TO 20 LANES3

X16 PCI-E

T3900

PG 39

Conns

Audio

U3700

Audio

U6201

Mikey

U6806

Codec

PG 19

PCI

0

RGMII

PCI-E

SMB

MIKEY

HDA

(UP TO FOUR PORTS)

DIMM’s

PG 18

E-NET

Speaker

Amps

U6400, U6500

GB

RTL8211CLGR

Line In

Int/Ext Mics

Headphones

J6600,J6601,J6602,J6603

051-7845

A.0.0

2 OF 110

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

System Block Diagram

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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8 7 5 4 2 1

PAGE 6

MXM 20" INVERTER

CPU_CORE

PAGE 76

PPVTT_S0_FSB

PM_SLP_S3

CPU_AVDD

DDR3 MAIN MEMORY

PPVCORE_CPU

PAGE 71-72

PAGE 74

MCP, CPU FSB (VTT)

MCP_PLL

CPU_VCCP

PP1V8_S0_REG

MCP

PP1V1_S5

SMBUS

PAGE 78

PPDDR_S3_REG

PP5V_S3_REG

CAMERA

MEM_VTT

AP PCIE

AUDIO

20" PANEL

24" PANEL

FANS

MCP_ENET

FW

AP

ETHERNET

PAGE 78

USB

PP12V_S0

MCP

PAGE 76

BT

HDD

20" PANEL

PP12V_S5

CLOCK

PAGE 38

PP1V2_S3

PAGE 75

PP1V5_S0

PP0V75_S0

ENET

PAGE 75

PM_SLP_S3_OD

12V_S5

MAIN MEMORY

MCP79 MEM

TEMP SENSOR

CONTROL

PP12V_S0_INV

PP12V_S0_HDD

HARD DRIVE

PAGE 79

PP5V_S0

IR

BOOT ROM

AC/DC POWER SUPPLY

PAGE 76

MCP_CORE

DCM/FCM

PAGE 80

OPTICAL

MCP_VDD_AUXC

MXM

PAGE 74

P5VS0_EN

FIREWIRE PORTS

AUDIO

PPMCPCORE_S0_REG

MXM

FW

PP3V3_S3

P3V3S3_EN

P3V3S0_EN

PP3V3_S0

PAGE 78

AUDIO

PAGE 42

PP1V_S5

SMC

PP3V3_S5_REG

3 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

Power Block Diagram

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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345678

D

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8 7 5 4 2 1

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

CPUS

BOM Variants

(338S0563 - BLNK)

K22 PARTS

COMMON

MCP -J SKU HAS INTEGRATED GPU

GROUND

7

6

5

4

BOTTOM

SIGNAL

POWER

GROUND

2 3

TOP

SIGNAL

POWER

BOARD STACK-UP

SIGNAL

MCP -D SKU DOES NOT

ALTERNATES

BOM GROUPS

4 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

K22,3P06GHZ_CPU,BASIC,MXM,K22_MXM

K22,3P16GHZ_CPU,BASIC,IG

630-9878

PCBA,3.06 GHZ CPU,IG,K22(Investigation)

PCBA,MLB,3.06GHZ,MXM,K22

PCBA,MLB,3.16GHZ,IG,K22

PCBA,MLB,3.16GHZ,MXM,K22

PCBA,MLB,3.33GHZ,IG,K22

PCBA,MLB,3.33GHZ,MXM,K22

PCBA,MLB,DEV,K22

CRITICAL 3P33GHZ_CPU

2P93GHZ_CPU

3P06GHZ_CPU

CPU

WLF,SLB9L,PRQ,3.33G,65W,1333,E0,6M,LGA

WLF,SLB9K,PRQ,3.16G,65W,1333,E0,6M,LGA

WLF,SLB9J,PRQ,3.0G,65W,1333,E0,6M,LGA

WLF,SLB9J,PRQ,2.83G,65W,1333,E0,6M,LGA

WLF,QXXX,QS,2.80G,65W,1066,R0,3M,LGA

CRITICAL

3P0GHZ_CPU

630-9768

639-0036

COMMON,ALTERNATE,MCP7A,XDP,BETTER,MCP_ISL9563A,MLB_PNL_PWR,PRODUCTION

WLF,SLGU9,PRQ,2.80G,65W,1066,R0,2M,LGA

337S3807

337S3766

337S3745

337S3742

337S3726

337S3715

337S3727

WLF,SLB9L,PRQ,2.93G,65W,1333,E0,6M,LGA

WLF,SLB9L,PRQ,3.06G,65W,1333,E0,6M,LGA

CPU

K22,2P80GHZ_CPU,BASIC,MXM,K22_MXM

PCBA,2.8 GHZ CPU,MXM,K22

2P80GHZ_2M_CPU337S3804 CRITICAL

1

CPU

1

CRITICAL

CPU

CRITICAL

3P16GHZ_CPU

CRITICAL

K22,2P80GHZ_CPU,BASIC,IG

SYNC_MASTER=MASTER

SYNC_DATE=N/A

BOM Configuration

PCBA,MLB,GOOD,K22

825-7122 MLB LABEL,48.0X4.8

X14

CRITICAL

1

CRITICAL12P80GHZ_CPU

2P83GHZ_CPU

1

CPU

DEV_GROUP

XDP_CONN,LPCPLUS,VREFMRGN,MCP_PWR_SENSE,MCP_CPU_TDIODE,PECI_SMB,MOJOMUX

1

U4900 CRITICAL341T0168 IC,SMC,K22

K22

IC,XIO2211ZAY,1394B,167BGA

338S0765 U4100

1

CRITICAL

IC,MCP,MCP7A-DA,B03,35X35MM,BGA1437,DT

1

MXM

338S0732 U1400

127S0060 C6211127S0111 AUDIO, NEED QUAL

CPU

1

PCBF,K22,MLB MLB1

1

820-2494

K22

U3700 CRITICAL

1

IC,RTL8251CA,GIGE TRANSCEIVER, 48P TQFP

338S0694

341T0170

1

CRITICALU6100IC,EFI BOOTROM,K22/K23

IC,GMCP,MCP7A-JA,B03,35X35MM,BGA1437,DT

1

338S0731 IGU1400

SCH,K22,MLB SCH1051-7845

1

K22

BOOT_MODE_USER,MEMRESET_HW,MEMRESET_MCP

MCP7A

BASIC

CRITICAL

1

CPU

CRITICAL

1

K22,2P80GHZ_2M_CPU,BASIC,IG

PCBA,2.8 GHZ-2M CPU,IG,K22

639-0392

K22,2P80GHZ_2M_CPU,BASIC,MXM,K22_MXMPCBA,2.8 GHZ-2M CPU,MXM,K22

639-0393

639-0184

PCBA,2.93 GHZ CPU,IG,K22 K22,2P93GHZ_CPU,BASIC,IG

K22,2P93GHZ_CPU,BASIC,MXM,K22_MXM

PCBA,2.93 GHZ CPU,MXM,K22

639-0186

PCBA,3.0 GHZ CPU,IG,K22

639-0037

K22,3P0GHZ_CPU,BASIC,IG

PCBA,MLB,CTO,K22

K22,3P0GHZ_CPU,BASIC,MXM,K22_MXM

639-0183 K22,3P06GHZ_CPU,BASIC,IG

639-0511

639-0510

639-0324

K22,3P16GHZ_CPU,BASIC,MXM,K22_MXM

K22,3P33GHZ_CPU,BASIC,IG639-0206

639-0207

K22,3P33GHZ_CPU,BASIC,MXM,K22_MXM

DEVELOPMENT,DEV_GROUP

607-4426

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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345678

D

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8 7 5 4 2 1

5 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

BLANK PAGE

IN

G

S

D

G

S

D

IN

G

S

D

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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8 7 5 4 2 1

ON IN RUN AND SLEEP

SILKSCREEN:4

518-0352

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

PLACE AT J600.

"S5" RAILS

GND RAILS

SILKSCREEN:2

SILKSCREEN:1

ONLY ON IN RUN

EMC: C600,C626,C627,C628,C629,C630,C631

SILKSCREEN:3

"S0" RAILS "S3" RAILS

6 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

9

8

7

6

5

4

3

2

14

13

12

11

10

1

J600

2

1

C631

2

1

C630

2

1

C623

2

1

C600

2

1

3

Q610

2

1

C626

2

1

C624

2

1

C627

2

1

3

Q602

2

1

LED602

2

1

R602

2

1

3

Q604

2

1

LED604

2

1

R604

2

1

LED603

2

1

R603

2

1

LED605

2

1

R600

2

1

LED601

2

1

R601

=PP1V05_S0_MCP_PEX_DVDD

PP3V3_S3

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAX_NECK_LENGTH=3 MM

VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_S3_MINI

=PP1V05_S0_MCP_HDMI_VDD_R

=PP5V_S3_1V8

=PP5V_S3_MCPREG =PP5V_S3_CAMERA =PP5V_S3_IR

=PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET =PPDDR_S3_S0FET

PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM

=PP3V3_S0_VRD

=PPSPD_S0_MEM_B

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

PPVTT_S0_FSB_REG

MIN_LINE_WIDTH=0.6 mm

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE VOLTAGE=1.2V

=PPVTT_S0_FSB_CPU

PPMCPCORE_S0_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

=PP1V05_S0_MCP_PLL_UF

PM_ACDC_PS_ON

=PP5V_S3_PWRCTL

=PP5V_S3_VTTCLAMP

=PP1V5_S3_MEM_A

PP3V3_S5_REG

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL =PP3V3_S5_S3FET =PP3V3_S5_S0FET =PP3V3_S5_ENET_FET

LCD_PWM

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_MCPREG

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

PPVTT_S0_DDR_LDO

MAKE_BASE=TRUE VOLTAGE=0.75V MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_MCP =PP3V3_S5_MCP_GPIO

=PP0V75_S0_MEM_VTT_A

=SMB_ACDC_SDA

PP12V_S5

=PP5V_S3_S0FET

PP1V1_S5_REG

MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.1V

=PP1V1_S5_ENET_FET

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S5_ROM =PP3V3_S5_RTC_D

=PP3V3_S5_SMC

=PP3V3_S5_LPCPLUS

=PP3V3_S5_MEMRESET

ITS_ALIVE

PP3V3_S5_REG

=PP5V_S5_AVREF

=PP3V3_S5_SMCUSBMUX

MXM_GOOD

PP3V3_S3

CORE_VOLTAGES_ON

ITS_PLUGGED_IN

LCD_SHOULD_ON

PP3V3_S3

GPU_PRESENT_R

=PP12V_S5_PWRCTL

PPDDR_S3_REG

NET_SPACING_TYPE=PPDDR_MEM MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.5V MIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_P1V1S5

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.1V MIN_LINE_WIDTH=0.6MM

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR

=PP3V3_S5_SMBUS_SMC_BSA

PM_SLPS3_BUF2_L

=PPDDR_S3_PGCMP

CORE_VOLTAGES_ON_R

LCD_BKL_ON

=PPVTT_S0_CPU

=PP3V3_S3_VREFMRGN

PP5V_S5_LDO

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V

MAX_NECK_LENGTH=3 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

=PP12V_S5_FW =PPVIN_S5_DDRREG =PPVIN_S5_P3V3S5 =PPVIN_S5_P5VS3 =PP12V_S5_REG

PP12V_S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE VOLTAGE=12V

=PP5V_S0_SATA

=SMB_ACDC_SCL

GPU_PRESENT_DRAIN

PP5V_LCD_CONN

ALL_SYS_PWRGD_R

PP3V3_S0

=PP5V_S0_VRD

=PP5V_S0_MXM

=PP5V_S0_LCD

=PP5V_S0_ISENSE

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_AUDIO

=PPSPD_S0_MEM_A

=PP3V3_S0_XDP

=PP3V3_S0_VIDEO

=PP3V3_S0_TSENS

=PP3V3_S0_SMC_LS

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_MGMT

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SATALED

=PP3V3_S0_PWRCTL

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCPTHMSNS

=PP3V3_S0_FAN

=PP3V3_S0_DPCONN

=PP3V3_S0_AUDIO =PP3V3R1V5_S0_MCP_HDA

=PPV_S0_MXM_PWR =PPVIN_S0_PPVTT_FSB

=PPVIN_S0_MCPCORE

=PP12V_S0_VRD

=PP1V05_S0_MCP_AVDD_UF

=PPVTT_S0_XDP =PP1V05_S0_MCP_FSB

=PP3V3R1V8_S0_MCP_IFP_VDD_R =PP1V8_S0_PGCMP

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MXM

=PP3V3_S0_ODD

=PP5V_S0_SATA

=PP5V_S0_PWRCTL

=PP12V_S0_FAN =PP12V_S0_AUDIO_SPKRAMP

PP12V_S0

MAX_NECK_LENGTH=3 MM

VOLTAGE=12V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

PP1V8_S0_REG

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.1 MM

VOLTAGE=1.8V

=PP1V05_S0_MCP_SATA_DVDD0

PP12V_S0

=PPVTT_S3_DDR_BUF

=PP3V3_S3_BT

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_SDCARD

=PP3V3_S3_SMC

=PP5V_S3_USB

=PP5V_S3_DDRREG

PP5V_S3_REG

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

VOLTAGE=5V MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PPVCORE_S0_MCP

=PPVCORE_S0_CPU

=PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP

=PP1V5_S0_AUD_DIG

=PP1V5_S0_CPU_VCCPLL

=PP1V5_FWRS0_FWXIO

PP1V5_S0

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE VOLTAGE=1.5V

NET_SPACING_TYPE=PWR

=PP3V3_FW_FWPHY

PP5V_S0

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

VOLTAGE=5.0V MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

=PP5V_S0_LPCPLUS

=PP3V3_FWRS0_FWXIO

PP3V3_S0

MAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR

VOLTAGE=3.3V MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.30MM

MAX_NECK_LENGTH=4.1 MM

MAKE_BASE=TRUE

GND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

Power Conn / Alias

SYNC_MASTER=MASTER

SYNC_DATE=N/A

70

2N7002

SOT23-HF1

2.0X1.25MM-SM

GREEN-3.6MCD

1/16W

1K

5% MF-LF

402

9

2N7002

SOT23-HF1

MXM

2.0X1.25MM-SM

GREEN-3.6MCD

MF-LF

5% 1/16W

1K

402

MXM

2.0X1.25MM-SM

GREEN-3.6MCD

5% MF-LF

1/16W

1.5K

402

GREEN-3.6MCD

DEVELOPMENT

2.0X1.25MM-SM

DEVELOPMENT

1K

5% 1/16W MF-LF 402

MF-LF 402

5% 1/16W

1K

GREEN-3.6MCD

2.0X1.25MM-SM

CRITICAL

76833-0100

M-RT-TH

0.001UF

402

10% X7R

50V 50V

X7R

0.001UF

10%

402

10UF

20% 10V X5R 805

0.001UF

50V X7R 402

10%

2N7002

SOT23-HF1

402

10% X7R

50V

0.001UF

10% 16V

1210

10UF

X5R-CERM

70 50 49 9

0.001UF

402

50V X7R

10%

28 25

110 78 6 34

26

80

74

47

108 32 30

33

78

75

71

32

21 19 18

26

25 22 21

30 25 16

76

12 11

74 54

25

70

78

108 31 30

76 6

70

78

38

90

52

74

75

25 22

20 18

31

52

6

78

79

38

25 22

61 51

28

50 49

51

33

76 6

50

46

110 78 6

78 70 38

75

79

72 71

52

70 90 89

71 55 50 10

29

76

43

75

76

73

76

6

45 6

52

90

78 6

71

84

90

53

93

68 62

31

13

90 89

55

55 50

54 53 50

52

45

70

25

55

57 56

94

68 67 66 65 64 62

25 21

53

76

74

71 70

25

13

25 22 14

26

70

52

85 84

45

45 6

80

57 56

67

70 6

80

28 20

70 6

29

47

21

47

46

75 30

110 73

25 22

12

32

78

62

12

41

54

43 42 41

110 78 51

41

78 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BACKER PLATE NUTS

REAR COVER STANDOFFS

4 MM PLATED HOLES FOR CPU HEATSINK

DIMM CONNECTOR NUTS

998-0850

870-1125 FOR MCP HEATSINK

7 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

1

SDF0717

1

SDF0716

1

SDF0715

1

SDF0714

1

SDF0750

1

SDF0751

1

SDF0752

1

SDF0753

1

SDF0703

1

SDF0702

1

SDF0701

1

SDF0700

1

SDF0713

1

SC0701

1

SC0700

1

ZH0703

1

ZH0702

1

ZH0701

1

ZH0700

HOLES & STANDOFFS

SYNC_MASTER=MASTER

SYNC_DATE=N/A

CRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICALCRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICALCRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

STDOFF-6.8OD15.0H-1.56-TH

CRITICAL

CLIP-SM1

CRITICAL

EMI-SPRING

CLIP-SM1

EMI-SPRING

CRITICAL

OMIT

4P75R4

OMIT

4P75R44P75R4

OMITOMIT

4P75R4

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

NC ON UNUSED ALIASES

MCP HAS INTERNAL 15K PULL-DOWNS

UNUSED MEMORY SIGNALS

UNUSED GMUX JTAG FROM MCP

8 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_PE4_CLKREQ_L NC_PE4_CLKREQ_L

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_ENET_PWRDWN_L

USB_MINI_N

NC_USB_MINI_N

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_USB_10P

TP_USB_10N

NC_USB_MINI_P

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_MINI_P

NO_TEST=TRUE

NC_USB_EXCARD_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_P

USB_EXCARD_N

MAKE_BASE=TRUE

NC_ENET_INTR_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_KBDRSTIN_L

TP_PCIE_PE4_D2RN

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_P

NO_TEST=TRUE

NC_MCP_PCI_GNT0_L

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCI_AD<8>

NO_TEST=TRUE

NC_PCI_AD<8>

MAKE_BASE=TRUE

TP_PCI_AD<12..10>

NO_TEST=TRUE

NC_PCI_AD<12..10>

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

ODD_PWR_EN_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ODD_PWR_EN_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_10P

NO_TEST=TRUE

NC_USB_10N

MAKE_BASE=TRUE

TP_SB_A20GATE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SB_A20GATE

TP_PE4_PRSNT_L

NO_TEST=TRUE

NC_PE4_PRSNT_L

MAKE_BASE=TRUE

PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

NC_PCIE_EXCARD_PRSNT_L

NO_TEST=TRUE

TP_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P

TP_PCI_PAR

TP_PCI_INTZ_L

TP_PCI_INTW_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_FRAME_L

TP_PCI_CLK1

TP_PCI_CLK0

TP_PCI_C_BE_L<3>

PCIE_EXCARD_D2R_N

TP_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_PE4_R2D_CP

PCIE_EXCARD_D2R_P

NO_TEST=TRUE

NC_USB_TPAD_P

MAKE_BASE=TRUE

TP_PCIE_PE4_D2RP

NC_PCIE_PE4_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_PE4_D2RP

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

NC_MEM_A_CLK2P

NO_TEST=TRUE

GMUX_JTAG_TMS

NC_MCP_BUF_SIO_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_IRDY_L

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

CRT_IG_G_Y_Y

TP_PCI_AD<31..15>

NC_PCI_FRAME_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ENET_PWDWN_L

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_CLK0

NC_PCI_CLK1

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_TPAD_N

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_AD<31..15>

NC_PCI_PERR_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_GPIO_18

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_INTW_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_INTY_L

NO_TEST=TRUE

NC_PCI_INTZ_L

MAKE_BASE=TRUE

MCP_TV_DAC_RSET

MCP_CLK27M_XTALOUT

TP_PCI_IRDY_L

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_PCI_C_BE_L<1..0>

TP_ENET_INTR_L

TP_MCP_KBDRSTIN_L

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MCP_BUF_SIO_CLK

MAKE_BASE=TRUE

NC_LPC_DRQ0_L

NO_TEST=TRUE

TP_LPC_DRQ0_L

TP_PCI_PERR_L

MAKE_BASE=TRUE

NC_MEM_A_CLK2N

NO_TEST=TRUE

NC_MEM_A_CLK5P

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_MEM_A_CLK5P

NC_MEM_A_CLK5N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TCK_L

NO_TEST=TRUE

MAKE_BASE=TRUE

GMUX_JTAG_TCK_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TDO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TDI

GMUX_JTAG_TDI

MAKE_BASE=TRUE

NC_GMUX_JTAG_TMS

NO_TEST=TRUE

NC_PCI_C_BE_L<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

CRT_IG_VSYNC

NO_TEST=TRUE

NC_MEM_B_CLK2P

MAKE_BASE=TRUE

TP_MEM_B_CLK2P

NO_TEST=TRUE

NC_MEM_B_CLK2N

MAKE_BASE=TRUE

TP_MEM_B_CLK2N

NO_TEST=TRUE

NC_MEM_B_CLK5P

MAKE_BASE=TRUE

TP_PCI_INTY_L

NC_MLB_RAM_SIZE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MEM_B_CLK5P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_VSYNC

TP_PCI_DEVSEL_L

TP_PCI_SERR_L NC_PCI_SERR_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_DEVSEL_L

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MEM_A_CLK5N

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

PCIE_EXCARD_R2D_C_N

TP_PCI_RESET1_L

TP_PCI_STOP_L

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TP_PCI_TRDY_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4N

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

NC_PCI_TRDY_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_GNT1_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_STOP_L

TP_MEM_B_CLK5N

NO_TEST=TRUE

NC_PCI_INTX_L

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MLB_RAM_SIZE

TP_MCP_GPIO_18

NC_MEM_B_CLK5N

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_PE4_R2D_CP

GMUX_JTAG_TDO

USB_TPAD_P

NC_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_N

NO_TEST=TRUE

NC_USB_TPAD_N

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCI_INTX_L

NO_TEST=TRUE

NC_PCI_PAR

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_RESET1_L

MAKE_BASE=TRUE

SYNC_MASTER=MASTER

SYNC_DATE=N/A

UNUSED SIGNAL ALIAS

17

18

20

17

19

17

21

17

19

17

19

18

19

20

18

19

18

19

18

21

19

16

17

19

18

15

19

16

19

16

17

19

15

16

21

17

20

19

OUT

IN

OUT

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USB PORT 2 AND 3 (C AND D) SHARE OVER-CURRENT WITH PORT 2 PREVIOUSLY, PORT 3 HAD ITS OWN BUT EFI MAPS THAT TO EXPRESSCARD SEE RDAR://6250424

K22/K23 Use one GPIO for both ports 2&3 OC

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

MCP_CPUVDD_EN WILL ASSERT AFTER MCP_PS_PWRGD IS UP

Audio Mux aliasing

K23 Uses this to control the DP audio mux. K22 does not need this signal

K23 uses a mux between the DP audio source and the audio in port

this alias connects spdif directly from the I/O port to the codec

SIGNAL ALIAS

(P50 HAS A 100K TO GROUND)

MCP79 PCIe PRSNT# Straps

DisplayPort / TMDS Support

PEG Slot Support

9 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R993

2

1

R912

21

R911

21

R910

21

R930

2

1

R955

21

R983

21

R981

21

R992

21

R990

21

R991

21

R971

2

1

C973

21

R925

21

R972

21

R926

21

R929

21

R900

PCIE_RESET_L

PCA9557D_RESET_L

LPC_RESET_L

PM_CLK32K_SUSCLK

PM_CLK32K_SUSCLK_R

LPC_CLK33M_SMC

PEG_RESET_L

MINI_RESET_L

MCP_MII_NU

MAKE_BASE=TRUE

LPC_CLK33M_SMC_R

=MCP_MII_CRS

LPC_CLK33M_LPCPLUS

SMC_LRESET_L

FW_RESET_L

=MCP_MII_COL

=MCP_MII_RXER

DEBUG_RESET_L

MEM_VTT_EN_R

DDRVTT_EN

CARDREADER_PLT_RST_L

MCP_CPUVDD_EN

MCP_CPU_VLD

AUD_SPDIF_IN_CODEC

TP_AUD_MUX_CNTRL

MAKE_BASE=TRUE

AUD_SPDIF_IN

AUD_MUX_CNTRL

PM_SLPS3_BUF1_L

MAKE_BASE=TRUE

PM_SLP_S3_L

MAKE_BASE=TRUE

PM_SLPS3_BUF2_L

PCIE_FW_PRSNT_L

PCIE_MINI_PRSNT_L

GPU_CLK100M_PCIE_P

MAKE_BASE=TRUE

GPU_CLK100M_PCIE_N

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

MXM_DETECT_L

MAKE_BASE=TRUE

DP_IG_ML_P<3>

MAKE_BASE=TRUE

DP_IG_ML_N<3> DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

MAKE_BASE=TRUE

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_DATA DP_IG_HPD

MAKE_BASE=TRUE

HPLUG_DET2

MAKE_BASE=TRUE

=DVI_HPD_GMUX_INT

PEG_CLK100M_P

PEG_CLK100M_N =PEG_R2D_C_P<0..15> =PEG_R2D_C_N<0..15> =PEG_D2R_P<0..15> =PEG_D2R_N<0..15>

PEG_PRSNT_L

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

TP_MLB_RAM_VENDOR

MXM_GOOD

MAKE_BASE=TRUE

USB_EXTD_OC_L

MAKE_BASE=TRUE

USB_EXTC_OC_L

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SIGNAL ALIASES

47

5%

402

MF-LF

0

1/16W

62

62 103 66

402

100K

5% 1/16W MF-LF

402

MF-LF

1/16W

5%

15

5%

1/16W

402

MF-LF

15

21

PLACEMENT_NOTE=Place close to U1400

22

1/16W

5%

MF-LF

402

21

1/16W

47K

402

MF-LF

5%

51

49

41

34

90 87

29

78 75

103 49

103 51

103 49

402

1/16W

5%

MF-LF

33

PLACEMENT_NOTE=Place close to U1400

MF-LF

1/16W

5%

33

402

PLACEMENT_NOTE=Place close to U1400

103 19

402

0

5% 1/16W MF-LF

402

0

5% MF-LF

1/16W

0

MF-LF

5%

402

1/16W

0

MF-LF

5%

402

0.47UF

6.3V CERM-X5R

10%

402

NO STUFF

402

33

PLACEMENT_NOTE=Place close to U1400

5% 1/16W MF-LF

402

MF-LF

33

1/16W

5%

402

5% 1/16W MF-LF

33

PLACEMENT_NOTE=Place close to U1400

1/16W

5%

MF-LF

22

402

PLACEMENT_NOTE=Place close to U1400

17

19

103 19

103 21

1/16W

5%

20K

MF-LF

402

17 85

17

18

91

93

107 91

102 87

102 87 17

17

102 86

17

17 102 86

102 86

18

94 73

102 21 70 50 49 6

18

21 6

46

46 20

BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

BI

IN

A_34* A_35*

REQ_4*

A_7*

DBSY*

INIT*

A_20*

A20M*

ADS*

ADSTB_0*

ADSTB_1*

A_3* A_4*

A_6*

A_8*

A_10*

A_14* A_15* A_16*

A_17* A_18* A_19*

A_21* A_22* A_23* A_24* A_25* A_26* A_27* A_28* A_29* A_30* A_31* A_32* A_33*

BCLK_0 BCLK_1

BNR*

BPRI*

BR_0*

DEFER*

DRDY*

FERR_PBE*

IERR*

IGNNE*

LINT0 LINT1

REQ_0* REQ_1*

REQ_3*

RS_0* RS_1* RS_2*

SMI*

STPCLK*

REQ_2*

A_13*

A_12*

A_11*

A_9*

A_5*

LOCK*

RESET*

TRDY*

HIT*

HITM*

CONTROL

ADDR GROUP0

(1 OF 7)

CLK

SB

ADDR GROUP1

IN

OUT

IN

IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI

D_11*

D_10*

D_9*

D_1* D_2*

D_8*

D_7*

D_6*

DBI_0*

DBI_1*

DBI_2*

DBI_3*

DSTBN_0*

DSTBN_1*

DSTBN_2*

DSTBN_3*

DSTBP_0

DSTBP_1

DSTBP_2

DSTBP_3

D_0*

D_3* D_4* D_5*

D_12* D_13* D_14* D_15*

D_16* D_17* D_18* D_19* D_20* D_21* D_22* D_23* D_24* D_25* D_26* D_27* D_28* D_29* D_30* D_31*

D_32* D_33* D_34* D_35* D_36* D_37* D_38* D_39* D_40* D_41* D_42* D_43* D_44* D_45* D_46* D_47*

D_48* D_49* D_50* D_51* D_52* D_53* D_54* D_55* D_56* D_57* D_58* D_59* D_60* D_61* D_62* D_63*

(2 OF 7)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE W/ A TESTPOINT W/ A GND NEARBY

CPU GTLREF

(63.5% OF 1.2V) = 0.762V

GTLREF VOLTAGE SHOULD BE 0.635 * VTT

10 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1044

2

1

R1043

2

1

R1001

2

1

C1042

21

R1045

2

1

C1043

2

1

R1041

2

1

C1040

2

1

R1040

2

1

C1041

21

R1042

C17

G19

E12

B9

A16

G20

G12

C8

C20

D19

G11

A8

A11

A10

A7

B22

A22

A19

B19

B7

B21

C21

B18

A17

B16

C18

B15

C14

C15

A14

B6

D17

D20

G22

D22

E22

G21

F21

E21

F20

E19

A5

E18

F18

F17

G17

G18

E16

E15

G16

G15

F15

C6

G14

F14

G13

E13

D13

F12

F11

D10

E10

D7

A4

E9

F9

F8

G9

D11

C12

B12

D8

C11

B10

C5

B4

J1000

E3

M3

P2

A3

F5

B3

G23

J6

K6

M6

J5

K4

C3

L1

K1

P3

N2

AB2

E4

D4

R3

C1

G7

B2

F3

G8

C2

G28

F28

AD5

R6

D2

T5

R4

M4

L4

M5

P6

AJ6

AJ5

AH5

AH4

AG5

AG4

L5

AG6

AF4

AF5

AB4

AC5

AB5

AA5

AD6

AA4

Y4

Y6

W6

AB6

W5

V4

V5

U4

U5

T4

U6

K3

J1000

2

1

R1004

2

1

R1003

2

1

R1000

PPCPU_VTT_OUT_LEFT

FSB_BPRI_L

FSB_DEFER_L

FSB_DBSY_L

FSB_BREQ0_L

CPU_FERR_L

PPCPU_VTT_OUT_RIGHT

CPU_STPCLK_L

CPU_NMI

FSB_HIT_L FSB_HITM_L

FSB_CPURST_L

CPU_IERR_L CPU_INIT_L

FSB_RS_L<0> FSB_RS_L<1>

PPCPU_VTT_OUT_RIGHT

FSB_RS_L<2>

FSB_TRDY_L

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_D_L<27>

CPU_GTLREF1

FSB_BNR_L

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_DINV_L<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<25>

FSB_DSTB_L_P<0>

FSB_DINV_L<0>

FSB_D_L<13>

FSB_D_L<11>

FSB_ADS_L

=PPVTT_S0_CPU

CPU_IGNNE_L

FSB_DSTB_L_N<0>

FSB_D_L<12>

FSB_D_L<9>

FSB_LOCK_L

FSB_A_L<3>

FSB_D_L<10>

FSB_D_L<1> FSB_D_L<2>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_DINV_L<2>

FSB_DINV_L<3>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_D_L<0>

FSB_D_L<3> FSB_D_L<4> FSB_D_L<5>

FSB_D_L<14> FSB_D_L<15>

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26>

FSB_D_L<30> FSB_D_L<31>

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

PPCPU_VTT_OUT_LEFT

CPU_GTLREF0

CPU_GTLREF_DIV0

FSB_REQ_L<4>

FSB_A_L<7>

CPU_A20M_L

FSB_ADSTB_L<0>

FSB_A_L<4>

FSB_A_L<6>

FSB_A_L<10>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30>

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_DRDY_L

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<3>

CPU_SMI_L

FSB_REQ_L<2>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<5>

FSB_A_L<31>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_INTR

FSB_A_L<8>

PPCPU_VTT_OUT_LEFT

CPU_GTLREF_DIV1

SYNC_MASTER=MASTER

CPU FSB

SYNC_DATE=N/A

100

1% 1/16W MF-LF 402

MF-LF

57.6

402

1% 1/16W

MF-LF

5%

402

62

1/16W

1UF

6.3V CERM 402

10%

MF-LF

402

1%

10

1/16W

X7R-CERM

NOSTUFF

220PF

10%

402

50V

1% 1/16W MF-LF

100

402

CERM

10%

6.3V

1UF

402

1/16W

57.6

402

MF-LF

1%

10%

402

X7R-CERM

50V

220PF

NOSTUFF

1/16W

10

1%

MF-LF

402

CPU

CRITICAL

WOLFDALE-SKT-1

BGA-NOHSK

100 14

CPU

CRITICAL

WOLFDALE-SKT-1

BGA-NOHSK

200

1/16W 402

5% MF-LF

402

62

MF-LF

5% 1/16W

MF-LF

5%

402

62

1/16W

100 14

100 14 13

100 14

12 11 10

100

12 11 10

100 29 11

71 55 50 6

12 11 10

100 29 11

12 11 10

IN IN

OUT

IN IN

BI BI

BI

IN

BI

TESTHI_0

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5*

DBR*

FC3

FC8 FC10 FC15 FC18 FC23 FC26

FC27/BPMB0*

FC28/TDO_M

FC29 FC30 FC31 FC32 FC33 FC34 FC35 FC36 FC37 FC39 FC40

FC41/BPMB1*

ITPCLK_0 ITPCLK_1

RSVD_A20

RSVD_AC4 RSVD_AE4

RSVD_AE6

RSVD_AH2

RSVD_D1

RSVD_D14

RSVD_D16

RSVD_E5

RSVD_E6

RSVD_E7

RSVD_E23 RSVD_F23

RSVD_F29

RSVD_G6

RSVD_J3

RSVD_N4

RSVD_N5

RSVD_P5

RSVD_V2

TCK TDI TDO

TESTHI_1 TESTHI_2 TESTHI_3 TESTHI_4 TESTHI_5 TESTHI_6 TESTHI_7

TESTHI_8/BPMB3*

TESTHI_9/BPMB2*

TESTHI_10

TESTHI_12/TDI_M

TMS TRST*

(4 OF 7)

RESERVED

TEST JTAG

XDP/ITP

PROCHOT* THERMTRIP*

GTLREF1 GTLREF0

THERMDC

FC5/GTLREF2

BOOTSELECT

BSEL_0 BSEL_1 BSEL_2

COMP_0 COMP_1 COMP_2 COMP_3 COMP_8

DPRSTP*

DPSLP*

IMPSEL

MSID_0

MSID_1

PECI

PSI*

PWRGOOD

SKTOCC*

SLP*

THERMDA

VRDSEL

FC38/GTLREF3

(3 OF 7)

THERMAL

PWR MGMT

BI

BI BI

BI BI BI BI

OUT OUT OUT

IN OUT OUT OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(TDI)

WITHIN 38MM (1.5IN) OF THE CPU

FROM 975X PDG: IMPSEL 0 - 51 PD TO GND

IPU

NC

NC NC NC

PLACE TMS/TMI/TCK TERMINATION

(TMS)

(TCK)

NC

(ALSO WRITTEN AS BPM2)

CPU BPMB TERM

KENTSFIELD CPU SUPPORT

CPU BPM TERM

(SELECTS 50 OHM SYSTEM IMPEDANCE)

11 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1150

2

1

R1120

2

1

R1121

2

1

R1122

2

1

R1123

2

1

R1128

2

1

R1151

2

1

R1109

2

1

R1129

2

1

R1180

2

1

R1181

2

1

R1182

2

1

R1183

2

1

R1130

2

1

R1133

2

1

R1132

2

1

R1135

AL3

M2

AK1

AL1

L2

AE8

N1

Y3

AL2

G5

V1 W1

F6

H2 H1 F2

G10

P1

T2

B13

R1

G2

T1

A13

G30

H30

G29

Y1

J1000

AG1

AC1

G4 G3

F24

G24

G26

G27

G25

F25

W2

H5

W3

F26

AF1

AD1

AE1

V2

P5

N5

N4

J3

G6

F29

F23

E7

E6 E5

E23

D16

D14

D1

AH2

AE6

AE4

AC4

A20

AJ3

AK3

AK6

C9

AM6

AA2

AB3

AD3

H4

J17

H16

H15

J16

U3

J2

U2

U1

G1

E29

A24

AE3

H29

E24

AC2

AG3

AF2

AG2

AD2

AJ1

AJ2

J1000

2

1

R1191

2

1

R1195

2

1

R1190

2

1

R1192

2

1

R1193

2

1

R1194

21

R1102

21

R1101

21

R1100

CPU_PWRGD

CPU_DPRSTP_L

CPU_DPSLP_L

CPU_PROCHOT_L

PPCPU_VTT_OUT_RIGHT

CPU_GTLREF1

CPU_BOOT

CPU_BSEL<0> CPU_BSEL<1>

CPU_PSI_L

FSB_CPUSLP_L

CPU_BSEL<2>

CPU_THERMD_N

CPU_THERMD_P

CPU_PECI_L

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<0>

CPU_GTLREF0

CPU_COMP<0>

CPU_COMP<1>

CPU_COMP<8>

CPU_COMP<2>

CPU_COMP<3>

=PPVTT_S0_FSB_CPU

PPCPU_VTT_OUT_LEFT

CPU_XDP_BPM_L<3> CPU_XDP_BPM_L<4> CPU_XDP_BPM_L<5>

CPU_XDP_BPM_L<1> CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<0>

PPCPU_VTT_OUT_RIGHT

CPU_XDP_TCK CPU_XDP_TDI

CPU_XDP_TMS

CPU_TESTHI_M

CPU_TESTHI_2_7

PPCPU_VTT_OUT_RIGHT

PPCPU_VTT_OUT_LEFT

CPU_TESTHI_0 CPU_TESTHI_1

CPU_TESTHI_10

PM_PGOOD_PVCORE_CPU

CPU_XDP_BPMB<0> CPU_XDP_BPMB<1>

CPU_XDP_BPMB<3>

CPU_XDP_BPMB<2>

CPU_XDP_BPMB<0>

CPU_XDP_BPMB<1>

CPU_XDP_TDO

CPU_XDP_TRST_L

CPU_XDP_BPM_L<0> CPU_XDP_BPM_L<1> CPU_XDP_BPM_L<2> CPU_XDP_BPM_L<3> CPU_XDP_BPM_L<4> CPU_XDP_BPM_L<5>

CPU_XDP_BPMB<2>

CPU_XDP_BPMB<3>

XDP_DBRESET_L

PM_THRMTRIP_L

CPU_COMP<1>

CPU_COMP<8> CPU_PD_IMPSEL

SYNC_DATE=N/A

SYNC_MASTER=MASTER

CPU TEST & MISC.

71 70

100 50 14

71

100 14

100 14 13

100 14

402

1/16W MF-LF

130

1%

NOSTUFF

MF-LF

1/16W 402

1%

49.9

402

MF-LF

49.9

1% 1/16W 1/16W

1%

402

MF-LF

49.9 49.9

1% 1/16W MF-LF 402

1%

402

MF-LF

1/16W

24.9

402

5% 1/16W MF-LF

51

108 55

51

402

1/16W

5% MF-LF

100 14

MF-LF

51

1/16W

5%

402

100 13 11

5% 1/16W

402

MF-LF

51

5% 1/16W

402

51

MF-LF

5%

402

MF-LF

1/16W

51

5% 1/16W MF-LF 402

51

100 13 11

MF-LF

402

51

1/16W

5%

MF-LF

402

1/16W

5%

51 51

1/16W

5%

402

MF-LF MF-LF

51

5%

402

1/16W

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

BGA-NOHSK

WOLFDALE-SKT-1

CRITICAL

CPU

1/16W

5% MF-LF

402

51

MF-LF

51

1/16W

5%

402402

1/16W

51

MF-LF

5%

51

402

MF-LF

1/16W

5%

51

402

MF-LF

1/16W

5%

51

1/16W

5% MF-LF

402

100 13 11

51

5%

402

1/16W MF-LF

5%

51

402

MF-LF

1/16W

5%

51

402

1/16W MF-LF

28 13

100 13 11

100 13

12 11 10

100 29 10

100 11

100 29 10

100 11

12 6

12 11 10

100 13 11

12 11 10

100 11

OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

VCCP

VTT_C29 VTT_C30 VTT_D25 VTT_D26 VTT_D27 VTT_D28 VTT_D29 VTT_D30

VTT_OUT_RIGHT VTT_OUT_LEFT VTT_SEL

VTT_C28

VTT_C27

VTT_C26

VTT_C25

VTT_B29

VTT_B28

VTT_B27

VTT_B26

VTT_B25

VTT_A30

VTT_A29

VTT_A28

VTT_A27

VTT_A26

VTT_A25

VTT_B30

VCCA

VCCIOPLL

VCCP

VCCPLL

VCC_MB_REGULATION

VCC_SENSE

VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 VID_7

VID_SELECT

VSSA

VSS_MB_REGULATION

VSS_SENSE

VCCP

(7 OF 7)

OUT

GND GND

(5 OF 7)

GNDGND

(6 OF 7)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

POWER

GND

VCC PLL DECOUPLING

(SEE VREG PAGE)

VCCP CORE DECOUPLING

~125MA CURRENT

THIS IS FOR OLDER CPU SUPPORT

GND

WILL PLACE FILTER BUT NOT CONNECT FOR WOLFDALE

VID PULLUPS WITH VREG

FSB VTT DECOUPLING

12 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1200

V25

E20

R7

V27

R5

V28 V29

R2

V30

V26

E26

P7

P4

N7

N6

N3

M7

M1

L7

L6

C13

V7

B8

B5

B1

D3 D5

R30

D6

C4

D9

E2

H6

T7

Y2

H3

AN24 AN27 AN28

E27

H12

B11

K7

B14

C22

K2

C24

D12

C10

C19

AN2

D18

F7

D21

E11

Y5

L28

E14

H7 H8

H28

H9

AN23

AN20

J4

K5

J7

L25

D24

E28

F10 F13 F16

F22

F4

E17

F19

C16

H13 H14 H17 H18 H19 H20 H21 H22

H10

H23 H24 H25

B17

H26

B20

E8

H27

L3

B24

L23 L24

H11

L26 L27

Y7

D15

L29

L30

C7

P23

W7

P25

W4

P26 P27

V6

P28 P29

V3

P30

R23 R24

U7

R25 R26 R27 R28 R29

E25

T6

V23 V24

T3

P24

J1000

AN10

AA24 AA25 AA26 AA27

AN13

AA28

AM4

AA29

AA30

AB23 AB24 AB25

AN16

AB26

AB1

AB27

AN17

AB28 AB29 AB30

AK24

AJ27

AH1

AE26

AJ4

A9

A6

A2

A18

AF13

AE10

AF16 AF17

AG24

AF23 AF24 AF25 AF26 AF27

AL7 AJ7

AH7

AK7

AF7

AK23

AL10

AF28

AE16

AN1

AF29

AL17

AL13

AM1

AM27

AK20

AK16

AL20

AK13

AL24

AL16

AM24

AE24

AF10

AE30

AE29

AF30

AE28

A12

AL23

AK30

AG7

AE13

AJ23

AM10

AK10

AH3

AJ17

AK29

AF6

AG10

AE17

AJ16

AK5

AF3

AJ10

AJ30

AH24

AM13

AE7

AH23

AE5

AH20

AH17

AK17

AH16

AD7

AH13

AJ28

AE27

AG13

AE25

AM16

AH6

AC7

AC6

AC3

AM17

AG16

AJ24

AB7

AA6

AG17

AA7

AA3

AM20

AK28

AK27

AJ29

AE2

A21

AH10

A15

AM23

AG20

AD4

AL27

AG23

AJ20

AJ13

AM28

AF20

AK2

AL28

AA23

AE20

J1000

F27

AA1

J1

D30

D29

D28

D27

D26

D25

C30

C29

C28

C27

C26

C25

B30

B29

B28

B27

B26

B25

A30

A29

A28

A27

A26

A25

B23

AN4 AN6

AN7

AM7

AM5

AL4

AK4

AL6

AM3

AL5

AM2

D23

AM15

AD23

AF11

AK15

AG27

J21

J18

J26

AL15

AF18

AD29

AH15

AN9

AG26

AJ15

J10

AK26

AG11

AN29

AK22

AF22

AL29

AF9

N26

AG9

AN12

AK8

T27

AJ19

U26

AJ8

AN15

AG8

AL22

AH12

N28

T26

AM8

AL19

K23

P8

K25

J11

AA8

J29

AH9

AJ25

AL30

N29

AG14

AK11

AJ9

AL12

AH25

AG18

AN30

AL14

K30

AJ11

AL11

AM11

AJ21

AG30

AK21

AK14

J30

Y24

AF21

AD30

AL9

AG19

J27

J12

W28

T28

J13

AF14

J24

AM12

AL26

AG28

AH27

AH29

AH19

J15

AL8

AE11 AE12

AM26

K29

AG22

AJ14

AB8

AM19

AM18

AC27

J23

U24

M29

AC29

Y26

AD28

AH11

AN14

Y30

W30

AC25

AL18

Y28

T25

W25

W24

W23

AK9

M27

Y25

Y27

AN18

AN11

AN25

AN26

Y23

AC23

AC24

U29

M28

W29

N23

AE14

AC8

AF15

AM9

T30

J28

J8

AC26

AF12

W26

AE18

N25

AC28

T8

AN21

M24

K27

M30

AE15

N8

AC30

AE19

AM30

AE21

K8

V8

AN19

AE22 AE23

AD24

AF19

K28

U28

AM22

N27

AG29

M23

U23

AD27

AJ12

Y8

K26

U25

L8

M26

M25

AM29

AJ26

AD26

N30

M8

AD25

J14

AM21

AG21

T24

J22

AG15

AK19

AK25

Y29AE9

AM25

AN22

AM14

T29

AH22

AK12

AH21

AH28

K24

AD8

AK18

U8

N24

R8 T23

AH14

AN8

AL25

W27

AH26

AH18

J20

AJ22

AH8

AG12

AH30

J19

AJ18

AG25

AL21

U30

J25

AF8

W8

J9

U27

C23

A23

AN3 AN5

J1000

2

1

C1200

2

1

C1201

2

1

C1281

2

1

C1280

2

1

C1210

2

1

C1213

2

1

C1211

2

1

C1212

21

R1211

21

R1210

21

L1210

2

1

C1238

2

1

C1237

2

1

C1236

2

1

C1235

2

1

C1234

2

1

C1226

CPU_VCC_PKG_SENSE_P

CPU_VCC_SENSE

CPU_VID_SELECT

PPCPU_VTT_OUT_RIGHT

=PPVCORE_S0_CPU

PPCPU_VTT_OUT_RIGHT

MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.2V

CPU_VID_SELECT

=PPVTT_S0_FSB_CPU

TP_CPU_VSS_SENSE

=PPVTT_S0_FSB_CPU

CPU_VID<4>

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.2V

CPU_VCCIOPLL

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.2V

CPU_VCCA

CPU_VID<3>

=PP1V5_S0_CPU_VCCPLL

VOLTAGE=1.2V

PPCPU_VTT_OUT_LEFT

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPCPU_VTT_OUT_LEFT

=PP1V5_S0_CPU_VCCPLL

CPU_VCCA_FLT

CPU_VID<0>

CPU_VSSA

CPU_VID<6>

CPU_VID<5>

CPU_VID<2>

CPU_VCCIOPLL

CPU_VCCA

PPCPU_VTT_OUT_RIGHT

TP_VTT_SEL

CPU_VID<1>

CPU_VCC_PKG_SENSE_N

CPU_VID<7>

=PPVTT_S0_FSB_CPU

MAX_NECK_LENGTH=3 MM

NET_SPACING_TYPE=PWR

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPU_VSSA

VOLTAGE=0V

SYNC_MASTER=MASTER

SYNC_DATE=N/A

CPU POWER, GND, DECAPS

CERM 402

20%

0.1UF

10V

20% 402

10V CERM

0.1UF

CERM

10V 402

20%

0.1UF

402

10V

20% CERM

0.1UF

402

0.1UF

10V

20% CERM

10V

20%

0.1UF

CERM 402

MF-LF

1/16W

5%

680

402

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

100 71

BGA-NOHSK

WOLFDALE-SKT-1

CPU

CRITICAL

20%

0.1UF

10V CERM 402

0.1UF

CERM 402

20% 10V

0.01UF

CERM

10% 16V

402

20%

10UF

X5R

6.3V 603

22UF

20%

6.3V CERM-X5R 805-3

20%

603

10uF

X5R

6.3V

6.3V CERM

402

10%

1UF

NOSTUFF

402

CERM

10%

1UF

6.3V

NOSTUFF

0

5% 1/10W MF-LF

603

1/10W

0

603

5% MF-LF

CONROE

0603

FERR-120-OHM-0.2A

100 71

108 53

100 71

12

12 11 10

6

12

11 10

12

12 11 6

12

12 6

12

11 10

12 11 10

12 6

12

12 11 10

12 11 6

12

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

IN IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PWRGD/HOOK0

OBSDATA_A3

OBSDATA_A2

TRSTn

DBR#/HOOK7

RESET#/HOOK6

OBSFN_D1

OBSFN_D0

OBSDATA_C1

OBSDATA_C0

OBSFN_C1

OBSFN_C0

OBSDATA_C2 OBSDATA_C3

OBSDATA_B3

OBSDATA_D1

OBSDATA_A1

MCP79-specific pinout

OBSFN_A1

HOOK3

OBSFN_B1

OBSDATA_B2

TDO

TDI

XDP_PRESENT#

TMS

TCK0

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_B0

OBSFN_A0

HOOK1

OBSDATA_D0

VCC_OBS_CD

OBSDATA_A0

OBSFN_B0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_D2

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

HOOK2

VCC_OBS_AB

13 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1301

2

1

R1316

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1300

21

R1303

2

1

C1301

2

1

C1300

2

1

R1315

21

R1399

TP_XDP_OBSFN_B0

FSB_CLK_ITP_P

CPU_XDP_TDO

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TDI JTAG_MCP_TMS

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

JTAG_MCP_TRST_L

JTAG_MCP_TDO

=PP3V3_S0_XDP

CPU_XDP_BPMB<1>

CPU_XDP_BPMB<3>

MCP_DEBUG<4> MCP_DEBUG<5>

CPU_XDP_BPM_L<0>

CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<1>

CPU_XDP_BPM_L<4>

CPU_XDP_TMS

CPU_XDP_TDI

MCP_DEBUG<6>

FSB_CPURST_L

MCP_DEBUG<7>

CPU_XDP_BPM_L<5>

CPU_PWRGD

CPU_XDP_BPM_L<3>

=PPVTT_S0_XDP

TP_XDP_OBSFN_B1

XDP_DBRESET_L

XDP_PWRGD

JTAG_MCP_TCK

PM_LATRIGGER_L

SMBUS_MCP_0_CLK

CPU_XDP_TRST_L

CPU_XDP_TCK

SMBUS_MCP_0_DATA

XDP_OBS20

CPU_XDP_BPMB<0>

CPU_XDP_BPMB<2>

SYNC_DATE=N/A

SYNC_MASTER=MASTER

eXtended Debug Port (XDP)

51

402

5%

XDP

1/16W MF-LF

100 11

MF-LF

1/16W

XDP

62

5%

402

19

28 11

100 11

100 14

21

19

21

100 11

LTH-030-01-G-D-A-TR

XDP_CONN

CRITICAL

F-ST-SM

5%

1/16W

XDP

1K

402

PLACEMENT_NOTE=Place close to CPU to minimize stub.

MF-LF

100 14 10

100 11

X5R

16V

402

10%

0.1uF

XDP

16V

402

X5R

10%

0.1uF

XDP

MF-LF

1/16W

1%

54.9

402

106 52 21

XDP

1/16W

5%

MF-LF

1K

402

100 14 11

100

6

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT

IN

BI BI

CPU_ADSTB0*

CPU_BPRI*

CPU_A25*

CPU_A24*

CPU_D4*

BCLK_OUT_CPU_N

BCLK_VML_COMP_GND

BCLK_VML_COMP_VDD

CPU_A14* CPU_A15*

CPU_A10* CPU_A11*

CPU_A13*

CPU_A12*

CPU_A16*

CPU_A31*

CPU_A18*

CPU_A30*

CPU_A26*

CPU_A33*

CPU_A21*

CPU_A20*

CPU_A23*

CPU_A19*

CPU_A22*

CPU_A28* CPU_A29*

CPU_A7*

CPU_A17*

CPU_A27*

CPU_A35*

CPU_A34*

CPU_A32*

CPU_REQ2*

CPU_A9*

CPU_REQ3*

CPU_A4*

CPU_A8*

CPU_A3*

CPU_ADSTB1*

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

CPU_COMP_GND

CPU_COMP_VCC

CPU_D1*

CPU_D3*

CPU_D15*

CPU_D11*

CPU_D10*

CPU_D8*

CPU_D13*

CPU_D9*

CPU_D23*

CPU_D19*

CPU_D21* CPU_D22*

CPU_D2*

CPU_D18*

CPU_D20*

CPU_D17*

CPU_D31*

CPU_D28*

CPU_D27*

CPU_D25* CPU_D26*

CPU_D24*

CPU_D7*

CPU_D30*

CPU_D29*

CPU_D38*

CPU_D33*

CPU_D32*

CPU_D39*

CPU_D37*

CPU_D36*

CPU_D5*

CPU_D42*

CPU_D44*

CPU_D43*

CPU_D40* CPU_D41*

CPU_D45*

CPU_D49*

CPU_D55*

CPU_D6*

CPU_D50*

CPU_D53*

CPU_D52*

CPU_D51*

CPU_D48*

CPU_D54*

CPU_D59*

CPU_D57*

CPU_D62*

CPU_D58*

CPU_D0*

CPU_D61*

CPU_D60*

CPU_D63*

CPU_D56*

CPU_D14*

CPU_D12*

CPU_DBI1*

CPU_DBI2*

CPU_DPRSTP*

CPU_DPSLP*

CPU_DPWR*

CPU_DSTBN0*

CPU_DSTBN2*

CPU_DSTBN3*

CPU_DSTBP0*

CPU_DSTBP1*

CPU_DSTBP2*

CPU_DSTBP3*

CPU_FERR*

CPU_HIT*

CPU_LOCK*

CPU_NMI

CPU_PECI CPU_PROCHOT*

CPU_REQ0* CPU_REQ1*

CPU_A6*

CPU_RESET*

CPU_RS0* CPU_RS1* CPU_RS2*

CPU_SLP*

CPU_SMI*

CPU_THERMTRIP*

CPU_TRDY*

V1P1_DLLDLCELL_AVDD

V1P1_PLL_CPU

V1P1_PLL_FSB

V1P1_PLL_MCLK

CPU_D16*

CPU_D47*

CPU_D46*

CPU_A5*

CPU_DBI3*

CPU_D35*

CPU_D34*

BCLK_OUT_ITP_N

CPU_DEFER*

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P

BCLK_IN_N

BCLK_OUT_NB_N

BCLK_OUT_NB_P

CPU_INIT*

BCLK_IN_P

CPU_A20M*

CPU_IGNNE*

CPU_INTR

CPU_PWRGD

CPU_STPCLK*

CPU_BR0* CPU_BR1* CPU_DBSY* CPU_DRDY*

CPU_HITM*

CPU_BNR*

CPU_ADS*

CPU_REQ4*

CPU_DBI0*

CPU_DSTBN1*

FSB

(1 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

20 mA 29 mA 15 mA

206 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Loop-back clock for delay matching.

270 mA (A01)

NC

14 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R1420

2

1

R1421

2

1

R1422

AH27 AG28 AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC39

AC37

AE38

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

T43

T41

W41

H39

H43

K41

J40

V42

H41

H42

L41

M43

M42

K42

N41

N40

M40

P41

Y39

L42

H40

J39

J38

J37

L39

L38

L37

N38

N36

Y42

R39

N33

R37

R38

N34

P35

R34

R35

U38

R33

W42

U37

U36

U35

U34

U33

W38

W35

W34

W33

AA34

Y40

AA37

AA36

AA35

AA38

R42

P42

R41

U41

T39

T42

Y43

Y41

AM43 AM42

F42 D42 F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AE34

AE35

AC34

AC35

AC33

AE37

AN34

AR39

AN36

AN35

AN38

AL33

AB35

AN37

AL34

AL35

AJ33

AL38

AL39

AJ36

AL37

AJ35

AF41

AJ37

AJ38

AG33

AJ34

AG34

AG35

AF35

AG37

AG38

AE33

AG39

AM39 AM40

AL41 AK42

AL43 AL42

G42 G41

AJ40

AK41

U1400

2

1

R1416

2

1

R1440

2

1

R1410

2

1

R1435

2

1

R1430

2

1

R1431

2

1

R1436

=PP1V05_S0_MCP_FSB

CPU_FERR_L

=PP1V05_S0_MCP_FSB

FSB_ADSTB_L<0>

FSB_DEFER_L

FSB_BPRI_L

FSB_A_L<25>

FSB_D_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_MCP_N

FSB_CLK_MCP_P

FSB_A_L<14>

FSB_A_L<11>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<16>

FSB_A_L<31>

FSB_A_L<18>

CPU_A20M_L

FSB_A_L<26>

FSB_A_L<33>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<28>

FSB_A_L<7>

FSB_A_L<27>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<32>

FSB_REQ_L<2>

FSB_A_L<9>

FSB_REQ_L<3>

FSB_A_L<4>

FSB_A_L<8>

FSB_A_L<3>

FSB_ADS_L

FSB_ADSTB_L<1>

FSB_BNR_L FSB_BREQ0_L

FSB_D_L<1>

FSB_D_L<3>

FSB_D_L<15>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<8>

FSB_D_L<13>

FSB_D_L<9>

FSB_D_L<23>

FSB_D_L<19>

FSB_D_L<21> FSB_D_L<22>

FSB_D_L<2>

FSB_D_L<18>

FSB_D_L<20>

FSB_D_L<17>

FSB_D_L<31>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<25> FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<7>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<35>

FSB_D_L<38>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<34>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<5>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<40> FSB_D_L<41>

FSB_D_L<49>

FSB_D_L<55>

FSB_D_L<6>

FSB_D_L<50>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<48>

FSB_D_L<54>

FSB_D_L<59>

FSB_D_L<57>

FSB_D_L<62>

FSB_D_L<58>

FSB_D_L<0>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<63>

FSB_D_L<56>

FSB_D_L<14>

FSB_D_L<12>

FSB_DINV_L<0>

FSB_DINV_L<1>

FSB_DINV_L<2>

FSB_DBSY_L

CPU_DPRSTP_L

FSB_DRDY_L

FSB_DSTB_L_N<0>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>

FSB_DSTB_L_P<1>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_HITM_L FSB_LOCK_L

CPU_PECI_MCP

FSB_REQ_L<0> FSB_REQ_L<1>

FSB_REQ_L<4>

FSB_A_L<6>

FSB_CPURST_L

FSB_RS_L<0>

CPU_STPCLK_L

FSB_D_L<16>

FSB_D_L<47>

FSB_D_L<46>

FSB_A_L<5>

FSB_DINV_L<3>

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<17>

FSB_A_L<23>

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_IGNNE_L

FSB_D_L<45>

FSB_D_L<42>

FSB_A_L<24>

MCP_CPU_COMP_GND

MCP_BCLK_VML_COMP_GND

MCP_BCLK_VML_COMP_VDD

FSB_CPUSLP_L CPU_DPSLP_L

MCP_CPU_COMP_VCC

PP1V05_S0_MCP_PLL_FSB

FSB_RS_L<2>

FSB_RS_L<1>

FSB_HIT_L

CPU_BSEL<2> CPU_BSEL<1> CPU_BSEL<0>

FSB_A_L<21> FSB_A_L<22>

FSB_A_L<29> FSB_A_L<30>

PM_THRMTRIP_L

CPU_PROCHOT_L

FSB_TRDY_L

FSB_BREQ1_L

CPU_INIT_L

MCP CPU Interface

SYNC_MASTER=MASTER

SYNC_DATE=N/A

402

470

MF-LF

1/16W

5%

1/16W MF-LF

5%

470

402

1/16W MF-LF

5%

470

402

OMIT

BGA

MCP7A

5%

62

MF-LF 402

1/16W

5%

MF-LF 402

1/16W

150

NO STUFF

1/16W MF-LF

402

62

5%

MF-LF 402

1% 1/16W

49.9

1/16W

1%

402

MF-LF

49.9

MF-LF

402

1%

1/16W

MF-LF 402

1% 1/16W

49.9

100 10

100 50 11

108 55

100 11

100 10

100 11

100 13 11

100 10

100 13

100 10

100 13 10

100 10

100 11

25 22 14 6

100

25

100

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

MDQ0_1

MDQ0_2

MCLK0A_1_N

MCLK0A_0_P

MCS0A_0*

MDQ0_63 MDQ0_62 MDQ0_61

MDQS0_1_P

MDQS0_0_P

MDQ0_57

MDQ0_41 MDQ0_40

MDQ0_28

MDQ0_42

MDQ0_43

MDQ0_44

MDQ0_45

MDQ0_46

MDQ0_47

MDQ0_48

MDQ0_49

MDQ0_38

MA0_0

MA0_1

MA0_10

MA0_11

MA0_12

MA0_13

MA0_14

MA0_2

MA0_4

MA0_5

MA0_6

MA0_7

MA0_8

MA0_9

MBA0_0

MBA0_1

MBA0_2

MCAS0*

MCKE0A_0

MCKE0A_1

MCLK0A_0_N

MCLK0A_1_P

MCLK0A_2_N

MCLK0A_2_P

MCS0A_1*

MDQ0_0

MDQ0_10

MDQ0_11

MDQ0_12

MDQ0_13

MDQ0_14

MDQ0_15

MDQ0_16

MDQ0_17

MDQ0_18

MDQ0_20

MDQ0_21

MDQ0_22

MDQ0_23

MDQ0_24

MDQ0_25

MDQ0_26

MDQ0_27

MDQ0_29

MDQ0_3

MDQ0_30

MDQ0_31

MDQ0_32

MDQ0_33

MDQ0_34

MDQ0_35

MDQ0_36

MDQ0_37

MDQ0_39

MDQ0_4

MDQ0_5

MDQ0_55

MDQ0_56

MDQ0_58

MDQ0_59

MDQ0_6

MDQ0_60

MDQ0_7

MDQ0_9

MDQM0_0

MDQM0_1

MDQM0_2

MDQM0_3

MDQM0_4

MDQM0_5

MDQM0_6

MDQM0_7

MDQS0_0_N

MDQS0_1_N

MDQS0_2_N

MDQS0_2_P

MDQS0_3_N

MDQS0_3_P

MDQS0_4_N

MDQS0_4_P

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MODT0A_0

MODT0A_1

MRAS0*

MWE0*

MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50

MA0_3

MDQ0_19

MDQ0_8

0A

MEMORY

CONTROL

MEMORY PARTITION 0

(2 OF 11)

MDQ1_43

MA1_0

MA1_1

MA1_10

MA1_11

MA1_12

MA1_13

MA1_14

MA1_2

MA1_3

MA1_4

MA1_5

MA1_6

MA1_7

MA1_8

MA1_9

MBA1_0

MBA1_1

MBA1_2

MCAS1*

MCKE1A_0

MCS1A_0*

MDQ1_0

MDQ1_1

MDQ1_10

MDQ1_11

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_16

MDQ1_17

MDQ1_18

MDQ1_19

MDQ1_2

MDQ1_20

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_25

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_3

MDQ1_30

MDQ1_31

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_4

MDQ1_40

MDQ1_41

MDQ1_42

MDQ1_44

MDQ1_45

MDQ1_46

MDQ1_47

MDQ1_48

MDQ1_49

MDQ1_5

MDQ1_50

MDQ1_51

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_55

MDQ1_56

MDQ1_57

MDQ1_58

MDQ1_59

MDQ1_6

MDQ1_61

MDQ1_62

MDQ1_63

MDQ1_7

MDQ1_8

MDQ1_9

MDQM1_0

MDQM1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQS1_0_N

MDQS1_0_P

MDQS1_1_N

MDQS1_1_P

MDQS1_2_P

MDQS1_3_N

MDQS1_3_P

MDQS1_4_N

MDQS1_4_P

MDQS1_5_N

MDQS1_5_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_7_P

MODT1A_1

MRAS1*

MWE1*

MDQ1_60

MDQS1_2_N

MCLK1A_2_P MCLK1A_2_N

MCLK1A_1_P MCLK1A_1_N

MCLK1A_0_P MCLK1A_0_N

MCS1A_1*

MODT1A_0

MCKE1A_1

MEMORY

CONTROL

1A

MEMORY PARTITION 1

(3 OF 11)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

15 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BA16

AW16

BB13 AY15

AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

AT5 BA2

AY7 BA11 BB34 BB38 AY43 AR42

AW42 AW41 AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9 BB10 BB12 AW12

BB8

BB9 AY12 BA12 BC32 AW32

AU40

BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40

AU41

BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40

AR41 AP42

BB14 BB16

BA42 BB42

BB22 BA22

BA19 AY19

AY31 BB30

BA15

BB29 BB18 BB17

BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25

BA29 BA14 AW28 BC28 BA17

BB25 BA18

U1400

AR17

AV17

AP15 AV15

AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

AN5

AU5 AR10 AN13 AN27 AW29 AV35 AR34

AT37 AU37 AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5 AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9 AP11

AW6

AY5

AU9

AV9

AR38

AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25

AV38

AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31

AW38

AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31

AR35 AP35

AT15 AR18

AW33 AV33

BA24 AY24

BB20 BC20

AU23 AT23

AP17

AP23 AP19 AW17

AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19

AR23 AU15 AN23 AW21 AN19

AT19 AR19

U1400

MEM_A_DQ<9> MEM_A_DQ<8>

MEM_A_ODT<1>

MEM_B_DQ<43>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_DQ<1>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<2>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<3>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<4>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<5>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<6>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_ODT<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQ<60>

MEM_B_DQS_N<2>

TP_MEM_B_CLK2P TP_MEM_B_CLK2N

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_A_DQ<55>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CS_L<0>

MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<57>

MEM_A_DQ<41> MEM_A_DQ<40>

MEM_A_DQ<28>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<38>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CAS_L

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_CS_L<1>

MEM_A_DQ<0>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<3>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<39>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<56>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<6>

MEM_A_DQ<60>

MEM_A_DQ<7>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_ODT<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50>

MEM_A_A<3>

MEM_A_DQ<19>

MEM_B_DQ<0>

MEM_B_ODT<0>

MEM_B_CKE<0>

MCP Memory Interface

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP7A

OMIT

BGA

OMIT

BGA

MCP7A

101 33

101 32

101 33

101 32

101 33

101 31

101 33

101 31

101 33

8

8 8

8

MRESET0*

MCLK0B_0_P

MCLK0B_1_P MCLK1B_1_P

MCLK1B_2_P

GND

MCKE1B_0 MCKE1B_1

MCLK0B_2_N

MCLK0B_2_P

MCLK1B_0_N

MCLK1B_0_P

MCLK1B_1_N

MCS0B_0* MCS1B_0*

MCS1B_1*

MODT0B_1 MODT1B_1

V1P1_PLL_DP

V1P8_MEM_VDDP

GND

MEM_COMP_1P8V

MEM_COMP_GND

V1P1_PLL_XREF_XS

V1P1_PLL_CORE

V1P1_PLL_V

MCKE0B_1

MODT0B_0

MCLK0B_0_N

MCLK0B_1_N

MODT1B_0

MCLK1B_2_N

MCS0B_1*

MCKE0B_0

MEMORY CONTROL 1B

MEMORY CONTROL 0B

(4 OF 11)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER SIZE

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A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA 39 mA

TP or NC for DDR2.

87 mA (A01)

16 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

AR16

AV16

AP24

AP20

AN22

BC29

AN16

AM29

AM27

AM25

AP16

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AT17

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AN24

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AN20

AM17

T27

T28 U28 U27

AY32

BC13

AY16

AN15

AN17

AM41 AN41

BA13

BC16

AR15

AU17

BA41 BB41

AY23 BA23

BA20 AY20

AU33 AU34

BB24 BC24

BA21 BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

2

1

R1611

2

1

R1610

MCP_MEM_RESET_L

MEM_B_CKE<3>

MEM_A_CLK_P<3>

MEM_A_CLK_P<4> MEM_B_CLK_P<4>

TP_MEM_B_CLK5P

MEM_B_CKE<2>

TP_MEM_A_CLK5P

MEM_B_CLK_N<4>

MEM_B_CS_L<3>

MEM_A_ODT<3> MEM_B_ODT<3>

MEM_A_CKE<3>

MEM_A_CLK_N<3>

MEM_B_ODT<2>

TP_MEM_B_CLK5N

MEM_A_CS_L<3>

MEM_A_CKE<2>

=PP1V8R1V5_S0_MCP_MEM

MEM_A_CS_L<2>

MEM_A_ODT<2>

MEM_A_CLK_N<4>

TP_MEM_A_CLK5N

PP1V05_S0_MCP_PLL_CORE

=PP1V8R1V5_S0_MCP_MEM

MEM_B_CLK_P<3> MEM_B_CLK_N<3>

MEM_B_CS_L<2>

MCP_MEM_COMP_VDD

MCP_MEM_COMP_GND

SYNC_DATE=N/A

SYNC_MASTER=MASTER

MCP MEMORY CNTRL & MISC

33

40.2

MF-LF

1%

1/16W

402

1%

40.2

1/16W

402

MF-LF

MCP7A

BGA

OMIT

101 32

101 33

101 33 101 33

8

101 32

8

101 33

101 32

101 31 101 32

101 31

101 33

101 32

8

101 31

30 25 16 6

101 31

101 33

8

25

30 25 16 6

101 33

101 32

101

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

PEB_CLKREQ*/GPIO_49 PEB_PRSNT*

PE0_RX13_N PE0_RX14_P

PEE_CLKREQ*/GPIO_16

V1P1_PEX_AVDD0

V1P1_PEX_AVDD1

V1P1_PEX_DVDD0

V1P1_PEX_DVDD1

V1P1_PLL_PEX

PE_WAKE*

PE0_PRSNT_16*

PE0_REFCLK_N

PE0_REFCLK_P

PE0_RX0_N

PE0_RX0_P

PE0_RX1_N

PE0_RX1_P

PE0_RX10_N

PE0_RX10_P

PE0_RX11_N

PE0_RX11_P

PE0_RX12_N

PE0_RX12_P

PE0_RX13_P

PE0_RX14_N

PE0_RX15_N

PE0_RX15_P

PE0_RX2_N

PE0_RX2_P

PE0_RX3_N

PE0_RX3_P

PE0_RX4_P

PE0_RX6_N

PE0_RX6_P

PE0_RX7_N

PE0_RX7_P

PE0_RX8_N

PE0_RX8_P

PE0_RX9_N

PE0_RX9_P

PE0_TX0_N

PE0_TX0_P

PE0_TX1_N

PE0_TX1_P

PE0_TX10_P

PE0_TX11_N

PE0_TX11_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_N

PE0_TX13_P

PE0_TX14_N

PE0_TX14_P

PE0_TX15_N

PE0_TX15_P

PE0_TX2_N

PE0_TX2_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_N

PE0_TX4_P

PE0_TX5_N

PE0_TX5_P

PE0_TX6_N

PE0_TX6_P

PE0_TX7_N

PE0_TX7_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_N

PE0_TX9_P

PE1_REFCLK_N

PE1_REFCLK_P

PE1_RX0_N

PE1_RX0_P

PE1_RX1_N

PE1_RX1_P

PE1_RX2_N

PE1_RX2_P

PE1_RX3_N

PE1_RX3_P

PE1_TX0_N

PE1_TX0_P

PE1_TX1_N

PE1_TX1_P

PE1_TX2_N

PE1_TX2_P

PE1_TX3_N

PE1_TX3_P

PE3_REFCLK_N

PE3_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_N

PE6_REFCLK_P

PEC_CLKREQ*/GPIO_50 PEC_PRSNT*

PED_CLKREQ*/GPIO_51 PED_PRSNT*

PEE_PRSNT*/GPIO_46

PEF_CLKREQ*/GPIO_17 PEF_PRSNT*/GPIO_47

PEX_CLK_COMP

PEX_RST0*

PE0_RX5_P PE0_RX5_N

PE0_RX4_N

PE0_TX10_N

PE2_REFCLK_N

PE2_REFCLK_P

PEG_PRSNT*/GPIO_48

PEG_CLKREQ*/GPIO_18

PCI EXPRESS

(5 OF 11)

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

84 mA (A01)

Int PU

Minimum 1.025V for Gen2 support

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Int PU

57 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

Int PU

17 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

R12

P12

M12

AB12

AA12

W12

V12

AD12

U12

T12

N12

AC12

Y12

K11

A11

M19

M17

M18

M16

L18

L16

B10

M15

C10

E8

D9

D5

F17

N14 M14

L14 K14

J13 H13

G13 F13

J11 J10

B6 C6

A7 B7

B8 A8

D8 C8

H7 G7

F9 E9

H9 G9

K9 J9

G11 F11

H3 H2

G3 H4

F3 F4

E2 F2

D2 E1

C1 D1

B3 B2

A4 A3

C4 B4

M2 M1

M4 M3

L4 L3

K2 K3

J2 J3

H1 J1

C5 D4

L11 L10

J5 J4

J7 J6

G5 H5

C3 D3

E4 E3

E5 F5

E6 F6

D7 C7

N5 N4

N7 N6

N9 P9

N11 N10

L7 L6

L9 L8

F7 E7

E11 D11

C9

U1400

2

1

R1710

PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N

=PEG_R2D_C_N<10>

=PEG_D2R_N<4>

=PEG_D2R_N<5>

=PEG_D2R_P<5>

PCIE_RESET_L

TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N

PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N

TP_PCIE_PE4_D2RP

PCIE_EXCARD_D2R_P

PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N

=PEG_R2D_C_P<9> =PEG_R2D_C_N<9>

=PEG_R2D_C_P<8> =PEG_R2D_C_N<8>

=PEG_R2D_C_P<7> =PEG_R2D_C_N<7>

=PEG_R2D_C_P<6> =PEG_R2D_C_N<6>

=PEG_R2D_C_P<5> =PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<15> =PEG_R2D_C_N<15>

=PEG_R2D_C_P<14> =PEG_R2D_C_N<14>

=PEG_R2D_C_P<13> =PEG_R2D_C_N<13>

=PEG_R2D_C_P<12> =PEG_R2D_C_N<12>

=PEG_R2D_C_P<11> =PEG_R2D_C_N<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_P<0> =PEG_R2D_C_N<0>

=PEG_D2R_P<9> =PEG_D2R_N<9>

=PEG_D2R_P<8> =PEG_D2R_N<8>

=PEG_D2R_P<7> =PEG_D2R_N<7>

=PEG_D2R_P<6> =PEG_D2R_N<6>

=PEG_D2R_P<4>

=PEG_D2R_P<3> =PEG_D2R_N<3>

=PEG_D2R_P<2> =PEG_D2R_N<2>

=PEG_D2R_N<14>

=PEG_D2R_P<13>

=PEG_D2R_P<12> =PEG_D2R_N<12>

=PEG_D2R_P<11> =PEG_D2R_N<11>

=PEG_D2R_P<10> =PEG_D2R_N<10>

=PEG_D2R_P<1> =PEG_D2R_N<1>

=PEG_D2R_N<0>

PEG_CLK100M_P PEG_CLK100M_N

=PP1V05_S0_MCP_PEX_AVDD1

=PEG_D2R_P<14>

=PEG_D2R_N<13>

PCIE_MINI_PRSNT_L

=PP1V05_S0_MCP_PEX_AVDD0

=PEG_D2R_P<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2> =PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

MCP_PEX_CLK_COMP

PP1V05_S0_MCP_PLL_PEX

=PP1V05_S0_MCP_PEX_DVDD1

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_D2RN

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_MINI_D2R_N

GMUX_JTAG_TDO

TP_PE4_CLKREQ_L

PCIE_FW_PRSNT_L

=PEG_D2R_P<15> =PEG_D2R_N<15>

PEG_PRSNT_L

MINI_CLKREQ_L

FW_CLKREQ_L

EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L

PCIE_WAKE_L

PCIE_MINI_D2R_P

=PP1V05_S0_MCP_PEX_DVDD0

TP_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L

CARDREADER_RESET

MCP PCIe Interfaces

SYNC_MASTER=MASTER

SYNC_DATE=N/A

47

MCP7A

BGA

OMIT

67

8

9

2.37K

402

MF-LF

1% 1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

9

8

102 34

8

102 41

102 34

8

9

34

8

102 41

34

42

9

102 34

9

8

28

28 25

102

25

28

8

28 25

8

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

IN OUT

IN IN IN

BI

XTALIN_TV

RGB_DAC_RSET

MII_COMP_GND

MII_COMP_VDD

V1P1_DUAL_MACPLL

MII_COL/GPIO_20/MSMB_DATA

BUF_25MHZ

DDC_CLK0

DDC_CLK2/GPIO_23

DDC_CLK3

DDC_DATA0

DDC_DATA2/GPIO_24

DDC_DATA3

DP_AUX_CH0_N

DP_AUX_CH0_P

GPIO_6/FERR*/IGPU_GPIO6 GPIO_7/NFERR*/IGPU_GPIO7

HDMI_RSET

HDMI_TXC_N/ML0_LANE3_N

HDMI_TXC_P/ML0_LANE3_P

HDMI_TXD0_N/ML0_LANE2_N

HDMI_TXD0_P/ML0_LANE2_P

HDMI_TXD1_N/ML0_LANE1_N

HDMI_TXD1_P/ML0_LANE1_P

HDMI_TXD2_N/ML0_LANE0_N

HDMI_TXD2_P/ML0_LANE0_P

HDMI_VPROBE

HPLUG_DET2/GPIO_22 HPLUG_DET3

IFPA_TXC_N

IFPA_TXC_P

IFPA_TXD0_N

IFPA_TXD0_P

IFPA_TXD1_N

IFPA_TXD2_N

IFPA_TXD2_P

IFPA_TXD3_N

IFPA_TXD3_P

IFPAB_RSET

IFPAB_VPROBE

IFPB_TXC_N

IFPB_TXC_P

IFPB_TXD4_N

IFPB_TXD4_P

IFPB_TXD5_N

IFPB_TXD5_P

IFPB_TXD6_N

IFPB_TXD6_P

IFPB_TXD7_N

IFPB_TXD7_P

LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58

MII_RESET*

MII_RXER/GPIO_36

MII_VREF

V3P3_DUAL_RMGT0 V3P3_DUAL_RMGT1

V1P0_DUAL_RMGT_0 V1P0_DUAL_RMGT_1

V3P3_PLL_HDMI

V3P3_PLL_IFPAB

V3P3_RGBDAC_VDD

V3P3_TVDAC_VDD

V1P1_HDMI_VDD

V1P8_IFPA_VDD V1P8_IFPB_VDD

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB_DAC_RED

RGB_DAC_VREF

RGB_DAC_VSYNC

MII_MDC

MII_MDIO

MII_PWRDWN/GPIO_37

MII_RXCLK MII_RXDV

MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3

MII_TXD0 MII_TXD1 MII_TXD2

TV_DAC_BLUE

TV_DAC_GREEN

TV_DAC_HSYNC/GPIO_44

TV_DAC_RED

TV_DAC_RSET TV_DAC_VREF

TV_DAC_VSYNC/GPIO_45

XTALOUT_TV

MII_TXEN

MII_TXCLK

MII_TXD3

RGB_DAC_GREEN

IFPA_TXD1_P

MII_CRS/GPIO_21/MSMB_CLK

MII_INTR/GPIO_35

DACS

LAN

FLAT PANEL

(6 OF 11)

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: HDMI port requires level-shifting. IFP interface can

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

TP_DP_IG_AUX_CHP/N

TMDS_IG_HPD

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0> =MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

be used to provide HDMI or dual-channel TMDS without

DP_IG_DDC_DATA

DP_IG_DDC_CLK

Interface Mode

level-shifters.

DP_IG_AUX_CH_P/N

NOTE: 20K pull-down required on DP_HPD_DET.

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

TMDS_IG_DDC_DATA

MCP Signal

=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD

8 mA 8 mA

16 mA (A01)

95 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_ML_P/N<0>

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

18 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

D38

C38

K32

J32

M28 M29

K24

J24

M26

M27

T25

T23

V23

U23

C37

A35

E36

A36

D36

B36 C36

A41

B38

C39

B39

A40

A39 B40

E28

C26

D25

C25

C24

B24

D24F23

C22

A24

E24

B23

C23

A23

J23

G23

C21

D21

J22

B22

C27 B27

B26

F40

E37

G39

N30 M30

L30 K30

L29 K29

J29 H29

L31 K31

G31

E32

B34 C34

D33 C33

D32 C32

B32 A32

B35 C35

F31

C31

J30

J33 H33

F33 G33

G35 F35

D35 E35

J31

B15

E16

D43 C43

E31

B30

A31

D31

C30

B31

E23

U1400

2

1

R1820

2

1

R1860

2

1

R1861

2

1

R1850

2

1

R1811

2

1

R1810

MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN

TP_MCP_RGB_DAC_RSET

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

PP1V05_ENET_MCP_PLL_MAC

=MCP_MII_COL

MCP_CLK25M_BUF0_R

MCP_DDC_CLK0

LVDS_IG_DDC_CLK

=MCP_HDMI_DDC_CLK

MCP_DDC_DATA0

LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_DATA

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

LPCPLUS_GPIO DP_IG_CA_DET

MCP_HDMI_RSET

=MCP_HDMI_TXC_N

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXD_P<2>

MCP_HDMI_VPROBE

=DVI_HPD_GMUX_INT =MCP_HDMI_HPD

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<3>

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

ENET_RESET_L

=MCP_MII_RXER

MCP_MII_VREF

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_RMGT

PP3V3_S0_MCP_VPLL

PP3V3_S0_MCP_DAC

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_RED

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_VSYNC

ENET_MDC ENET_MDIO

TP_ENET_PWRDWN_L

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2>

CRT_IG_B_COMP_PB

CRT_IG_G_Y_Y

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_TV_DAC_RSET

CRT_IG_VSYNC

MCP_CLK27M_XTALOUT

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

TP_MCP_RGB_GREEN

LVDS_IG_A_DATA_P<1>

=MCP_MII_CRS

TP_ENET_INTR_L

=PP3V3_S5_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<3>

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP Ethernet & Graphics

104 37

102 26

104 37

102 26

9

89

107 89

104 37

107 89

104 37

107 89

104 37

MCP7A

BGA

OMIT

5%

47K

402

MF-LF

1/16W

51

402

MF-LF

5%

1/16W

100K

402

5%

100K

1/16W MF-LF

10K

402

1/16W

5%

MF-LF

9

8

93

MF-LF

49.9

402

1%

1/16W

1% 1/16W MF-LF

402

49.9

8

107 26

9

107 93

9

89

8

37

104 37

104 38

104 37

25

104

25

38 25 18

38 25

26

8

20 6

38 25 18

21 19 6

OUT

BI BI BI BI

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

(7 OF 11)

PCI

GND

LPC

PCI_AD28

PCI_REQ4*/GPIO_52/RS232_SIN*

PCI_REQ2*/GPIO_40/RS232_DSR*

PCI_AD31

LPC_PWRDWN*/GPIO_54/EXT_NMI*

LPC_RESET0*

LPC_AD1 LPC_AD2 LPC_AD3

LPC_CLK0

LPC_FRAME*

PCI_TRDY*

PCI_STOP*

PCI_SERR*

PCI_RESET1*

PCI_RESET0*

PCI_REQ3*/GPIO_38/RS232_CTS*

PCI_REQ1*/FANRPM2

PCI_REQ0*

PCI_PME*/GPIO_30

PCI_PERR*/GPIO_43/RS232_DCD*

PCI_PAR

PCI_IRDY*

PCI_INTZ*

PCI_INTY*

PCI_INTX*

PCI_INTW*

PCI_GNT4*/GPIO_53/RS232_SOUT*

PCI_GNT3*/GPIO_39/RS232_RTS*

PCI_GNT2*/GPIO_41/RS232_DTR*

PCI_GNT1*/FANCTL2

PCI_GNT0*

PCI_FRAME*

PCI_DEVSEL*

PCI_CLKRUN*/GPIO_42

PCI_CLKIN

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CBE3*

PCI_CBE2*

PCI_CBE1*

PCI_CBE0*

PCI_AD30

PCI_AD29

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

PCI_AD22

PCI_AD21

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD0

LPC_SERIRQ

LPC_DRQ0*

LPC_AD0

GND GND

LPC_DRQ1*/GPIO_19

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

19 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2 AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

21

R1953

21

R1952

21

R1951

21

R1950

21

R1960

2

1

R1961

21

R1992

21

R1994

21

R1990

21

R1991

21

R1989

2

1

R1910

TP_PCI_AD<26>

PCI_CLK33M_MCP

TP_PCI_GNT0_L

TP_PCI_AD<28>

MCP_RS232_SIN_L

CRTMUX_SEL_TV_L

TP_PCI_AD<31>

LPC_PWRDWN_L

LPC_RESET_L

LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

TP_PCI_TRDY_L

TP_PCI_STOP_L

TP_PCI_SERR_L

TP_PCI_RESET1_L

MEM_VTT_EN_R

AUD_IPHS_SWITCH_EN

PCI_REQ1_L

PCI_REQ0_L

PM_LATRIGGER_L

TP_PCI_PERR_L

TP_PCI_PAR

TP_PCI_IRDY_L

TP_PCI_INTZ_L

TP_PCI_INTY_L

TP_PCI_INTX_L

TP_PCI_INTW_L

MCP_RS232_SOUT_L

GMUX_JTAG_TDI

GMUX_JTAG_TMS

TP_PCI_GNT1_L

TP_PCI_FRAME_L

TP_PCI_DEVSEL_L

PM_CLKRUN_L

PCI_CLK33M_MCP_R

TP_PCI_CLK1

TP_PCI_CLK0

TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<0>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<27>

TP_PCI_AD<25>

TP_PCI_AD<24>

TP_PCI_AD<23>

TP_PCI_AD<22>

TP_PCI_AD<21>

TP_PCI_AD<20>

TP_PCI_AD<19>

TP_PCI_AD<18>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<15>

TP_PCI_AD<14>

TP_PCI_AD<13>

TP_PCI_AD<12>

TP_PCI_AD<11>

TP_PCI_AD<10>

TP_PCI_AD<9>

TP_PCI_AD<8>

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

MCP_DEBUG<4>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

LPC_SERIRQ

TP_LPC_DRQ0_L

LPC_AD_R<0>

FW_PME_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

LPC_AD<0>

LPC_FRAME_L

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

MCP_RS232_SOUT_L

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L

MCP PCI & LPC

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP7A

BGA

OMIT

8

68

13

19

42

9

402

MF-LF1/16W

5%

22

5%

1/16W MF-LF

402

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

1/16W MF-LF

402

22

5%

MF-LF 402

1/16W

5%

10K

19

8.2K

5%

1/16W MF-LF

402 402

MF-LF1/16W

8.2K

5%

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

PLACEMENT_NOTE=Place close to pin R8

MF-LF 402

1/16W

5%

22

51 49

103 9 51 49

51 49

103 51 49

103 9

103 51 49

8

103

8

103

8

103 19

8

103

8

103

21 18 6

19

103 19

19

BI BI

IN IN IN

OUT OUT

IN

OUT OUT

IN IN

USB9_P USB9_N

USB8_P USB8_N

USB7_P USB7_N

USB6_P USB6_N

USB5_P USB5_N

USB4_P USB4_N

USB3_P USB3_N

USB2_P USB2_N

USB11_P USB11_N

USB10_P USB10_N

USB1_P USB1_N

USB0_P

USB_RBIAS_GND

USB_OC3*/GPIO_28/MGPIO

USB_OC2*/GPIO_27/MGPIO

USB_OC1*/GPIO_26

USB_OC0*/GPIO_25

SATA_TERMP

SATA_C1_RX_P

SATA_C1_RX_N

SATA_C0_TX_P SATA_C0_TX_N

SATA_C0_RX_P

SATA_C0_RX_N

SATA_B1_TX_P SATA_B1_TX_N

SATA_B1_RX_P

SATA_B1_RX_N

SATA_B0_TX_P SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_RX_N

SATA_A1_TX_P SATA_A1_TX_N

SATA_A1_RX_P

SATA_A1_RX_N

SATA_A0_TX_N

SATA_A0_RX_N

V3P3_PLL_USB

V1P1_SATA_DVDD1

V1P1_SATA_DVDD0

V1P1_SATA_AVDD1

V1P1_SATA_AVDD0

GND

SATA_A0_TX_P

SATA_C1_TX_N

SATA_C1_TX_P

SATA_LED*

V1P1_PLL_SATA

USB0_N

SATA_A0_RX_P

USB

SATA

(8 OF 11)

BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

19 mA (A01)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

External D

External A

Camera

Bluetooth

IR

External B

External C

Minimum 1.025V for Gen2 support

43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

Minimum 1.025V for Gen2 support

ExpressCard

20 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

L28

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AE16

A27

H21

J21

K21

L21

H25 J25

K25 L25

D27 E27

F27 G27

J26 J27

K27 L27

F29 G29

A28 B28

C28 D28

K23 L23

F25 G25

C29 D29

AE3

E12

AP3 AP2

AN2

AN3

AN1 AM1

AM3

AM2

AM4 AL3

AK3

AL4

AK2 AJ3

AJ1

AJ2

AJ11 AJ10

AK9

AJ9

AJ7 AJ6

AJ4

AJ5

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

U1400

2

1

R2050

2

1

R2051

2

1

R2052

2

1

R2053

2

1

R2060

2

1

R2010

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L

EXCARD_OC_L

PP3V3_S0_MCP_PLL_USB

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

SATA_HDD_D2R_P

USB_EXTA_N

PP1V05_S0_MCP_PLL_SATA

TP_MCP_SATALED_L

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

SATA_HDD_R2D_C_P

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RN TP_SATA_F_D2RP

MCP_SATA_TERMP

MCP_USB_RBIAS_GND

USB_EXTA_P

USB_MINI_N

USB_MINI_P

TP_USB_10P

USB_EXTD_N

USB_EXTD_P

USB_CAMERA_N

USB_CAMERA_P

USB_IR_N

USB_IR_P

USB_TPAD_P

USB_BT_N

USB_EXTB_P

USB_EXCARD_N

USB_EXCARD_P

USB_EXTC_N

USB_EXTC_P

SATA_ODD_D2R_N

TP_SATA_D_D2RN

USB_EXTB_N

USB_SDCARD_N

USB_SDCARD_P

TP_USB_10N

MCP SATA & USB

SYNC_MASTER=MASTER

SYNC_DATE=N/A

103 47

MCP7A

BGA

OMIT

102 45

402

1/16W MF-LF

5%

8.2K

5%

8.2K

1/16W

402

MF-LF

402

1/16W MF-LF

5%

8.2K

5%

8.2K

MF-LF

1/16W

402

806

MF-LF

1%

1/16W

402

MF-LF

1% 1/16W

402

2.49K

46 9

46

103 46

8

103 46

103 47

8

103 47

103 46

8

103 46

25

18 6

25

45

28

28 6

28

102

103

8

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

IN

OUT

IN

OUT

IN

EXT_SMI*/GPIO_32

V1P1_PLL_NV_H

A20GATE

BUF_SIO_CLK

CPU_DPRSLPVR

CPU_VLD

CPUVDD_EN

FANCTL0/GPIO_61

FANCTL1/GPIO_62

FANRPM0/GPIO_60

FANRPM1/GPIO_63

GPIO_1/PWRDN_OK/SPI_CS1 GPIO_12/SUS_STAT*/ACCLMTR_EXT_TRIG

HDA_BITCLK

HDA_RESET*

HDA_SDATA_IN0

GPIO_2/HDA_SDATA_IN1/PS2_KB_CLK

GPIO_3/HDA_SDATA_IN2/PS2_KB_DATA

HDA_SDATA_OUT

HDA_SYNC

INTRUDER*

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST*

KBRDRSTIN*

LID* LLB*

GPIO_13/MCP_VID0 GPIO_14/MCP_VID1 GPIO_15/MCP_VID2

V3P3_DUAL_HDA_0 V3P3_DUAL_HDA_1

V1P1_PLL_SP_SPREF

PKG_TEST

PS_PWRGD

PWRBTN*

PWRGD_SB

RSTBTN*

RTC_RST*

SIO_PME*

SLP_RMGT*

SLP_S3*

SMB_ALERT*/GPIO_64

SMB_CLK0

SMB_CLK1/MSMB_CLK

SMB_DATA0

SMB_DATA1/MSMB_DATA

GPIO_11/SPI_CLK

GPIO_10/SPI_CS0

GPIO_8/SPI_DI GPIO_9/SPI_DO

SPKR

SUS_CLK/GPIO_34

TEST_MODE_EN

THERM_DIODE_N

THERM_DIODE_P

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

SLP_S5*

GPIO_5/HDA_DOCK_RST*/PS2_MS_DATA

GPIO_4/HDA_DOCK_EN*/PS2_MS_CLK

HDA_PULLDN_COMP

HDA

MISC

(9 OF 11)

OUT

IN

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLK

SPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

SAFE mode: For ROMSIP recovery

USER mode: Normal

Connects to SMC for

(MXM_OK for MXM systems)

automatic recovery.

Int PU

NC

21 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

B19

B16

A19

A16

K16

J16

AE17

AE18

B11 C11

K22

B18

C13

F21

K19 G21

L19

M23

H17

G17 J17

C19

C20

D16

D20

C16

E20

L22

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15G15

K15

A15

E15

B14

C15

L17

K17

J15

J14

L24

M21

M20

L20

L26

D13

C14

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

2

1

R2140

2

1

R2143

1

2

R2154

2

1

R2151

2

1

R2155

2

1

R2156

2

1

R2157

2

1

R2141

2

1

R2142

2

1

R2147

2

1

C2172

2

1

C2170

2

1

C2173

2

1

C2171

2

1

R2150

2

1

R2110

21

R2172

2

1

R2181

2

1

R2180

2

1

R2160

2

1

R2163

21

R2173

21

R2171

21

R2170

2

1

R2190

2

1

R2120

2

1

R2121

MCP_PS_PWRGD

SMC_RUNTIME_SCI_L

PP1V05_S0_MCP_PLL_NV

TP_SB_A20GATE

MCP_CPUVDD_EN

ODD_PWR_EN_L

MEM_EVENT_L

SMC_IG_THROTTLE_L

=SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDIN0

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

HDA_SDOUT_R

HDA_SYNC_R

SM_INTRUDER_L

JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS

TP_MCP_KBDRSTIN_L

TP_MCP_LID_L PM_BATLOW_L

MCP_VID<0> MCP_VID<1>

=PP3V3R1V5_S0_MCP_HDA

PM_RSMRST_L

PM_SYSRST_DEBOUNCE_L

SMC_WAKE_SCI_L

PM_SLP_RMGT_L

PM_SLP_S3_L

SMBUS_MCP_0_CLK

SMBUS_MCP_1_CLK

SPI_CLK_R

SPI_CS0_R_L

SPI_MISO SPI_MOSI_R

MCP_SPKR

PM_CLK32K_SUSCLK_R

MCP_TEST_MODE_EN

MCP_THMDIODE_N

MCP_THMDIODE_P

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

PM_SLP_S4_L

AUD_I2C_INT_L

MCP_GPIO_4

MCP_HDA_PULLDN_COMP

AP_PWR_EN

AUD_I2C_INT_L

MCP_GPIO_4

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V3_G3_RTC

=PP3V3R1V5_S0_MCP_HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

ARB_DETECT

HDA_SYNC

MEM_EVENT_L SMC_IG_THROTTLE_L

=PP3V3_S0_MCP

TP_MCP_BUF_SIO_CLK

=PP3V3_S3_MCP_GPIO

MCP_CPU_VLD

PM_PWRBTN_L

MCP_VID<2>

MCP_VID<1>

MCP_VID<0>

=PP3V3_S0_MCP_GPIO

JTAG_MCP_TRST_L JTAG_MCP_TCK

ARB_DETECT

AP_PWR_EN

SMBUS_MCP_1_DATA

SMBUS_MCP_0_DATA

MCP_VID<2>

RTC_RST_L

MCP HDA & MISC

SYNC_MASTER=MASTER

SYNC_DATE=N/A

103 51

103 61 51

28

49

70

103 28

MCP7A

BGA

OMIT

50 21

50

10K

5%

MF-LF

1/16W

402

MF-LF 402

1/16W

5%

10K

1/16W MF-LF

5%

100K

402

MF-LF

5% 1/16W

100K

402

1/16W

22K

5%

MF-LF

22K

5%

MF-LF

1/16W

402

22K

5%

MF-LF

1/16W

402

1/16W MF-LF

5%

10K 10K

5% 1/16W

402

MF-LF

402

1/16W MF-LF

5%

100K

55 49 32 31 21

50 49

9 9

68 21

8

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

10PF

50V

5%

402

CERM

13

402

1/16W MF-LF

5%

10K

49.9

MF-LF

1/16W

1%

402

51

402

5%

22

1/16W MF-LF

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

MF-LF

8.2K

5% 1/16W

402

MF-LF 402

5%

10K

1/16W

5%

22

MF-LF

1/16W

402

MF-LF

5%

1/16W

402

22

MF-LF

402

5%

22

1/16W

49

103 9

402

MF-LF

1K

1% 1/16W

1%

49.9K

MF-LF

402

1/16W

MF-LF

1/16W

1%

402

49.9K

103 62

49

70

108 55

21

74 21

108 55

74 21

52

106 52 13

52

106 52 13

102 70

102 9

103 61 51

25

8

103 21

8

9

103 21

8

25 21 6

21

103

21

68 21

21

28 22

25 21 6

103 21

21

55 49 32 31 21

50 21

25 22 6

8

6

74 21

19 18 6

21

V1P0_CORE_VDD

V3P3

V3P3_DUAL_USB

V3P3_DUAL

V3P3_VBAT

V1P0_VDD_AUXC

V1P2_CPU_VTT

V1P2_CPUCLK_VTT

(10 OF 11)(11 OF 11)

GNDGND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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8 7 5 4 2 1

23065 mA (A01, 1.2V)

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

1182 mA (A01)

450 mA (A01)

22 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

AG32

AL31

AD32

AK32

AK31

W32

V32

AJ32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

AH32

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

AE32

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

AF32

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

P31

R32

V21

U21

T21

AC21

AA16

AC20

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AC19

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AC18

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AC17

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AC16

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AA28

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

AA27

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AA26

AA25

U1400

=PP1V05_S5_MCP_VDD_AUXC

PP3V3_G3_RTC

=PP3V3_S5_MCP

=PP3V3_S0_MCP

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

MCP Power & Ground

SYNC_MASTER=MASTER

SYNC_DATE=N/A

MCP7A

OMIT

BGA

OMIT

BGA

MCP7A

25 6

28 21

25 6

25 21 6

25 6 25 14 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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A

B

C

345678

D

B

8 7 5 4 2 1

23 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=MASTER

SYNC_DATE=N/A

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

24 OF 110

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BLANK PAGE

SYNC_DATE=12/08/2008

SYNC_MASTER=K51

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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8 7 5 4 2 1

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTIONPART#

TABLE_5_ITEM

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP SATA (DVDD) Power

NV: 1X 4.7UF 0402, 2X 1UF 0402, 2X 0.1UF 0402 (6.9UF)

84 mA (A01)

270 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

19 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

5 mA (A01)

87 mA (A01)

562 mA (A01)

84 mA (A01)

BALLS FOR AVDD0 SO 80% OF CAPACITANCE ON AVDD0

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

450 mA (A01)

57 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

83 mA (A01)

131 mA (A01)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

MCP 3.3V Ethernet Power

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

4771 mA (A01, DDR3)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 1.05V AUX Power

105 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

MCP PCIE (DVDD) Power

APPLE: 4X 4.7UF 0402, 4X 1UF 0402, 6X 0.1UF 0402 (23.4 UF)

MCP Core Power

DIFFERENT THAN ON T18

PEX_AVDD RAIL SPLIT BASED ON IG VS. EG. 12 OUT OF 15

PEX_DVDD RAIL SPLIT BASED ON IG VS. EG. 8 OUT OF 10

CAPACITANCE ON DVDD0

BALLS FOR DVDD0 SO 80% OF

Apple: 7x 2.2uF 0402 (15.4 uF)

43 mA (A01)

333 mA (A01)

MCP 1.05V RMGT Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

K50: 2X 2.2UF 0402, 2X 1UF 0402, (6.4 UF)

25 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C2597

2

1

C2528

2

1

C2529

2

1

C2596

2

1

C2587

2

1

C2585

2

1

C2583

2

1

C2581

2

1

C2518

2

1

C2521

2

1

R2591

2

1

C2591

2

1

R2590

21

L2595

2

1

C2595

2

1

C2590

2

1

C2589

2

1

C2560

2

1

C2525

2

1

C2526

21

L2580

2

1

C2501

2

1

C2500

21

L2555

21

L2586

21

L2588

21

L2584

21

L2582

21

L2575

21

L2570

2

1

C2580

2

1

C2564

2

1

C2562

2

1

C2540

2

1

C2541

2

1

C2542

2

1

C2543

2

1

C2544

2

1

C2545

2

1

C2546

2

1

C2547

2

1

C2548

2

1

C2549

2

1

C2550

2

1

C2551

2

1

C2552

2

1

C2553

2

1

C2575

2

1

C2576

2

1

C2573

2

1

C2574

2

1

C2570

2

1

C2520

2

1

C2571

2

1

C2572

2

1

C2515

2

1

C2516

2

1

C2517

2

1

C2530

2

1

C2531

2

1

C2532

2

1

C2533

2

1

C2534

2

1

C2535

2

1

C2536

2

1

C2512

2

1

C2513

2

1

C2508

2

1

C2509

2

1

C2510

2

1

C2511

2

1

C2504

2

1

C2505

2

1

C2506

2

1

C2507

2

1

C2502

2

1

C2555

2

1

C2586

2

1

C2584

2

1

C2588

2

1

C2582

2

1

C2503

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP

=PP1V05_S0_MCP_AVDD_UF

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

=PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PP1V05_S0_MCP_PEX_AVDD0

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP

=PP3V3R1V5_S0_MCP_HDA

MCP_MII_VREF

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_PLL_MAC

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_FSB

=PP1V05_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

=PPVCORE_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_PEX_DVDD0

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

MCP Standard Decoupling

C2574,C2518

2

IGRES,0,5%,0402116S0004

4.7UF

X5R 402

20%

4V

4.7UF

20%

402

X5R

20%

402

X5R

4V

4.7uF

10V

20%

402

0.1uF

CERM

4.7UF

X5R

4V

20%

402

4.7UF

4V X5R

20%

402

4.7UF

X5R

4V

20%

402

4.7UF

20% 4V X5R 402

20% 4V

4.7UF

402

X5R

MXM

402-LF

6.3V CERM

20%

2.2UF

0.1uF

20% 10V

402

CERM

18

402

1.47K

1/16W

1%

MF-LF

402

10V

20%

CERM

0.1UF

402

MF-LF

1%

1/16W

1.47K

0402

30-OHM-1.7A

402

X5R

4V

4.7UF

20%

402

20%

2.2UF

X5R

4V

4.7UF

402

20% 4V X5R

CERM 402-LF

20%

2.2UF

6.3V

402

10V

0.1uF

20% CERM

402

10V

0.1uF

20% CERM

30-OHM-1.7A

0402

402

X5R

20%

4.7UF

4V

4.7UF

402

X5R

20%

4V

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

30-OHM-5A

0603

30-OHM-5A

0603

4.7UF

20% X5R

402

4V

6.3V

2.2UF

20%

402-LF

CERM

20%

2.2UF

6.3V 402-LF

4V

402

X5R

4.7UF

20%

402

10V

20% CERM

0.1UF

402

CERM

10V

0.1UF

20%

0.1UF

CERM 402

10V

20%

402

10V CERM

20%

0.1UF

402

CERM

10V

20%

0.1UF 0.1UF

CERM 402

20% 10V

402

10V CERM

20%

0.1UF

402

10V CERM

20%

0.1UF

402

10V CERM

20%

0.1UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

6.3V

2.2UF

402-LF

20%

2.2UF

6.3V CERM CERM

402-LF

20%

6.3V

2.2UF

402-LF

2.2UF

CERM

20%

6.3V

2.2UF

6.3V

20%

402-LF

CERM

MXM

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

20%

402-LF

CERM

6.3V

MXM

20%

2.2UF

6.3V CERM 402-LF

X5R

4.7UF

4V

20%

402

MXM

6.3V

2.2UF

20%

402-LF

CERM

MXM

6.3V

20%

402-LF

CERM

2.2UF

20%

CERM

6.3V

MXM

402-LF

2.2UF

10V X5R 402-1

1UF

10%

X5R

MXM

10V

10%

1UF

402-1

6.3V

2.2UF

20%

402-LF

CERM

2.2UF

CERM

6.3V

20%

402-LF

CERM 402-LF

20%

2.2UF

6.3V 402-LF

CERM

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

6.3V CERM 402-LF

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

1UF

402-1

10% X5R

10V 10V

X5R 402-1

1UF

10%

4.7UF

402

X5R

20%

4V

CERM

20%

6.3V

2.2UF

402-LF

402

X5R

20%

4.7UF

4V

402

X5R

4V

20%

4.7UF

402

X5R

4V

4.7UF

20%

402

X5R

20%

4.7UF

4V

14

6 22 21 6

6

28

16

6

20

21

28 17

38 25 18 22 6

21 6

38 25 18

38 18

17

20

22 6

22 14 6

38 18

28 28

22 6

30 16 6

28 6 28 17

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

190 mA (A01, 1.8V)

95 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Apple: ???

16 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R2680

21

R2690

21

R2650

2

1

C2616

2

1

C2641

21

L2640

2

1

C2640

2

1

C2615

2

1

C2630

2

1

R2630

2

1

C2620

2

1

C2610

2

1

R2620

MCP_HDMI_VPROBE

MCP_HDMI_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_HDMI_VDD

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_VPLL

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_DAC

MAKE_BASE=TRUE

POWER_MCP_DAC

=PP3V3_S0_MCP_VPLL_UF

MCP_IFPAB_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD

MXM

C2641

1

RES,0,5%,402116S0004

1

116S0004 RES,0,5%,402

MXM

C2610

116S0004

1

RES,0,5%,402 C2616

MXM

SYNC_DATE=N/A

SYNC_MASTER=MASTER

MCP Graphics Support

CERM

20%

6.3V 402-LF

2.2UF

IG

MF-LF

1% 1/16W

402

1K

IG

1/16W MF-LF

5%

0

402

MF-LF

IG

0

402

5%

1/16W

1/16W MF-LF

5%

402

0

0.1UF

CERM

IG

20%

402

10V

IG

CERM

20% 10V

402

0.1uF

IG

0402

30-OHM-1.7A

4.7UF

20%

6.3V

IG

X5R-CERM

402

X5R 402

IG

4.7UF

20%

4V

402

CERM

10V

20%

0.1UF

NO STUFF

1%

1K

402

1/16W MF-LF

0.1UF

402

CERM

10V

20%

NO STUFF

107 18

6

18

102 18

18

6

102 18

18

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

27 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=12/08/2008

SYNC_MASTER=K51

BLANK PAGE

IN

OUT

NCNC

IN

OUT

IN

OUT

NCNC

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

10K pull-up to 3.3V S0 inside MCP

RTC Power Sources

Reset Button

Coin-Cell Holder

IMAC

PEG POWER ALIAS/OPTION TO GND UNUSED POWER PIN

UNPOWER PEG INTERFACE WHEN IG IS USED

DVDD DOES NOT NEED FILTER

AVDD IS FILTERED ON P25

UNPOWER PEG INTERFACE WHEN IG IS USED

SATA ALIAS/GROUNDING UNUSED DVDD1 AND AVDD1

PLACE AT LEAST 1 CAP NEAR MCP PIN A20

511S0054

fault protection for RTC battery.

NOTE: R2800 and D2800 form the double-

RTC Crystal

MCP 25MHz Crystal

28 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

Y2815

41

Y2810

21

R2882

21

R2880

2

1

R2898

2

1

C2899

21

R2899

2

1

R2816

21

R2815

21

C2816

21

C2815

2

1

C2801

2

1

C2802

1

2

J2800

2

5

3

6

4

1

D2800

21

R2896

2

1

R2811

21

R2810

21

C2811

21

C2810

12

R2800

2

1

C2800

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PPVBATT_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PPVBATT_G3_RTC_R

VOLTAGE=3.3V

PM_SYSRST_DEBOUNCE_L

=PP1V05_S0_MCP_SATA_DVDD0

PP3V3_G3_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PM_SYSRST_L

=PP3V3_S5_RTC_D

XDP_DBRESET_L

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

PP1V05_S0_MCP_PEX_DVDD0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE VOLTAGE=1.05V

=PP1V05_S0_MCP_PEX_DVDD1

PP1V05_S0_MCP_PEX_AVDD0

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_DVDD

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALIN

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

SYNC_DATE=N/A

SYNC_MASTER=MASTER

SB Misc

6.3V

1UF

10%

CERM

402

25.0000M

SM-3-LF

CRITICAL

32.768K-12.5PF

SM-HF

CRITICAL

5% 1/16W MF-LF

402

0

MXM

0

5%

402

1/16W MF-LF

MXM

SILK_PART=RESET_BTN

603

1/10W

NO STUFF

MF-LF

5%

0

49

NO STUFF

X5R

10%

1UF

10V

402

33

MF-LF

1/16W

402

5%

103 21

NO STUFF

10M

1/16W

402

MF-LF

5%

402

0

MF-LF

5%

1/16W

20PF

5%

402

CERM

50V

20PF

402

CERM

50V

5%

0.1UF

20%

402

CERM

10V

402

10V

0.1UF

20% CERM

103 21

SM

CRITICAL

BB10201-C1403-7H

BAT54DW-X-G

SOT-363

XDP

5%

1/16W

0

402

MF-LF

10M

1/16W MF-LF

402

5%

MF-LF

402

0

5%

1/16W

5%

402

CERM

12pF

50V

12pF

402

5%

50V

CERM

1/16W MF-LF

1K

402

5%

21 13 11

20 6

22 21 6

25 17

17

25 17

20

25

17

25

25 6

20

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

OUT

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Place close to J3200.1

PRODUCTION

- =I2C_VREFDACS_SCL

Signal aliases required by this page:

- =PPVTT_S3_DDR_BUF

Required zero ohm resistors when no VREF margining circuit stuffed

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

DAC channel A B A B C

ADDR=0x30(WR)/0x31(RD)

MEM B VREF DQ

Min DAC code 0x00 0x00 0x00 0x00 0x00 Max DAC code 0x87 0x87 0x87 0x87 0x55 Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

CPU FSB VREF

MEM B VREF CA

Power aliases required by this page:

Page Notes

MEM A VREF DQ MEM A VREF CA

(per DAC LSB)

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

BOM options provided by this page: VREFMRGN

10mA max load

PLACE CLOSE TO U1000

Place close to J3200.126

Place close to J3100.1

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

Place close to J3100.126

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

PLACE CLOSE TO U1000

ADDR=0x98(WR)/0x99(RD)

29 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

B4

B1

A4

A1

A2

A3

U2904

21

R2913

21

R2914

21

R2903

21

R2905

21

R2909

21

R2911

B4

B1

A4

A1

A2

A3

U2902

B4

B1

C4

C1

C2

C3

U2902

B4

B1

A4

A1

A2

A3

U2903

B4

B1

C4

C1

C2

C3

U2904

21

R2912

21

R2916

21

R2910

21

R2906

21

R2904

B4

B1

C4

C1

C2

C3

U2903

21

R2915

2

1

C2905

2

1

C2900

2

1

C2901

5

4

2

1

8

7

6

3

10

9

U2900

21

R2908

2

1

C2904

21

R2907

21

R2901

21

R2902

2

1

C2902

2

1

C2903

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2901

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CPUFSB_EN0

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

TP_PCA9557_P7

TP_PCA9557_P6

=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN1

VREFMRGN_CPUFSB_EN0

PCA9557D_RESET_L

VREFMRGN_CPUFSB1

=PPVTT_S3_DDR_BUF

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm

=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA

CPU_GTLREF0

VREFMRGN_CPUFSB_EN1

VREFMRGN_DQ_SODIMMA_EN

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMM

=PP3V3_S3_VREFMRGN

VREFMRGN_CPUFSB0

CPU_GTLREF1

VREFMRGN_CPUFSB_BUF1

VREFMRGN_CPUFSB_BUF0

CRITICAL

R2903

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

PRODUCTION

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

1

CRITICAL

R2905 PRODUCTION

RES,MTL FILM,0,5%,0402,SM,LF

R2909

116S0004 CRITICAL1PRODUCTION

VREFMRGN

RES,MTL FILM,200,1%,0402,SM,LF

114S0149

1

CRITICAL

R2911

1

114S0149

RES,MTL FILM,200,1%,0402,SM,LF

VREFMRGN

R2909

CRITICAL

RES,MTL FILM,0,5%,0402,SM,LF

R2911

116S0004

1

CRITICAL

PRODUCTION

CRITICAL

1

114S0149 VREFMRGN

R2905

RES,MTL FILM,200,1%,0402,SM,LF

CRITICAL

R2903

1

114S0149

RES,MTL FILM,200,1%,0402,SM,LF

VREFMRGN

FSB/DDR3 Vref Margining

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

100 11 10

0.1UF

20%

402

10V CERM

VREFMRGN

100K

VREFMRGN

MF-LF

402

5%

1/16W

20% CERM

402

10V

VREFMRGN

0.1UF

6.3V

2.2UF

CERM

20%

VREFMRGN

402-LF

10V

VREFMRGN

20% CERM

402

0.1UF

52

MSOP

VREFMRGN

DAC5574

52

9

402

100K

MF-LF

5%

1/16W

VREFMRGN

402

VREFMRGN

20%

0.1UF

10V CERM

QFN

PCA9557

VREFMRGN

1/16W MF-LF

402

5%

100K

VREFMRGN

5%

VREFMRGN

MF-LF

402

100K

1/16W

MF-LF

1/16W

100K

402

5%

VREFMRGN

MAX4253

VREFMRGN

UCSP

VREFMRGN

1/16W

100K

5%

402

MF-LF

FSB_VREFMRGN

1% 1/16W MF-LF

402

100

100 11 10

OMIT

402

MF-LF

1/16W

200

1%

OMIT

200

402

1/16W

1%

MF-LF

OMIT

402

1/16W

200

1%

MF-LF

200

OMIT

402

MF-LF

1/16W

1%

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

VREFMRGN

UCSP

MAX4253

VREFMRGN

0.1UF

20% 10V

402

CERM

MAX4253

VREFMRGN

UCSP

402

1/16W

VREFMRGN

1%

MF-LF

100

FSB_VREFMRGN

1/16W

1% MF-LF

402

100

VREFMRGN

100

1% 1/16W MF-LF

402

VREFMRGN

1/16W

100

1%

402

MF-LF

VREFMRGN

1% 1/16W

100

MF-LF

402

UCSP

MAX4253

VREFMRGN

29

32

29

6

31

29

31

29

6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

EXTRA DECOUPLING CAPS FOR MCP MEM RAIL

CAPS TO COUPLE PP5V_S3 UNDER DIMM CONNECTORS

DIMM B (CLOSER TO MCP)

CAPS TO COUPLE MCP 1V5_S0_MEM

DIMM A (FURTHER FROM MCP)

4771 mA (A01, DDR3)

DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR

DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

30 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C30A5

2

1

C30C0

2

1

C30C1

2

1

C30C2

2

1

C30C3

2

1

C30C4

2

1

C30C5

2

1

C30C6

2

1

C30C7

2

1

C30C8

2

1

C30C9

2

1

C30CA

2

1

C30CB

2

1

C30CC

2

1

C30CD

2

1

C30CE

2

1

C30CF

2

1

C30E0

2

1

C30E1

2

1

C30E2

2

1

C30E3

2

1

C30B0

2

1

C30B1

2

1

C30B2

2

1

C30B3

2

1

C30B4

2

1

C30D1

2

1

C30D2

2

1

C30B5

2

1

C30B6

2

1

C30B7

2

1

C30B8

2

1

C30B9

2

1

C30BA

2

1

C30BB

2

1

C30BC

2

1

C30BD

2

1

C30BE

2

1

C30BF

2

1

C30D0

2

1

C30D3

2

1

C30A0

2

1

C30A1

2

1

C30A2

2

1

C30A3

2

1

C30A4

2

1

C3002

2

1

C3001

2

1

C3000

2

1

C3099

2

1

C3098

2

1

C3040

2

1

C3043

2

1

C3045

2

1

C3047

2

1

C3048

2

1

C3049

2

1

C3090

2

1

C3091

2

1

C3092

2

1

C3093

2

1

C3094

2

1

C3095

2

1

C3096

2

1

C3097

2

1

C3070

2

1

C3071

2

1

C3072

2

1

C3073

2

1

C3074

2

1

C3075

2

1

C3076

2

1

C3077

2

1

C3078

2

1

C3079

2

1

C3080

2

1

C3081

2

1

C3082

2

1

C3083

2

1

C3084

2

1

C3085

2

1

C3050

2

1

C3051

2

1

C3052

2

1

C3053

2

1

C3054

2

1

C3055

2

1

C3056

2

1

C3057

2

1

C3058

2

1

C3059

2

1

C3060

2

1

C3061

2

1

C3062

2

1

C3063

2

1

C3064

2

1

C3065

2

1

C3010

2

1

C3019

2

1

C3018

2

1

C3017

2

1

C3016

2

1

C3035

2

1

C3034

2

1

C3033

2

1

C3032

2

1

C3031

2

1

C3030

2

1

C3014

2

1

C3023

2

1

C3022

2

1

C3021

2

1

C3020

2

1

C3029

2

1

C3028

2

1

C3027

2

1

C3026

2

1

C3025

2

1

C3041

2

1

C3042

2

1

C3044

2

1

C3046

=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

=PP1V8R1V5_S0_MCP_MEM

=PP5V_S3_DDRREG

SYNC_DATE=N/A

SYNC_MASTER=MASTER

MEMORY CAPS

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

10V CERM

0.1UF

20%20%

0.1UF

CERM

10V 402

0.1UF

10V CERM 402

20%20%

0.1UF

CERM

10V 402

CERM

20% 10V

402

0.1UF

402

20%

0.1UF

CERM

10V

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20%

402

10V CERM

0.1UF

20% 10V CERM 402

20%

0.1UF

402

10V CERM

0.1UF

20% 10V CERM

0.1UF

20%

402402

CERM

0.1UF

20% 10V

402

10V CERM

20%

0.1UF

402

10V CERM

20%

0.1UF0.1UF

402

20% 10V CERMCERM

20%

0.1UF

10V 402

0.1UF

402

10V

20% CERM

402

20% 10V CERM

0.1UF 0.1UF

402

10V CERM

20%

402

10V CERM

20%

0.1UF

402

CERM

10%

1UF

6.3V

402

CERM

6.3V

1UF

10%

402

10% CERM

6.3V

1UF

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402 402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V 6.3V

1UF

10% CERM

402

CERM

6.3V

1UF

10%

402

10% CERM

6.3V

1UF

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402 402

CERM

10%

1UF

6.3V 402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

1UF

10% CERM

402

CERM

1UF

6.3V

10%

402

CERM

10%

1UF

6.3V 6.3V 402

CERM

10%

1UF

402

CERM

10%

1UF

6.3V 6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

CERM

10%

1UF

6.3V

402

10% CERM

6.3V

1UF

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402 402

CERM

10%

1UF

6.3V

20%

6.3V X5R 603

10UF

603

10UF

6.3V X5R

20%

402

10% CERM

1UF

6.3V

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

603

20%

6.3V X5R

10UF

603

10UF

6.3V

X5R

20%

402

10% CERM

1UF

6.3V

10%

6.3V

1UF

CERM 402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

6.3V

1UF

10% CERM

402

30 25

16 6

30 25 16 6

108 31 6

108 32 6

30 25 16 6

75 30 6

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54 DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6 DQ7

VREFDQ VSS_1

VSS_3

DQ0 DQ1

DM0 VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30 DQ31

VSS_25

VDD_1

CKE1

A15 A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2 A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA SCL

DQ2 DQ3 VSS_6 DQ8 DQ9 VSS_8 DQS1* DQS1 VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2 VSS_17

DQS2*

VSS_14

VSS_21

DQ24 DQ25

DQ19 VSS_19

VSS_24

DQ27

DQ26

DM3 VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16 TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6* DQS6

VSS_40

DQ49

DQ50

VSS_45 DQ56 DQ57 VSS_47 DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9 VSS_8 DQS1* DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47 DM7

DQ58 DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6 VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26 DQ32 DQ33

TEST

VDD_16

S1*

A13

CAS* VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0 NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0 VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46 DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38 DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6 A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15 A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30 DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18 DQ19

DQ25

DQ24

DM3 VSS_22

DQ27 VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- ALL DQ, DQS, DM SIGNALS; TO FACILITATE BITSWAPS WITH ALIASES

- =I2C_SODIMMA_SCL

Page Notes

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

(NONE)

Power aliases required by this page:

Signal aliases required by this page:

DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD) DIMM2 SPD ADDR=0XA4(WR)/0XA5(RD)

DIMM 2

DIMM 0

31 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B

99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B 202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B 188B

169B 171B

152B 154B

135B 137B

62B 64B

45B 47B

27B 29B

10B 12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B 97B

78B 80B

119B

83B 84B

107B

98B

J3100

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A

99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A 202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A 188A

169A 171A

152A 154A

135A 137A

62A 64A

45A 47A

27A 29A

10A 12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A 97A

78A 80A

119A

83A 84A

107A

98A

J3100

2

1

R3143

2

1

R3142

2

1

C3140

2

1

R3140

2

1

R3141

2

1

C3150

2

1

C3151

2

1

C3135

2

1

C3136

2

1

C3130

2

1

C3131

=MEM_A_DQS_P<5>

=MEM_A_DM<4>

=MEM_A_DQ<58> =MEM_A_DQ<59>

MEM_DIMM0_SA<0> =PPSPD_S0_MEM_A

=MEM_A_DM<7>

=PP0V75_S0_MEM_VTT_A

=MEM_A_DQ<57>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<43>

=MEM_A_DQ<34>

MEM_A_A<10>

=PP1V5_S3_MEM_A

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<0>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

=MEM_A_DQ<51>

=MEM_A_DQ<56>

=I2C_SODIMMA_SCL

=MEM_A_DQ<50>

MEM_A_A<13> MEM_A_CS_L<1>

=MEM_A_DQ<32> =MEM_A_DQ<33>

=MEM_A_DQS_N<4>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1> MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<7>

MEM_A_A<11>

=MEM_A_DQ<3>

=MEM_A_DQ<9>

=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>

=MEM_A_DQ<26>

MEM_A_CKE<2>

MEM_A_BA<2>

MEM_A_A<9>

MEM_A_A<8>

=PP1V5_S3_MEM_A

=MEM_A_CLK_N<2>

MEM_A_A<10> MEM_A_BA<0>

MEM_DIMM2_SA<0>

=PP0V75_S0_MEM_VTT_A

MEM_DIMM2_SA<1>

=PPSPD_S0_MEM_A

=MEM_A_DM<7>

=MEM_A_DQ<58> =MEM_A_DQ<59>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<42>

=MEM_A_DM<5>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<32> =MEM_A_DQ<33>

MEM_A_CS_L<3>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

=MEM_A_CLK_P<2>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<12>

=MEM_A_DQ<11>

=MEM_A_DQ<16>

=MEM_A_DQ<10>

=MEM_A_DQ<8>

=MEM_A_DM<0>

=MEM_A_DQ<2>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<0> =MEM_A_DQ<1>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=PP0V75_S0_MEM_VTT_A

=MEM_A_DQ<63>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

MEM_EVENT_L

=MEM_A_DQ<62>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

=MEM_A_DQ<61>

=MEM_A_DQ<52>

=MEM_A_DQ<44>

=MEM_A_DQS_N<5>

=MEM_A_DQ<46> =MEM_A_DQ<47>

=MEM_A_DQ<45>

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

=MEM_A_DQ<37>

MEM_A_BA<1>

MEM_A_ODT<2>

=MEM_A_CLK_P<3>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<6> MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<15> MEM_A_A<14>

MEM_A_CKE<3>

=MEM_A_DM<1>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

MEM_RESET_L

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<21>

=MEM_A_DM<2>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQS_N<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DM<3>

=MEM_A_DQ<27>

=MEM_A_CLK_N<3>

MEM_A_RAS_L

MEM_A_CS_L<2>

MEM_A_ODT<3>

MEM_A_CAS_L

MEM_A_WE_L

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQS_P<0>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

MEM_RESET_L

=MEM_A_DQ<13>

=MEM_A_DM<1>

=MEM_A_DQ<21>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3>

=MEM_A_DQ<29>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_CLK_P<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_RAS_L

=MEM_A_CLK_N<1>

MEM_A_BA<1>

MEM_A_CS_L<0>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DM<4>

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DM<6>

MEM_EVENT_L

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=MEM_A_DQ<8>

=MEM_A_DQS_N<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<24>

=MEM_A_DQ<26>

=MEM_A_DM<3>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DM<5>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

MEM_A_A<12>

MEM_A_BA<2>

=PP0V75_S0_MEM_VTT_A

MEM_DIMM0_SA<1>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

=PPSPD_S0_MEM_AMEM_DIMM0_SA<1>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP0V75_S0_MEM_VTT_A

=PPSPD_S0_MEM_A

MEM_DIMM0_SA<0>

=MEM_A_DQS_P<1>

=MEM_A_DQ<16>

=MEM_A_DQ<25>

=MEM_A_DQ<27>

MEM_A_CKE<0>

=MEM_A_CLK_N<0>

MEM_A_BA<0>

=MEM_A_CLK_P<0>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<4>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQS_P<2>

MEM_A_A<5>

=MEM_A_DQS_P<3>

MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<6>

=MEM_A_DQ<5>

=MEM_A_DQ<12>

=MEM_A_DM<2>

=MEM_A_DQ<9>

=MEM_A_DQ<3>

=MEM_A_DQ<2>

=MEM_A_DM<0>

MEM_A_A<15>

=PP1V5_S3_MEM_A

MEM_A_CKE<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<17>

=MEM_A_DQ<38>

=MEM_A_DQ<43>

=MEM_A_DQ<48> =MEM_A_DQ<49>

=MEM_A_DQS_N<6>

=I2C_SODIMMA_SDA

=MEM_A_DQ<36>

=MEM_A_DM<6>

=MEM_A_DQ<39>

DDR3 SO-DIMMs 0 & 2

SYNC_DATE=N/A

SYNC_MASTER=MASTER

F-RT-TH

DDR3-SODIMM-DUAL

CRITICAL

F-RT-TH

DDR3-SODIMM-DUAL

CRITICAL

10K

402

5% 1/16W MF-LF

10K

5%

402

1/16W MF-LF

402-LF

6.3V CERM

20%

2.2UF

5%

10K

1/16W

402

MF-LF MF-LF

5%

402

10K

1/16W

6.3V

2.2UF

20%

402-LF

CERM CERM

402-LF

6.3V

2.2UF

20%

402-LF

20%

CERM

6.3V

2.2UF

10V

20%

0.1UF

402

CERM

2.2UF

20%

6.3V

402-LF 402

10V

0.1UF

20%

CERM

33

31

33

33 31

31

31 6

33 31

31 6

33 31

101 31 15

108 31 30 6

33 31

52 31

33 31

101 31 15

101 15

33 31

101 31 15

101 31 15 101 31 15

101 31 15

33 31

101 16

101 31 15

108 31 30 6

33

101 31 15

31

31 6

31

31 6

33 31

101 16

101 31 15

33

101 31 15

33 31

31 29

33 31

52 31

31 6

33 31

55 49 32 31 21

33 31

31

33 31

31 29

108 31 30 6

33 31

101 31 15

101 16

33

101 31 15

33 31

101 31 15

101 16

33 31

33 32 31

33 31

31

33 31

33

101 31 15

101 16

101 31 15

33 31

33 32 31

33 31

33

101 15

101 31 15

33

101 31 15

101 15

33 31

31 29

33 31

55 49 32 31 21

33 31

101 31 15

31 6

31

31 6 31

31 29

29

31 6

31

33 31

101 15

33

101 31 15

33

31 29

33 31

101 31 15

33 31

101 31 15

33 31

108 31 30 6

101 15

33 31

52 31

33

33 31

S1*

A13

VDD_14

CAS*

VDD_12

BA0

A10_AP

WE*

A3

DQ54 DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQS0*

DQ5

DQ4

DQ6 DQ7

VREFDQ VSS_1

VSS_3

DQ0 DQ1

DM0 VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

RESET*

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

DQS3*

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30 DQ31

VSS_25

VDD_1

CKE1

A15 A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2 A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

RAS*

VDD_11

CK1*

BA1

S0*

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

DQS5*

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*

VSS_51

DQ63

DQ62

VSS_49

SDA SCL

DQ2 DQ3 VSS_6 DQ8 DQ9 VSS_8 DQS1* DQS1 VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2 VSS_17

DQS2*

VSS_14

VSS_21

DQ24 DQ25

DQ19 VSS_19

VSS_24

DQ27

DQ26

DM3 VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

CK0*

DQ33

VSS_26

VDD_16 TEST

DQ32

DQ34

VSS_31

DQS4

DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6* DQS6

VSS_40

DQ49

DQ50

VSS_45 DQ56 DQ57 VSS_47 DM7

DQ58

VSS_48

DQ59

SA0

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ51

VTT_0

SA1

VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9 VSS_8 DQS1* DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP BA0

SA0

VTT_0

SA1

VDDSPD

VSS_50

VSS_47 DM7

DQ58 DQ59

DQ57

DQ56

VSS_45

DQ51

DQ50

DQS6 VSS_43

DQS6*

VSS_40

DQ49

DQ48

VSS_38

DQ43

DQ42

VSS_36

DM5

VSS_35

DQ41

DQ40

DQ35

DQ34

VSS_31

DQS4

DQS4*

VSS_28

VSS_26 DQ32 DQ33

TEST

VDD_16

S1*

A13

CAS* VDD_14

WE*

VDD_12

VDD_10

CK0

A1

A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0 NC_0

DQ11

DQ16

VSS_12

DQ10

DQ8

DM0 VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3

DQ1

VSS_1

SCL

SDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41

DQ53

DQ55

VSS_44

DQ54

VSS_42

DQ61

DQ52

DQ44

VSS_34

DQS5*

VSS_37

DQ46 DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCA

VDD_17

DQ37

DQ38 DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0

A2

A6 A4

A7

A11

VDD_9

VDD_7

VDD_5

VDD_3

A15 A14

CKE1

VDD_1

DM1

DQ15

DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13

DQ20

DQ12

DQ7

DQ6

DQ5

DQ4

VSS_7

DQS0*

VSS_2

VSS_0

DQS0

VSS_5

DQ21

VSS_15

DM2

VSS_16

DQ22

VSS_18

DQ23

DQ28

VSS_20

DQ29

DQS3

VSS_23

DQS3*

DQ30 DQ31

VSS_25

VSS_14

DQ17

DQS2*

VSS_17

DQS2

DQ18 DQ19

DQ25

DQ24

DM3 VSS_22

DQ27 VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =I2C_SODIMMB_SCL

Signal aliases required by this page:

TO FACILITATE BITSWAPS WITH ALIASES

- ALL DQ, DQS, DM SIGNALS;

(NONE)

Power aliases required by this page:

Page Notes

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMB_SDA

BOM options provided by this page:

DIMM1 SPD ADDR=0XA2(WR)/0XA3(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

DIMM 1

DIMM 3

32 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B

178B

173B

172B

168B167B

9B

162B161B

156B155B

151B

150B

145B

144B

139B

138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B

54B

49B

48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B

99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B 202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B 188B

169B 171B

152B 154B

135B 137B

62B 64B

45B 47B

27B 29B

10B 12B

23B

21B

18B

16B

194B

192B

182B

180B

6B

193B

191B

183B

181B

176B

174B

166B

164B

177B

175B

4B

165B

163B

160B

158B

148B

146B

159B

157B

149B

147B

17B

142B

140B

132B

130B

143B

141B

131B

129B

70B

68B

15B

58B

56B

69B

67B

59B

57B

52B

50B

42B

40B

7B

53B

51B

41B

39B

36B

34B

24B

22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B

102B

103B

101B

115B

79B

108B

109B

85B

89B

86B

90B

91B 92B

95B 96B 97B

78B 80B

119B

83B 84B

107B

98B

J3200

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A

178A

173A

172A

168A167A

9A

162A161A

156A155A

151A

150A

145A

144A

139A

138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A

54A

49A

48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A

99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A 202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A 188A

169A 171A

152A 154A

135A 137A

62A 64A

45A 47A

27A 29A

10A 12A

23A

21A

18A

16A

194A

192A

182A

180A

6A

193A

191A

183A

181A

176A

174A

166A

164A

177A

175A

4A

165A

163A

160A

158A

148A

146A

159A

157A

149A

147A

17A

142A

140A

132A

130A

143A

141A

131A

129A

70A

68A

15A

58A

56A

69A

67A

59A

57A

52A

50A

42A

40A

7A

53A

51A

41A

39A

36A

34A

24A

22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A

102A

103A

101A

115A

79A

108A

109A

85A

89A

86A

90A

91A 92A

95A 96A 97A

78A 80A

119A

83A 84A

107A

98A

J3200

2

1

R3241

2

1

R3240

2

1

C3240

2

1

R3242

2

1

R3243

2

1

C3250

2

1

C3251

2

1

C3235

2

1

C3236

2

1

C3230

2

1

C3231

=MEM_B_DQ<58> =MEM_B_DQ<59>

MEM_DIMM1_SA<0> =PPSPD_S0_MEM_B MEM_DIMM1_SA<1>

=MEM_B_DQ<51>

=MEM_B_DM<7>

=PP0V75_S0_MEM_VTT_B

MEM_B_A<5>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<7>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<8>

MEM_B_A<1>

=MEM_B_CLK_N<0>

=PP1V5_S3_MEM_B

MEM_B_A<10> MEM_B_BA<0>

=PP1V5_S3_MEM_B

=MEM_B_DQS_N<3>

=MEM_B_DQ<22>

=MEM_B_DQ<12> =MEM_B_DQ<13>

=MEM_B_CLK_P<3> =MEM_B_CLK_N<3>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_CS_L<2> MEM_B_ODT<2>

MEM_B_ODT<3>

=PP1V5_S3_MEM_B

MEM_B_A<0>

=MEM_B_DQ<3>

=MEM_B_DQ<9>

=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>

=MEM_B_DQ<26>

MEM_B_CKE<2>

MEM_B_BA<2>

MEM_B_A<9>

MEM_B_A<8>

=PP1V5_S3_MEM_B

=MEM_B_CLK_N<2>

MEM_B_A<10> MEM_B_BA<0>

MEM_DIMM3_SA<0>

=PP0V75_S0_MEM_VTT_B

MEM_DIMM3_SA<1>

=PPSPD_S0_MEM_B

=MEM_B_DM<7>

=MEM_B_DQ<58> =MEM_B_DQ<59>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<51>

=MEM_B_DQ<50>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DM<5>

=MEM_B_DQ<41>

=MEM_B_DQ<40>

=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

=MEM_B_DQ<32> =MEM_B_DQ<33>

MEM_B_CS_L<3>

MEM_B_A<13>

MEM_B_CAS_L

MEM_B_WE_L

=MEM_B_CLK_P<2>

MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<12>

=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQ<10>

=MEM_B_DQ<8>

=MEM_B_DM<0>

=MEM_B_DQ<2>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<0> =MEM_B_DQ<1>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=PP0V75_S0_MEM_VTT_B

=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

MEM_EVENT_L

=MEM_B_DQ<62>

=MEM_B_DM<6>

=MEM_B_DQ<60>

=MEM_B_DQ<53>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<44>

=MEM_B_DQS_N<5>

=MEM_B_DQ<46> =MEM_B_DQ<47>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DM<4>

=MEM_B_DQ<36>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

MEM_B_A<2>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<15> MEM_B_A<14>

MEM_B_CKE<3>

=MEM_B_DM<1>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

=MEM_B_DQ<13>

MEM_RESET_L

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQS_N<0> =MEM_B_DQS_P<0>

=MEM_B_DQ<21>

=MEM_B_DM<2>

=MEM_B_DQ<22> =MEM_B_DQ<23>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQ<17>

=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DM<3>

=MEM_B_DQ<27>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_CAS_L

MEM_B_A<3>

=MEM_B_DQ<54> =MEM_B_DQ<55>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<6> =MEM_B_DQ<7>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<0> =MEM_B_DQ<1>

=MEM_B_DM<0>

=MEM_B_DQ<20>

=MEM_B_DQ<15>

=MEM_B_DQ<14>

MEM_RESET_L

=MEM_B_DM<1>

=MEM_B_DQ<21>

=MEM_B_DQ<23>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_B_DM<2>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30> =MEM_B_DQ<31>

MEM_B_CKE<1>

MEM_B_A<11>

MEM_B_A<2> MEM_B_A<0>

=MEM_B_CLK_P<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_RAS_L

=MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_CS_L<0>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DM<4>

=MEM_B_DQ<47>

=MEM_B_DQ<44>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

=MEM_B_DQ<45>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<53>

=MEM_B_DM<6>

=PP0V75_S0_MEM_VTT_B

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

MEM_EVENT_L

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

=MEM_B_DQ<2> =MEM_B_DQ<3>

=MEM_B_DQ<8> =MEM_B_DQ<9>

=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>

=MEM_B_DQ<16>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<24>

=MEM_B_DQ<19>

=MEM_B_DQ<26>

=MEM_B_DM<3>

=MEM_B_CLK_P<0>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

=MEM_B_DQ<35>

=MEM_B_DQ<41>

=MEM_B_DQ<40>

=MEM_B_DM<5>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<48>

=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<56> =MEM_B_DQ<57>

MEM_DIMM3_SA<0>

MEM_DIMM3_SA<1>

=PPSPD_S0_MEM_B

MEM_DIMM1_SA<0>

MEM_DIMM1_SA<1>

=PPSPD_S0_MEM_B

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B

=PP0V75_S0_MEM_VTT_B

=PPSPD_S0_MEM_B

=MEM_B_DQ<25>

MEM_B_BA<2>

MEM_B_A<12> MEM_B_A<9>

MEM_B_CKE<0>

=MEM_B_DQ<27>

=MEM_B_DQ<32>

MEM_B_WE_L

DDR3 SO-DIMM CONNECTOR B

SYNC_MASTER=MASTER

SYNC_DATE=N/A

F-RT-TH

CRITICAL

DDR3-SODIMM-DUAL

F-RT-TH

CRITICAL

MF-LF

1/16W

5%

402

10K

MF-LF

1/16W

402

5%

10K

CERM 402-LF

6.3V

2.2UF

20%

5%

402

1/16W MF-LF

10K

MF-LF

1/16W

5%

402

10K

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

6.3V

402-LF

CERM

2.2UF

6.3V CERM

20%

402-LF

20%

0.1UF

CERM 402

10V

402-LF

6.3V

20%

2.2UF

CERM

402

CERM

10V

20%

0.1UF

33 32

32

32 6

32

33 32

32 6

101 32 15

33 32

101 32 15

33

108 32 30 6

101 32 15

108 32 30 6

33 32

33

101 32 15

101 16

108 32 30 6

101 32 15

33 32

101 16

101 32 15

108 32 30 6

33

101 32 15

32

32 6

32

32 6

33 32

101 16

101 32 15

33

101 32 15

33 32

32 29

33 32

52 32

32 6

33 32

55 49 32 31 21

33 32

32 29

33 32

101 32 15

33 32

101 32 15

101 16

33 32

33 32 31

33 32

101 15

101 32 15

33 32

32 29

33 32

33 32 31

33 32

101 15

101 32 15

33

101 15

101 32 15

33

101 32 15

101 15

33 32

32 29

33 32

32 6

33 32

55 49 32 31 21

33 32

52 32

33 32

33

33 32

32

32 6

32

32 6

32 29

32 6

33 32

101 32 15

101 15

33 32

101 32 15

IN

G

S

D

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP CHANNEL A DQS 7 -> DIMM A DQS 7

MCP CHANNEL A DQS 1 -> DIMM A DQS 1

MCP CHANNEL B DQS 7 -> DIMM B DQS 7

MCP CHANNEL B DQS 4 -> DIMM B DQS 4

MCP CHANNEL A DQS 6 -> DIMM A DQS 6

MCP CHANNEL A DQS 5 -> DIMM A DQS 5

MCP CHANNEL A DQS 4 -> DIMM A DQS 4

MCP CHANNEL A DQS 3 -> DIMM A DQS 3

MCP CHANNEL A DQS 2 -> DIMM A DQS 2

3.3V input must be stable before

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

DDR3 RESET Support

before 1.5V starts to rise to avoid glitch on MEM_RESET_L.

MCP CHANNEL B DQS 2 -> DIMM B DQS 2

MCP CHANNEL B DQS 1 -> DIMM B DQS 1

MCP CHANNEL A DQS 0 -> DIMM A DQS 0 MCP CHANNEL B DQS 0 -> DIMM B DQS 0

MCP CHANNEL B DQS 6 -> DIMM B DQS 6

MCP CHANNEL B DQS 5 -> DIMM B DQS 5

MCP CHANNEL B DQS 3 -> DIMM B DQS 3

MCP MEMORY CLOCK ALIASES

MCP MEMORY TEST POINT ALIASES

33 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

3

Q3306

2

3

1

Q3305

2

1

R3309

2

1

R3300

2

1

C3300

2

1

R3301

2

1

R3305

2

1

R3310

MEM_RESET_RC_L

MEM_B_CLK_P<1>

MAKE_BASE=TRUE

MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<5>

MAKE_BASE=TRUE

=MEM_A_DQ<4> =MEM_A_DQ<5> =MEM_A_DQ<3>

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MEM_A_DQ<59>

MAKE_BASE=TRUE

=MEM_A_DQ<61> =MEM_A_DQ<60>

=MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

=MEM_A_DQS_N<7>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<15>

=MEM_A_DQ<13>

MEM_A_DM<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MAKE_BASE=TRUE

MEM_A_DM<0>

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

=MEM_A_DQS_P<0>

=MEM_A_DQ<7>

=MEM_A_DQ<1>

=MEM_A_DQS_P<1> =MEM_A_DM<1>

=MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQ<0>

=MEM_A_DQ<6>

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQ<11>

MAKE_BASE=TRUE

=MEM_B_DQS_P<6>

MEM_B_DQ<55>

MAKE_BASE=TRUE

=MEM_A_DQS_P<5>

=MEM_A_DM<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<39> =MEM_A_DQ<38> =MEM_A_DQ<37>

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DM<6>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<52>

=MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<6>

=MEM_B_DQ<1>

=MEM_B_DQ<3> =MEM_B_DQ<2> =MEM_B_DQ<5>

=MEM_B_DQ<23>

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

=MEM_A_DQ<24>

=MEM_A_DQ<27>

=MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQ<50>

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<10>

=MEM_B_DQS_N<1>

=PP3V3_S5_MEMRESET

=MEM_A_DQ<23>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MAKE_BASE=TRUE

MEM_A_DQ<16>

=MEM_B_DM<3>

=MEM_B_DQ<30> =MEM_B_DQ<29>

=MEM_B_DQ<27>

=MEM_B_DQ<25>

=MEM_A_DM<2>

=MEM_A_DQ<21>

=MEM_A_DQS_P<3> =MEM_A_DM<3> =MEM_A_DQ<31>

=MEM_A_DQ<29> =MEM_A_DQ<28>

=MEM_A_DQS_P<4>

=MEM_B_DM<6>

MAKE_BASE=TRUE

MEM_B_DQ<49>

=MEM_A_DQS_N<5>

=MEM_A_DQ<32>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

=MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

=MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<30>

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DM<2>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<36> MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DM<6>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

=MEM_A_DQ<50>

=MEM_A_DM<7> =MEM_A_DQ<63>

MEM_A_DM<7>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<39>

=MEM_A_DQS_P<2>

MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<36>

MEM_B_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<37>

=MEM_B_DM<0>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQS_P<3> MEM_B_DM<3>

MAKE_BASE=TRUE

MEM_B_DM<0>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<48>

=MEM_A_DQS_N<6>

=MEM_B_DQ<57>

=MEM_B_DQ<58>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<62>

=MEM_B_DQ<63>

=MEM_B_DM<7>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

=MEM_B_DQ<48>

=MEM_B_DQ<53>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

=MEM_B_DQ<22>

=MEM_B_DQS_P<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<42>

=MEM_A_DQS_P<6> =MEM_A_DM<6> =MEM_A_DQ<55> =MEM_A_DQ<54> =MEM_A_DQ<53>

=MEM_A_DQ<62> =MEM_A_DQ<57> =MEM_A_DQ<56> =MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<31>

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<33>

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

=MEM_B_DQS_P<2> =MEM_B_DM<2>

=MEM_A_DQ<9>

=MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MEM_A_DQ<13>

MAKE_BASE=TRUE

MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<2>

=MEM_B_DQ<0>

=MEM_B_DQ<7> =MEM_B_DQ<6>

MEM_B_DQ<2>

MAKE_BASE=TRUE

=MEM_B_DQ<21>

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DM<4>

MAKE_BASE=TRUE

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DQS_N<3>

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<3>

=MEM_A_DQ<40>

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MAKE_BASE=TRUE

=MEM_A_DQS_P<7>

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DM<5>

MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<5>

MAKE_BASE=TRUE

=MEM_B_DQ<8>

=MEM_B_DQ<17> =MEM_B_DQ<16>

=MEM_B_DQ<26>

=MEM_B_DM<4>

=MEM_B_DQ<38>

=MEM_B_DQ<36> =MEM_B_DQ<35>

=MEM_B_DQ<33> =MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_B_DQ<40>

=MEM_A_DQ<41>

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQ<12>

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DM<1>

MAKE_BASE=TRUE

MEM_B_DQ<15> MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<8>

=MEM_A_DQ<11> =MEM_B_DQ<11>

=MEM_B_DQ<9>

=MEM_B_DQ<12>

=MEM_B_DQ<10>

=MEM_B_DQ<14> =MEM_B_DQ<13>

=MEM_B_DQ<15>

=MEM_B_DM<1>

MEM_B_DQS_P<1>

MAKE_BASE=TRUE

=MEM_A_DQ<20>

=MEM_A_DQ<22>

=MEM_B_DQ<20>

MEM_B_DQ<22>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DM<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

=MEM_A_DQ<12>

MEM_B_DQ<21>

MAKE_BASE=TRUE

=MEM_B_DQ<19> =MEM_B_DQ<18>

=MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<25>

=MEM_A_DQ<26> =MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQ<33>

=MEM_A_DM<5> =MEM_A_DQ<47>

=MEM_A_DQ<33>

=MEM_A_DQ<34>

=MEM_A_DQ<36> =MEM_A_DQ<35>

=MEM_B_DQ<52>

=MEM_B_DQ<49>

=MEM_B_DM<5>

=MEM_A_DQ<46>

=MEM_B_DQ<42> =MEM_B_DQ<41>

=MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<51>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<53>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

MEM_B_DQ<0>

MAKE_BASE=TRUE

=MEM_A_DQ<0>

=MEM_A_DQ<2>

MEM_A_DQ<3>

MAKE_BASE=TRUE

=MEM_A_DM<0>

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

=MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQ<30>

=MEM_B_DQS_N<6>

=MEM_B_DQ<40>

MAKE_BASE=TRUE

MEM_B_DQ<41>

MAKE_BASE=TRUE

MEM_B_DQ<42>

MEM_B_DQ<45>

MAKE_BASE=TRUE

=MEM_B_DQ<45>

=MEM_B_DQ<47> =MEM_B_DQ<46>

=MEM_B_DQS_N<5>

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MAKE_BASE=TRUE

MEM_B_DM<5>

MAKE_BASE=TRUE

MEM_B_DQ<47>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DQ<44>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<60>

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DM<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MEM_B_DQ<56>

MAKE_BASE=TRUE

=MEM_B_DQ<56>

=MEM_B_DQ<37>

=MEM_B_DQ<39>

=MEM_B_DQ<44>

=MEM_B_DQS_P<5>

=MEM_B_DQ<43>

=MEM_A_DQ<14>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<31>

=MEM_B_DQ<28>

=MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DM<4>

=MEM_A_CLK_P<0> =MEM_A_CLK_N<0>

MAKE_BASE=TRUE

MEM_A_CLK_N<0>

=MEM_A_CLK_P<1> =MEM_A_CLK_N<1>

MEM_A_CLK_N<3>

MAKE_BASE=TRUE

MEM_A_CLK_P<4>

MAKE_BASE=TRUE

=MEM_A_CLK_N<3>

=MEM_B_CLK_P<0>

MEM_B_CLK_P<0>

MAKE_BASE=TRUE

=MEM_B_CLK_N<0>

=MEM_B_CLK_N<1>

MEM_B_CLK_N<1>

MAKE_BASE=TRUE

=MEM_B_CLK_P<2>

MEM_B_CLK_P<3>

MAKE_BASE=TRUE

MEM_B_CLK_N<4>

MAKE_BASE=TRUE

MEM_A_DM<3>

=MEM_A_CLK_P<3>

=MEM_A_CLK_N<2>

=MEM_A_CLK_P<2>

MEM_A_CLK_N<1>

MAKE_BASE=TRUE

MEM_A_CLK_P<1>

MAKE_BASE=TRUE

MEM_A_CLK_P<0>

MEM_A_CLK_P<3>

MAKE_BASE=TRUE

=MEM_B_CLK_N<3>

MEM_B_A<15>

MAKE_BASE=TRUE

MEM_B_CLK_P<4>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

MEM_B_CLK_N<3>

MAKE_BASE=TRUE

MEM_A_A<15>

=MEM_B_CLK_P<3>

=MEM_B_CLK_N<2>

=MEM_B_CLK_P<1>

MAKE_BASE=TRUE

MEM_A_CLK_N<4>

MEM_B_CLK_N<0>

MAKE_BASE=TRUE

MCP_MEM_RESET_L

MEM_RESET

=PP1V5_S3_MEMRESET

MEM_RESET_L

SYNC_DATE=10/13/2008

SYNC_MASTER=K51

DDR3 SUPPORT AND BITSWAPS

402

MF-LF

1/16W

MEMRESET_HW

20K

5%

32 31

MF-LF

MEMRESET_HW

5%

402

20K

1/16W

SOT23-HF1

2N7002

MEMRESET_HW

SOT23

MMBT3904G

MEMRESET_HW

402

0

1/16W

5%

MF-LF

MEMRESET_MCP

16

MF-LF

402

1/16W

5%

10K

MEMRESET_HW

10V

MEMRESET_HW

0.1UF

20%

CERM 402

5% 1/16W MF-LF

1K

402

101 15

101 15 31

31

101 15

101 15 101 15

101 15

31

101 15 31

31

101 15

31

101 15

31

101 15

32

101 15

31

101 15

32

101 15

32

101 15

31

101 15

32

6

31

101 15

32

31

32

101 15

31

101 15

32

101 15

32

101 15

31

101 15

31

101 15

32

101 15

31

32

31

101 15

32

31

101 15

31

32

101 15

32

101 15

31

101 15

31

101 15

32

101 15

31

101 15

31 32

32

101 15

31

32

101 15

31

101 15

32

32 101 15

101 15

31

101 15

31

32

31

32

32 101 15 31

31

32

101 15

31

101 15

31

101 15

31

101 15

31

101 15

32

101 15

101 15 32

32

32 101 15

101 15

101 15 32

32

31

32

31

101 15

31

101 15

31

101 16

31

32

101 15

32

101 15

32

101 16

101 15

31

101 15

101 16

32

101 16

31

32

101 16

101 15

6

IN

OUT

IN

OUT

SYM_VER-1

IN

SYM_VER-2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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518S0731

34 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

4

3 2

1

L3440

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

J3400

4 3

21

L3430

21

L3400

21

C3430

21

C3431

2

1

C3402

2

1

C3401

2

1

C3400

PCIE_CLK100M_MINI_CON_N PCIE_CLK100M_MINI_CON_P

PCIE_MINI_R2D_L_P

PCIE_MINI_R2D_L_N

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_P

PCIE_MINI_R2D_N

PCIE_WAKE_L

MINI_CLKREQ_L

PP3V3_MINI

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MINI_RESET_L

PCIE_CLK100M_MINI_N

PCIE_MINI_D2R_N PCIE_MINI_D2R_P

=PP3V3_S3_MINI

PCIE_CLK100M_MINI_P

SYNC_DATE=N/A

SYNC_MASTER=MASTER

PCI-E Wireless Connector

12-OHM-100MA

TCM1210-4SM

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

F-ST-SM

20247-916E-01F

CRITICAL

102 17

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

90-OHM-100MA

DLP11S

FERR-120-OHM-1.5A

0402-LF

102 17

17

9

0.1uF

402

10%

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

X5R

16V

402

X5R

10% 16V

0.1uF

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

10uF

X5R

20%

6.3V 603

0.1uF

10V

CERM

20%

402

10V

0.1uF

402

20%

CERM

6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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35 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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36 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1 CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1] MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1

LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

IN IN IN IN

IN

IN BI

IN

BI

BI BI

OUT

OUT OUT OUT OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

Configuration Settings:

PHYAD = 01 (PHY Address 00001) AN[1:0] = 11 (Full auto-negotiation)

TXDLY = 0 (No TXCLK Delay)

RXDLY = 0 (RXCLK transitions with data)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect)

(19mA typ - Energy Detect)

(43mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

If internal switcher is not used, VDDREG and REGOUT can float.

per RealTek request.

Reserved for EMI

WF: Verify that ENET_RESET_L does not assert when WOL is active.

If false, ENET_RESET_L should be removed.

If true, RC and 0-ohm resistor should be removed.

37 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R3780

2

1

C3790

2

1

C3714

2

1

C3710

2

1

C3711

2

1

L3715

2

1

C3716

2

1

C3715

2

1

R3751

2

1

R3750

2

1

R3757

2

1

R3752

2

1

R3756

2

1

R3755

21

R3795

21

R3794

21

R3793

21

R3792

21

R3791

21

R3790

2

1

C3702

2

1

C3701

2

1

C3700

2

1

C3706

45

44

26

25

24

23

27

22

18

17

16

14

13

19

46

48

29

31

11 12

8 9

4 5

1 2

30

38

35

34

473320

7

3

39

372115

36

28

32

43

42

41

6

40

10

U3700

2

1

C3705

2

1

L3705

2

1

R3720

2

1

R3725

2

1

R3730

2

1

C3725

21

R3724

=PP3V3_ENET_PHY_VDDREG

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_PHYAVDD

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

ENET_TXD<1>

ENET_MDIO

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_CLK125M_TXCLK_R

=RTL8211_REGOUT

ENET_CLK125M_RXCLK_R

ENET_RXD_R<1>

ENET_RXD_R<3>

ENET_RXCTL_R

RTL8211_PHYAD1

ENET_TXD<2>

ENET_RX_CTRL

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

=PP1V05_ENET_PHY

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_P<3> ENET_MDI_N<3>

RTL8211_RXDLY

ENET_MDI_P<2> ENET_MDI_N<2>

=RTL8211_ENSWREG

ENET_MDC

ENET_RESET_L

RTL8211_CLK25M_CKXTAL1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_ENET_PHYAVDD

VOLTAGE=1.05V

RTL8211_PHYAD0

ENET_MDI_N<0>

ENET_MDI_P<0>

ENET_RXD_R<2>

ENET_RXD_R<0>

ENET_TXD<0>

TP_RTL8211_CLK125

TP_RTL8211_CKXTAL2

=PP3V3_ENET_PHY

RTL8211_RSET

RTL8211_PHYRST_L

ENET_TXD<3>

SYNC_MASTER=K51

Ethernet PHY (RTL8211CL)

SYNC_DATE=12/08/2008

104 18

1/16W

402

22

MF-LF

5%

NO STUFF

10PF

50V

CERM

5%

402

0.1UF

X5R 402

10% 16V

10%

402

X5R

16V

0.1UF

402

10% X5R

16V

0.1UF

CRITICAL

0402-LF

FERR-120-OHM-1.5A

10%

402

X5R

0.1UF

16V

10%

402

X5R

16V

0.1UF

402

1/16W

5%

4.7K

MF-LF

402

MF-LF

4.7K

5%

1/16W

5% MF-LF

4.7K

402

1/16W

4.7K

5%

402

MF-LF

38

1/16W

5%

MF-LF

4.7K

402

1/16W

5%

MF-LF

4.7K

402

104 18

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

22

5%

1/16W MF-LF

402

22

5%

1/16W MF-LF

402

22

1/16W5%MF-LF

104 39

104 38

18

104 18

10%

402

X5R

16V

0.1UF

10%

402

X5R

0.1UF

16V

10%

402

X5R

16V

0.1UF

402

X5R

0.1UF

10% 16V

TQFP

RTL8211CLGR

OMIT

CRITICAL

402

X5R

16V

0.1UF

10%

0402-LF

FERR-120-OHM-1.5A

CRITICAL

402

1/16W

5%

MF-LF

10K

MF-LF 402

4.7K

5% 1/16W

NOSTUFF

402

1/16W

1%

MF-LF

2.49K

402

0.1UF

CERM

20% 10V

NOSTUFF

402

MF-LF

5%

1/16W

100

38

104

38

104

38

IN

OUT

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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ENET ALIASES

NOTE: NOT USING THE BUILT-IN 1.05V REGULATOR OF THE PHY

RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

3.3V ENET FET

1.1V ENET FET

38 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

3

Q3850

2

1

3

Q3800

1

9

6

8

2

3

4

7

5

U3850

2

1

C3850

2

1

C3800

1

9

6

8

2

3

4

7

5

U3800

21

R3895

=RTL8211_ENSWREG

MCP_CLK25M_BUF0_R

=RTL8211_REGOUT

=PP3V3_ENET_PHY

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_PHY

=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_RMGT

=PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

NO_TEST=TRUE

NC_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

PP3V3_RMGT

MAKE_BASE=TRUE

PP1V1_RMGT

RTL8211_CLK25M_CKXTAL1

ENET_EN

MIN_NECK_WIDTH=0.1 MM NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=1.05V

PP1V1_RMGT

=PP12V_S5_PWRCTL

=PP1V1_S5_ENET_FET

NET_SPACING_TYPE=PWR

VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm

MAX_NECK_LENGTH=3 MM

MIN_LINE_WIDTH=0.5 mm

PP3V3_RMGT

=PP12V_S5_PWRCTL

=PP3V3_S5_ENET_FET

P1V1_ENET_EN

P3V3_ENET_EN

MAKE_BASE=TRUE

Ethernet Support

SYNC_MASTER=MASTER

SYNC_DATE=N/A

CRITICAL

SOT23

IRLML2502GPBF

SOT23

CRITICAL

70 38

TDFN

SLG5AP001

CRITICAL

402

10% 16V X5R

0.1UF

70 38

402

0.1UF

10% X5R

16V

TDFN

SLG5AP001

CRITICAL

104 37

1/16W MF-LF

5%

PLACEMENT_NOTE=Place close to U1400

22

402

104 18

37

25 18

37

25

25 18

37

38

78 70 38 6

6

38

78 70 38 6

6

MCT1

MX1+

MX1-

MCT2 MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

TD1+

TCT1

TCT2

TD1-

TD2+

TD2-

TD3+

TCT3

TD3-

TD4+

TCT4

TD4-

1CT:1CT

ENET_MDI

TRAN_P0 TRAN_N0 TRAN_P1 TRAN_P2 TRAN_N2 TRAN_N1 TRAN_P3 TRAN_N3

PINS

SHIELD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE INFORMATION CONTAINED HEREIN IS THE

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NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.

NOTE: BOB SMITH TERMINATION FOR EMC.

PLACE ONE CAP PER TCT PIN

514-0654

39 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

7

4

3

1

8

5 6

2

9

10

J3900

11

12

8

9

5

6

2

3

10

7

4

1

14

13

17

16

20

19

23

22

15

18

21

24

T3900

2

1

C3904

2

1

C3903

2

1

C3902

2

1

C3901

2

1

C3900

2

1

R3903

2

1

R3902

2

1

R3901

2

1

R3900

CRITICAL

LFE9287APF

ENET_MCT_BS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

ENET_MCT3

ENET_MDI_T_P<3>

ENET_MDI_N<1>

ENET_MDI_P<3>

ENET_MDI_N<0>

ENET_MDI_T_P<0>

ENET_MDI_P<0>

ENET_MDI_P<2>

ENET_MDI_N<3>

ENET_MCT2

ENET_MDI_T_N<3>

ENET_MDI_T_N<0>

ENET_TCT

ENET_MDI_N<2>

ENET_MDI_P<1>

ENET_MDI_T_N<2>

ENET_MCT0

ENET_MCT1

ENET_MDI_T_P<2>

ENET_MDI_T_N<1>

ENET_MDI_T_P<1> ENET_MDI_T_P<0>

ENET_MDI_T_N<0>

ENET_MDI_T_P<3>

ENET_MDI_T_P<1>

ENET_MDI_T_N<2> ENET_MDI_T_N<1>

ENET_MDI_T_N<3>

ENET_MDI_T_P<2>

ETHERNET CONNECTOR

SYNC_MASTER=MASTER

SYNC_DATE=N/A

RJ45-10/100TX-K22

F-ANG-TH

SOI

CERM

10V

0.1UF

20%

402

10V CERM

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

1206

1000PF

10%

NOSTUFF

2KV CERM

MF-LF 402

1/16W

5%

7575

1/16W MF-LF 402

5%

MF-LF

75

402

5% 1/16W

75

5% MF-LF

402

1/16W

104 39

104 37

104 39 104 37

104 37

104 37 104 39

104 39

104 37

104 39

104 39 104 39

104 39

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

40 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

OUT

TRI-ST/NC

VCC

GND

NC

NC NC

NC NC NC NC NC NC NC NC

NC

OUT

IN

OUT

IN

OUT

BI BI

IN

BI BI

BI

BI BI

IN

RSVD_19

LKON_DS2_P

XI

CNA CPS

PD

R1

R0

D6

D5

D4

D3

D2

D1

D0

CTL0 CTL1

LREQ_P

LREQ_L

LPS_P

LPS_L

PINT_P

PCLK_P

PINT_L

LCLK_P

LCLK_L

LINKON_L

DS1

DS0

PC2

PC0 PC1

PHY_RESET*

TPB2_N

TPB2_P

TPB1_N

TPB1_P

TPB0_N

TPB0_P

TPA2_N

TPA2_P

TPA1_N

TPA1_P

TPA0_N

TPA0_P

TPBIAS2

TPBIAS1

TPBIAS0

SE

TESTW_VREG_PD

SM

TESTM

BMODE

PLLGND

GND

DVDD_3_3

PLLVDD_3_3

VDDA_33

AVDD_3_3

VDD_15

VDDA_15

DVDD_CORE

VDD_15_COMB

VDD_33_COM_IO

VDD_33_COMB

VDD_33

PLLVDD_CORE

PCLK_L

VSSA_PCIE

VSSA

VSS

REF0_PCIE REF1_PCIE

PERST*

RXN

RXP

TXN

TXP

CLKREQ*

REFCLK_P REFCLK_M

REFCLK_SEL

SCL SDA

GPIO0

GPIO2

GPIO1

GPIO3 GPIO4 GPIO5

GPIO7

GPIO6

OHCI_PME*

GRST*

RSVD_1

RSVD_0

RSVD_3

RSVD_2

RSVD_4

RSVD_6

RSVD_5

RSVD_9

RSVD_7 RSVD_8

RSVD_10 RSVD_11

RSVD_14

RSVD_12 RSVD_13

RSVD_16 RSVD_17 RSVD_18

RSVD_15

D7

CYCLEOUT

PCI EXPRESS

1394B OHCI & PHY

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Strap DSx high on unused ports.

page assumes no more than

Alias =FWPHY_PC0

(JTAG_TCK)

(JTAG_TDI)

(JTAG_TDO)

(JTAG_TMS)

(IPU)

Ground TPBx_P/TPBx_N

PC[0:2] = ’100’

Multiple-ports:

Unused Ports:

TP/NC TPAx_P/TPAx_N

TP/NC TPBIASx

Single-port:

DS2 hard-strapped to 1,

2 FW800 connectors

PC[0:2] = ’000’

as appropriate

(VDD_33_AUX)

Power Aliases:

FWRS0_FWXIO nets are OHCI/PCIe power, and can be S0.

5K pull-down device detect circuit.

For single-port systems, all FW power should be tied together and powered by S0 or by the

FW_FWPHY nets are PHY power, and for multi-port systems must come from bus power.

(IPU)

(JTAG_TRST)

(Snoop Enable, for FireBug)

41 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R4189

2

1

R4135

2

1

C4190

4

13

2

Y4190

2

1

R4190

2

1

R4125

2

1

C4120

2

1

C4130

2

1

C4125

2

1

C4131

2

1

C4132

2

1

C4121

2

1

C4122

2

1

C4123

2

1

C4126

2

1

C4127

2

1

C4128

2

1

C4124

2

1

R4171

21

R4191

2

1

C4135

2

1

C4139

21

R4170

2

1

R4175

2

1

C4138

2

1

C4137

P4

C7C6C5

C4

B6

C10

F5

A7

A14

A10

C3

B5B7B9

B10

B11

C11

B12M5J10

H10

G10

E3

C12

B8P7M6

K10H3G3

A9 A8

E13

G13

K13

D14 E14

H14 J14

M14 N14

B14 C14

F14 G14

K14 L14

A6

B2

P14

P13

H12

J13

A4 A3

M12

M11

M8

L13

L12

K12

G12

F13

P3

D13

D12

P11

P10

N13

N12

N11

N10

M13

F12

E12

H13

A1 B1

A12

A13

M1

N1

M7

N7

N5

D3

D2

B4

B13

B3

F1

G1

A11

E8

E9

P8

E2

F2

C2

C1

D1

E1

H2

G2

C13

N6

P6

P5

N4

N3

P2

N2

P1

G8G7G6G5F9F8F7

K8K7K6

K5F6J8J7J6J5H9H8H7H6H5

G9

E7

E6

M9F3C9

K3J3C8

P9

N9

M3

M2

L3

L2

L1

K1

K2

J2

N8

J1

H1

P12

A2

J12

A5

M4

M10K9J9

F10

E10

U4100

2

1

R4186

2

1

R4185

2

1

C4189

2

1

C4105

2

1

C4104

2

1

C4103

2

1

C4108

2

1

C4115

2

1

C4107

2

1

C4106

2

1

C4114

2

1

C4113

2

1

C4102

2

1

C4101

2

1

C4100

2

1

C4112

2

1

C4111

2

1

C4110

2

1

R4110

2

1

R4117

2

1

R4119

2

1

C4119

2

1

C4118

2

1

R4140

2

1

C4117

2

1

R4141

21

C4140

21

C4141

2

1

R4152

2

1

R4151

21

C4145

21

C4146

2

1

R4150

2

1

R4153

2

1

R4160

2

1

R4180

1

2

R4182

2

1

R4181

42

TP_FWPHY_CNA

1UF

402

10%

CERM

MF-LF

1K

5%

402

1/16W

CERM

6.3V

402

10%

1UF

402

1UF

CERM

6.3V

10%

6.3V

402

1UF

CERM

402

1

MF-LF

1/16W

5%

4.7

MF-LF

5% 1/16W

402

98P3040MHZ

SM

10%

6.3V

CERM-X5R

402

0.22UF

1

5%

MF-LF

1/16W

402

5%

402

MF-LF

1K

1/16W

NO STUFF

MF-LF

1/16W

402

5%

47K

NO STUFF

1/16W

402

5%

1K

MF-LF

42

1K

5%

402

1/16W MF-LF

PLACEMENT_NOTE=Place C4146 next to C4145

16V10% 402X5R

0.1uF

PLACEMENT_NOTE=Place C4145 close to UA200

16V10% 402X5R

0.1uF

402

5%

MF-LF

1/16W

1K

1/16W

5%

402

MF-LF

220

1/16W

5%

402

MF-LF

220

PLACEMENT_NOTE=Place C4141 next to C4140

0.1uF

16V10% 402X5R

PLACEMENT_NOTE=Place C4140 close to U1400

16V10% 402X5R

0.1uF

MF-LF 402

1/16W

1%

232

1UF

402

CERM

6.3V

10%

17 102

42

MF-LF

1/16W

402

5%

1K

9

14.3K

1% 1/16W MF-LF

402

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

MF-LF

1

5%

1/16W

402

1

5%

MF-LF

1/16W

402

MF-LF

1

5% 1/16W

402

1UF

402

CERM

10%

6.3V

1UF

CERM

6.3V

10%

402

17 102

6.3V

1UF

402

CERM

10%

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

1UF

402

6.3V

10%

1UF

402

CERM

6.3V

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

17 102

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

42

17 102

42

10%

0.22UF

6.3V CERM-X5R 402

17 102

1%

6.34K

402

1/16W MF-LF

5%

MF-LF

1/16W

402

390K

CRITICAL

OMIT

BGA

XIO2213B

402

6.3V CERM

10%

CERM

1UF

402

10%

6.3V

MF-LF

10K

5% 1/16W

402

42

402

5%

MF-LF

1/16W

1K

42

1UF

402

CERM

6.3V

10%

1UF

402

CERM

6.3V

10%

1/16W

402

5%

MF-LF

22

470

402

5% 1/16W MF-LF

1UF

10%

6.3V CERM

402

10%

6.3V

1UF

CERM

10%

1UF

6.3V CERM

402

6.3V CERM

10%

402

1UF

CERM

402

6.3V

1UF

10%

6.3V

1UF

CERM

402

10%

6.3V

10%

1UF

402

CERM

1UF

402

10%

6.3V 6.3V

10%

1UF

402

CERM

FireWire LLC/PHY (XIO2213B)

SYNC_MASTER=MASTER

SYNC_DATE=N/A

FWOHCI_LREQ

CLK98M_FW_XI

TP_FWXIO_JTAG_TDO

TP_FWXIO_JTAG_TMS

TP_FWXIO_GRST_L

FW_RESET_L

FWXIO_REFCLK_SEL

FWXIO_SDA

FWXIO_SCL

FW_P1_TPBIAS FW_P2_TPBIAS

FW_P2_TPA_N

FW_P2_TPA_P

FW_P1_TPA_P

FW_P0_TPB_P

=PPVP_FW_PHY_CPS

FW_P0_TPA_P

FWXIO_REF1_PCIE

FWXIO_REF_PCIE

PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N

TP_FWOHCI_XO

=FWPHY_DS1

=FWPHY_DS0

FWXIO_REF0_PCIE

FW_P0_TPBIAS

FW_P0_TPA_N

FW_P1_TPA_N

=FW_CLKREQ_L

PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N

=FW_PME_L

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

FWXIO_CYCLEOUT

CLK98M_FW_XI_R

FWPHY_LKON_DS2

=PP3V3_FW_FWPHY

=FWPHY_PC0

FWOHCI_LINKON_L

FWOHCI_LPS

FWPHY_PINT

FWOHCI_CLK98M_LCLK

FWPHY_CLK98M_PCLK

FWPHY_R1

FWPHY_R0

FWPHY_RESET_L

FWPHY_CPS

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_FW_PLLVDD

MIN_LINE_WIDTH=0.3 mm

=PP3V3_FWRS0_FWXIO

VOLTAGE=1.96V

PP1V96_FW_XTAL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PCIE_FW_R2D_N

PCIE_FW_R2D_P

VOLTAGE=3.3V

PP3V3_FW_AVDD

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

PP3V3_FW_VDDA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP1V95_FW_FWPHY

FWXIO_VDD33COMIO

FWXIO_VDD33COMB

FWXIO_VDD15COMB

=PP3V3_FW_FWPHY

PP1V96_FW_PLLVDD

MIN_LINE_WIDTH=0.3 mm VOLTAGE=1.96V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP1V5_FW_VDDA

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

=PP1V5_FWRS0_FWXIO

FW_P0_TPB_N

FWXIO_SNOOP_EN

TP_FWXIO_JTAG_TDI

FWPHY_TESTM

FWPHY_BMODE

=PP3V3_FW_FWPHY

FWPHY_TESTW

42

102

6 41 42 43

6

102

42

6 41 42 43

6

6 41 42 43

OUT

IN

NR

NC

THRML

EN

GND

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Peak Current: 100mA

FireWire Aliases For Connectivity

1394 PHY STRAPPING OPTIONS

IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.

2ND & 3RD TPA/TPB PAIR UNUSED

Place close to FireWire PHY

Termination

iMacs are now one port only and have Power Code "000"

THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT

TI PHY requires 1UF, not 0.33uF spec value.

TI PHY "Peaking Inductors" To improve Data Eye.

1394 PHY 1.95V SUPPLY

42 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

L4251

21

L4250

21

L4253

21

L4252

2

1

C4200

2

1

C4201

2

1

C4202

7

1 2

5

6

3

4

U4200

2

1

R4257

2

1

R4258

2

1

C4254

2

1

R4254

2

1

R4252

2

1

R4253

2

1

R4250

2

1

R4251

2

1

C4250

2

1

R4256

2

1

R4255

402

0.01UF

=PP3V3_FW_FWPHY

MAKE_BASE=TRUE

CRITICAL

FW_P2_TPA_P

FW_P2_TPBIAS

MAKE_BASE=TRUE

FW_CLKREQ_L

MAKE_BASE=TRUE

FW_PORT0_TPB_P

FW_P0_TPB_P

MAKE_BASE=TRUE

FW_PORT0_TPB_N

MAKE_BASE=TRUE

FW_PORT0_TPA_N

FW_P0_TPA_C

MAKE_BASE=TRUE

FW_PHY_DS1

FW_PHY_DS0

P1V95_FW_NR

FW_P2_TPA_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW_PORT2_TPA_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW_PORT2_TPA_P

NO_TEST=TRUE

NC_FW_PORT2_TPBIAS

MAKE_BASE=TRUE

FW_P1_TPA_N

NC_FW_PORT1_TPA_N

MAKE_BASE=TRUE

NO_TEST=TRUE

FW_P1_TPA_P

NC_FW_PORT1_TPA_P

MAKE_BASE=TRUE

NO_TEST=TRUE

FW_P1_TPBIAS

NC_FW_PORT1_TPBIAS

MAKE_BASE=TRUE

NO_TEST=TRUE

=FW_CLKREQ_L

=FWPHY_PC0 FW_PHY_PC0

MAKE_BASE=TRUE

=FWPHY_DS1

=FWPHY_DS0

=PP3V3_FW_FWPHY

=FW_PME_L

FW_PME_L

MAKE_BASE=TRUE

PPVP_FW_PHY_CPS

=PPVP_FW_PHY_CPS

MAKE_BASE=TRUE

FW_PORT0_TPA_P

VOLTAGE=1.86V

MIN_NECK_WIDTH=0.08MM

FW_P0_TPBIAS

MIN_LINE_WIDTH=0.1MM

FW_P0_TPA_P FW_P0_TPA_N

FW_P0_TPB_N

VOLTAGE=0V NO_TEST=TRUE

FW_P0_TPB_L_N

FW_P0_TPA_L_N

VOLTAGE=1.86V NO_TEST=TRUE

FW_P0_TPB_L_P

VOLTAGE=0V NO_TEST=TRUE

FW_P0_TPA_L_P

VOLTAGE=1.86V NO_TEST=TRUE

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=1.95V

PP1V95_FW_FWPHY

SYNC_DATE=N/A

SYNC_MASTER=MASTER

FW: 1394B MISC

18NH-250MA

0402

18NH-250MA

0402

18NH-250MA

0402

18NH-250MA

6.3V CERM

1UF

10%

402

16V

CERM

10%

402

4V

20%

2.2UF

X5R

SON

TPS799195

1/16W

5% MF-LF

402

10K

1/16W

5% MF-LF

402

10K

25V

5%

CERM

220PF

402

4.99K

1% 1/16W MF-LF

1/16W

402

MF-LF

1%

56.2

MF-LF 402

1/16W

1%

56.2

1/16W

402

MF-LF

1%

56.2

1/16W

1%

402

MF-LF

402

10%

6.3V

1UF

CERM

402

MF-LF

1/16W

5%

10K

402

MF-LF

NOSTUFF

5% 1/16W

10K

41

17

105 43

41

105 43

41

43 42 41 6

41

43 42 41 6

41 19

43 41

105 43

41

105

41

GND

V+

SHIELD

PINS

VG

TPA-

TPA(R)

TPB-

TPB(R)

TPB+ VP

TPA+

SC/NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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DRAWING NUMBER SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

7 WATTS MAX PER PORT

POUR COPPER TO SINK HEAT

"Snapback" & "Late VG" Protection

IT IS HERE FOR SAFETY ONLY

THIS FUSE WILL NOT BLOW

FAST NON-RESETABLE FUSE

SHOULD BE DONE AS A POWER STRIP(SUBPLANE)

1394B

5.1V NC

PLACE CLOSE TO COMPARATOR

ESD Rail

IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP

CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V

[ LATE VG NOTES ]

514-0656

PORT 0

12 VOLTS

5.1V

PLACE CLOSE TO COMPARITOR

INRUSH RESETABLE PTC

43 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

8

6

9 2

1

5 4

3

7

11

10

J4300

21

XW4300

21

F4300

21

R4305

3 1

D4303

2

1

C4305

2

1

R4306

21

R4304

8

1

7

3

5

2

6

4

U4300

2

1

C4304

31

D4302

2

3

1

Q4302

2

1

R4301

2

1

C4302

2

1

R4307

2

1

R4302

2

1

R4303

21

D4300

21

R4352

2

3

1

Q4301

21

R4300

4

3

6521

Q4300

21

F4301

3

1

D4301

2

1

C4300

2

1

R4335

2

1

C4335

2

1

C4332

21

L4300

2

1

C4311

2

1

C4310

2

1

C4313

2

1

C4312

21

R4390

31

D4390

6

2

1

DP4311

6

2

1

DP4310

3

5

4

DP4311

3

5

4

DP4310

5%

0.33

MF

1W

2512

MIN_LINE_WIDTH=1.7MM

P12V_S5_FW_R=PP12V_S5_FW

MIN_NECK_WIDTH=0.5MM

P12V_S5_FW_D

MIN_LINE_WIDTH=1.7MM

VOLTAGE=12V

FW_PORT0_VP

MIN_NECK_WIDTH=0.5MM VOLTAGE=12V

MIN_LINE_WIDTH=1.7MM

FW_PORT0_VP_F

MIN_NECK_WIDTH=0.5MM

MIN_LINE_WIDTH=1.7MM

VOLTAGE=12V

FW_CURRENT_LIMIT

=PP12V_S5_FW

FW_CURRENT_LIMIT

PP3V3_FW_ESD

FW_FET_LINEAR_LIMIT_OUT

FW_FET_LINEAR_LIMIT_IN

FW_CURRENT_LIMIT_R

PP3V3_FW_ESD

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=3.3V

=PP3V3_FW_FWPHY

FW_FET_LINEAR_LIMIT_FB

FW_CURRENT_LIMIT_RD

FW_PORT0_TPA_N

FW_PORT0_TPA_P

FW_PORT0_TPA_R

FW_PORT0_TPB_P

FW_PORT0_TPB_N

FW_FET_LINEAR_LIMIT_IN

FW_FET_LINEAR_LIMIT_OUT

FW_CURRENT_LIMIT_Q

FW_TURN_ON_V

P12V_S5_FW_CL

MIN_LINE_WIDTH=1.7MM MIN_NECK_WIDTH=0.5MM VOLTAGE=12V

PPVP_FW_PHY_CPS

VOLTAGE=12V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=12V

MIN_NECK_WIDTH=0.5MM

PP3V3_FW_ESD

SYNC_DATE=N/A

SYNC_MASTER=MASTER

FIREWIRE CONNECTOR

F-ANG-TH

CRITICAL

1394B-K22

SM

PLACEMENT_NOTE=PLACE CLOSE TO F4300

3AMP-32V

603

CRITICAL

100K

1/16W

402

MF-LF

5%

SOT23

MMBZ5231BXG

16V X5R

10%

2.2UF

603

200K

1/16W MF-LF

5%

402

MF-LF

1/16W

5%

100K

SOI-HF

LM393

10% 16V

402

0.1UF

X7R-CERM

BAS40XG

SOT23

MMBT2222A7F

5% 1/16W

10K

MF-LF 402

20%

CERM

402

16V

0.01UF

402

MF-LF

1/16W

5%

20K

603

1/10W

5% MF-LF

15K

MF-LF

1/16W 402

5%

20K

SM

CRITICAL

CRS08-1.5A-30V

MF-LF

1%

1/16W

51.1K

402

SOT23

60V-600MA

MMBT2907AXG

SSOT6

FDC610PZ

CRITICAL

0.3AMP-60V

CRITICAL

SMD030F-SM

MMBZ5231BXG

SOT23

10% 50V X7R

0.01UF

603-1

402

1%

MF-LF

1/16W

1M

603-1

0.1UF

10% 50V X7R

10%

402

0.001UF

CERM

50V

SM

CRITICAL

FERR-250-OHM

0.01UF

50V 402

10% X7R

402

0.01UF

50V

10% X7R

X7R

0.01UF

50V 402

10%

X7R 402

50V

10%

0.01UF

1/16W MF-LF

1%

402

332

MMBZ5227BLT1H

SOT23

CRITICAL

BAV99DW-X-G

SOT-363

BAV99DW-X-G

CRITICAL

SOT-363

BAV99DW-X-G

CRITICAL

SOT-363

CRITICAL

SOT-363

BAV99DW-X-G

NOSTUFF

43 6

43

43 6

43

43 42 41 6

105 42

43

42

43

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

44 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=10/13/2008

SYNC_MASTER=K51

BLANK PAGE

OUT

KEY

GND

MD

+5V

DP

BB+

GND

A-

A+

GND

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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A

B

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345678

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8 7 5 4 2 1

518-0361

SATA PORT A1 FOR SLIMLINE ODD

SATA PORT A0 FOR HDD

518S0251

SATA Activity LED

45 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

P3

P2

P4

15

14

S7

S4

S1

P6

P5

P1

S6

S5

S2 S3

J4520

7

6

5

4

3

2

1

J4510

2

1

R4530

2

1

C4531

2

1

C4530

21

C4519

21

C4520

21

C4517

21

C4518

2

1

DS4599

2

1

R4599

21

C4516

21

C4515

21

C4511

21

C4510

SATA_ODD_R2D_P

SATA_ODD_R2D_N

SATA_ODD_D2R_C_N

=PP5V_S0_SATA

SMC_ODD_DETECT

SATA_ODD_D2R_C_P

SATA_HDD_R2D_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

MCP_SATALED_L

MAKE_BASE=TRUE

TP_MCP_SATALED_L

SATA_HDD_D2R_N

SMC_EXCARD_OC_L

=PP3V3_S0_SATALED

MCP_SATALED_R_L

SATA_ODD_R2D_C_P

=PP3V3_S0_ODD

SATA_ODD_D2R_P

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_P

SATA_ODD_R2D_C_N

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SATA Connectors

102 20

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

SILK_PART=SATA ACTIVE

DEVELOPMENT

1/10W

5%

330

603

MF-LF

102 20

0.01UF

CERM

40210% 16V

40210%

CERM

16V

0.01UF

CERM

402

0.01UF

16V10%

CERM

40210% 16V

0.01UF

M-ST-TH

1735574

EP00-081-91

M-ST-SM

CRITICAL

603

MF-LF

1/10W

5%

33K

0.1UF

402

10% 25V X5RX5R

402

25V

10%

0.1UF

10%

0.01UF

402

CERM

16V

0.01UF

10% 402

CERM

16V

10%

0.01UF

402

CERM

16V

10% 402

CERM

0.01UF

16V

102 20

110 102

6

110 49

110 102

20

50 49

6

110 102

EN1*

OC1*

IN

OUT1

GND

TPAD

OUT2

OC2*

EN2*

G

S

D

EN1*

OC1*

IN

OUT1

GND

TPAD

OUT2

OC2*

EN2*

IOIONC

GND

VBUS

NC

SYM_VER-1

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

VBUS DATA-

GND

DATA+

VBUS DATA-

GND

DATA+

VBUS

DATA-

GND

DATA+

VBUS DATA-

GND

DATA+

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

514-0659

514-0672

(PUT CAP ON CONNECTOR SIDE)

SEL=0: CHOOSE SMC

PORT 3

D+

USB/SMC DEBUG MUX

D+ GND

D-

VDD

PORT 2

D+

D-

VDD

VDD DD+ GND

GND

VDD D-

PORT 0

GND

(PUT CAP ON CONNECTOR SIDE)

SEL=1: CHOOSE USB

(PUT CAP ON CONNECTOR SIDE)

PORT 1

46 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

1

6

5

4

3

2

J4620

1

6

5

4

3

2

J4630

1

6

5

4

3

2

J4610

1

6

5

4

3

2

J4600

1 2

9

10

8

5 4

3

7 6

U4650

4 3

21

L4631

4 3

21

L4621

4 3

21

L4611

4 3

21

L4601

2

1

C4600

2

1

C4610

2

1

C4620

2

1

C4606

2

1

C4621

21

L4630

6

32 45

1

D4630

2

1

C4630

2

1

C4631

9

6

7

5

8

2

1

4

3

U4601

2

1

C4611

2

1

C4603

2

1

C4601

2

1

C4605

2

1

R4600

2

1

3

Q4600

2

1

C4602

9

6

7

5

8

2

1

4

3

U4600

21

R4652

21

R4651

2

1

C4650

6

32 45

1

D4600

6

32 45

1

D4610

6

32 45

1

D4620

21

L4600

21

L4610

21

L4620

K22

CRITICALC4606

150UF, TANY-POLY BULK CAP

1

128S0225

K23

CRITICALC4602

330UF, TANT-POLY BULK CAP

1

128S0238

OMIT

6.3V

330UF

CRITICAL

20%

CASE-D3L-SM1

POLY-TANT

0.1UF

USB_EXTD_OC_L

USB_EXTC_OC_L

=PP5V_S3_USB

USB_D_MUXED_P

USB_D_MUXED_N

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_USB2_PORT2

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5V_USB2_PORT3

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

=PP3V3_S5_SMCUSBMUX

USB_EXTC_P

PP5V_USB2_PORT0 MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V MIN_NECK_WIDTH=0.2MM

USB_EXTC_N

USB_EXTB_N

USB_EXTB_P

USB_EXTA_N

USB_EXTA_P

PM_EN_USB_PWR

USB_EXTA_OC_L

USB_EXTB_OC_L

PP5V_USB2_PORT1

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

USB_EXTD_P

USB_DEBUGPRT_EN_L

=PP5V_S3_USB

SMC_TX_L

SMC_RX_L

USB_PWR_ENA_L

USB_EXTD_N

USB_PORT0_P

USB_PORT0_N

PP5V_USB2_PORT0_F VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

USB_PORT1_P

USB_PORT1_N

PP5V_USB2_PORT1_F

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V MIN_NECK_WIDTH=0.2MM

USB_PORT3_P

USB_PORT3_N

PP5V_USB2_PORT3_F MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V MIN_NECK_WIDTH=0.2MM

USB_PORT2_P

USB_PORT2_N

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP5V_USB2_PORT2_F

EXTERNAL USB CONNECTORS

SYNC_DATE=N/A

SYNC_MASTER=MASTER

SLP1210N6

RCLAMP0502N

CRITICAL

SLP1210N6 CRITICAL

RCLAMP0502N

SLP1210N6

CRITICAL

SM

CRITICAL

FERR-250-OHM

USB-K22

CRITICAL

F-ANG-TH

CRITICAL

USB-K22

F-ANG-TH

USB-K22

CRITICAL

F-ANG-TH1

CRITICAL

USB-K22

F-ANG-TH1

CRITICAL

PI3USB102ZLE

MOJOMUX

TQFN

CRITICAL

DLP0NS

120-OHM-90MA

DLP0NS

120-OHM-90MA

CRITICAL

DLP0NS

120-OHM-90MA

DLP0NS

120-OHM-90MA

CRITICAL

0.01uF

CERM

402

16V

20%

402

CERM

16V

20%

0.01uF

20%

0.01uF

16V

CERM

402

6.3V

CRITICAL

CASE-D2-SM

POLY-TANT

20%

150UF

0.1UF

20%

402

10V CERM

SM

FERR-250-OHM

CRITICAL

SLP1210N6

RCLAMP0502N

CRITICAL

402

16V

CERM

20%

0.01uF

0.1UF

20% 10V

402

CERM

CRITICAL

TPS2060

MSOP

402

CERM

20% 10V

0.1UF

CERM

0.1UF

20%

402

10V

10V 402

0.1UF

CERM

20%

5% MF-LF

1/16W 402

10K

SOT23-HF1

2N7002

MSOP

TPS2060

CRITICAL

PRODUCTION

0

MF-LF

5%

402

1/16W

PRODUCTION

1/16W MF-LF

5%

0

402

CERM

20%

0.1UF

10V

CRITICAL

SM

FERR-250-OHM

SM

CRITICAL

CERM 402

20% 10V

9

20 9

46 6

103

6

103 20

70

20

103 20

50 49

46 6

51 50 49

103 20

103

SYM_VER-1

D

SG

D

SG

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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A

B

C

345678

D

B

8 7 5 4 2 1

IR RECEIVER CONNECTOR

518S0668

PLACE C4700, C4701 & L4700 NEAR J4700 PINS 4 AND 5 IN THE

CAMERA CONNECTOR & FILTER

BOTH SIDES OF THE PIN.

ORDER LISTED, AND NOT ON

LAYOUT NOTE:

518S0688

K37L (BLUETOOTH) CONNECTOR

SD Card Reader Board Connector

518S0690

47 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

6

5

4

3

2

1

8

7

J4750

5

4

3

2

1

7

6

J4720

4

5

3

Q4700

1

2

6

Q4700

4 3

21

L4720

21

L4721

2

1

C4750

21

L4751

4 3

21

L4750

4

3

2

1

6

5

J4780

5

4

3

2

1

7

6

J4700

4 3

21

L4702

21

L4703

4 3

21

L4701

2

1

C4720

2

1

C4721

2

1

C4781

2

1

C4700

2

1

C4701

21

L4700

USB_IR_P

USB_IR_L_N USB_IR_L_P

USB_BT_N

=PP3V3_S3_BT

=PP5V_S3_IR

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP5V_S3_IR

USB_CAMERA_N

USB_CAMERA_P

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S3_CAMERA

MIN_LINE_WIDTH=0.6MM

USB_CAMERA_L_P USB_CAMERA_L_N

=PP5V_S3_CAMERA

USB_SDCARD_N

=PP3V3_S3_SDCARD

USB_SDCARD_P

USB_IR_N

CARDREADER_RESET

CARDREADER_PLT_RST_L

CARDREADER_PLT_RST

USB_BT_L_N USB_BT_L_P

PP3V3_S3_BT VOLTAGE=3.3V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

USB_BT_P

PP3V3_S3_SDCARD VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

USB_SDCARD_L_P

USB_SDCARD_L_N

CARDREADER_RESET_L

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

Internal USB Connections

53261-8606

M-RT-SM

CRITICAL

M-RT-SM

53261-8605

SSM6N15FEAPE

SOT563

SSM6N15FEAPE

SOT563

120-OHM-90MA

CRITICAL

DLP0NS

SM

CRITICAL

FERR-250-OHM

10%

1UF

6.3V CERM

402

SM

FERR-250-OHM

CRITICAL

120-OHM-90MA

DLP0NS

CRITICAL

53261-8604

M-RT-SM

CRITICAL

M-RT-SM

53780-8605

CRITICAL

DLP0NS

120-OHM-90MA

SM

CRITICAL

FERR-250-OHM

DLP0NS

120-OHM-90MA

CRITICAL

10UF

CERM

6.3V 805-1

20%

402

CERM

10V

20%

0.1UF

10%

6.3V CERM

1UF

402

805-1

20%

6.3V

10UF

CERM

0.1UF

20% 10V

402

CERM

FERR-250-OHM

CRITICAL

SM

103 20

110 103

103 20

6

103 20

110 103

6

103 20

6

103 20

17

9

110 103

103 20

110 103

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

C

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

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A

B

C

345678

D

B

8 7 5 4 2 1

48 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=K51

SYNC_DATE=10/13/2008

BLANK PAGE

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Unused pins have "SMC_Pxx" names. Unused

those designated as inputs require pull-ups.

(OC)

(DEBUG_SW_1) (DEBUG_SW_2)

(OC)

If SMS interrupt is not used, pull up to SMC rail.

(OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NOTE: P94 and P95 are shorted, P95 could be spare.

pins designed as outputs can be left floating,

49 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

A3

C5

B11

F10

L3

D2

E1

H10

M1

B1

D3

E3

E5

H1

D1

A2

H3

L9

L11

M12

U4900

C4

B3

A4

J2

F2

E2

L6

M7

N6

K6

K7

K8

N7

M8

M4

L4

N4

M5

L5

M6

N5

K5

K4

J1

K2

J3

K1

L7

K9

N8

M9

L8

K10

N9

M10

J13

H11

G12

G10

H13

F12

G13

G11

A11

C11

B10

C10

A10

B9

C9

B8

L2

K3

L1

N2

M2

M3

N1

N3

U4900

F1

F4

G4

H4

G1

H2

G3

J4

C6

B5

A6

D5

C7

B6

A7

L12

N13

M13

N12

N11

L10

M11

N10

H12

J11

J10

K13

J12

K11

K12

L13

E4

F3

G2

C3

C1

B2

C2

A1

B4

A5

D4

D6

D7

D8

A8

B7

C8

D9

A9

E10

F13

E12

E13

F11

D12

E11

D13

D10

C12

C13

D11

B13

A12

A13

B12

U4900

2

1

R4998

2

1

R4903

2

1

R4902

2

1

R4901

2

1

R4909

2 1

XW4900

21

R4999

2

1

C4920

2

1

C4907

2

1

C4906

2

1

C4905

2

1

C4904

2

1

C4903

2

1

C4902

GND_SMC_AVSS

PM_CLKRUN_L LPC_PWRDWN_L

SMC_LRESET_L

SMB_0_S0_DATA

PM_CLK32K_SUSCLK

PM_SLP_S5_L

PM_SLP_S4_SMC_L

SMC_RX_L

SMC_TX_L

SMC_WAKE_SCI_L

SMC_GPU_VSENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMC_GFX_THROTTLE_L

SMS_ONOFF_L

SMB_MGMT_DATA

LPC_SERIRQ

LPC_CLK33M_SMC

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SMC_P26

SMC_P24

ESTARLDO_EN

PM_PWRBTN_L

ALL_SYS_PWRGD_SMC

SMC_RSTGATE_L

SMC_PROCHOT_3_3_L

PM_RSMRST_L

RSMRST_PWRGD

ALS_GAIN

SMC_PH2

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_A_S3_CLK

SMB_A_S3_DATA

SMB_BSA_CLK

SMB_BSA_DATA

=SMC_SMS_INT

SMC_MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

SMC_CASE_OPEN

SMC_NB_DDR_ISENSE

SMC_NB_CORE_ISENSE

SMC_ANALOG_ID

SMS_Y_AXIS

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

SMC_EXCARD_CP

NC_SMC_PB3

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

PM_BATLOW_L

SYS_ONEWIRE

PM_SYSRST_L

SMC_PA1

MEM_EVENT_L

SMC_PA5

USB_DEBUGPRT_EN_L

SMC_PM_G2_EN

PM_EN_PVCORE_CPU

VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

PP3V3_S5_AVREF_SMC

SMC_TRST_L

SMC_KBC_MDE

SMC_VCL

SMC_NMI

SMC_EXTAL

SMC_PA0

SMC_P41

SMC_EXCARD_PWR_EN

SMC_ADAPTER_EN

SMC_RESET_L

SMC_XTAL

SMC_MD1

=PP3V3_S5_SMC

SMC_PBUS_VSENSE

SMC_NB_MISC_ISENSE

SMC_BATT_ISENSE

SMC_DCIN_ISENSE

SMC_GPU_ISENSE

SMC_BC_ACOK

SMB_MGMT_CLK

SMC_ONOFF_L

PM_SLPS3_BUF2_L

SMC_BS_ALRT_L

ALS_RIGHT

ALS_LEFT

SMS_Z_AXIS

SYNC_DATE=N/A

SYNC_MASTER=MASTER

SMC

50

52

103 9

50

70 50

70 50 9 6

52

50

103 9

9

103 51 19

LGA-HF

OMIT

H8S2117

LGA-HF

OMIT

H8S2117

LGA-HF

H8S2117

OMIT

50

50 21

50

51 19

21

51

28

55 32 31 21

51 19

50

51 50 49 46

50

52

50

51 50

50

51 50

50

56

57

50

57

56

50 45

21

55

110 45

21

50

50 46

10K

MF-LF

5% 1/16W

402

NO STUFF

0

MF-LF

5% 1/16W

402

1/16W

5% MF-LF

10K

402

MF-LF

10K

5% 1/16W

402

51

10K

MF-LF

5%

1/16W

402

52

50

51 50 49 46

50

108 53

20% CERM

0.1UF

402

10V

50

70

21

20% CERM

0.1UF

402

10V

71

21

SM

20% CERM

0.1UF

402

10V

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

4.7

1/16W

5%

MF-LF

402

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

402

20%

CERM

0.1UF

10V

20% CERM

10V 402

0.1UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

6.3V

0.47UF

CERM-X5R

402

10%

50

51 50

51 19

22UF

20%

6.3V

CERM-X5R

805-3

54 53 50

50

50 6

G

D

S

IN

OUT

GND

OUT

IN

BI

OUT

G

D

S

OUT

IN

G

D

S

G

D

S

CD

GND

NC

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

UNUSED TP/NC ALIASES

PULL-UP ON PAGE 14

ANALOG SENSORS

MISC. SIGNAL ALIASES

518S0665

SMC Crystal Circuit

SMC AVREF Supply

FROM MXM

NC

FROM SMC

TO SMC

TO CPU

FROM SMC

SMC & MXM THERMTRIP LEVEL SHIFTING

UNUSED TP/NC ALIASES - PORT D - INTERNAL PULLUPS

FOR <RDAR://PROBLEM/5925345>

SMC Reset Button / Brownout Detect

POWER BUTTON

SMC PROCHOT 3.3V LEVEL SHIFTING

50 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

43

21

S5010

43

21

S5000

2

1

4

3

J5010

2

1

R5050

1

4

2

3

5

U5000

2

1

R5068

21

R5020

21

R5019

2

1

R5069

4

5

3

Q5096

1

2

6

Q5096

21

R5099

21

R5018

1

2

6

Q5095

21

R5098

21

R5049

21

R5047

21

R5097

21

R5095

21

R5093

21

R5092

21

R5089

21

R5096

21

R5091

21

R5090

2

1

R5078

2

1

R5070

4

3

5

Q5077

21

R5071

1

6

2

Q5077

21

R5043

21

R5010

2

1

C5010

21

R5094

2

1

Y5020

21

R5046

21

R5042

21

R5041

21

R5040

21

R5039

21

R5038

21

R5037

21

R5036

21

R5035

21

R5034

21

R5033

21

R5032

21

3

VR5065

2

1

C5066

2

1

C5067

2

1

C5065

4

5

3

Q5095

21

C5021

21

C5020

2

1

C5001

2

1

R5000

2

1

C5000

POWER_BUTTON_L

SMC_MANUAL_RST_L

SMC_SYS_LED

TP_SMC_SYS_LED

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

PM_THRMTRIP_L

SMC_ONOFF_L

SMC_ANALOG_ID

NO_TEST=TRUE

NC_SMC_ANALOG_ID

MAKE_BASE=TRUE

ESTARLDO_EN

MAKE_BASE=TRUE

TP_ESTARLDO_EN

SMC_P41

SMC_P26

TP_SMC_P26

MAKE_BASE=TRUE

SMC_P24

TP_SMC_P24

MAKE_BASE=TRUE

SMS_ONOFF_L

MAKE_BASE=TRUE

TP_SMS_ONOFF_L

SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

SMC_EXCARD_PWR_EN

SMC_PM_G2_EN

TP_SMC_PM_G2_EN

MAKE_BASE=TRUE

SMC_SYS_KBDLED

TP_SMC_SYS_KBDLED

MAKE_BASE=TRUE

ALS_GAIN

MAKE_BASE=TRUE

NC_ALS_GAIN

NO_TEST=TRUE

SMC_NB_MISC_ISENSE

SMC_NB_CORE_ISENSE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_BATT_ISENSE

SMS_X_AXIS

MAKE_BASE=TRUE

SMC_1V5_S0_VSENSE

SMS_Y_AXIS

SMC_MCP_CORE_VSENSE

MAKE_BASE=TRUE

SMC_NB_DDR_ISENSE

MAKE_BASE=TRUE

SMC_1V5_S0_ISENSE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_CPU_INPUT_VSENSE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_CPU_INPUT_ISENSE

MAKE_BASE=TRUE

SMC_UNUSED_ADC_PORT7

MXM_PWR_LEVEL

MAKE_BASE=TRUE

CPU_PROCHOT_BUF

SMC_BC_ACOK

SMC_FAN_3_TACH

SMC_ADAPTER_EN

MAKE_BASE=TRUE

SMC_SMS_INT

MXM_OVERT_L

=PP3V3_S0_SMC_LS

SMC_MCP_SAFE_MODE

=PP5V_S5_AVREF

SMC_XTAL

PP3V3_S5_AVREF_SMC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

SMC_EXTAL

MIN_LINE_WIDTH=0.4 mm

GND_SMC_AVSS

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

SMC_ONOFF_L SMC_LID SMC_PH2 SMC_TX_L SMC_RX_L SYS_ONEWIRE SMC_BS_ALRT_L

SMC_TDO SMC_TDI SMC_TCK SMC_EXCARD_OC_L SMC_PA0 SMC_PA1 SMC_BIL_BUTTON_L SMC_FAN_3_CTL

=PP3V3_S0_SMC

SMC_GFX_OVERTEMP_L

MXM_THRMTRIP_L

SMC_THRMTRIPMXM_THRMTRIP

=PPVTT_S0_CPU

SMC_PROCHOT_3_3_L

CPU_PROCHOT_L_R

SMC_PROCHOT

=PP3V3_S5_SMC

SMC_TMS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMS_Z_AXIS

NO_TEST=TRUE

NC_ALS_RIGHT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ALS_LEFT

MAKE_BASE=TRUE

ALS_LEFT

SMC_GFX_OVERTEMP_L

SMC_PA5

SMS_Z_AXIS

ALS_RIGHT

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

SMC_GFX_THROTTLE_L

CPU_PROCHOT_L

MCP_SPKR

MXM_ALERT_L

MAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_RESET_L

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

USB_DEBUGPRT_EN_L

=SMC_SMS_INT

=PP3V3_S0_SMC_LS

PM_SLP_S5_L

PM_SLPS3_BUF2_L

SMC_CASE_OPEN

PM_SLP_S4_SMC_L

MAKE_BASE=TRUE

SMC Support

SYNC_DATE=N/A

SYNC_MASTER=MASTER

Intersil ISL60002-33

353S1278

ALL

353S1381

10%

CERM

0.01UF

16V 402

22PF

CERM

50V 402

5%

CERM

50V

22PF

5%

402

50 49

SILK_PART=SYS POWER

NTC020-CC1J-B260T

DEVELOPMENT

SM

NTC020-CC1J-B260T

SILK_PART=SMC RESET

DEVELOPMENT

SM

CRITICAL

SILK_PART=PWR BTN

M-RT-SM

53261-8602

5%

10K

1/16W MF-LF 402

CRITICAL

SOT23-5-HF

NCP303LSN

MF-LF

1/16W

5%

10K

402

MXM

IG

51

MF-LF

5%

1/16W

402

MF-LF

0

1/16W

402

5%

1/16W MF-LF 402

5%

3.3K

MXM

2N7002DW-X-G

SOT-363

MXM

2N7002DW-X-G

SOT-363

MXM

5%

402

10K

1/16W MF-LF

MF-LF

5%

0

1/16W

402

MXM

85

49

100 14 11

SOT-363

2N7002DW-X-G

402

5%

10K

1/16W MF-LF

5%

MF-LF

10K

402

1/16W

MF-LF

402

1/16W

5%

10K

MF-LF1/16W

402

5%

100K

402

5%

MF-LF1/16W

5%

402

10K

1/16W MF-LF

MF-LF

402

5%

1/16W

10K

5%

1/16W

402

MF-LF

100K

PLACEMENT_NOTE=PLACE CLOSE TO U4900(SMC)

10K

402

5%

1/16W MF-LF

1/16W MF-LF 402

1K

5%

402

MF-LF1/16W

5%

10K

1/16W5%MF-LF

402

49

100 14 11

MF-LF

1/16W 402

5%

470

1/16W MF-LF 402

5%

3.3K

MMDT3904-X-G

SOT-363-LF

MF-LF

1/16W

5%

402

3.3K

SOT-363-LF

MMDT3904-X-G

402

NO STUFF

10K

5%

1/16W MF-LF

1K

402

1/16W MF-LF

5%

402

CERM

20% 10V

0.1UF

49

51 49

1/16W MF-LF

402

100K

5%

20.000M

CRITICAL

SM-4

MF-LF

402

10K

1/16W

5%

10K

MF-LF

402

1/16W

5%

MF-LF

402

1/16W

10K

1/16W5%MF-LF

402

10K

MF-LF1/16W

10K

402

5%

402

MF-LF1/16W

5%

100K

2.0K

MF-LF1/16W

5%

402

100K

402

MF-LF

5%

1/16W

MF-LF

5%

402

10K

1/16W

MF-LF

10K

5%

1/16W

402

MF-LF1/16W

5%

100K

1/16W

10K

402

MF-LF

5%

SOT23-3

REF3133

CRITICAL

6.3V 603

10uF

20% X5R

0.01UF

10% CERM

402

16V

10%

6.3V CERM-X5R 402

0.47UF

2N7002DW-X-G

SOT-363

CERM

0.1uF

20% 10V

402

49

49 108 54

49

49 108 54

49 53

85

49

49 21

55 50 6

49

6

49

54 53 49

50 49

49

51 49 46

49

51 49

49 45

49

54 53 6

50 49

71 55 10 6

50 49 6

51 49

49

50 49

49

21

49

21

85

50 49 6

49 46

49

55 50 6

49

70 49 9 6

49

70 49

IN

BI

IN

OUT

OUT IN

IN

OUT

OUT IN

BI

IN

BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

516S0573

FRANK CONNECTOR

LPC+SPI Connector

SPI Bus Series Resistance Option

Alternate SPI ROM Support

Pull-up on debug card

51 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J5100

21

R5145

2

1

C5144

21

R5146

2

1

R5144

5

6

2

1

3 4

U5100

2

1

R5140

21

R5158

21

R5157

21

R5156

=SPI_CS1_R_L_USE_MLB

SPI_CS0_R_L

SPI_MLB_CS_L

=PP3V3_S5_ROM

SPI_CS0_L

SPI_ALT_CS_L

MAKE_BASE=TRUE

SPIROM_USE_MLB

PM_CLKRUN_L

LPC_FRAME_L

LPC_AD<1>

LPC_AD<2> LPC_AD<3>

SPI_ALT_CLK

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK

LPCPLUS_GPIO

SPI_ALT_CLK

SMC_TX_L

SMC_MD1

SMC_TRST_L

SMC_TDO

DEBUG_RESET_L

SMC_TMS

SPI_ALT_MISO

SPI_ALT_MOSI

LPC_AD<0>

SMC_RX_L

SMC_NMI

SMC_RESET_L

SPIROM_USE_MLB

LPC_CLK33M_LPCPLUS

=PP5V_S0_LPCPLUS

=PP3V3_S5_LPCPLUS

SPI_MISO

SPI_MOSI_R

=PP3V3_S5_LPCPLUS

SPI_ALT_MISO

SPI_ALT_MOSI

SPI_CLK_R

=PP3V3_S5_LPCPLUS

SYNC_MASTER=MASTER

SYNC_DATE=N/A

LPC+SPI Debug Connector

PRODUCTION

5%

MF-LF

0

402

1/16W

PLACEMENT_NOTE=PLACE NEXT TO U5100

402

MF-LF

1/16W

5%

20K

NC7SB3157P6XG

SC70

CRITICAL

PATH=I96

LPCPLUS

61

51

MF-LF

402

5%

1/16W

100K

51

PLACEMENT_NOTE=Place next to R6105

402

1/16W

5%

MF-LF

0

LPCPLUS

103 61 21

51

PLACEMENT_NOTE=Place next to R6152

402

0

MF-LF

5%

1/16W

LPCPLUS

103 61 21

51

LPCPLUS

402

PLACEMENT_NOTE=Place next to R6150

5%

MF-LF

0

1/16W

103 61 21

103 9

103 49 19

51

49 19

50 49

49

50 49 46

18

55909-0374

CRITICAL

LPCPLUS

M-ST-SM

103 49 19

51

103 49 19

51

49 19

50 49

9

49

50 49

49

50 49 46

21

103 21

PLACEMENT_NOTE=Place near U1400

LPCPLUS

402

5% 1/16W MF-LF

0

0.1UF

CERM

10V

20%

402

61 6

103

51

6

51 6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

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SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Also reserve 0x56 and 0x32 per spec

CPU - PECI DTS

DIODE2: CPU

UNUSED SMC "BATTERY A" SMBUS CONNECTIONS

(WRITE: 0X54 READ: 0X55)

3

2

1

4

6

5

DIODE

EMC1047-2 HEX DIODE SENSOR

(MASTER)

MCP HEATSINK

CPU HEATSINK

AMBIENT TEMP

ODD TEMP LCD TEMP

MXM HEATSINK

FUNCTION

SMC

U4900

INA219: ACDC THRU J600

(WRITE: 0X80, READ: 0X81))

OUTPUT VOLTAGE, CURRENT, POWER

AC/DC PS POWER

3 SENSE POINTS - PRIMARY, SECONDARY, AMB

(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)

EMC1403-[1,2]: ACDC THRU J600

AC/DC PS TEMPS

REMOTE TEMPS

EMC1047-2, U5500, SEE TABLE

(WRITE: 0X90 READ: 0X91)

(WRITE: 0X72 READ: 0X73)

MCP79 SMBUS "1" CONNECTIONS

(WRITE: 0X9A READ: 0X9B)

MAX6618 - U5570

SMC "0" SMBus Connections

SMBUS 0 ALSO GOES TO THE XDP CONNECTOR

SMC

GPU ON CARD - J8400

EMC1403-2: U5535

DIODE1: MCP

DIE TEMPS

SO-DIMM "B"

MXM CARD (WRITE: 0X98 READ: 0X99)

SMC "MANAGEMENT" SMBUS CONNECTIONS

U4900

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE

MARGINGING CONTROL

(MASTER)

U4900

(MASTER)

U2900

U2901

(Write: 0x98 Read: 0x99)

VREF DAC

(WRITE: 0X30 READ: 0X31)

MCP79 SMBUS "0" CONNECTIONS

J9800

MIKEYMCP79

U1400

(MASTER)

(WRITE: 0XA2 READ: 0XA3)

J3200

SO-DIMM "A"

J3100

MCP79

U1400

(MASTER) (MASTER)

SMC

U4900

SMC "A" SMBus Connections

U4900

(Write: 0xA0 Read: 0xA1) (MASTER)

MXM TEMP

NV INSIDE (WRITE: 0X9E READ: 0X9F)

SMC

SMC "B" SMBus Connections

52 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R5202

2

1

R5203

2

1

R5250

2

1

R5251

2

1

R5270

2

1

R5271

2

1

R5260

2

1

R5261

2

1

R5290

2

1

R5291

2

1

R5281

2

1

R5280

2

1

R5201

2

1

R5200

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

=SMB_MXM_THRM_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

=SMB_ACDC_SDA

=SMB_ACDC_SCL

=SMB_REMOTE_TEMP_SDA

=SMB_REMOTE_TEMP_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS

=SMB_CPU_PECI_SCL

=SMB_CPU_PECI_SDA

=SMB_MXM_THRM_SCL

=PP3V3_S0_SMBUS_SMC_MGMT

SMB_0_S0_CLK

=I2C_AUDIO_SDA

=I2C_AUDIO_SCL

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMB_BSA_CLK

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

MAKE_BASE=TRUE

SMBUS_MCP_1_CLK

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

SMB_MGMT_DATA

SMB_MGMT_CLK

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

SMB_BSA_DATA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

=PP3V3_S5_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

=PP3V3_S0_SMBUS

=SMB_MCP_CPU_THRM_SDA

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

SMB_A_S3_CLK

SMB_A_S3_DATASMB_0_S0_DATA

=SMB_MCP_CPU_THRM_SCL

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SMBUS CONNECTIONS

1/16W MF-LF

5%

2.2K

402

1/16W MF-LF

5%

2.2K

402

5%

4.7K

MF-LF

1/16W

402

5% MF-LF

1/16W

4.7K

402

5%

MF-LF

1/16W

100K

MF-LF

5% 1/16W

100K

402

MF-LF

1/16W

5%

402

2.2K

1/16W

5%

MF-LF

402

2.2K

4.7K

MF-LF

1/16W

402

5%

4.7K

5% 1/16W

402

MF-LF

402

5% 1/16W MF-LF

100K

MF-LF

5%

402

1/16W

100K

5%

4.7K

1/16W 402

MF-LF

402

1/16W

5%

4.7K

MF-LF

106

85

49

6

55

6

52 6

55

85

6

49

68

106

49

21

29

49

29

49

106

6

106 21 13

32

52 6

55

6

106

31

49

49 49

55

106

RS_P RS_M

OUT

GND

VCC

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CPU CURRENT SENSE AMP & FILTER

CPU Voltage Sense / Filter

CPU CORE INPUT SIDE CURRENT & VOLTAGE SENSE

PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)

AMPLIFIED AND FILTERED ISNS TO SMC

Place RC close to SMC

MXM PWRSRC (GPU CORE & MEM) CURRENT SENSE

GAIN = 20

353S2291

K51 SET FOR APPROX 1.98V AT 5.5A ON PWRSRC

COUNT

.0087518 A/COUNT

2.778 A/V

2 A/V

4 V/V

MXM PWRSRC VOLTAGE SENSE

.0129 V/COUNT

COUNT

0 TO 3.3V

(SCALING 12V INPUT VOLTAGE TO SMC)

PCB: PLACE C5359 WITHIN 1" OF SMC (U4900)

0 TO 3.3V

ADC IS 10BIT 0 TO 1023

SCALE

K50 SET FOR APPROX 2V AT 4A ON PWRSRC

COUNT

.0064453 A/COUNT

SCALE

ADC IS 10BIT 0 TO 1023

SCALE

ADC IS 10BIT 0 TO 1023

PLACE RC CLOSE TO SMC

53 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R5361

5

2

4

1

3

U5360

2

1

R5331

2

1

C5330

2

1

R5330

3

1

6

4

5

2

U5320

2

1

C5321

2

1

C5320

21

R5321

21

R5360

21

R5363

21

C5360

21

R5364

2

1

C5362

3

4 5

1

2

U5380

2

1

C5381

43

21

R5380

2

1

C5380

2

1

R5354

2

1

R5353

2

1

C5359

2

1

C5309

21

R5309

OMIT

0.22UF

X5R

20%

6.3V

402

0.22UF

6.3V

20% X5R

MXM

1/16W MF-LF 402

18.2K

1%

MXM

1/16W

6.04K

MF-LF 402

1%

0.22UF

X5R

6.3V 402

20%

MXM

1%

2512-1

1W

0.025

MF

OMIT

16V

10%

CERM-X7R 402

MXM

MAX4073TAXK+G65

SC70

12 108

49 108

CERM-X5R

10%

0.22UF

6.3V 402

5.1K

402

5% 1/16W MF-LF

16V

20%

0.01UF

CERM

402

21K

402

1% 1/16W MF-LF

1%

10K

1/16W

402

MF-LF

71 108

MF-LF

4.53K

402

10V

0.1UF

DEVELOPMENT

CERM

20%

INA210

DEVELOPMENT

CRITICAL

SC70

402

18.2K

1/16W

1% MF-LF

0.22UF

6.3V X5R 402

20%

1/16W

1%

402

6.04K

MF-LF

OPA348 SC70-5

402

MF-LF

1/16W

1%

10K

49 108

4.53K

402

MF-LF

1%

1/16W

0.22UF

X5R

20%

6.3V

402

CPU/MXM CURRENT AND VOLTAGE SENSE

SYNC_MASTER=MASTER

SYNC_DATE=N/A

107S0111

1

18 MILLIOHM R5380 CRITICAL K23_MXM

C5381

MXM

CAP,0.082UF,402

1

C5381 IGRES,10KOHM,5%,402

VR_ISNS_CPU_P

VR_ISNS_CPU_N

SNS_PS_CPU_ISNS

CPU_INPUT_ISENSE_N

CPU_INPUT_ISENSE_P

SMC_CPU_INPUT_VSENSE

=PP3V3_S0_SMC

SMC_CPU_INPUT_ISENSE

PP12V_S0_CPU_FLTRD

GND_SMC_AVSS

VR_CPU_IOUT

SMC_CPU_ISENSE

=PP5V_S0_ISENSE

GND_SMC_AVSS

PPV_S0_MXM_PWRSRC

SMC_GPU_VSENSE

GND_SMC_AVSS

CPU_VCC_SENSE

=PPV_S0_MXM_PWR

MAX_NECK_LENGTH=3 MM

PPV_S0_MXM_PWRSRC

VOLTAGE=12V MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm NET_SPACING_TYPE=PWR

MAKE_BASE=TRUE

MXM_PWRSRC_SENSOR_N

GND_SMC_AVSS

=PP3V3_S0_SMC

SMC_CPU_VSENSE

CRITICAL

=PPV_S0_MXM_PWRSRC

132S0242

116S0090

SMC_GPU_ISENSE

0.082UF

MXM_PWRSRC_SENSOR_P

OMIT

107S0063

1

R538025 MILLIOHM CRITICAL K22_MXM

SMC_CPU_INPUT_IOUT

1%

1/16W

1

132S0080 C5321 DEVELOPMENT

C5321

1

116S0004 PRODUCTION

CAP, 0.22UF, 0402

RES, 0-Ohm, 0402

DEVELOPMENT

108

71

50

6 50 53 54

50

71 72

49 50 53 54

49 50 53

6

49 50 53 54

49 108

49 50 53 54

53

49 108

49 50 53 54

6

108

53

108

49 50 53 54

84

6 50 53 54

54

V+

REFIN+

IN-

OUT

GND

OUT

IN

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Place RC close to SMC

MCP CORE CURRENT SENSE

GAIN = 200V/V

MCP CORE VOLTAGE SENSE

SCALE IS 0.116 V/A

TRANSFER RATIO = 0.4V/A

1.5V S0 VOLTAGE SENSE

1.5V S0 CURRENT SENSE

353S2073

54 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R5405

2

1

C5404

21

R5404

21

R5403

2

1

C5403

2

1

C5402

21

R5402

2

1

C5400

2

1

C5401

43

21

R5400

21

R5401

3

1

6

4

5

2

U5400

402

X5R

6.3V

20%

0.22UF

1%

1/16W

402

MF-LF

4.53K

6.3V X5R 402

0.22UF

20%

1%

4.53K

402

1/16W MF-LF

RES, 0 OHM, 0402

CAP, 0.22UF, 0402

1/16W

6.3V 402

OMIT

C5401

116S0004

132S0080

20%

0.22UF

X5R

MCP_PWR_SENSE

1

PRODUCTION

RES,0 OHM,1206,20MILLIOHM MAX

101S0414 PRODUCTIONR5400

1

CRITICAL

RES,2 MILLIOHM,1206104S0018 MCP_PWR_SENSER5400 CRITICAL

1

1/4W

0.002

=PP3V3_S0_SMC

SMC_1V5_S0_ISENSE_R

SMC_1V5_S0_ISENSE

PP1V5_S0

MCPCORES0_IMON

SENSE_1V5_S0_N

SENSE_1V5_S0_P

PP1V5_S0

PPMCPCORE_S0_REG

SMC_MCP_CORE_VSENSE

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

GND_SMC_AVSS

SMC_1V5_S0_VSENSE

GND_SMC_AVSS

PP1V5_S0_FET

SYNC_DATE=12/08/2008

SYNC_MASTER=K51

MCP CURRENT AND VOLTAGE SENSE

6.3V X5R 402

20%

0.22UF

1%

4.53K

402

1/16W MF-LF

MCP_PWR_SENSE

402

X5R

6.3V

20%

0.22UF

1206

1%

MF-LF

OMIT

1%

4.53K

402

MF-LF

MCP_PWR_SENSE

1/16W

402

NOSTUFF

4.53K

MF-LF

1%

108 74 108 50

MCP_PWR_SENSE

SC70

INA210

1

53 50 6

108

108 50

54 6

108

54 6

74 6 108 50

54 53 50 49

108 50

54 53 50 49

78

BI

DN2/DP3

DP1

DN1

DP2/DN3

SMCLK

GND

THERM*

SMDATA

VDD

ALERT*

BI

DP2/DN3 DN2/DP3

DP1/DN6

DN1/DP6

GND

SMDATA

SMCLK

DN4/DP5

DP4/DN5

VDD

BI

AGND

VREF

PECI

SDA SCL

AD0

AD2 AD1

GND

VCC

OUT

GND

V+

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

518S0677

SENSOR CH2 SENSOR CH3

is on csa 70 with power sequencing

power/gnd and ref for this dual part

Must pull high to 2.5V for compatibility with all drives

Cannot pull low because some drives use this bit to determine 1.5 Gbps vs. 3.0 Gbps SATA

Drive disconnected = pulled high

Drive asleep = HDD drives HDD_OOB_TEMP low

Drive active = valid signal protocol

FROM DRIVE: LOW: -0.3V TO 0.5V HIGH: 2.0V TO 3.6V

TO SMC

HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING

CPU PECI DTS OPTIONS

PLACEMENT NOTE: PLACE U5535 NEAR MCP, TOP SIDE UNDER HEATSINK

PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU

518S0678

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

SENSOR CH4

353S2224

SENSOR CH1

SENSOR CH6

MCP & CPU T-Diode Thermal Sensor

SENSOR CH5

REMOTE THERMAL SENSORS

Consider 3rd option - direct to SMC

518S0678

HEATSINKS, AMBIENT, PANEL AND ODD

REMOTE THERMAL SENSORS (HEATSINKS AND ODD)

518S0698

518S0678

55 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

8

1

3

2

4

U7030

2

1

4

3

J5535

2

1

4

3

J5550

2

1

R5553

21

R5550

2

1

R5554

2

1

R5551

21

L5536

21

L5535

2

1

C5580

21

R5571

2

1

C5571

2

1

C5570

10

6

4 5

1

7

2

8 9 3

U5570

21

R5570

1

9 10

6

8

4

2

7

5

3

U5500

3

2

1

5

4

J5521

2

1

C5535

21

R5535

2

1

4

3

J5511

21

L5511

21

L5510

21

L5521

21

L5520

2

1

4

3

J5510

21

L5513

21

L5512

21

L5523

21

L5522

2

1

4

3

J5520

21

L5554

21

L5553

2

1

4

3

J5551

21

L5552

2

1

C5536

1

7

9

10

6

4

2

5

3

8

U5535

2

1

R5537

2

1

R5536

21

R5538

2

1

C5501

21

R5500

2

1

C5502

2

1

C5503

2

1

C5504

CRITICAL

0402

10%

0.0022UF

CERM

50V 402

SIGNAL_MODEL=EMPTY

0.0022UF

10%

402

CERM

50V

SIGNAL_MODEL=EMPTY

0.0022UF

10% 50V

CERM

402

5%

MF-LF

1/16W

22

402

10V X5R

402-1

10%

1UF

5%

402

MF-LF

0

1/16W

MF-LF

1/16W

5%

100K

402

MCP_CPU_TDIODE

402

1/16W

5% MF-LF

10K

MCP_CPU_TDIODE

52

MCP_CPU_TDIODE

EMC1403-2-AIZL

CRITICAL

TSSOP

CERM

402

10% 50V

0.0022UF

SIGNAL_MODEL=EMPTY

MCP_CPU_TDIODE

21 108

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

MXM

FERR-220-OHM

SILK_PART=CPU HSK

53398-8602

M-ST-SM

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

M-ST-SM

CRITICAL

53398-8602

MXM

SILK_PART=MXM HSK

MCP_CPU_TDIODE

402

MF-LF

5%

22

1/16W

10% 10V X5R 402-1

1UF

MCP_CPU_TDIODE

CRITICAL

53780-8603

M-RT-SM

CRITICAL

EMC10472AIZL

TSSOP

11 108

20

MF-LF

5%

1/16W

402

PECI_MCP

14 108

MAX6618

USOP-HF

PECI_SMB

10V

20%

0.1UF

402

CERM

PECI_SMB PECI_SMB

10V

20%

0.1UF

402

CERM

402

MF-LF

1/16W

5%

20

PECI_SMB

SIGNAL_MODEL=EMPTY

402

CERM

50V

10%

0.0022UF

MCP_CPU_TDIODE

11 108

0402

FERR-220-OHM

MF-LF

1/16W

5%

1K

402

MF-LF

5% 1/16W

62K

402

MF-LF

402

5%

1/16W

3.3K

MF-LF

5%

1/16W

200K

402

CRITICAL

53398-8602

LM393

SOI-HF

CRITICAL

Thermal Sensors

SYNC_DATE=N/A

SYNC_MASTER=MASTER

SNS_AMB_N

SNS_AMB_PSNS_LCD_P

SNS_LCD_N

SMC_EXCARD_CP

SMC_HDD_OOB_TEMP

MAKE_BASE=TRUE

=PP3V3_S0_SMC_LS

HDD_OOB_TEMP_R

12VS5_1V60_REF

HDD_OOB_TEMP

=PP3V3_S0_TSENS

CPU_PECI_MCP

=SMB_CPU_PECI_SDA

HDD_OOB_TEMP_FILT

SNS_ODD_N

SNS_T_DP4_DN5

=SMB_MCP_CPU_THRM_SCL

SNS_MCP_P

=SMB_CPU_PECI_SCL

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0_MCPTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

SNS_T_DN4_DP5

=SMB_REMOTE_TEMP_SDA

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_TSENS_R

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

SNS_MXM_N

SNS_MXM_P

=SMB_REMOTE_TEMP_SCL

=PP3V3_S0_TSENS

DIFFERENTIAL_PAIR=SNS_T1

SNS_T_DN1_DP6

SNS_T_DP4_DN5

=PPVTT_S0_CPU

MEM_EVENT_L

SNS_T_DN4_DP5

DIFFERENTIAL_PAIR=SNS_T3

SNS_T_DP2_DN3

MCPTHMSNS_ALERT_L

SNS_T_DN2_DP3

DIFFERENTIAL_PAIR=SNS_T2

SNS_T_DP2_DN3

MCP_THMDIODE_P

=SMB_MCP_CPU_THRM_SDA

MCPTHMSNS_THERM_L

SNS_T_DN1_DP6

SNS_T_DP1_DN6

SNS_T_DP2_DN3

SNS_T_DN2_DP3

SNS_CPU_H_N

SNS_T_DN4_DP5

SNS_CPU_H_P

SNS_ODD_P

SNS_T_DP4_DN5

DIFFERENTIAL_PAIR=SNS_T3

SNS_T_DN2_DP3

DIFFERENTIAL_PAIR=SNS_T2

DIFFERENTIAL_PAIR=SNS_T1

SNS_T_DP1_DN6

=PP3V3_S0_MCPTHMSNS

MCP_THMDIODE_N

SMB_PECI_L

CPU_PECI_L

M-ST-SM

SILK_PART=MCP HSK

SILK_PART=AMBIENT TEMP

SNS_MCP_N

0402

SNS_T_DP1_DN6

SILK_PART=ODD TEMP

M-RT-SM

CRITICAL

53780-8602

CRITICAL

M-RT-SM

SILK_PART=LCD TEMP

53780-8602

SILK_PART=HDD TEMP

53780-8602

M-RT-SM

CRITICAL

108 110

108 110 108 110

108 110

49

108

6 50

108

70

6 55

52

108

108 110

55 108

108

52

55 108

52

108

52

6 55

55 108

55

55 108

6 10 50 71

21 31 32 49

55 108

108

55 108

108

108 110

55 108

6

108

G

S

D

G

S

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

FAN 0

518S0592

GND

TACH

MOTOR CONTROL

518S0592

GND

TACH

MOTOR CONTROL

FAN 1

ODD FAN

NOTE: ADDED TO PROTECT SMC

HD FAN

12V DC

56 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C5605

2

1

C5628

2

1

R5630

2

1

R5620

21

L5640

21

L5630

21

L5620

21

L5610

21

L5601

21

L5600

2

1

C5608

2

1

C5609

2

1

C5606

2

1

C5607

4

3

2

1

6

5

J5600

4

3

2

1

6

5

J5601

2

1

C5602

2

1

3

Q5605

2

1

3

Q5602

21

R5698

21

R5699

2

1

R5611

2

1

R5610

3

1

D5601

21

R5609

2

1

C5603

2

1

R5607

5

4

87632

1

Q5603

2

1

R5606

21

R5605

2

1

C5601

3

1

D5600

2

1

R5603

5

4

87632

1

Q5600

2

1

R5602

2

1

R5601

2

1

R5600

MIN_NECK_WIDTH=0.25MM

1.5K

F1_VOLTAGE8R5 MIN_LINE_WIDTH=0.5MM

402

MF-LF

1/16W

10K

5%

MF-LF

5%

10K

1/16W 402

1206

MF-LF

1/4W

1.5K

5%

NTHS5443T1H

CRITICAL

1206A-03-HF

SOT23

5%

402

10K

1/16W MF-LF

NTHS5443T1H

CRITICAL

1206A-03-HF

MMBD914XG

SOT23

1/4W 1206

5% MF-LF

1.5K

10K

MF-LF 402

5% 1/16W

MF-LF

5%

47K

1/16W

402

47K

5% 1/16W MF-LF

402

2N7002

SOT23-HF1

2N7002

SOT23-HF1

20% 16V ELEC

6.3X5.5-SM1-HF

100UF

CRITICAL

53780-8604

M-RT-SM

53780-8604

CRITICAL

402

20% CERM

16V

0.01UF

20% CERM

1206-1

16V

4.7UF

16V

20%

0.01UF

402

CERM

X5R 603

10% 16V

2.2UF

0402

CRITICAL

FERR-220-OHM

0402

FERR-220-OHM

CRITICAL

220-OHM-1.4A

CRITICAL

0603

220-OHM-1.4A

0603

CRITICAL

220-OHM-1.4A

0603

220-OHM-1.4A

0603

CRITICAL

MF-LF

1/10W

5%

0

603

PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

0

603

MF-LF

1/10W

5%

PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3

16V

10%

2.2UF

603

X5R

CRITICAL

20% 16V ELEC

6.3X5.5-SM1-HF

100UF

HD AND OD FAN

SYNC_MASTER=MASTER

SYNC_DATE=N/A

FAN_1_GND MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

FAN_0_GND MIN_NECK_WIDTH=0.25MM

SMC_FAN_1_CTL

FAN_TACH0

FAN_0_PWR

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM

=PP3V3_S0_FAN

SMC_FAN_1_TACH

SMC_FAN_0_TACH

=PP3V3_S0_FAN

FAN_TACH1

=PP12V_S0_FAN

SMC_FAN_0_CTL

FAN_TACH0_L

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM

FAN_0_PWR_L

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MM

PP12V_S0_FAN0_L

MIN_NECK_WIDTH=0.25MM

FAN_1_PWR

MIN_LINE_WIDTH=0.5MM

FAN_TACH1_L

FAN_1_PWR_L

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM

MIN_NECK_WIDTH=0.25MM VOLTAGE=12V

MIN_LINE_WIDTH=0.5MM

PP12V_S0_FAN1_L

=PP12V_S0_FAN

CRITICAL

MMBD914XG

MIN_LINE_WIDTH=0.5MM

805

5%

1/8W

MF-LF

1.5K

F0_GATESLOWDN

0.47UF

X7R

10% 16V

805

1/8W

5%

MF-LF

3.9K

F0_VOLTAGE8R5 MIN_LINE_WIDTH=0.5MM

805

MF-LF

5%

1/8W

F1_GATESLOWDN

0.47UF

10%

805

X7R

16V

805

5%

1/8W

MF-LF

3.9K

110

49

6 56 57

49

6 56 57

49

110

6 56 57

G

S

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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THE INFORMATION CONTAINED HEREIN IS THE

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C

A

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

518S0592

MOTOR CONTROL

FAN 2

CPU FAN

12V DC

GND

TACH

57 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

4

3

2

1

6

5

J5700

2

1

R5720

21

L5720

21

L5710

21

L5701

2

1

C5709

2

1

C5708

2

1

C5702

2

1

3

Q5702

21

R5797

2

1

R5705

2

1

R5704

21

R5703

2

1

C5701

2

1

R5701

3

1

D5700

5

4

87632

1

Q5700

2

1

R5700

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

F2_VOLTAGE8R5

805

MF-LF

3.9K

5%

1/8W

0.47UF

10% 16V X7R 805

F2_GATESLOWDN

1/8W

805

5%

1.5K

MF-LF

CRITICAL

FAN_2_PWR

=PP3V3_S0_FAN

SMC_FAN_2_TACH

=PP3V3_S0_FAN

SMC_FAN_2_CTL

FAN_TACH2

=PP12V_S0_FAN

FAN_2_GND MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP12V_S0_FAN2_L

MIN_NECK_WIDTH=0.25MM

FAN_2_PWR_L

MIN_LINE_WIDTH=0.5MM

FAN_TACH2_L

SYNC_DATE=N/A

SYNC_MASTER=MASTER

CPU FAN

47K

5% 1/16W MF-LF

402

MF-LF

10K

402

5% 1/16W 5%

1/4W

1.5K

1206

MF-LF

SOT23

MMBD914XG

NTHS5443T1H

1206A-03-HF

1/16W MF-LF 402

5%

10K

M-RT-SM

53780-8604

CRITICAL

603

1/10W

5%

0

MF-LF

PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3

0603

CRITICAL

220-OHM-1.4A

0603

220-OHM-1.4A

CRITICAL

0402

FERR-220-OHM

CRITICAL

402

CERM

0.01UF

16V

20%

4.7UF

1206-1

CERM

16V

20%

100UF

20% 16V ELEC

6.3X5.5-SM1-HF

CRITICAL

SOT23-HF1

2N7002

57 56 6

49

57 56 6

49

56 6

110

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

B

C

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D

B

8 7 5 4 2 1

58 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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C

A

D

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A

B

C

345678

D

B

8 7 5 4 2 1

59 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=12/08/2008

SYNC_MASTER=K51

BLANK PAGE

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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D

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8 7 5 4 2 1

60 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

SO

VDD

CE*

SCK

VSS

HOLD*

SI

WP*

OUT

IN

IN IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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8 7 5 4 2 1

0

SPI_CLK

0

1

SST25VF016B max speed for READ command is 25MHz.

MCP79 SPI Frequency Select

SPI_MOSI

NOTE: MCP79 only issues ’READ’ (0x03) commands

frequency and part selection.

not ’READ_FAST’ (0x0B). Limits SPI bus

0

Frequency

31 MHz

1

25 MHz

1 MHz

42 MHz

0

61 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R6191

2

1

R6190

21

R6150

21

R6152

21

R6105

3

4

8

2

5

6

7

1

U6100

2

1

R6100

2

1

R6101

2

1

C6100

=PP3V3_S5_ROM

SPI_WP_L SPI_HOLD_L

SPI_CLK

SPI_MOSI

SPI_MLB_CS_L

SPI_CLK_R

SPI_MOSI_R

SPI_MISO_R

SPI_MISO

SYNC_DATE=12/08/2008

SPI ROM

SYNC_MASTER=K51

MF-LF

5% 1/16W

10K

402

MF-LF

5%

1/16W

10K

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%

1/16W

0

402

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%

1/16W

0

402

103 51 21 103 51 21

51

103 51 21

CRITICAL

SST25VF016B

OMIT

SOI

16MBIT

1/16W

5%

MF-LF

3.3K

402

1/16W

5%

3.3K

MF-LF 402

10V

0.1UF

CERM

20%

402

51 6

103 103

103

IN

OUT

IN

OUT

OUT OUT

OUT

IN

IN IN IN IN

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

IN

OUT

IN

OUT

IN

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

/SPDIF_OUT2

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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8 7 5 4 2 1

APPLE P/N 353S2456

4.5V POWER SUPPLY FOR CODEC

NC

DAC2/3 FSOUTPUTSE= 1.34VRMS

HP OUT ZOBEL NETWORK

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS

NC

K22 = NC

APPLE P/N 353S2592

K23 LOW = S/PDIF IN, HIGH = DP SPDIF

AUDIO CODEC

62 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C6207

2

1

C6202

2

1

C6205

27

1

3

44 41

9

28

29

24

46

25

49

10

48

47

13

5

8

11

19 20

18 17

16

32 33

36 37

31 30

35 34

23

21

22

39

40

38

15

14

12

2

45

42

43

4

7

6

26

U6201

2

1

C6204

2

1

R6295

2

1

C6297

2

1

C6298

2

1

R6297

2

1

R6296

21

R6257

2

1

R6298

2

1

R6299

2

1

C6266

1

3

5

6

2

4

VR6201

2

1

C6259

2

1

C6260

2

1

C6262

2

1

C6263

2

1

C6261

21

R6254

2

1

R6267

2

1

R6263

2

1

R6255

2

1

C6265

2

1

C6258

2

1

C6264

2

1

C6201

21

R6201

21

L6201

2

1

C6213

2

1

C6203

2

1

C6211

2

1

C6208

2

1

C6206

21

XW6201

CRITICAL

X5R

MIN_LINE_WIDTH=0.30MM

CS4206_FP

CS4206_FLYC

2.2UF

AUD_LO1_P_L

TP_AUD_LO1_N_L

AUD_LO1_P_R

AUD_LI_COM

MAKE_BASE=TRUE

AUD_LI_P_L

CS4206_VCOM

CS4206_FN

TP_AUD_LO1_N_R

AUD_LO2_P_R

TP_AUD_LO2_N_R

AUD_CODEC_MICBIAS

TP_AUD_LO2_N_L

CS4206_FLYP

AUD_MUX_CNTRL

AUD_SENSE_A

AUD_GPIO_1 AUD_GPIO_2 AUD_GPIO_3

GND_AUDIO_HP_AMP_L

PP4V5_AUDIO_ANALOG

HDA_SDOUT HDA_RST_L

AUD_LO2_P_L

VBIAS_DAC

CS4206_FLYN

AUD_LI_P_R

AUD_MIC_INP_L AUD_MIC_INN_L

HDA_SYNC

TP_AUD_DMIC_CLK

AUD_SDI_R

HDA_BIT_CLK

AUD_MIC_INN_R

AUD_MIC_INP_R

CS4206_VREF_ADC

AUD_SPDIF_OUT

VOLTAGE=0V

GND_AUDIO_HP_AMP_L

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_Z_L

AUD_LI_N_L

=PP3V3_S0_AUDIO

=PP5V_S0_AUDIO

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

HDA_SDIN0

AUD_LI_N_R

4V5_NR

AUD_Z_R

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_GPIO_1

=PP1V5_S0_AUD_DIG

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L

=PP5V_S0_AUDIO

VOLTAGE=4.5V MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.20MM

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_R

=PP3V3_S0_AUDIO

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM

4V5_REG_IN

VOLTAGE=5V

4V5_REG_EN

=PP3V3_S0_AUDIO

AUD_SPDIF_IN_CODEC

AUD_SPDIF_CHIP

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

GND_AUDIO_CODEC

VOLTAGE=4.5V

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

SYNC_DATE=06/01/2009

SYNC_MASTER=SKIPAUDIO

AUDIO: CODEC/REGULATOR

402-1

1UF

X5R

10% 10V

402-1

1UF

X5R

10% 10V

10UF

X5R

6.3V

20%

603

62

QFN

CS4206ACNZC

X5R

6.3V

20%

10UF

603

1/16W

402

100K

1%

MF-LF

9

103 66

63 62

X7R-CERM

0.1UF

16V 402

10%

0.1UF

X7R-CERM

10% 16V

402

MF-LF

1/16W

5%

39

MF-LF

5%

39

402

1/16W

402

22

1/16W

5%

MF-LF

62

68 67 66 65 64 62 6

EDUCATION

1/16W

MF-LF

5%

10K

402

MF-LF

402

5%

100K

BETTER

1/16W

16V

X7R-CERM

402

10%

0.1UF

SON

TPS71745

1UF

402-1

10% 10V X5R

68 62 6

68 67 66 65 64 62 6

62

66

62

68 67 66 65 64 62 6

68 62 6

16V

10UF

20%

CASE-B2-SM

POLY-TANT

CASE-B2-SM

16V

20% POLY-TANT

10UF

CRITICAL

10UF

CASE-B2-SM

POLY-TANT

20% 16V

10% 10V

402

0.47UF

402

5%

MF-LF

22

1/16W

NOSTUFF

100K

5%

402

MF-LF

1/16W

NOSTUFF

MF-LF

0

5%

402

MF-LF

2.67K

1/16W

1%

X5R 402

0.47UF

10% 10V

402

10V X5R

10%

0.47UF

10% 10V X5R 402

402-1

1UF

X5R

10% 10V

1/16W MF-LF

402

1%

2.21K

FERR-220-OHM

0402

63

20%

CRITICAL

10UF

6.3V 603

X5R

67

68

63

67

65

64

63 62

68 64

68 65 64

67

103 21

4.7UF

4V X5R 402

20%

CRITICAL

10%

1UF

TANT

CASE-R-HF

20V

402-LF

20%

6.3V CERM

6.3V

2.2UF

402-LF

20% CERM

SM

103

9

66 63 62

103

66 63 62

6

68 67 65 64 63 62

IN

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1ST ORDER DAC FILTER PLACEHOLDER

NET RIN = 18K OHMS

VIN = 2VRMS, CODEC VIN = 1.14 VRMS

FC = 5 HZ Max

CODEC Nom SE RIN = 20K OHMS

63 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R6305

2

1

C6304

21

R6306

2

1

R6303

2

1

C6301

2

1

R6301

21

R6300

21

C6305

21

C6303

21

C6302

21

C6300

21

R6325

2

1

C6321

2

1

C6320

21

R6324

AUD_HP_R

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GND_AUDIO_HP_AMP_L

AUD_HP_PORT_R

AUD_HP_PORT_L

AUD_HP_L

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC

AUD_LI_L

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LI_N_L

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

MIN_NECK_WIDTH=.2MM MIN_LINE_WIDTH=.3MM

AUD_LI_P_L

AUD_LI_LF

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

AUD_LI_GND

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

AUD_LI_R

MIN_LINE_WIDTH=0.3MM

AUD_LI_GND

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

AUD_LI_RF

AUD_LI_P_R

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM

AUD_LI_N_R

AUDIO: FILTER/BUFFER

SYNC_DATE=06/01/2009

SYNC_MASTER=SKIPAUDIO

21.5K

1% 1/16W MF-LF

402

10%

820PF

402

CERM

50V

NOSTUFF

MF-LF

1/16W

402

7.87K

1%

MF-LF

1/16W

1%

10

402

10%

820PF

CERM

50V 402

NOSTUFF

21.5K

1% 1/16W MF-LF

402

MF-LF

1/16W

7.87K

1%

402

10% 16V X5R

2.2UF

603

CRITICAL

10% 16V X5R 603

2.2UF

CRITICAL

10% 16V X5R

2.2UF

CRITICAL

603

10% 16V X5R 603

CRITICAL

2.2UF

66 63

66

68 67 65 64 62

66 63

66

62

66 62

1/10W

5%

0

MF-LF

603

66

62

NOSTUFF

5%

50V

C0G-CERM

2200PF

CRITICAL

603

NOSTUFF CRITICAL

603

50V

5%

C0G-CERM

2200PF

603

5% 1/10W MF-LF

0

IN

OUT

REG

VS

C1P

BOOT

C1N

OUTL1-

OUTL1+

OUTL2-

OUTL2+

OUTR1-

OUTR1+

OUTR2-

OUTR2+

NC1 NC2 NC3

FBL

COM

INL

INR FBR

MONO SHDN*

MOD

REGEN

MUTE*

THM

PGNDAGND

PVDD

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

RIN = 17.4 OHMS

TURN ON TIME: 110MS TURN ON DELAY: 150MS

FC = 19.5 HZ

AMP VOUT = 7.355VRMS

GAIN = -4.8(20K/17.4K)

POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

TWEETER SPEAKER AMPLIFIER

MAX9736B APN:353S2042

CODEC OUT = 1.335VRMS

64 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R6407

21

R6405

2

1

C6499

2

1

C6498

2

1

R6406

21

C6495

21

C6496

21

R6404

21

R6402

2

1

C6404

21

R6403

21

C6413

2

1

C6405

21

R6401

21

R6400

21

C6412

2

1

C6403

2

1

C6402

16

10

11

15

30

27

29

28

26 24

25 23

32 2

31 1

17

8

7

9

4

20

18

6

19

5

33

12

22 21

3

14

13

U6400

2

1

C6410

21

L6403

2

1

C6407

2

1

C6406

2

1

C6401

2

1

C6411

21

L6401

21

L6402

2

1

C6408

2

1

C6409

21

L6400

AUD_SPKR_OUTLO1R_NOUT

AUD_SPKR_OUTLO1R_POUT

AUD_SPKR_OUTLO1L_NOUT

AUD_SPKR_OUTLO1L_POUT

MIN_LINE_WIDTH=0.6MM

PP12V_AUD_SPKRAMP_PLANE

VOLTAGE=12V

MIN_NECK_WIDTH=0.2MM

GND_AUDIO_SPKRAMP_PLANE

AUD_L_P1

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.3MM

AUD_LO1_P_R

MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

AUDSAMPCPP1

AUDSAMPCPN1

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

AUD_L_N1

0.5MM

0.2MM

AUD_R_N1

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MAX9736_INT_1REG

AUD_R_P1

0.2MM

0.5MM

AUD_MAX9736_1VREG

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_MAX9736_1FBL AUD_MAX9736_1INL

AUD_MAX9736_1COM AUD_MAX9736_1INR

AUD_MAX9736_1FBR

AUD_BOOT1

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LO1_P_L

MIN_LINE_WIDTH=0.3MM

L01_P_L

MIN_NECK_WIDTH=0.2MM

=PP3V3_S0_AUDIO

AUD_SPKRAMP_1SHDN_L

GND_AUDIO_SPKRAMP_PLANE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V MIN_NECK_WIDTH=0.2MM

AUD_GPIO_3

GND_AUDIO_CODEC

AUD_GPIO_2

AUD_SPKRAMP_1MUTE_L

L01_P_R

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GND_AUDIO_SPKRAMP_PLANE

SYNC_DATE=06/01/2009

SYNC_MASTER=SKIPAUDIO

AUDIO: SPEAKER AMP

MF-LF

1%

402

1/16W

17.4K

1%

402

MF-LF

1/16W

20.0K

402

0.001UF

X7R

50V

10%

NOSTUFF

402-1

X5R

10%

1UF

10V

402-1

X5R

1UF

10V

10%

MAX9736BETJ+

CRITICAL

TQFN

X7R

25V

1UF

10%

805

180-OHM-1.5A

0603-LF

CRITICAL

5%

1000PF

402

NP0-C0G

25V

25V 402

NP0-C0G

5%

1000PF

0.1UF

CERM

603

16V

20%

X7R

50V

10%

603-1

0.1UF

0603-LF

CRITICAL

180-OHM-1.5A

CRITICAL

0603-LF

180-OHM-1.5A

1000PF

5%

NP0-C0G

402

25V

402

25V

1000PF

5% NP0-C0G

180-OHM-1.5A

0603-LF

CRITICAL

66

0

1/16W

5%

402

MF-LF

NOSTUFF

MF-LF

402

5%

1/16W

0

68 62

20%

100UF

TANT

16V

D-HF

20%

100UF

TANT

16V

D-HF

MF-LF

1/16W

5%

100K

402

67 65 64

68 65 62

68 67 66 65 64 62 6

62

0.47UF

X5R

10V

10%

402

62

67 65 64

10% X5R

0.47UF

402

10V

67 65 64

67 65

MF-LF

1/16W

5%

0

402

MF-LF

1/16W

1%

17.4K

402

100PF

5% CERM

50V 402

1%

MF-LF

402

1/16W

20.0K

NOSTUFF

0.001UF

402

X7R

50V

10%

402-1

10% X5R

1UF

10V

68 67 65 63 62

REG

VS

C1P

BOOT

C1N

OUTL1-

OUTL1+

OUTL2-

OUTL2+

OUTR1-

OUTR1+

OUTR2-

OUTR2+

NC1 NC2 NC3

FBL

COM

INL

INR FBR

MONO SHDN*

MOD

REGEN

MUTE*

THM

PGNDAGND

PVDD

PAD

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AMP VOUT = 7.355VRMS

GAIN = -4.8(20K/17.4K)

MAX9736B APN:353S2042

TURN ON TIME: 110MS TURN ON DELAY: 150MS

FC = 19.5 HZ

CODEC OUT = 1.335VRMS POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

WOOFER SPEAKER AMPLIFIER

RIN = 17.4 OHMS

65 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C6599

2

1

C6598

2

1

R6506

2

1

C6505

2

1

C6503

21

C6595

21

C6596

21

C6513

21

C6512

21

R6503

21

R6502

21

R6500

21

R6501

2

1

C6507

2

1

C6508

21

L6502

21

L6501

2

1

C6509

21

R6504

2

1

C6511

21

L6503

21

L6500

2

1

C6502

2

1

C6501

21

R6505

2

1

C6504

16

10

11

15

30

27

29

28

26 24

25 23

32 2

31 1

17

8

7

9

4

20

18

6

19

5

33

12

22 21

3

14

13

U6500

2

1

C6510

2

1

C6506

AUD_MAX9736_INL

AUD_MAX9736_FBL

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

AUD_R_NOUT

0.2MM

0.5MM

AUD_R_POUT

0.2MM

0.5MM

AUD_L_NOUT

MIN_LINE_WIDTH=0.5MM

AUD_L_POUT

MIN_NECK_WIDTH=0.2MM

AUD_MAX9736_COM

=PP3V3_S0_AUDIO

AUD_MAX9736_FBR

AUD_BOOT

GND_AUDIO_SPKRAMP_PLANE

AUD_SPKRAMP_MUTE_L

GND_AUDIO_SPKRAMP_PLANE

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

AUD_SPKRAMP_SHDN_L

GND_AUDIO_SPKRAMP_PLANE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MAX9736_INT_REG

MIN_NECK_WIDTH=0.2MM

L02_P_L

MIN_LINE_WIDTH=0.3MM

AUD_MAX9736_VREG

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MM

AUD_LO2_P_R

MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

L02_P_R

AUDSAMPCPP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LO2_P_L

MIN_LINE_WIDTH=0.2MM

AUDSAMPCPN

MIN_NECK_WIDTH=0.15MM

=PP3V3_S0_AUDIO

AUD_GPIO_3

GND_AUDIO_CODEC

AUD_MAX9736_INR

VOLTAGE=12V

MIN_LINE_WIDTH=0.6MM

PP12V_AUD_SPKRAMP_PLANE

MIN_NECK_WIDTH=0.2MM

AUD_SPKR_OUTLO2L_POUT

AUD_SPKR_OUTLO2L_NOUT

AUD_SPKR_OUTLO2R_POUT

AUD_SPKR_OUTLO2R_NOUT

AUDIO: SPEAKER AMP

SYNC_MASTER=SKIPAUDIO

SYNC_DATE=06/01/2009

20%

100UF

TANT

16V

D-HF

20%

100UF

TANT

16V

D-HF

100K

5% 1/16W MF-LF 402

10V

1UF

X5R

10%

402-1

10V

1UF

10% X5R

402-1

0.47UF

10%

402

10V X5R

402

0.47UF

X5R

10% 10V

67 65 64

68 64 62

68 67 66 65 64 62 6

62

67 64

10% 50V X7R 402

0.001UF

NOSTUFF

0.001UF

50V

10% X7R

402

NOSTUFF

20.0K

1/16W

402

MF-LF

1%1%

402

17.4K

1/16W MF-LF

402

1%

20.0K

1/16W MF-LF

402

1%

17.4K

402

25V

1000PF

5% NP0-C0G

25V 402

NP0-C0G

5%

1000PF

180-OHM-1.5A

0603-LF

CRITICAL

180-OHM-1.5A

0603-LF

66

402

25V

1000PF

5% NP0-C0G

MF-LF

1/16W

5%

0

402

0.1UF

603-1

10% 50V X7R

CRITICAL

0603-LF

180-OHM-1.5A

CRITICAL

0603-LF

10V

1UF

X5R

10%

402-1

CERM

20% 16V

0.1UF

603

0

MF-LF

402

5%

1/16W

100PF

5% CERM

50V 402

CRITICAL

MAX9736BETJ+

TQFN

X7R

25V

1UF

10%

805

5%

NP0-C0G

402

25V

1000PF

68 67 64 63 62

IN

OUT

IN

IN IN IN

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AUD_HP_GND_JACK

AUD_LI_GND_JACK

PP3V3_AUDIO_SPDIF_JACK

APPLE P/N 518S0723

NC

TWEETER (SECONDARY)

PROPERTIES FOR ALL SPKR NETS

WOOFER (PRIMARY)

TWEETER (SECONDARY)

REMOTE I/O CONNECTOR

SPEAKER CABLE CONNECTORS

APPLE P/N 518S0656

APPLE P/N 518S0748

INTERNAL MIC CON

APPLE P/N 518S0677

PROPERTIES FOR ALL SPKR NETS

66 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

4

3

2

1

J6602

5

4

3

2

1

J6603

21

L6618

21

L6616

21

R6610

21

R6617

21

XW6617

21

L6613

21

L6612

21

L6606

21

R6601

21

L6605

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J6600

3

2

1

5

4

J6601

21

L6615

2

1

C6600

2

1

DZ6603

2

1

DZ6615

2

1

DZ6606

2

1

DZ6608

2

1

DZ6610

2

1

DZ6612

2

1

DZ6614

21

L6609

21

L6608

21

L6607

2

1

C6601

2

1

R6600

2

1

DZ6607

2

1

DZ6604

21

L6614

2

1

DZ6609

2

1

DZ6605

2

1

DZ6611

2

1

DZ6613

2

1

DZ6601

2

1

DZ6600

21

L6604

21

L6601

21

L6603

21

L6600

21

L6602

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_HP_GND_JACK

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

AUD_HP_L_JACK

MIN_LINE_WIDTH=0.2MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM

PP3V3_AUDIO_SPDIF_JACK

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_HP_TIPDET_JACK

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

HS_MIC_HI_JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

HS_MIC_LO_JACK

AUD_SPKR_OUTLO1R_POUT

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

AUD_SPDIF_OUT_JACK

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

AUD_LI_DET_JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_L_JACK

AUD_SPKR_OUTLO1L_POUT

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

AUD_SPKR_OUTLO2L_POUT

AUD_SPKR_OUTLO1L_NOUT

AUD_SPKR_OUTLO2L_NOUT NC_J6702_3

NO_TEST

MIN_NECK_WIDTH=0.1MM

VOLTAGE=0V MIN_LINE_WIDTH=0.2MM

GND_AUDIO_MIC1_CONN

AUD_SPDIFIN_JACK

MIN_NECK_WIDTH=0.2MM

AUD_LI_GND_JACK

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

AUD_LI_R_JACK

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.2MM

AUD_MIC_IN1_P_CONN

GND_AUDIO_HP_AMP_L

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.2MM

AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_HP_TYPEDET_JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

AUD_HP_R

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_HP_L

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_HP_TIP_DET

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_R

AUD_LI_TIP_DET

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_GND

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_IP_PERPH_DET

HS_MIC_LO

VOLTAGE=0V

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

AUD_SPDIF_OUT

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_HP_TYPE

AUD_LI_L

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

HS_MIC_HI

AUD_SPDIF_IN

AUD_MIC_IN1_N_EMI

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.2MM

AUD_MIC_IN1_P_EMI

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_MIC1_IN_N

=PP3V3_S0_AUDIO

AUD_MIC1_IN_P

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

AUD_MIC_IN1_N_CONN

AUD_HP_R_JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

AUD_IP_PERPH_JACK

AUD_SPKR_OUTLO1R_NOUT

AUD_SPKR_OUTLO2R_NOUT

AUD_SPKR_OUTLO2R_POUT

SYNC_DATE=06/01/2009

SYNC_MASTER=SKIPAUDIO

Audio: MLB to I/O Conn.

M-RT-SM

78048-0473

CRITICAL

M-RT-SM

78048-0573

220-OHM-0.7A-0.28-OHM

0402

220-OHM-0.7A-0.28-OHM

0402

603

5%

0

1/10W MF-LF

MF-LF

603

5%

0

1/10W

SM

63

67

62

0402

FERR-1000-OHM

0402

FERR-1000-OHM

0402

67

103 9

5%

1/16W

402

22

MF-LF

0402

FERR-1000-OHM

20143-020E-20F

CRITICAL

F-RT-SM

53780-8603

CRITICAL

M-RT-SM

FERR-1000-OHM

0402

10V X5R

402-1

1UF

10%

6.8V-100PF

402

CRITICAL

402

6.8V-100PF

402

CRITICAL

6.8V-100PF

402

CRITICAL

6.8V-100PF

402

CRITICAL CRITICAL

402

6.8V-100PF

402

CRITICAL

6.8V-100PF

67

63 62

68

FERR-1000-OHM

0402

63

FERR-1000-OHM

0402

63

FERR-1000-OHM

0402

10V X5R

10%

0.47UF

402

1/16W

0

402

MF-LF

5%

67

65

64

65

64

68 67 65 64 62 6

67

103 62

CRITICAL

402

6.8V-100PF

402

CRITICAL

6.8V-100PF

FERR-1000-OHM

0402

6.8V-100PF

CRITICAL

402

CRITICAL

402

6.8V-100PF

402

CRITICAL CRITICAL

402

6.8V-100PF

402

CRITICALCRITICAL

6.8V-100PF

402

FERR-1000-OHM

0402

FERR-1000-OHM

0402

FERR-1000-OHM

0402

FERR-1000-OHM

0402

110

G

S

D

G

S

D

G

S

D

OUT

IN

OUT

IN

OUT

G

S

D

IN

G

S

D

G

S

D

IN

G

S

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

IPHS HS DETECT DEBOUNCE CKT

NC

DIGITAL OUT

HEADPHONE OUT

NC

PLACE ACROSS GROUND SPLIT

AUDIO GROUND RETURNS

LI INSERT DETECT

MICROPHONE IMPEDANCE MATCHING CIRCUIT

67 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

21

R6749

21

R6748

2

1

R6768

2

1

3

Q6703

2

1

R6762

4

5

3

Q6700

1

2

6

Q6700

2

1

R6730

2

1

R6731

21

R6732

2

1

C6740

21

R6700

2

1

R6797

4

5

3

Q6701

2

1

R6792

2

1

R6793

21

R6747

2

1

C6751

2

1

R6798

2

1

R6791

21

C6796

2

1

R6701

21

R6796

2

1

C6797

21

R6799

2

1

R6794

2

1

R6744

2

1

C6750

2

1

R6795

2

1

R6790

1

2

6

Q6701

1

2

6

Q6702

4

5

3

Q6702

21

L6739

21

L6738

21

XW6704

21

XW6703

21

R6743

21

XW6705

21

XW6702

21

C6795

GND_AUDIO_CODEC

AUD_IP_PERPH_DET_R

AUD_IP_PERIPHERAL_DET

AUD_IP_PERPH_DET_DB

AUD_IP_PERPH_DET_INV

AUD_IP_PER_DEB

AUD_IP_PERPH_DET

AUD_SENSE_A

=PP3V3_S0_AUDIO

AUD_SENSE_A

AUD_Q6702_D3

AUD_HP_TYPE_INV

AUD_Q6701_D6

=PP3V3_S0_AUDIO

AUD_LI_TIP_D

AUD_LI_TIP_DET_INV

GND_AUDIO_CODEC

=PP12V_S0_AUDIO_SPKRAMP

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GND_AUDIO_SPKRAMP_PLANE

PP12V_AUD_SPKRAMP_PLANE

MIN_NECK_WIDTH=0.2MM VOLTAGE=12V

MIN_LINE_WIDTH=0.6MM

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_MIC1_IN_P

AUD_MIC1_IN_G

MIN_NECK_WIDTH=0.2MM

AUD_MIC1_IN_N

MIN_LINE_WIDTH=0.3MM

AUD_CODEC_MICBIAS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_INTMICBIAS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_MIC_INN_R

AUD_LI_TIP_DET

AUD_HP_TYPE

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_HP_TIP_DET

AUD_HP_TIP_DET_INV

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_MIC_INP_R

=PP3V3_S0_AUDIO

AUDIO: Detects/Grounding

SYNC_DATE=06/01/2009

SYNC_MASTER=SKIPAUDIO

402

5%

0

MF-LF

NOSTUFF

1/16W

402

5%

0

MF-LF

NOSTUFF

1/16W

5%

MF-LF

402

100K

SOT23-HF1

2N7002

68 67 66 65 64 62 6

MF-LF

1/16W

5%

100K

402

NTZD3154NT1H

SOT-563-HF

NTZD3154NT1H

68 67 66 65 64 62 6

5%

MF-LF

402

1/16W

100K

402

MF-LF

1/16W

5%

0

1/16W MF-LF

0

5%

402

NOSTUFF

66

10% 16V X5R 402

0.1UF

17.4K

402

1% 1/16W MF-LF

1/16W 402

100K

5% MF-LF

SOT-563-HF

NTZD3154NT1H

3.40K

1%

402

1/16W MF-LF

3.40K

MF-LF

1/16W

1%

402

62

402

5%

0

MF-LF

NOSTUFF

1/16W

603-HF

6.3V

20%

TANT

CRITICAL

4.7UF

62

1/16W

5%

MF-LF

100K

402

68 67 65 64 63 62

65 64

65 64 6

67 62

66

67 62

68

67 66 65 64 62 6

66

68 67 66 65 64 62 6

67 62

66

MF-LF 402

1/16W

5%

100K

10% X5R

402

16V

0.1UF

MF-LF

10K

1%

402

1/16W

5%

402

MF-LF

1/16W

0

X5R

NOSTUFF

10% 16V

0.1UF

402

MF-LF

1/16W

5%

0

402

17

0.1%

402

1/16W

20K

CRITICAL

MF

1% MF-LF

402

39.2K

1/16W

402

10% 25V

0.0082UF

X7R

100K

1/16W

402

MF-LF

5%

402

100K

5% 1/16W MF-LF

NTZD3154NT1H

SOT-563-HF

NTZD3154NT1H

SOT-563-HF

NTZD3154NT1H

FERR-250-OHM

SM-1

FERR-250-OHM

SM-1

OMITSM

2.2K

5%

402

MF-LF

1/16W

SM

OMIT

SM

0.1UF

402

16V X5R

10%

68 67 65 64 63 62

68 67 66 65 64 62 6

IN

BI

OUT

IN

OUT

IN

OUT

IN

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASSINT*

SCL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

APN 353S2256

MIKEY RECEIVER CKT

WRITE: 0X72 READ: 0X73

0X0C

GPIO 3

CNTRL

FHP = 80 HZ

MIKEY

FLP = 8.82 KHZ

MICBIAS 80%

N/A

0X04

N/A

0X0A

0X10 0X0F

FUNCTION

PRIMARY SECONDARY

0X0B

0X09

LINE INPUT BUILT-IN MICROPHONE HEADSET MICROPHONE

0X0D(13,B,RIGHT)

TYPE

DETECT/INTERRUPT

N/A

LINE IN

N/A

N/A MCP GPIO_5

0X09 (A)

GPIO 3

ENABLE/

VOLUME

0X05

N/A

0X06

0X03

N/A

0X06

0X02

N/A

0X08

0X06

0X02

0X03

0X04

N/A

0X07

0X05

CONVERTER

0X0D (13,V22,B,LEFT) SPDIF OUT SPDIF IN

HEADPHONES

MIKEY

MIKEY N/A N/A MCP GPIO_38

0X0C (B)

68 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

11

5

6

1

7

4

9

8

2

10

3

U6806

21

C6802

21

C6801

2

1

D6800

2

1

C6853

21

R6810

2

1

R6808

2

1

C6852

2

1

C6854

21

R6805

21

R6804

21

R6803

21

R6802

2

1

R6806

2

1

R6807

21

L6840

2

1

C6899

2

1

R6852

2

1

R6809

2

1

C6857

HS_MIC_BIAS

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

VOLTAGE=3.3V

PP3V3_S0_HS_F

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

HS_SW_DET

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

HS_RX_BP

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

HS_MIC_LO

=PP3V3_S0_AUDIO

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

AUD_MIC_INN_L

AUD_MIC_INF

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.15MM

AUD_MIC_INP_L

AUD_GPIO_3

HS_MIC_HI

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

AUD_GPIO_2

=PP5V_S0_AUDIO

=I2C_AUDIO_SCL

HS_SCL HS_SDA

=I2C_AUDIO_SDA

HS_INT_L

AUD_I2C_INT_L

HS_RST

AUD_IPHS_SWITCH_EN

GND_AUDIO_CODEC

SYNC_MASTER=SKIPAUDIO

SYNC_DATE=06/01/2009

AUDIO: Mikey

25V X7R 402

10%

0.01UF

1/16W

5%

402

1K

MF-LF MF-LF

2.2K

1/16W 402

5%

402-1

10V X5R

1UF

10%

CRITICAL

DRC

CD3275

X5R

10% 16V

402

0.1UF

10% X5R

16V 402

0.1UF

1N4148WS-X-G

SOD-323-HF

NOSTUFF

65 64 62

64 62 64 62

65 64 62

402

25V X7R

10%

0.0082UF

2.2K

402

5%

MF-LF

1/16W

100K

1/16W MF-LF 402

5%

X5R

CRITICAL

20%

603

6.3V

10UF

67 66 65 64 62 6

62 6

62

66

4.7UF

603-HF

6.3V

20% TANT

CRITICAL

19

21

52

5%

0

MF-LF

402

1/16W

0

5%

1/16W

402

MF-LF

402

1/16W

0

5%

402

MF-LF

5%

0

1/16W

47K

1/16W MF-LF

5%

402

NOSTUFF

1/16W 402

MF-LF

5%

100K

FERR-1000-OHM

0402

68 67 65 64 63 62

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

12V_S0 SUPPLIED BY AC/DC, GATED BY PM_SLP_S3_L

5V_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT

3V3_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT; SLOWER THAN 5V_S0

1V8_S0 LDO SOURCED FROM 5V_S0, ENABLED BY 5V_S0 WITH RC DELAY

1V5_S0 FET SOURCED FROM 1V5_S3, GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

MCP_VCORE REGULATOR INTERNAL LOGIC POWERED FROM 5V_S3, SOURCED FROM 12V_S5,

1V05_S0 REGULATOR SHARES INTERNAL LOGIC POWER WITH 3V3_S5 REG, SOURCED FROM 12V_S0 ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

CPU_VCORE

VTT_S0_DDR_LDO

1V05_S0

MCP_VCORE

1V5_S0

1V8_S0

MCP: PM_SLP_RMGT_L

1V05_RMGT FET SOURCED FROM 1V05_S5, ENABLED BY PM_SLP_RMGT_L

PM_SLP_RMGT_L FOLLOWS PM_SLP_S4_L TIMING CLOSELY

3V3_RMGT FET SOURCED FROM 3V3_S5, ENABLED BY PM_SLP_RMGT_L

12V_S5

3V3_RMGT

1V05_RMGT

RMGT POWER RAIL SEQUENCING

3V3_S5

1V05_S5

S5 POWER RAIL SEQUENCING

3V3_S5 SWITCHER LOGIC POWERED BY INTERAL LDO, SOURCED FROM 12V_S5

12V_S5 SUPPLIED BY AC/DC MAX RAMP TIME < 50MS MAX RAMP RATE 10V/MS

1V05_S5 SWITCHER SOURCED FROM 3V3_S5 AND ENABLED FROM 3V3_S5_PGOOD

OUTPUT SOURCED FROM 12V_S5 AND ENABLED BY PM_SLP_S4_L + LDO OUTPUT GOOD

5V_S3 SWITCHER LOGIC POWERED BY INTERNAL LDO (EN BY SLP_S4_L)

5V3_S3

3V3_S3

3V3_S3 FET GATED BY PM_SLP_S4_L

1V5_S3 SWITCHER LOGIC POWERED BY 5V_S3 SO ENABLED BY PGOOD_5V_S3

MCP: PM_SLP_S4_L

S3 POWER RAIL SEQUENCING

SB: PM_SLP_S3_L

COUNT

S0 POWER RAIL SEQUENCING

SOURCED BY 12V_S5; MUST RAMP IN < 2MS

NOTE: NO SEQUENCING REQUIREMENTS FOR THESE 3 RAILS

Soft-Off (S5/M-Off)

Sleep (S3/M-Off)

Soft-Off (S5/M1)

Sleep (S3/M1)

Run (S0/M0)

State

Battery Off (G3Hot)

On

N/A

On

Off

N/A

Manageability

1

0

1

SMC_PM_G2_ENABLE

1

0

1

0 0

1

PM_S4_STATE_L

0

1

PM_SLP_S3_L

0 0

0

1

PM_SLP_S4_L

1

1 1

PM_SLP_M_L

0

1

1 1

0

SB: PM_SLP_S4_L

12V_S0

5V_S0

STARTUP (BOOT OR WAKE) TIMING

BOOT UP

SMC: IMVP_VR_ON

SMC STARTS

SHUT DOWN (SHUTDOWN OR SLEEP) TIMING

POWER RAILS SHUT DOWN CPU VTT_PWRGD LOW

POWER RAILS ON DURING THIS TIME

SLEEP OR SHUTDOWN

SUSPEND SOON

SB SAYS

SB: PM_SLP_S3_L

SB: PM_SUS_STAT#

VREGS: ALL_SYS_PWR_GD

OS COMMANDS

VREG IN RESPONSE TO

SMC SAYS SHUTDOWN CPU

SB PWROK DISABLE

CLK GEN DISABLED

CPU_PWRGD DISABLED

CPU VCORE OFF

IMVP6: VR_PWRGOOD_DELAY

SMC: IMVP_VR_ON

SB: PM_SLP_S3_L

3V3_S0

SB: PM_SLP_S4_L

VREGS: ALL_SYS_PWRGD

IMVP6 ON

99 MS

IMVP: VR_PWRGOOD_DELAY

AND GATE: MCP_PS_PGOOD ALL_SYS_PWRGD * VR_PWRGOOD_DELAY

AND GATE: MCP_PS_PGOOD

MCP: CPUPWRGD

1V5_S3

69 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=12/08/2008

POWER SEQUENCING BLOCK DIAGRAM

SYNC_MASTER=K51

IN

OUT

Y

B

A

IN

OUT

IN

Y

B

A

IN

OUT

IN

OUT

GND

V+

OUT

IN

OUT

IN

GND

V+

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

USING COMPARTOR INSTEAD OF REGULATOR

NO INTERNAL POWER TO PULL PGOOD

(PM_SLP_S3_L_BUF)

12V_S0 NEED TO BE ON BEFORE MCP REG AND 1.05_S0 REG EN

Enable FET

DELAY OF ~15MS FROM PM_SLP_S3_L

DELAY OF ~18MS FROM PM_SLP_S3_L

DELAY OF ~16MS FROM PM_SLP_S3_L

(PM_S4_STATE_L)

FROM COMPARATOR

Enable regulator

PGOOD Comparators

(9.91V/9.58V; 330MV HYSTERESIS)

IRF7410 IRF7413

3.7A

PLACE RESISTORS CLOSE TO U7020

18mOHM 35mOHM

5.8A

9.6A

I

1V05V_S0 DERIVES FROM 3.3V_S5

PM_MXM_PGOOD IS PULLED UP TO IT

WHICH GOES INTO PGOOD_SB OF MCP

FROM THIS SMC GENERATES PM_RSMRST_L DELAY IS ABOUT 200MS

To SMC (2)

Rds(on)

7mOHM

25V 20V

PM_SLP_S4_L

1

PM_SLP_S3_L

0

1

0

0 0

0

8V

Vgs +/-

12V

20V

70mOHM

115mOHM

65mOHM

1.6A

13A

8.8A IRF7406 IRF6402 SI2302

FDS4435

Battery Off (G3Hot)

Sleep (S3)

Soft-Off (S5)

State

Run (S0)

1

0

SMC_PM_G2_ENABLE (PORTABLES)

From SMC (6)

1.5V_S3 NEED TO BE ON BEFORE S0 FET ON

Enable regulator

AND GATE BY THE FACT THAT

ALL_SYS_PWRGD IS ALSO AN INPUT TO THIS

S0 RAILS PGOOD

Enable FET

PLACE SHORTS CLOSE TO PLANE CUTS

NOT COME UP, PPDDR REGULATOR HAS LOW

HYSTERESIS NUMBERS CALCULATED BASED ON OUPTPUT PULL UP OF 3.3V

PGOOD OUTPUT BECAUSE IF 5V_S3 DOES

(1.30V/1.22V; 80MV HYSTERESIS)

(1.67V/1.53V; 132MV HYSTERESIS)

(PULLUPS ARE NEAR LOADS)

PM_MXM_PGOOD IS OPEN DRAIN SIGNAL, IT’S PULLED UP TO ALL_SYS_PWRGD

MXM CARD INPUT POWER ARE 12V_S0, 3V3_S0, 5V_S0

MXM POWER SEQUENCE

ALL_SYS_PWRGD ENABLES MXM REGULATORS

Enable regulator

USB Port Switch

Power Control Signals

3.3V,5V S3 enable

Enable FET

To SMC

FROM MCP (6)

(PM_SLP_S3_L)

ENABLE REGULATOR

Enable FET

70 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C7083

21

R7083

21

R7085

21

R7054

21

R7053

21

R7052

21

R7051

21

R7050

8

7

5

6

4

U7030

2

1

R7022

2

1

C7025

2

1

R7020

2

1

R7006

8

1

7

3

5

2

6

4

U7010

21

R7099

21

R7098

2

1

R7007

21

XW7001

21

R7001

21

XW7000

21

XW7002

2

1

R7040

2

1

R7033

2

1

C7031

2

1

R7031

21

R7002

21

R7000

2

1

R7014

2

1

R7019

2

1

R7021

2

1

R7013

2

1

R7018

2

1

C7010

2

1

R7008

4

5

3

1

2

U7059

2 1

C7058

2

1

C7080

2

1

C7081

2

1

C7082

2

1

R7080

2

1

R7081

2

1

R7082

2

1

R7030

4

5

3

1

2

U7020

2

1

C7020

2

1

R7072

5

4

1

2

3

U7056

21

C7056

=PP12V_S0_VRD

PM_SLP_S3_L_AND_S0_RDY

P3V3S0_EN

MAKE_BASE=TRUE

=PVTT_S0_EN

CPUVTTS0_EN

MAKE_BASE=TRUE

MCPCORES0_EN

=PP3V3_S5_PWRCTL

MCPDDR_EN

MAKE_BASE=TRUE

PM_SLP_S4_L

P3V3S3_EN

PM_SLP_S4_SMC_L

PM_SLP_RMGT_L

ENET_EN

PGOOD_1V5_S3

12VS5_9V00_REF

=PP12V_S5_PWRCTL

PGOOD_12V_S0

PGOOD_MCPCORE_S0

MAKE_BASE=TRUE

S0_PWR_CMP_PGOOD

12VS5_1V27_REF

=MCPCORES0_EN

ALL_SYS_PWRGD_R

PGOOD_1V05_S0

RSMRST_PWRGDPGOOD_1V1_S5

=PP3V3_S5_PWRCTL

MCP_PS_PWRGD

=MCPDDR_EN

PGOOD_1V5_S3

ALL_SYS_PWRGD

ALL_SYS_PWRGD_SMC

PM_PGOOD_PVCORE_CPU

PM_MXM_PGOOD

=PPDDR_S3_PGCMP

MAKE_BASE=TRUE

S0_PWR_REG_PGOOD

=PP3V3_S5_PWRCTL

PGOOD_1V5_S0

PGOOD_1V8_S0

=PP3V3_S5_PWRCTL

PP12V_S0

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

PGOOD_5V_S0

12VS0_COMP_REF

1V5S3_PG_CMP

1V5S3_COMP_REF

1V8S0_PG_CMP

12VS0_PG_CMP

12VS5_1V60_REF

PGOOD_1V8_S0

1V8S0_COMP_REF

=PP1V8_S0_PGCMP

ALL_SYS_PWRGD_R

MAKE_BASE=TRUE

PM_MXM_EN

=PM_MXM_PGOOD_PULLUP

=PP5V_S3_PWRCTL

MAKE_BASE=TRUE

PGOOD_5V_S3

=DDRREG_EN

PM_EN_USB_PWR

PGOOD_5V_S3

5VREG_EN

S0_RDY

MAKE_BASE=TRUE

PGOOD_12V_S0

PM_SLPS3_BUF2_L

=P3V3S0_EN

P5VS0_EN

MAKE_BASE=TRUE

=P5VS0_EN

SYNC_MASTER=MASTER

SYNC_DATE=N/A

PGOOD and Power Sequencing

CERM-X5R

10%

6.3V

0.47UF

402

5%

MF-LF

1/16W

2.2K

33

PLACEMENT_NOTE=Place close to U7059

50 49

33

PLACEMENT_NOTE=Place close to U1400

73

78

33

PLACEMENT_NOTE=Place close to U1400

33

PLACEMENT_NOTE=Place close to U1400

102 21

38

PLACEMENT_NOTE=Place close to U1400

33

NOSTUFF

21

0

SOI-HF

CRITICAL

LM393

MXM

402

1/16W MF-LF

5%

100K

70 46

70

78

0.1UF

20% 16V CERM 603

402

64.9K

1% 1/16W MF-LF

49.9K

1% 1/16W MF-LF 402

70

SOI-HF

CRITICAL

LM393

70 6

5%

33

402

1/16W MF-LF

402

1/16W MF-LF

33

5%

70

1/16W

49.9K

402

MF-LF

1%

SM

OMIT

1.21K

1/16W

402

MF-LF

1%

85

SM

OMIT

SM

10K

402

1/16W MF-LF

5%

MF-LF

1% 1/16W

10K

402

0.1UF

402

X5R

16V

10%

1/16W

1K

402

MF-LF

5%

402

1%

IG

1/16W

2.0K

MF-LF

1%

402

1/16W

4.99K

100K

1%

1/16W

402

MF-LF MF-LF

1/16W

402

1%

10K

1% 1/16W MF-LF 402

MF-LF

402

1/16W

33.2K

1%

1/16W

1%

84.5K

MF-LF

402

603

CERM

16V

20%

0.1UF

1% 1/16W

402

MF-LF

49.9K

70

85

TC7SZ08AFEAPE

SOT665

50 49 9 6

CERM

10V

0.1UF

20%

402

10%

6.3V CERM-X5R 402

0.47UF 0.47UF

6.3V CERM-X5R 402

10%

0.47UF

402

6.3V

10%

CERM-X5R

39K

MF-LF

5%

1/16W

402

5% 1/16W

43K

MF-LF

402

10K

5%

402

1/16W MF-LF

74

76

78

76

74

402

5%

10K

MF-LF

1/16W

TC7SZ08AFEAPE

SOT665

20%

0.1UF

10V

402

CERM

49

MF-LF

100K

5%

402

1/16W

75

49

21

71 11

MC74VHC1G08

SOT23-5-HF

0.1uF

20%

CERM

10V

402

71 6

70 6

78 38 6

79

70 6

70

6

70 6

6

70 6

6

55

6

70 6

6

70

IN

OUT

IN

OUT

IN

OUT

IN

ISEN4-

EN_VTT

THRM_PAD

VR_HOT

VR_FAN

ISEN4+

ISEN3-

ISEN3+

ISEN2-

ISEN2+

ISEN1+

PWM2

FB

PWM1

TCOMP

PSI*

IMON

OFS

VCC

VID0

VR_RDY

VID7

VID5

VID4

VID3

VID2

VID6

VID1

SS

FS

PWM3

PWM4

TM

REF

DAC

EN_PWR

RGND

VSEN

VDIFF

ISEN1-

COMP

SYM_VER_2

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

INPUT SENSE & FILTER

1.25 mOhm loadline

and LOW when VTM/VCC > 33%.

LAYOUT: PLACE RT7101 NEAR HOT SPOT.

70A AVE

75A PEAK

VR_HOT goes HIGH when VTM/VCC < 28%

K22/K23 65W

CPU CORE

71 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

RT7101

5678

4321

RP7191

5678

4321

RP7190

21

XW7130

21

XW7120

43

21

R7169

21

L7160

2

1

C7160

2

1

C7161

21

R7133

21

R7129

21

R7128

21

R7127

21

R7135

21

R7134

2

1

R7146

21

R7145

2 1

R7143

2 1

R7139

2 1

R7167

2 1

R7166

2 1

R7165

2

1

C7152

2

1

C7151

2

1

C7150

2

1

R7162

2

1

R7161

2

1

R7160

2

1

R7116

2

1

C7130

2

1

R7164

2

1

R7130

21

R7103

17

36

38

37

40

1

2

3

4

5

6

7

15

19

39

41

18

35

16

12

25

31

20

26

8

9

23 24

29 30

22 21

28 27

10

34

14

33

32

11

13

U7100

2

1

R7104

21

R7140

2

1

C7116

2

1

C7117

2 1

R7121

2

1

C7118

2 1

R7122

2

1

C7119

2

1

C7120

2 1

R7123

2

1

C7121

2 1

R7124

2

1

C7113

2

1

C7114

2 1

R7119

2

1

C7115

2 1

R7120

2

1

R7106

2

1

R7100

2

1

R7105

2

1

R7107

2

1

R7108

2

1

R7109

21

C7109

21

R7110

2

1

C7101

2

1

C7102

2

1

C7103

21

R7111

2

1

C7110

2

1

R7112

2

1

R7114

2

1

R7115

2

1

R7117

2

1

C7112

21

R7131

2

1

C7131

21

XW7101

2

1

R7132

21

R7101

21

C7105

2

1

C7107

21

C7104

21

R7163

21

C7106

21

R7102

2 1

R7118

150

MF-LF

1/16W

1%

402

1.5K

MF-LF

402

1/16W

1%

402

MF-LF

CPU_INPUT_ISENSE_N

100

0.001UF

VR_CPU_EN_PWR

75K

402

50V

CPU_VCC_PKG_SENSE_N

4.75K

1/16W

1%

402

MF-LF

4.75K

402

MF-LF

1%

1/16W

4.75K

MF-LF

1/16W

1%

402

20.0K

1/16W

1%

402

MF-LF

22.1K

402

MF-LF

1% 1/16W

10.7K

MF-LF

402

1%

1/16W

402

CERM

50V

5%

47PF

10%

1UF

X5R

10V 402

AGND_CPU

50V

CRITICAL

1UH-20A-4.5MOHM

VR_CPU_ISNS3_R_P

VR_CPU_OFS

VR_CPU_SS

VR_CPU_PWM4

VR_CPU_VSNS_R_P

0.1UF

402

PM_PGOOD_PVCORE_CPU

PPVCORE_S0_CPU

VR_CPU_ISNS2_R_N

CPU_INPUT_ISENSE_P

PP12V_S0_CPU_FLTRD

NET_PHYSICAL_TYPE=POWER

VOLTAGE=12V

CPU_PSI_L

=PPVTT_S0_CPU

CPU_VCC_PKG_SENSE_P

VR_CPU_VSNS_R_N

VR_CPU_FS

VR_CPU_TCOMP

VR_CPU_PWM3_R

VR_CPU_ISNS3_RR_P

VR_CPU_REF

NET_PHYSICAL_TYPE=POWER

VR_CPU_VSNS_GND

VOLTAGE=0V

PP5V_S0_CPU_VCORE_VCC

NET_PHYSICAL_TYPE=POWER

VR_CPU_VSNS_VCC

VOLTAGE=1.1V

MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.3MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM

PP5V_S0_CPU_VCORE_VCC

VR_CPU_COMP_R

VR_CPU_VDIFF_R1

VR_CPU_VDIFF_R2

VR_CPU_EN_VTT

VR_CPU_IOUT_PD

VR_CPU_ISNS1_RR_P

VR_CPU_ISNS2_P

VR_CPU_ISNS1_N

PP12V_S0_CPU_FLTRD

=PP5V_S0_VRD

=PP3V3_S0_VRD

=PP12V_S0_VRD

VR_CPU_VRDHOT

VR_CPU_FAN

VR_CPU_ISNS2_N

VR_CPU_COMP

VR_CPU_DAC

VR_CPU_ISNS1_R_N

VR_CPU_ISNS1_R_P

VR_CPU_VSNS_MI

VR_CPU_ISNS3_P

VR_CPU_IMON

VR_CPU_FB

VR_CPU_VDIFF

VR_CPU_PWM2_R

VR_CPU_ISNS2_R_P

VR_CPU_PWM3

VR_CPU_ISNS3_R_N

PM_EN_PVCORE_CPU

VR_CPU_TM

VR_CPU_COMP_RC

VR_CPU_PWM2

VR_CPU_ISNS3_N

VR_CPU_FB_R

PP5V_S0_CPU_VCORE_VCC

VR_CPU_VSNS_PL

NET_PHYSICAL_TYPE=POWER

VOLTAGE=12V

PP12V_S0_CPU_FLTRD_R

VR_CPU_ISNS2_RR_P

VR_CPU_ISNS1_P

VR_CPU_PWM1

MAX_NECK_LENGTH=3MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.3MM

CPU_VID<7..0>

SYNC_MASTER=MASTER

VREG: PPVCORE_S0_CPU

SYNC_DATE=N/A

10% 50V

560PF

402

CERM

MF-LF

0

5%

1/16W

402

50V

10%

470PF

402

CERM

1/8W

5%

2.2

MF-LF

805

6.8K

0603

SM-LF

680

1/16W

5%

SM-LF

680

5% 1/16W

SM

1%

0.002

1/4W

MF

1206

CRITICAL

TH-VERT-HF

CRITICAL

270UF

8X12-TH-HF

ELEC

16V

20%

CRITICAL

ELEC 8X12-TH-HF

16V

20%

270UF

12

MF-LF

1/16W

1K

402

5%

0

1/16W

402

5%

MF-LF

5%

0

402

1/16W MF-LF

5%

MF-LF

1K

402

1/16W

10

5%

MF-LF

1/16W

402

5%

1/16W

10

100 12

NOSTUFF

1M

1/16W MF-LF 402

5%

1/16W MF-LF

1%

402

47.5

MF-LF 402

1/16W

5%

0

5%

402

0

MF-LF

1/16W

MF-LF

5%

0

1/16W

402

1/16W

402

0

5%

MF-LF

1/16W MF-LF

0

5%

402

C0G

50V

NOSTUFF

1%

402

15PF

50V

NOSTUFF

1%

15PF

402

C0G

1%

NOSTUFF

15PF

C0G

50V 402

0

1/16W

5%

402

MF-LF

5%

MF-LF

402

0

NOSTUFF

1/16W

0

1/16W

402

MF-LF

5%

NOSTUFF

0

5% MF-LF

402

1/16W

10V CERM

20%

402

NOSTUFF

5%

MF-LF

1/16W

0

402

0

5% 1/16W MF-LF

NOSTUFF

ISL6334

QFN

100 12

402

5%

0

MF-LF

1/16W

0

402

MF-LF

1/16W

5%

11

50V

5%

68PF

402-1

CERM

AGND_CPU

10% 16V

0.1UF

X5R 402

402

383

1/16W

1%

MF-LF

CERM 402

10V

0.1UF

20%

SIGNAL_MODEL=EMPTY

108

72

108

72

402-1

68PF

CERM

50V

5%

AGND_CPU

X5R

16V

10%

402

0.1UF

1%

402

MF-LF

383

1/16W

20%

402

CERM

10V

0.1UF

SIGNAL_MODEL=EMPTY

108

72

108

72

AGND_CPU

50V

68PF

5% 402-1

CERM

X5R

0.1UF

16V 402

10%

383

MF-LF

1/16W

1%

402

CERM

10V

20%

SIGNAL_MODEL=EMPTY

0.1UF

108

72

108

72

AGND_CPU

1/16W MF-LF

100K

1%

1.02K

1/16W

402

MF-LF MF-LF

1%

402

1/16W

20.0K

MF-LF 402

1/16W

5%

100K

1/16W MF-LF

1%

402

0.0022UF

402

10%

CERM

MF-LF

402

1K

1/16W

1%

SIGNAL_MODEL=EMPTY

CERM

10%

402

50V

NOSTUFF

0.0022UF

AGND_CPU

CERM

10% 402

0.0022UF

50V 402

CERM

10%

VR_CPU_IOUT

108 53

70 11

49

10K

1/16W

402

MF-LF

5%

402

CERM

16V

10%

0.01UF

2.0K

1/16W

5% MF-LF

402

AGND_CPU

1/16W

49.9K

MF-LF 402

1%

402

1/16W

1% MF-LF

49.9K

402

10% 25V CERM

33NF

0

1

2

3

4

5

6

7

402

1/16W

5%

10K

MF-LF

10% 50V

402

CERM

SM

402

5%

1/16W

1K

MF-LF

72 6

108

53

72 71 53

55 50 10 6

71

72 71 53

6

70 6

108

71

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

PHASE 2

PHASE 3

PHASE 1

THESE TWO CAPS ARE FOR EMC

OUTPUT CAPS

72 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

321

4

5

Q7243

321

4

5

Q7223

321

4

5

Q7203

321

4

5

Q7241

321

4

5

Q7221

321

4

5

Q7201

2

1

C7292

2

1

C7293

2

1

C7294

2

1

C7296

2

1

C7295

2

1

C7297

2

1

C7298

2

1

C7299

2

1

C7280

2

1

C7281

2

1

C7282

2

1

C7283

2

1

C7284

2

1

C7285

2

1

C7286

2

1

C7287

2

1

C7291

2

1

C7290

2

1

C7289

2

1

C7288

2

1

C7249

2

1

C7229

2

1

C7205

2

1

C7215

2

1

C7211

2

1

C7210

2

1

C7207

2

1

C7260

2

1

C7261

2

1

C7262

2

1

C7263

2

1

C7264

2

1

C7265

2

1

R7247

9

8

1

11

4

10

7

6

5

3 2

U7241

2

1

C7242

2

1

C7240

2

1

R7242

2

1

R7245

2

1

R7241

2

1

C7241

2

1

R7244

2

1

C7243

2

1

C7248

2

1

R7246

2

1

C7245

5

4

3

2

1

D7240

2

1

C7246

2

1

C7247

2

1

XW7241

2

1

C7250

21

L7241

2

1

C7251

2

1

XW7242

2

1

R7227

9

8

1

11

4

10

7

6

5

3 2

U7221

2

1

C7222

2

1

C7220

2

1

R7222

2

1

R7225

2

1

R7221

2

1

C7221

2

1

R7224

2

1

C7223

2

1

C7228

2

1

R7226

2

1

C7225

5

4

3

2

1

D7220

2

1

C7226

2

1

C7227

2

1

XW7221

2

1

C7230

21

L7221

2

1

C7231

2

1

XW7222

5

4

3

2

1

D7200

2

1

C7200

2

1

R7205

2

1

R7207

2

1

R7202

2

1

R7201

2

1

C7201

2

1

C7202

9

8

1

11

4

10

7

6

5

3 2

U7201

2

1

R7204

2

1

C7203

2

1

C7208

2

1

R7206

2

1

XW7201

21

L7201

2

1

C7206

2

1

XW7202

DIDT=TRUE

0.001UF

402

CERM

10% 50V

0.001UF

CERM

10% 50V

402

0.001UF

402

10% CERM

50V

2.2

MF-LF

5% 1/8W

805

2.2

1/8W MF-LF 805

5%

2.2

1/8W MF-LF 805

5%

VR_CPU_PH1_SNUB

NET_PHYSICAL_TYPE=VR_CTL_PHY

CRITICAL

RJK0348DPA

WPAK

RJK0348DPA

CRITICAL

WPAK

RJK0348DPA

CRITICAL

WPAK

RJK0353DPA

WPAK

CRITICAL

RJK0353DPA

WPAK

CRITICAL

VR_CPU_BOOT1_RC

PP12V_S0_CPU_FLTRD

CTLSH3-30M833

TLM833

SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY

VR_CPU_ISNS1_P

MF-LF

10%

OMIT

NOSTUFF

1/10W

VR_CPU_DRV2_LGATE

VR_CPU_SW2

DIDT=TRUE

VR_CPU_DRV2_PVCC

1UF

10% 16V

VR_CPU_BOOT2_RC

NET_PHYSICAL_TYPE=POWER

VR_CPU_BOOT3_RC

71 108

SM

71 108

SIGNAL_MODEL=EMPTY

SM

16V

0.01UF

CERM 402

20%

CERM 402

16V

0.01UF

20%

SIGNAL_MODEL=EMPTY

SM

16V X5R

1UF

10% 603

16V X5R-CERM

10UF

CRITICAL

10% 0805

TLM833

CTLSH3-30M833

20%

270UF

8X12-TH-HF

ELEC

16V

CRITICAL

10UF

16V X5R-CERM

CRITICAL

10% 0805

10% 16V

0.22UF

X7R 603

MF-LF

5%

0

1/10W

603

X5R 603

1/10W

5%

10

MF-LF 603

5%

1/10W

0

MF-LF

5%

MF-LF

603

X5R

1UF

16V

10%

10% 16V

1UF

X5R 603

0

603

MF-LF

5% 1/10W

71

71 108

SM

71 108

SM

SIGNAL_MODEL=EMPTY

20%

402

CERM

0.01UF

16V

20%

402

CERM

0.01UF

16V

SIGNAL_MODEL=EMPTY

SM

603

10%

1UF

16V X5R

X5R-CERM 0805

CRITICAL

10%

10UF

16V

CTLSH3-30M833

TLM833

CRITICAL

20%

270UF

8X12-TH-HF

ELEC

16V

0.22UF

603

X7R

10% 16V

603

MF-LF

1/10W

5%

0

10%

1UF

16V X5R 603

10

5% MF-LF

1/10W 603

5%

1/10W

0

MF-LF

603

10

5%

MF-LF

1/10W

603

X5R

1UF

16V

10%

16V X5R 603

1UF

CRITICAL

DFN

ISL6622

0

NOSTUFF

603

MF-LF

1/10W

5%

71

10% 603

1UF

16V X5R

20% 402

CERM

16V

0.01UF

20% 402

0.01UF

16V

CRITICAL

X5R-CERM

16V

10UF

10% 0805

20%

8X12-TH-HF

ELEC

16V

CRITICAL

0805

10%

10UF

16V X5R-CERM

X5R-CERM

16V

10UF

10%

0805

CRITICAL

6.3V CERM-X5R

20%

22UF

critical

805-3

CERM-X5R

6.3V

20%

22UF

critical

805-3

20%

22UF

CERM-X5R

6.3V 805-3

critical

CERM-X5R

6.3V

20%

22UF

critical

805-3

6.3V CERM-X5R

20%

22UF

critical

805-3

6.3V CERM-X5R

20%

22UF

critical

805-3

6.3V CERM-X5R

20%

22UF

critical

805-3

6.3V CERM-X5R

20%

22UF

critical

805-3

CERM-X5R

6.3V

20%

22UF

critical

805-3

CERM-X5R

6.3V

20%

22UF

critical

805-3

CERM-X5R

6.3V

20%

22UF

critical

805-3

CERM-X5R

6.3V

20%

22UF

critical

805-3

6.3V CERM-X5R

22UF

20%

critical

805-3

6.3V CERM-X5R

22UF

20%

critical

805-3

22UF

6.3V CERM-X5R

20%

critical

805-3

CERM-X5R

6.3V

20%

805-3

CERM-X5R

6.3V

22UF

20%

critical

805-3

CERM-X5R

6.3V

20%

22UF

critical

805-3

6.3V CERM-X5R

20%

critical

805-3

22UF

6.3V CERM-X5R

22UF

20%

805-3

critical

10%

0.22UF

16V X7R 603

603

0

MF-LF

5%

1/10W

71

10% X5R

603

1UF

16V

71 108

603

10%

1UF

X5R

16V

NOSTUFF

603

MF-LF

10

5% 1/10W

10

5%

1/10W

0

NOSTUFF

603

MF-LF

1/10W

5%

0

603

5%

603

X5R

16V

10%

SYNC_DATE=N/A

SYNC_MASTER=MASTER

VREG: PPVCORE_S0_CPU

DIDT=TRUE

VR_CPU_DRV1_BOOT

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

VR_CPU_DRV3_UGATE

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PPVCORE_S0_CPU

VR_CPU_SW3

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PP12V_S0_CPU_FLTRD

DIDT=TRUE

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV1_UVCC

VR_CPU_DRV1_PVCC

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV3_BOOT

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PPVCORE_S0_CPU

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV3_UVCC

NET_PHYSICAL_TYPE=VR_CTL_PHY

VR_CPU_PH2_SNUB

VR_CPU_ISNS2_N

NET_PHYSICAL_TYPE=VR_CTL_PHY

DIDT=TRUE

VR_CPU_PH3_SNUB

VR_CPU_DRV2_BOOT

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

VR_CPU_ISNS2_P

VR_CPU_DRV3_GDSEL

VR_CPU_DRV2_GDSEL

NET_PHYSICAL_TYPE=POWER

VR_CPU_ISNS3_N

VR_CPU_ISNS1_N

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV3_VCC

VR_CPU_PWM3

PP12V_S0_CPU_FLTRD

PPVCORE_S0_CPU

PP12V_S0_CPU_FLTRD

VR_CPU_ISNS3_P

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV1_GDSEL

VR_CPU_PWM1

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV2_UGATE

DIDT=TRUE

VR_CPU_DRV2_UVCC

VR_CPU_DRV2_VCC

PP12V_S0_CPU_FLTRD

DIDT=TRUE

VR_CPU_DRV3_LGATE

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PP12V_S0_CPU_FLTRD

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV3_PVCC

NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

critical

POLY-TANT

330UF

20%

2.5V POLY-TANT

critical

330UF

20%

2.5V POLY-TANT

330UF

critical

20%

2.5V POLY-TANT

330UF

20%

2.5V

critical critical

POLY-TANT

330UF

20%

2.5V

330UF

20%

POLY-TANT

2.5V

critical

CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM

NET_PHYSICAL_TYPE=POWER

VR_CPU_PWM2

NET_PHYSICAL_TYPE=POWER

DFN

ISL6622

603

10

CRITICAL

NET_PHYSICAL_TYPE=POWER

OMIT

NET_PHYSICAL_TYPE=POWER

353S1733

2

U7221,U7241 CRITICAL

IC,ISL6612,SYNC,FETDRV,DFN10,LF

VR_CPU_DRV1_VCC

603

MF-LF

NET_PHYSICAL_TYPE=POWER

VR_CPU_SW1

CRITICAL

ISL6622

DFN

VR_CPU_DRV1_LGATE

VR_CPU_DRV1_UGATE

1/10W

1UF

22UF

critical

CERM

CRITICAL

0.36UH

CRITICAL

0.36UH

CRITICAL

0.36UH

270UF

MMD10EE-SM

108

53 71 72

6 71 72

108

53 71 72

6 71 72

53 71 72

6 71 72

53 71 72

G

D

S

G

D

S

IN

INTVCC

MODE/PLLIN

TG

VIN

SW

BOOST

FB

ITH

TK/SS

RUN

FREQ/PLLFLTR

ILIM

GND

SENSE-

SENSE+

BG

THRM

PAD

D

S

G

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AVE=3.19A

PEAK=3.31A

K22/K23

EMC: C7304,C7356

OSCILLATED AT APPR. 330KHZ

SOFT START TIME 8MS

BURST MODE

POWER BUDGET

PLACE AT L7320.1

PLACE XW CLOSE

TO L7320

(5VS3_VOUT)

PM_SLP3_BUF1_L

RB

RA

5V_S3

LTCMODE

STATE

1 0

0 1

1 0

CONT MODE

S3

S0

(5VS3_FB)

Mode

TO L7320

PLACE XW CLOSE

5VREG_PS_L

PLACE AT Q7330

EMC: C7353,C7354

5V S3 REGULATOR

73 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

3

Q7303

2

1

C7331

2

1

C7307

2

1

R7302

2

1

C7306

2

1

C7303

2

1

C7316

2

1

C7334

2

1

C7325

2

1

C7317

2 1

R7304

2

1

R7307

2

1

R7336

2

1

C7363

2

1

R7362

2

1

C7322

2

1

C7315

2 1

D7301

2

1

C7345

11

2

17

13 14

6 5

1

15

3

10

7

8

16

4

12

9

U7300

2

1

XW7300

2

1

R7312

2 1

R7310

2

3

1

Q7360

2

1

R7301

2

1

R7311

2 1

R7324

2 1

C7326

321

4

5

Q7335

5

4

3

2

1

D7300

321

4

5

Q7330

2 1

L7320

2

1

C7309

2

1

R7306

2

1

R7305

2

1

C7305

2

1

XW7301

2

1

C7301

2

1

C7356

2

1

C7342

2

1

C7354

2

1

C7300

2

1

C7335

2

1

C7353

2

1

C7332

2

1

C7302

2

1

C7304

100K

CSD58856Q5A

5% 1/10W

402

MIN_NECK_WIDTH=0.4MM

5V_SNUBBER

1/10W

MIN_NECK_WIDTH=0.2 MM

LTC3851EUD

603

5V_BOOT1_R

DIDT=TRUE

MF-LF

1

5%

1000PF

C0G-CERM

50V

1

MF-LF

5%

603

2.2UF

PP5V_S3_REG

MIN_LINE_WIDTH=0.4MM

5V_BOOT1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

=PPVIN_S5_P5VS3

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

5VS3_BG

5VS3_SENSEP

=PPVIN_S5_P5VS3

DIDT=TRUE

5VS3_SENSEN_R

5VS3_FB

DIDT=TRUE

5VS3_TG

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

5VS3_SENSEN

5VS3_TK_SS

5VS3_ITH

MIN_LINE_WIDTH=0.25MM

PM_SLPS3_BUF1_L

PM_SLPS3_BUF1_R_L

5VS3_ITH_R

LTCMODE

5VS3_SENSE

5VREG_PS_L

LTCMODE

LTCINTVCC

5VREG_EN

5VS3_FREQ

SWITCHNODE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

5VS3_SW

DIDT=TRUE

5V_S3 REGULATOR

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SI2301BDS

CRITICAL

SM-HF

402

0.1UF

10% 16V X5R

100PF

50V CERM 402

5%

24.9K

MF-LF 402

1/16W

1%

10% 50V

402

CERM

0.001UF

0.1UF

10%

402

25V X5R

402

16V

10%

CERM

0.01UF

402

10% 50V

CERM

0.001UF

35V

4.7UF

10%

X5R-CERM

0805

5% CERM

20PF

402

50V

402

CERM

10V

10%

0.22UF

0

402

5% 1/16W MF-LF

1%

1/16W

1.24K

MF-LF

402

1/16W

1%

MF-LF

1.5K

805-1

10UF

CERM

20%

6.3V

50V

5%

100PF

CERM

402

SOD-123-HF

B0530WXG

0805

X5R-CERM

16V

10UF

10%

603

16V X5R

CRITICAL

QFN

OMIT

SM

100K

1/16W

5% MF-LF

402

1/16W

402

MF-LF

10K

5%

MMBT3904G

SOT23

X5R-CERM

10%

10UF

16V

0805

X5R

10%

0.1UF

25V 402

1/16W MF-LF

402

5%

73

X5R-CERM

16V

10%

0805

10UF

100K

1/16W

5% MF-LF

402

CASE-D3L-SM

CRITICAL

20%

POLY-TANT

6.3V

330UF

X5R 402

10% 25V

0.1UF

MLP5X6-LFPAK-Q5A

CRITICAL

CTLSH3-30M833

TLM833

MLP5X6-LFPAK-Q5A

CSD58856Q5A

CRITICAL

SM

2.2UH-10A-11.6M-OHM

CRITICAL

50V

CERM

402

100PF

5%

402

MF-LF

1/16W

1%

8.06K

1/16W

402

MF-LF

1%

43.2K

20%

CRITICAL

330UF

CASE-D3L-SM

POLY-TANT

6.3V

OMIT

SM

6.3V

20% CERM

805-1

10UF

402

10% 25V

0.1UF

X5R

270UF

ELEC

20%

8X12-TH-HF

16V

CRITICAL

402

10% X5R

25V

0.1UF

110 6

73 6

94 9

73

108

G

D

S

G

D

S

OUT

IN

SOFT

RBIAS

VIN

UGATE

VW

VSS

VSEN

VR_ON

VO

VID1

VID0

THRM_PAD

RTN

PVCC

PHASEPGOOD

PGND

FDE

FB

BOOT

VDD

VID2 VID3

IMON

AF_EN

VDIFF

COMP

LGATE

ICOMP

ISN

OCSET

ISP

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

PLACE AT L7460

EMC: C7467,C7457

1.1V DEFAULT, OTHER VALUES TBD

VID<2:0> Voltage

000 +1.100V

(MCPCORES0_ICOMP)

CONNECT SENSE LINES TO CLOSEST

F = 200-300 KHZ

(MCPCORES0_VO)

(=PPMCPCORE_S0_REG)

MCP CORE

MAX CURRENT: 20A

Vout = See below

EMC:

(MCPCORES0_ISN)

(MCPCORES0_LGATE)

OF MCP

MCPCORE AND GND BALL

PLACE XW NEAR THE MCP,

(MCPCORES0_COMP)

(MCPCORES0_FB)

(MCPCORES0_VDIFF)

(MCPCORES0_RTN)

(MCPCORES0_ISP)

(MCPCORES0_VSEN)

(MCPCORES0_VW)

(MCPCORES0_UGATE)

PLACE AT Q7460

(MCPCORES0_PHASE)

74 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

R7485

2

1

R7484

4

15

8

29

12

14

27

26

25

24

7

16

18

33

2

9

1

22

1931

20

3

23

21

13 11

28

10

32

6

5

17

30

U7401

2

1

R7483

2

1

C7483

2

1

C7484

2

1

C7467

21

XW7462

21

XW7463

21

R7479

21

R7477

21

R7478

21

C7480

21

C7481

21

C7482

2

1

C7479

2

1

R7471

2

1

R7476

2

1

R7472

2

1

C7476

21

R7468

21

R7466

2

1

C7470

21

R7492

2

1

R7463

21

R7490

21

R7491

2

1

R7461

2

1

C7461

21

XW7461

2

1

R7475

2

1

R7473

21

R7474

2

1

C7462

2

1

R7469

321

4

5

Q7465

2

1

C7455

2

1

C7472

21

C7464

21

R7460

2

1

C7477

2

1

C7473

321

4

5

Q7460

2

1

C7478

2

1

R7470

2

1

R7464

21

R7465

2

1

C7463

2

1

R7462

2

1

XW7460

2

1

R7467

21

L7460

2

1

C7471

2

1

C7460

2

1

C7474

2

1

C7475

2

1

C7457

2

1

XW7402

2

1

C7465

2

1

C7469

2

1

C7466

2

1

C7468

10K

1/16W 402

MF-LF

1%

1K

10%

0.499

1/10W 603

MF

1%

10%

402

CERM

50V

0.0022UF

X7R

402

X5R

=PPVIN_S0_MCPCORE

MCP_ISL6263D

MIN_LINE_WIDTH=0.4MM

DIDT=TRUE

MIN_NECK_WIDTH=0.4MM

MCPCORES0_SNUBBER

MCPCORES0_UGATE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

PGOOD_MCPCORE_S0

MCP_VID3

MCP_ISL6263D_OFFSET0

MCP_VID<2>

MCP_VID2_R

MCPCORES0_SOFT

MCPCORES0_VSEN

MCPCORES0_FDE

=MCPCORES0_EN

MCPCORES0_RTN

MCPCORES0_COMP

MCPCORES0_FB

MCP_VID1_R

MCP_VID0_R

MCPCORES0_IMON MCPCORES0_BOOT

DIDT=TRUE

0.25 MM

0.2 MM

0.6 mm

VOLTAGE=5V

5V_S3_MCPREG_VIN

0.25 MM

0.2 MM

MCPCORES0_ISP_R

MCPCORES0_ISN_R

MCPCORES0_VDIF_C

MCPCORES0_COMP_C

PPMCPCORE_S0_REG

MCPCORES0_RSEN_L

MCPCORES0_RSEN_H

PPMCPCORE_S0_REG

MCPCORES0_ISN

MCP_VID<0>

MCP_VID<1>

MCPCORES0_VDIFF

MCPCORES0_VO

MCPCORES0_ISP

MCPCORES0_LGATE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE

MCPCORES0_VW

MCPCORES0_ICOMP

MCPCORES0_RBIAS

DIDT=TRUE

=PP3V3_S3_MCPREG

GND_MCPCORES0_AGND

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm

MCPCORES0_OCSET

PPMCPCORE_S0_REG

=PP5V_S3_MCPREG

MCPCORES0_PHASE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MCP CORE REGULATOR

SYNC_MASTER=MASTER

SYNC_DATE=N/A

U7401 MCP_ISL9563ACRITICALINTERSIL ISL9563A

1

353S2497

MCP_ISL6263DINTERSIL ISL6263D353S2303 U7401

1

CRITICAL

10UF

25V X5R

10%

805

MCP_ISL6263D

402

1/16W MF-LF

1%

20.0K

1%

20.0K

MF-LF

1/16W 402

QFN

OMIT

CRITICAL

ISL9563A

20.0K

MF-LF

1/16W

402

1%

603

X5R

4V

20%

10UF

20%

4V X5R 603

10UF

0.1UF

X5R

10% 25V

402

SM

OMIT

SM

OMIT

402

X5R

25V

21

402

MF-LF

2.21K

1/16W

1%

1% 1/16W MF-LF

402

133K

1% 1/16W MF-LF

402

100

68PF

50V

CERM

5%

402-1

CERM

402

50V

560PF

10%

402

CERM

50V

10%

560PF

10%

402

X7R

50V

0.001UF

OMIT

SM

1% 1/16W

402

100

MF-LF

402

1% 1/16W MF-LF

6.98K

402

1% MF-LF

150K

1/16W

0.1UF

X7R-CERM

402

10% 16V

1/16W

402

MF-LF

1%

20

402

1% 1/16W MF-LF

10% X7R

402

50V

0.001UF

0

MF-LF

5%

402

1/16W

1% MF-LF

402

1/16W

100

5%

MCP_ISL9563A

1/16W

402

0

MF-LF

1/16W

402

MF-LF

0

5%

70

MF-LF

1/16W 402

5%

16V 402

1UF

X5R

10%

SM

OMIT

MF-LF

1/16W 402

1%

59.0K

MF-LF

1/16W

10K

402

1%

0

1/10W

603

5%

MF-LF

402

16V X5R

10%

CSD58857Q5

MLP5X6-LFPAK-Q5

25V

10%

0.1UF

X5R

25V 402

10%

CERM

0.0027UF

402

10% 50V

1/10W

2.2

5%

MF-LF

603

X5R

25V

10%

0.1UF

402

0.12UF

CERM-X5R

10.0V 402

10%

MLP5X6-LFPAK-Q5A

CSD58856Q5A

CRITICAL

402

X5R

25V

0.1UF

10%

MF-LF

1% 1/16W

10K

402

11.3K

MF-LF

1/16W

1%

402

CRITICAL

0603-LF

10KOHM-5%

603

4V

X5R

10UF

20%

OMIT

MF-LF

1/16W 402

1%

1K

1.0UH-29A-2.5MOHM

CRITICAL

8X12-TH-HF

270UF

ELEC

20% 16V

CRITICAL

10UF

X5R

25V

10%

805

10UF

10%

805

25V X5R

0.22UF

603

16V

MCPCORES0_BOOT_R

0.1UF

10%

CRITICAL

2.5V POLY-TANT

330UF

20%

CRITICAL

POLY-TANT

2.5V

330UF

CASE-D2E-SM

1UF

0.1UF

MMD12EZ-SM

SWITCHNODE

SM

CRITICAL

108 54

74 54 6

6

74 54 6

6

108

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GNDPGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILTV5IN

SYM (2 OF 2)

IN IN

NC NC

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PEAK = 11.28A AVG = 6.72A

FEEDBACK THROUGH SHORT

14.75A MAX OUTPUT

<Rb>

<Ra>

EMC CAPS

f = 400 kHz

(Q7335 limit)

PLACE CLOSE TO L7530

VTTREF

S3

VDDQ

1.5 V DDR SUPPLY

VTT Enable

S0 S5

S3 LO HI

S5

VTT

HI ON

ON OFF OFF

ON

ON OFF

OFF

LO

ON

PPDDR_S3_REG VOUT = 1.5V

(DDRREG_DRVH)

VDDQ/VTTREF Enable

SHOULD NOT NEED TP

VOUT = 1.50V

(DDRREG_FB)

Vout = 0.75V * (1 + Ra / Rb)

LO

HI

STATE

EMC CAPS PLACE CLOSE TO FET

Vout = VDDQSNS/2

Vout = VTTREF

(DDRREG_VDDQSNS)

(DDRREG_CSGND)

(DDRREG_LL)

(DDRREG_DRVL)

10mA max load

VDDQ PGOOD

75 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

XW7501

2

1

C7563

2

1

R7562

2

1

C7512

2

1

C7513

2

1

C7511

2

1

C7510

321

4

5

Q7530

321

4

5

Q7535

21

R7525

21

L7530

2

1

C7545

2

1

C7540

2

1

C7541

2

1

XW7500

2

1

C7555

2

1

XW7545

2

1

C7531

2

1

C7530

2

1

R7510

2

1

C7500

2

1

C7550

21

XW7535

21

XW7560

2

1

C7560

2

1

C7561

21

R7505

2

1

C7505

2

5

1

24

23

8

9

22

15

14

25

11

10

13

18

12

7

4

20

3

19

21

17

16

6

U7500

2

1

C7520

2

1

C7532

2

1

R7521

2

1

R7520

21

C7525

MLP5X6-LFPAK-Q5

CRITICAL

CSD58857Q5

CRITICAL

MLP5X6-LFPAK-Q5A

CSD58856Q5A

CASE-D2-HF1

330UF-0.009OHM

POLY

CRITICAL

2V

20%

CASE-D2-HF1

330UF-0.009OHM

2V

20% POLY

CRITICAL

1.5UH-22A-4MOHM

PLACEMENT_NOTE=PLACE NEXT TO L7530

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

PP5V_S3_DDRREG_V5FILT

DDRVTT_EN

=PPVIN_S5_DDRREG

DIDT=TRUE

=PP5V_S3_DDRREG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST_R

DDRREG_VBST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

DDRREG_VTTSNS

NO_TEST=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_PGND

TP_PGOOD_DDRREG_S3

DDRREG_FB

MIN_NECK_WIDTH=0.4MM

DIDT=TRUE

MIN_LINE_WIDTH=0.4MM

1V5_SNUBBER

SWITCHNODE

SWITCH_NODE=TRUE

DDRREG_LL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH

DIDT=TRUE

GATE_NODE=TRUE

PPDDR_S3_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS

DDRREG_CSGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

DIDT=TRUE

DDRREG_DRVL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_CS

=DDRREG_EN

PPVTT_S3_DDR_BUF

PPVTT_S0_DDR_LDO

1.5V DDR SUPPLY

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SM

5%

1000PF

NP0-C0G

25V 402

NOSTUFF

MF

1%

0.499

603

1/10W

NOSTUFF

603

16V CERM

0.1UF

20%

16V CERM 603

0.1UF

20%

603

20% 16V CERM

0.1UF

16V CERM 603

20%

0.1UF

5%

603

1/10W MF-LF

0

MSQ12111R5LF-TH

6.3V

20%

10UF

X5R 603

SM

10UF

X5R

20%

6.3V 603

SM

ELEC

16V

20%

270UF

CRITICAL

8X12-TH-HF

270UF

ELEC

16V

20%

CRITICAL

8X12-TH-HF

5.90K

MF-LF

1%

402

1/16W

70

603

CERM

20%

6.3V

4.7UF

78 9

10% 16V

0.033UF

X5R 402

SM

PLACEMENT_NOTE=Place next to Q7335

SM

CRITICAL

20%

22UF

6.3V

CERM-X5R

805-3

20%

22UF

6.3V

CRITICAL

CERM-X5R 805-3

MF-LF

1/16W

5%

4.7

402

10V X5R

1UF

10%

402-1

CRITICAL

QFN

TPS51116

100PF

402

CERM

5%

50V

NO STUFF

10%

10UF

0805

X5R-CERM

16V

15.0K

402

1% MF-LF

1/16W

15.0K

MF-LF

1/16W

1%

402

0.1UF

20%

603

CERM

25V

6

30 6

6

OUT

ILIM1

NC

GND

PGND

THRM_PAD

ILIM2

REFIN2

EN2

OUT2

VIN

POK1

REF

TON

EN_LDO

LDO

LDOREFIN

BYP FB1

EN1

PVCC

LGATE2

BOOT2

PHASE2

UGATE2

POK2

SKIP*

VCC

OUT1

LGATE1

PHASE1

UGATE1

BOOT1

IN

D1

G1

S2

G2

S1/D2

D1

G1

S2

G2

S1/D2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CRITICAL BOM OPTION

TABLE_5_HEAD

PART# DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

AVE=0.46A

PEAK=0.69A

K22/K23

AVE=2.88A

PEAK=5.28A

K22/K23

POWER BUDGET

VTT_FSB_S0

FSB VTT AND 3.3V S5 RAILS

EN1 (PPVTT_S0) CONTROLLED SEPARATELY

Vout = 1.212V for Wolfdale

f = 200 kHz

(R7614 LIMIT)

6.7A MAX OUTPUT

PLACE CLOSE TO FET

EMC CAPS

(PVTTS0_LGATE)

(P1V05S0_UGATE)

EN REG ASAP AFTER LDO OUT

EN_LDO TIED TO 12V_S5 TO EN LDO FIRST & REGULATOR INTERNAL LOGIC GETS POWER EN2 (3V3_S5) IS TIED TO VCC, TIED INTERNALLY TO PVCC TIED EXTERNALLY TO LDO OUT. SO REGULATOR IS ENABLED AS SOON AS LDO OUTPUT IS GOOD

<Rb>

INPUT POWER OF 12V_S5

NC

Vout = 0.7V * (1 + Ra / Rb)

(PVTTS0_PHASE)

(=PVTTS0_EN)

SELECTS SWITCHING FREQUENCY

(3.3V NOMINAL)

SEL A3V3 S5

NC

EMC CAPS PLACE CLOSE TO FET

TO L

PLACE CLOSE

EMC CAPS

POWER BUDGET

EN LDO ASAP

<Ra>

TO L

PLACE CLOSE

EMC CAPS

INPUT POWER OF 12V_S0

76 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

5

4

3

7

6

1

2

Q7660

543

7

6

1

2

Q7610

2

1

C7678

2

1

C7679

2

1

C7608

2

1

C7609

2

1

R7663

2

1

C7662

2

1

C7663

2

1

R7662

21

L7660

2

1

C7694

2

1

C7626

2

1

C7625

2

1

C7624

2

1

C7623

2

1

C7611

2

1

C7622

2

1

C7613

2

1

R7622

2

1

R7643

2

1

XW7651

2

1

C7615

2

1

C7617

2

1

C7612

2

1

C7610

2

1

C7680

21

R7610

2

1

C7601

2

1

C7614

2

1

R7614

2

1

C7620

21

L7610

21

XW7616

2

1

R7620

2

1

C7616

2

1

C7621

2

1

R7621

2

1

C7683

2

1

C7681

6

3

2615

2

33

29

32

1

19

28

13

2516

22

3010

20

5

2318

8

7

3112

21

11

4

2714

9

2417

U7600

21

XW7650

2

1

C7685

2

1

R7667

2

1

C7670

2

1

R7650

21

R7666

2

1

C7689

2

1

R7675

2

1

C7666

2

1

C7675

2

1

C7691

2

1

C7692

2

1

C7693

110K

MF-LF 402

1% 1/16W

110K

1% MF-LF

402

1/16W

16V

10UF

=PPVIN_S0_PPVTT_FSB

=PPVIN_S5_P3V3S5

DIDT=TRUE

SWITCHNODE

MIN_NECK_WIDTH=0.20 MM

3V3S5_SW

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.20 MM

3V3S5_BG

DIDT=TRUE

MIN_NECK_WIDTH=0.20 MM

3V3S5_TG

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

PVTTS0_UGATE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

PVTTS0_LGATE

DIDT=TRUE

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12V

PPVIN_S5_3V3_VTT_R

MIN_NECK_WIDTH=0.1 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

3V3REG_VCC

3V3S5_OUT

MIN_NECK_WIDTH=0.20 MM

GND_PP3VREG_SGND

MIN_LINE_WIDTH=0.6 mm

PGOOD_1V05_S0

PGOOD_3V3_S5

DIDT=TRUE

MIN_NECK_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM

PVTT_SNUBBER

PP5V_S5_LDO

3V3REG_TON

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.25MM

PVTTS0_BOOT

3V3S5_ILIM

3V3S5_REF

3V3REG_VCC

3V3REG_TON

3V3S5_REF

=PP12V_S5_REG

0.2MM

0.25MM

3V3_BOOT2_R

DIDT=TRUE

0.25MM

0.2MM

3V3_BOOT2

PVTTS0_BOOT_R

MIN_LINE_WIDTH=0.25MM

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MIN_NECK_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MM

3V3_SNUBBER

PP3V3_S5_REG

PVTTS0_FB PVTTS0_ILIM

=PVTT_S0_EN

PVTTS0_VSNS

SWITCHNODE

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PVTTS0_PHASE

SYNC_DATE=N/A

SYNC_MASTER=MASTER

FSB VTT/3.3V S5 SUPPLIES

WPAK

CRITICAL

RJK0384DPA

WPAK

RJK0384DPA

CRITICAL

10% 16V

X5R-CERM

10UF

08050805

10UF

X5R-CERM

16V

10%

X5R-CERM

0805

16V

10UF

X5R-CERM

0805

16V

10%

10UF

1%

MF

1/10W

0.499

603

NOSTUFF

402

5% 25V NP0-C0G

1000PF

NOSTUFF

1000PF

5% 25V NP0-C0G 402

NOSTUFF

0.499

1/10W

1% MF

603

NOSTUFF

CRITICAL

MMD06EZ-SM

2.2UH-10A-13.6MOHM

6.3V

20% CERM

10UF

805-1

603

CERM

0.1UF

20% 16V

20%

0.1UF

603

CERM

16V

20%

0.1UF

603

CERM

16V

20%

603

CERM

16V

0.1UF

20%

603

CERM

16V

20%

603

16V

0.1UF

CERM

0805

X5R-CERM

10%

5%

402

1/16W MF-LF

0

402

MF-LF

1/16W

5%

0

NOSTUFF

SM

OMIT

X5R-CERM

10% 16V

0805

10UF

16V

0805

X5R-CERM

10UF

10% 16V

0805

X5R-CERM

0805

X5R-CERM

10% 16V

10UF

0805

10UF

16V

10%

1/10W

5%

0

MF-LF

603

16V

1206

X5R

10UF

10%

50V

10% X7R

603-1

0.1UF

50V

100PF

5%

CERM

402

NO STUFF

CRITICAL

1.5UH-12A

MMD06EZ-SM

SM

PLACEMENT_NOTE=Place next to C7516

1%

402

MF-LF

1/16W

7.32K

0.1UF

16V CERM

20%

603

402

0.5% 1/16W MF

10.0K

70

10% 16V

10UF

0805

16V

100UF

CRITICAL

20%

POLY

6.3X9-TH

ISL6237

QFN

CRITICAL

OMIT

SM

0.1UF

10% 16V

X7R-CERM

402

10%

603

16V

1UF

X5R

2.2

805

5% 1/8W MF-LF

603

MF-LF

1/10W

0

5%

603

20%

4.7UF

CERM

6.3V

5%

402

MF-LF

1/16W

200K

25V

10% X5R

402

0.1UF

10% 16V

1UF

603

X5R

70

20% 16V

CERM

0.1UF

603

20%

10UF

CERM

6.3V 805-1

330UF

20%

CRITICAL

6.3V

POLY-TANT

CASE-D3L-SM

2.5V

POLY-TANT

330UF

20%

0.1UF

PPVTT_S0_FSB_REG

CASE-D2E-SM

VOLTAGE=0V

X5R-CERMX5R-CERM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

OMIT

152S1078

1

IND,PWR,1.5UH,20%,9A,12mOHM

L7610 CRITICAL

CRITICAL

10%

6

108

6

76

6

76

6

108

6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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A

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77 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

BLANK PAGE

IN

D

SG

D

SG

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

IN

G

S

D

DGS

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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PAGE

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A

B

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345678

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8 7 5 4 2 1

60mA max load @ 0.75V 45mW max power

LOW THROUGH VTT TERMINATION RESISTORS.

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW

5V S0 FET

3.3V S0 FET

3.3V S3 FET

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY. MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

MCP79 DDRVTT FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

1.5V S0 FET

78 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

1

4

5

Q7850

1

4

5

Q7825

1

4

5

Q7800

3 2 1

4

5

Q7853

1

9

6

8

2

3

4

7

5

U7853

2

1

C7853

1

9

6

8

2

3

4

7

5

U7850

2

1

C7850

1

9

6

8

2

3

4

7

5

U7825

2

1

C7825

1

9

6

8

2

3

4

7

5

U7800

2

1

C7800

1

2

6

Q7875

2

1

C7876

2 1

R7875

2

1

R7876

4

5

3

Q7875

CRITICAL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAX_NECK_LENGTH=3 MM

PGOOD_1V5_S0

=PPDDR_S3_S0FET

P3V3S3_EN

=P3V3S0_EN

=PP12V_S5_PWRCTL

NET_SPACING_TYPE=PWR

VOLTAGE=1.5V

MAKE_BASE=TRUE

PP1V5_S0_FET

P3V3_S0_EN

VTTCLAMP_EN

=PP5V_S3_VTTCLAMP

=PPVTT_S0_VTTCLAMP

DDRVTT_EN

VTTCLAMP_L

=PP12V_S5_PWRCTL

PP3V3_S0

=PP3V3_S5_S0FET

=MCPDDR_EN

=PP12V_S5_PWRCTL

P5V_S0_EN

PP5V_S0

P1V5_S0_EN

=PP12V_S5_PWRCTL

P3V3_S3_EN

PP3V3_S3

=PP3V3_S5_S3FET

=P5VS0_EN

=PP5V_S3_S0FET

PGOOD_5V_S0

S3 & S0 FETs

SYNC_DATE=N/A

SYNC_MASTER=MASTER

70

CRITICAL

IRFH7914PBF

PQFN

CRITICAL

IRFH7914PBF

PQFN

IRFH7914PBF

CRITICAL

POWER33

FDMC8296

70

TDFN

SLG5AP001

402

0.1UF

10% X5R

16V

70

SLG5AP001

TDFN

CRITICAL

402

0.1UF

10% X5R

16V

SLG5AP001

TDFN

CRITICAL

70

X5R

0.1UF

10%

402

16V

70

CRITICAL

SLG5AP001

TDFN

402

0.1UF

10% X5R

16V

SOT563

SSM6N15FEAPE

CERM

50V

20%

402

0.001UF

NO STUFF

603

MF-LF

1/10W

5%

10

402

5% 1/16W MF-LF

100K

SOT563

SSM6N15FEAPE

75 9

54

6

78 70 38 6

6

78 70 38 6

6

78 70 38 6

110 6

78 70 38 6

110 6

6

THRM_PAD

PVINAVIN

PGMODE

OVT

FB

AGND PGND

SWEN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

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THE INFORMATION CONTAINED HEREIN IS THE

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PAGE

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A

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8 7 5 4 2 1

<Ra>

MAX Current = 0.55A

Vout = 1.1V

<Rb>

(ENABLED AT 2,8V MINIMUM)

MCP 1.1V_S5 AUXC SUPPLY

VOUT = 0.6V * (1 + Ra / Rb)

FREQ = 1Mhz

79 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C7901

2

1

R7923

2

1

C7983

2

1

R7980

2

1

R7981

21

L7920

2

1

C7982

2

1

C7920

2

1

R7922

2

1

C7981

11

1

10

2

8

5

7

4

6

9

3

U7950

BQA

CRITICAL

TPS62510

X5R

0.1UF

10% 16V

402

5% MF-LF

402

1

1/16W

805-3

CERM-X5R

6.3V

20%

22UF

402

50V

5% CERM

22PF

CRITICAL

2.2UH-3.25A

IHLP1616BZ-SM

402

1/16W

1% MF-LF

60.4K

402

1/16W MF-LF

1%

51.1K

805-3

CERM-X5R

20%

6.3V

22UF

23.2K

1% MF-LF

402

1/16W

NOSTUFF

0.1UF

10% 16V X5R 402

1V1 S5 POWER SUPPLY

SYNC_DATE=10/31/2008

SYNC_MASTER=K51

PP1V1_S5_REG

1V1S5_FB

P1V1_S5_EN

PGOOD_1V1_S5

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

1V1S5_AVIN

=PP3V3_S5_P1V1S5

MIN_NECK_WIDTH=0.1MM

SWITCHNODE

1V1S5_SW

MIN_LINE_WIDTH=0.3MM

DIDT=TRUE

6

70

6

VIN

GND

FB

SW

EN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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8 7 5 4 2 1

MAX CURRENT = 300MA

VOUT = 0.5 * (1 + RA/RB)

<RA)

<RB)

VOUT = 1.8V

MCP ONLY 1.8V_S0 POWER SUPPLY

80 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C8025

2

1

R8020

21

L8010

2

1

C8015

2

1

C8013

2

1

C8014

2

1

C8012

2

1

R8011

2

1

R8010

2

1

C8016

1

5

2

4 3

U8001

IG

PP1V8_S0_REG

20%

IG

DIDT=TRUE

MIN_LINE_WIDTH=0.3MM

1V8_SW

SWITCHNODE

MIN_NECK_WIDTH=0.1MM

=PP5V_S3_1V8

1V8_FB

1V8S0_EN

=PP5V_S0_PWRCTL

1V8 POWER SUPPLY

SYNC_MASTER=MASTER

SYNC_DATE=N/A

6.3V

IG

402

CERM

10%

0.68UF

MF-LF

402

1/16W

1%

49.9K

IG

10UH-1.7A

IG

MSCDRI5D48-SM

CRITICAL

50V

5%

402

CERM

100PF

NOSTUFF

805

IG

10V

10UF

20% X5R

10UF

805

X5R

10V

20%

33PF

402

NOSTUFF

CERM

5%

50V

IG

1% 1/16W MF-LF

402

18.2K

402

1/16W

1%

47.5K

IG

MF-LF

10UF

X5R

10V 805

SOT23-5-LF

CRITICAL

TPS62200

IG

6

108

6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

B

C

345678

D

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8 7 5 4 2 1

82 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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A

B

C

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D

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8 7 5 4 2 1

83 OF 110

051-7845

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

BLANK PAGE

SYNC_MASTER=K51

SYNC_DATE=12/08/2008

3V3

5V

PWR_SRC

(4 OF 4)

PCI-E

DP

(2 OF 4)

PEX_TX15*

DP_A_AUX*

PEX_TX1*

PEX_TX13

PEX_TX11*

PEX_TX7*

PEX_TX8*

PEX_TX9

PEX_TX10

PEX_STD_SW*

PEX_TX15

PEX_TX14* PEX_TX14

PEX_TX13*

PEX_TX12* PEX_TX12

PEX_TX11

PEX_TX10*

PEX_TX9*

PEX_TX8

PEX_TX7

PEX_TX6* PEX_TX6

PEX_TX5* PEX_TX5

PEX_TX4* PEX_TX4

PEX_TX3* PEX_TX3

PEX_TX2* PEX_TX2

PEX_TX1

PEX_TX0* PEX_TX0

PEX_REFCLK*

PEX_REFCLK

PEX_RST*

DP_C_HPD

DP_D_HPD

DP_B_HPD

DP_A_HPD

PEX_RX15* PEX_RX15

PEX_RX14* PEX_RX14

PEX_RX13* PEX_RX13

PEX_RX12* PEX_RX12

PEX_RX11* PEX_RX11

PEX_RX10* PEX_RX10

PEX_RX9* PEX_RX9

PEX_RX8* PEX_RX8

PEX_RX7* PEX_RX7

PEX_RX6* PEX_RX6

PEX_RX5* PEX_RX5

PEX_RX4* PEX_RX4

PEX_RX3* PEX_RX3

PEX_RX2* PEX_RX2

PEX_RX1* PEX_RX1

PEX_RX0* PEX_RX0

CLK_REQ*

DP_C_L0*

DP_C_L0

DP_C_L1*

DP_D_L0*

DP_C_L1

DP_D_L0

DP_C_L2*

DP_D_L1*

DP_C_L2

DP_D_L1

DP_C_L3*

DP_D_L2*

DP_C_L3

DP_D_L2

DP_D_L3*

DP_D_L3

DP_B_L0*

DP_B_L0

DP_B_L1*

DP_A_L0*

DP_B_L1

DP_A_L0

DP_B_L2*

DP_A_L1*

DP_B_L2

DP_A_L1

DP_B_L3*

DP_A_L2*

DP_B_L3

DP_A_L2

DP_A_L3*

DP_A_L3

DP_C_AUX*

DP_C_AUX

DP_D_AUX*

DP_D_AUX

DP_B_AUX*

DP_B_AUX

DP_A_AUX

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

A

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8 7 5 4 2 1

Page Notes

Signal aliases required by this page:

APPLE P/N: 516S0699

BOM options provided by this page:

- =PP3V3_S0_MXM

PLATFORM DEPENDENT

(NOT NECESSARILY THE SAME FOR EVERY MODULE)

MXM SPEC POWER REQUIREMENTS

VOLTAGE

PWR (7-20V)

- =PP5V_S0_MXM

(NONE)

12.5 W

3.3 W

POWER

CURRENT

UP TO 10 A

2.5 A

1.0 A

3V3 5V

Power aliases required by this page:

- =PPV_S0_MXM_PWRSRC

- MXM

84 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

84 86

90 92

96 98

102 104

108 110

114 116

120 122

136 138

48 50

54 56

60 62

66 68

72 74

78 80

142 144

148 150

19

85 87

91 93

97 99

103 105

109 111

115 117

121 123

135 137

49 51

55 57

61 63

67 69

73 75

79 81

141 143

147 149

156

153

155

224 226

218 220

212 214

206 208

236

230 232

217 219

211 213

205 207

199 201

234

223 225

264 266

258 260

252 254

246 248

274

270 272

271 273

265 267

259 261

253 255

276

277 279

154

J8400

E2 E1

9

7

5

3

1

280

278

J8400

2

1

C8415

2

1

C8416

2

1

R8400

2

1

C8414

2

1

C8413

2

1

C8412

2

1

C8410

2

1

C8401

2

1

C8400

MXM_PCIE_STD_SWING_L

MXM_RESET_L

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_N<11>

MXM_DP_A_ML_P<0> MXM_DP_A_ML_N<1> MXM_DP_A_ML_P<1> MXM_DP_A_ML_N<2> MXM_DP_A_ML_P<2>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<6>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_N<12>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<15>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_P<11>

MXM_PCIE_D2R_P<13> MXM_PCIE_D2R_N<14> MXM_PCIE_D2R_P<14> MXM_PCIE_D2R_N<15>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<3>

MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<0>

MXM_PCIE_R2D_N<2> MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<5> MXM_PCIE_R2D_P<5> MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<8>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_P<10>

MXM_PCIE_R2D_N<10>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_P<0>

MXM_PCIE_R2D_N<11>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_P<14>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_N<15>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_N<13>

MXM_PCIE_R2D_N<12>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_N<0>

MXM_DP_C_AUX_P

MXM_DP_B_ML_N<0>

MXM_CLKREQ_L

MXM_DP_B_AUX_P

MXM_DP_B_HPD

MXM_DP_B_ML_P<0>

CLK_100M_MXM_N

CLK_100M_MXM_P

MXM_DP_C_HPD

MXM_DP_D_HPD

MXM_DP_A_HPD

MXM_DP_C_ML_N<0> MXM_DP_C_ML_P<0> MXM_DP_C_ML_N<1>

MXM_DP_D_ML_N<0>

MXM_DP_C_ML_P<1>

MXM_DP_D_ML_P<0>

MXM_DP_C_ML_N<2>

MXM_DP_D_ML_N<1>

MXM_DP_C_ML_P<2>

MXM_DP_D_ML_P<1>

MXM_DP_C_ML_N<3>

MXM_DP_D_ML_N<2>

MXM_DP_C_ML_P<3>

MXM_DP_D_ML_P<2> MXM_DP_D_ML_N<3> MXM_DP_D_ML_P<3>

MXM_DP_B_ML_N<1>

MXM_DP_A_ML_N<0>

MXM_DP_B_ML_P<1> MXM_DP_B_ML_N<2> MXM_DP_B_ML_P<2> MXM_DP_B_ML_N<3> MXM_DP_B_ML_P<3>

MXM_DP_A_ML_N<3> MXM_DP_A_ML_P<3>

MXM_DP_C_AUX_N

MXM_DP_D_AUX_N MXM_DP_D_AUX_P

MXM_DP_B_AUX_N

=PP3V3_S0_MXM

MXM_DP_A_AUX_N MXM_DP_A_AUX_P

=PPV_S0_MXM_PWRSRC

=PP3V3_S0_MXM

=PP5V_S0_MXM

MXM PCIe, DP & Power

SYNC_DATE=10/31/2008

SYNC_MASTER=K51

B35P101-0121

MXM

F-RT-SM

CRITICAL

B35P101-0121

MXM

F-RT-SM

0.001UF

50V 402

X7R

10%

MXM

22UF

20%

6.3V

MXM

CERM-X5R 805-3

MXM

MF-LF

5%

1/16W

402

100K

0.001UF

50V 402

10% X7R

MXM

0.001UF

50V

10% X7R

402

MXM

0.001UF

50V 402

10% X7R

MXM

50V 402

X7R

10%

MXM

0.001UF

22UF

20%

6.3V

MXM

CERM-X5R 805-3

MXM

20%

6.3X5.5-SM1

ELEC

35V

22UF

85

87

102 86

107 91

102 86

87

91

87

107 91

87

107 91

87

85 84 6

107 93

53

85 84 6

6

WC*

SDA

SCL

E2/NC2 E1/NC1 E0/NC0

VSS

VCC

GPIO0

VGA_DISABLE*

TH_OVERT* TH_PWM

LVDS_DDC_CLK

LVDS_UTX1

LVDS_UTX2*

RSVD1

PNL_PWR_EN

LVDS_UTX1*

RSVD2

LVDS_UTX2

LVDS_UTX3*

LVDS_LCLK

PRSNT_R*

LVDS_LTX3

DVI_HPD

PWR_EN

SMB_CLK

LVDS_LTX0

LVDS_LTX0*

LVDS_LTX1

LVDS_LTX2

LVDS_LTX2*

LVDS_LTX3*

LVDS_UTX0

LVDS_UTX0*

LVDS_UTX3

PNL_BL_EN

PRSNT_L*

PWRGOOD

VGA_BLUE VGA_GREEN VGA_HSYNC VGA_RED VGA_VSYNC

VGA_DDC_DAT

GPIO1 GPIO2

HDMI_CEC

OEM0 OEM1 OEM2 OEM3 OEM4 OEM5

OEM7

VGA_DDC_CLK

RSVD3 RSVD4 RSVD5

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19

RSVD21

SMB_DAT

TH_ALERT*

LVDS_UCLK* LVDS_UCLK

RSVD20

LVDS_LCLK*

LVDS_LTX1*

RSVD6

RSVD0

RSVD22 RSVD23

PWR_LEVEL

LVDS_DDC_DAT

PNL_BL_PWM

OEM6

WAKE*

SYSTEM MANAGEMENT

(1 OF 4)

LVDS

ANALOG DISPLAY

POWER/THERMAL

MANAGEMENT

GNDGND

(3 OF 4)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FLOAT = LOW SWING GND = HIGH SWING

Signal aliases required by this page:

- =PP3V3_S0_MXM

Page Notes

Power aliases required by this page:

- =PM_MXM_PGOOD_PULLUP

STUFF FOR WRITE PROTECT

BOM options provided by this page:

PULLED TO GROUND ON MXM WE DON’T USE CARD DETECT

PLACE CLOSE TO J7800

MXM SYSTEM INFORMATION ROM

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR

SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

I2C ADDRESS: AC

- =SMB_MXM_THRM_CLK

- =SMB_MXM_THRM_DATA

PULLUPS & PULLDOWNS AT MXM CONNECTOR

FLOAT = NORMAL VGA MODE GND = SECONDARY DISPLAY CARD

85 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2 1

R8510

2 1

R8504

53

52

283

282

E4

275

269

268

263

47

262

257

256

251

250

E3

244

228

222

221

46

216

215

210

209

204

203

198

197

192

191

37

186

185

180

179

174

173

166

157

152

151

36

146

145

140

139

134

133

125

124

119

118

17

113

112

107

106

101

100

95

94

89

88

15

83

82

77

76

71

70

65

64

59

58

13

11

J8400

4

162

168

164

170

21

158

160

172

24

20

22

32

34

231

229

227

167

165

163

161

16

14

249

247

12

245

243

242

241

240

239

238

237

235

233

159

10

6

18

8

2

281

23

27

25

45

44

43

42

41

40

39

38

175 177

181 183

187 189

193 195

169 171

182 184

188 190

194 196

200 202

176 178

33

35

29

30

28

2631

J8400

2 1

R8503

21

R8501

7

4

8

5

6

3 2 1

U8570

2

1

C8570

2

1

R8570

21

R8500

MXM

NOSTUFF

0

5%

402

0

MF-LF

NOSTUFF

0

402

5% 1/16W MF-LF

402

CERM

20% 10V

0.1UF

MXM

100K

1/16W5%

402

MF-LF

M24C02-WMN6TPHF

SO8

CRITICAL

MXM

100K

5%MF-LF 1/16W

402

MF-LF 5%

10K

1/16W

B35P101-0121

MXM

F-RT-SM

MXM

B35P101-0121

402

5%MF-LF 1/16W

1/16W

MXM I/O

SYNC_DATE=10/31/2008

SYNC_MASTER=K51

MXM_PCIE_STD_SWING_L

TP_MXM_VGA_GREEN TP_MXM_VGA_HSYNC

MXM_PNL_BL_EN

=PP3V3_S0_MXM

MXM_DETECT_R

=PP3V3_S0_MXM

MXM_LVDS_A_DATA_N<0> MXM_LVDS_A_DATA_P<0>

MXM_VGA_DISABLE_L

MXM_LVDS_DDC_CLK

MXM_ROM_WP

MXM_LVDS_DDC_DAT

MXM_DETECT_L

PM_MXM_EN PM_MXM_PGOOD MXM_PWR_LEVEL

=SMB_MXM_THRM_SCL =SMB_MXM_THRM_SDA

MXM_ALERT_L MXM_OVERT_L

MXM_DETECT_L MXM_DETECT_R

TP_MXM_WAKE_L

MXM_LVDS_A_DATA_N<1> MXM_LVDS_A_DATA_P<1>

MXM_LVDS_A_DATA_P<2>

MXM_LVDS_A_DATA_N<3> MXM_LVDS_A_DATA_P<3>

MXM_LVDS_B_CLK_P

MXM_LVDS_B_CLK_N

MXM_LVDS_B_DATA_P<3>

MXM_LVDS_B_DATA_N<3>

MXM_LVDS_B_DATA_N<2>

MXM_LVDS_B_DATA_P<1>

MXM_LVDS_B_DATA_N<1>

MXM_LVDS_B_DATA_P<0>

MXM_LVDS_B_DATA_N<0>

MXM_LVDS_B_DATA_P<2>

PM_MXM_PGOOD

MXM_LVDS_A_DATA_N<2>

TP_MXM_VGA_BLUE

TP_MXM_VGA_VSYNC

TP_MXM_VGA_RED

TP_MXM_VGA_DDC_DAT

TP_MXM_VGA_DDC_CLK

TP_MXM_TH_PWM

MXM_LVDS_A_CLK_P

MXM_LVDS_A_CLK_N

TP_MXM_DVI_HPD

MXM_LVDS_DDC_DAT

MXM_LVDS_DDC_CLK

TP_MXM_GPIO0 TP_MXM_GPIO1 TP_MXM_GPIO2

TP_MXM_HDMI_CEC

=PM_MXM_PGOOD_PULLUP

MXM_PNL_PWR_EN

MXM_PNL_BL_PWM

MXM_VGA_DISABLE_L

84

85

89

6 84 85

85

6 84 85

89

85

85 89

9 85

70

70 85

50

52

50

9 85

85

89

70 85

89

85 89

70

89

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MXM RX CAPS

MXM TX CAPS

86 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

2

1

C8631

2

1

C8629

2

1

C8630

2

1

C8627

2

1

C8628

2

1

C8626

2

1

C8625

2

1

C8624

2

1

C8623

2

1

C8621

2

1

C8622

2

1

C8619

2

1

C8620

2

1

C8617

2

1

C8618

2

1

C8616

2

1

C8615

2

1

C8614

2

1

C8613

2

1

C8612

2

1

C8611

2

1

C8610

2

1

C8609

2

1

C8608

2

1

C8607

2

1

C8606

2

1

C8605

2

1

C8603

2

1

C8604

2

1

C8601

2

1

C8602

2

1

C8600

2

1

C8661

2

1

C8659

2

1

C8660

2

1

C8663

2

1

C8662

2

1

C8658

2

1

C8656

2

1

C8657

2

1

C8655

2

1

C8654

2

1

C8650

2

1

C8651

2

1

C8653

2

1

C8652

2

1

C8649

2

1

C8648

2

1

C8647

2

1

C8646

2

1

C8645

2

1

C8644

2

1

C8643

2

1

C8642

2

1

C8640

2

1

C8641

2

1

C8639

2

1

C8638

2

1

C8637

2

1

C8636

2

1

C8634

2

1

C8635

2

1

C8633

2

1

C8632

MXM_PCIE_R2D_P<11> MXM_PCIE_R2D_N<11>

MXM_PCIE_D2R_N<15>

PEG_D2R_N<0>

PEG_D2R_P<3>

PEG_D2R_N<12>

PEG_D2R_N<10>

PEG_R2D_C_N<5>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0> MXM_PCIE_D2R_N<0>

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_P<13> MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<12> MXM_PCIE_D2R_N<12>

MXM_PCIE_R2D_N<15>

PEG_R2D_C_P<0>

MXM_PCIE_R2D_P<14>

PEG_R2D_C_N<2>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_N<10>

PEG_R2D_C_P<13>

PEG_R2D_C_N<14> PEG_R2D_C_P<14>

PEG_R2D_C_N<15> PEG_R2D_C_P<15>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_N<12>

PEG_R2D_C_P<4>

PEG_R2D_C_P<1>

MXM_PCIE_D2R_N<14>

MXM_PCIE_D2R_P<14>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<10>

PEG_R2D_C_P<10>

MXM_PCIE_R2D_P<5>

MXM_PCIE_R2D_P<8>

PEG_D2R_P<4>

PEG_R2D_C_P<12>

PEG_R2D_C_N<12>

PEG_R2D_C_N<13>

PEG_R2D_C_N<10>

PEG_R2D_C_N<11>

PEG_R2D_C_P<5>

PEG_R2D_C_N<6> PEG_R2D_C_P<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<8> PEG_R2D_C_P<8>

PEG_R2D_C_P<11>

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

PEG_R2D_C_N<7>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_P<4> MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_P<2> MXM_PCIE_R2D_N<2>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_N<0>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<7> MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_P<6> MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<0>

MXM_PCIE_D2R_P<3> MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_N<11>

MXM_PCIE_D2R_P<11>

PEG_D2R_P<7>

PEG_D2R_P<12>

PEG_D2R_P<6>

PEG_D2R_N<7>

PEG_D2R_P<10>

PEG_D2R_N<14>

PEG_D2R_N<4>

PEG_D2R_N<9> PEG_D2R_P<9>

PEG_D2R_N<11>

PEG_D2R_N<13> PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<11>

PEG_D2R_N<6>

PEG_D2R_N<2>

PEG_D2R_P<2>

MXM_PCIE_R2D_N<13>

PEG_D2R_N<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<15>

PEG_D2R_N<1>

PEG_D2R_P<1>

PEG_D2R_P<0>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_P<6>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_R2D_C_N<0>

PEG_R2D_C_N<4>

PEG_R2D_C_P<3>

PEG_R2D_C_N<3>

PEG_R2D_C_P<2>

PEG_R2D_C_N<1>

MXM PCIE CAPS

SYNC_MASTER=MASTER

SYNC_DATE=N/A

102 84

16V 40210%

0.1UF

X5R

MXM

102 84

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V X5R 40210%

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

10% X5R 402

0.1UF

16V

MXM

16V10% 402

0.1UF

X5R

MXM

16V X5R 402

0.1UF

10%

MXM

16V10% X5R

0.1UF

402

MXM

16V10% X5R

0.1UF

402

MXM

102 84

0.1UF

40210% 16V X5R

MXM

102 84

0.1UF

40210% 16V X5R

MXM

0.1UF

16V10% X5R 402

MXM

0.1UF

16V10% X5R 402

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

40216V10% X5R

0.1UF

MXM

0.1UF

16V10% X5R 402

MXM

0.1UF

10% 16V 402X5R

MXM

0.1UF

402X5R10% 16V

MXM

402X5R10% 16V

0.1UF

MXM

0.1UF

402X5R10% 16V

MXM

102 9

402X5R10% 16V

0.1UF

MXM

0.1UF

402X5R10% 16V

MXM

0.1UF

40210% X5R16V

MXM

0.1UF

16V 402X5R10%

MXM

0.1UF

402X5R10% 16V

MXM

0.1UF

X5R10% 40216V

MXM

102 9

0.1UF

402X5R10% 16V

MXM

0.1UF

402X5R10% 16V

MXM

0.1UF

402X5R10% 16V

MXM

0.1UF

402X5R10% 16V

MXM

102 9

402X5R10% 16V

0.1UF

MXM

0.1UF

402X5R10% 16V

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

0.1UF

402X5R10% 16V

MXM

102 9

10%

0.1UF

X5R 40216V

MXM

102 9

16V10% X5R 402

0.1UF

MXM

0.1UF

402X5R10% 16V

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

102 84

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R 402

0.1UF

MXM

10% X5R

0.1UF

40216V

MXM

16V10% X5R 402

0.1UF

MXM

16V10% X5R

0.1UF

402

MXM

16V X5R 40210%

0.1UF

MXM

X5R 402

0.1UF

10% 16V

MXM

10% 16V

0.1UF

X5R 402

MXM

10% 16V 402

0.1UF

X5R

MXM

102 84

10% 402

0.1UF

X5R16V

MXM

102 9

102 84

102 9

0.1UF

402X5R10% 16V

MXM

10%

0.1UF

X5R 40216V

MXM

0.1UF

16V X5R10% 402

MXM

402X5R10% 16V

0.1UF

MXM

40216V

0.1UF

X5R10%

MXM

102 84

10% X5R

0.1UF

40216V

MXM

102 9

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(NONE)

Page Notes

(NONE)

- =PP5V_DP_AUX

BOM options provided by this page:

Power aliases required by this page:

Signal aliases required by this page:

UNUSED DP INTERFACES

MCP CONNECTIONS

87 OF 110

051-7845

A.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MXM_DP_C_HPD

MXM_DP_C_ML_P<0..3>

MAKE_BASE=TRUE

NC_MXM_DP_C_AUX_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MXM_DP_C_ML_N<0..3>

NO_TEST=TRUE

NC_MXM_DP_C_ML_P<0..3>

MAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MXM_DP_C_AUX_P

NO_TEST=TRUE

MXM_DP_C_AUX_N

MXM_DP_C_ML_N<0..3>

MAKE_BASE=TRUE

TP_MXM_DP_C_HPD

MXM_DP_C_AUX_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MXM_DP_B_ML_N<0..3>

MXM_DP_B_ML_N<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MXM_DP_B_AUX_N

MXM_DP_B_AUX_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MXM_DP_B_ML_P<0..3>

MXM_DP_B_ML_P<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MXM_DP_B_AUX_P

MXM_DP_B_AUX_P

MAKE_BASE=TRUE

TP_MXM_DP_B_HPD

MXM_DP_B_HPD

NC_MXM_DP_D_ML_N<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MXM_DP_D_ML_N<0..3>

NC_MXM_DP_D_ML_P<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

MXM_DP_D_ML_P<0..3>

NC_MXM_DP_D_AUX_N

NO_TEST=TRUE

MAKE_BASE=TRUE

MXM_DP_D_AUX_N

NC_MXM_DP_D_AUX_P

NO_TEST=TRUE

MAKE_BASE=TRUE

MXM_DP_D_AUX_P

TP_MXM_DP_D_HPD

MAKE_BASE=TRUE

MXM_DP_D_HPD

MAKE_BASE=TRUE

GPU_CLK100M_PCIE_P

CLK_100M_MXM_P

MAKE_BASE=TRUE

GPU_CLK100M_PCIE_N

CLK_100M_MXM_N

PEG_RESET_L

MAKE_BASE=TRUE

MXM_RESET_L

MXM ALIASES

SYNC_MASTER=MASTER

SYNC_DATE=N/A

84

102 9

84

102 9

84

90 9

84

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER SIZE

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PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=K51

SYNC_DATE=10/01/2008

BLANK PAGE

SYM_VER-1

SYM_VER-1SYM_VER-1

SYM_VER-1

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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DRAWING NUMBER SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

PLACE CHOKES CLOSE TO J9002

SHARE 0-OHM RES WITH CHOKE PADS

IG pullups always stuffed to prevent floating inputs

IN MXM CONFIG, PULL-UPS ON CARD

WE WILL ROUTE FROM MCP TO THE 0-OHM RESISTORS, THEN ON THROUGH MXM TO THE LCD CONNECTOR

THESE RESISTOR OPTIONS SELECT BETWEEN MCP AND MXM TO DRIVE THE INTERNAL DISPLAY

IG-ONLY O-OHM RESISTORS NEED TO BE PLACED AT THE MXM CONNECTOR TO AVOID STUBS

IF THIS ROUTING IS NOT FEASIBLE, MXM ALIASES WILL BE REPLACED WITH ADDITIONAL 0-OHM RESISTORS

89 OF 110

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3

4

2

1

RP8954

3

4

2

1

RP8953

3

4

2

1

RP8952

3

4

2

1

RP8951

4 3

21

L8954

21

R8957

4 3

21

L8953

21

R8956

21

R8955

4 3

21

L8952

21

R8954

21

R8953

4 3

21

L8951

3

4

2

1

RP8950

21

R8951

21

R8952

4 3

21

L8950

21

R8950

21

R8907

4 3

21

L8903

21

R8906

21

R8905

4 3

21

L8902

21

R8904

4 3

21

L8901

21

R8903

21

R8902

21

R8900

21

R8901

4 3

21

L8900

2

1

R8933

2

1

R8931

21

R8932

21

R8930

2

1

R8923

21

R8922

2

1

R8921

21

R8920

3

4

2

1

RP8903

3

4

2

1

RP8902

3

4

2

1

RP8901

4 3

21

L8904

3

4

2

1

RP8980

2

1

R8980

2

1

R8981

3

4

2

1

RP8904

3

4

2

1

RP8900

LCD_CONN_A_DATA_P<1>

LVDS_IG_B_DATA_P<2>

LVDS_B_DATA_N<3>

MAKE_BASE=TRUE

LCD_CONN_B_CLK_P

=PP3V3_S0_VIDEO

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

MXM_LVDS_DDC_CLK

LVDS_IG_BKL_PWM

LCD_BKL_ON

MAKE_BASE=TRUE

LCD_CONN_B_DATA_P<3>

LVDS_IG_B_DATA_P<0>

MXM_LVDS_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_B_DATA_N<2>

MAKE_BASE=TRUE

MXM_LVDS_B_DATA_P<0>

LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N

MXM_LVDS_B_CLK_P MXM_LVDS_B_CLK_N

LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3>

MXM_LVDS_B_DATA_N<3>

MXM_LVDS_B_DATA_P<3>

LVDS_IG_B_DATA_N<2>

MXM_LVDS_B_DATA_N<2>

LVDS_IG_B_DATA_P<1>

LVDS_B_CLK_N

MAKE_BASE=TRUE

LVDS_B_CLK_P

MAKE_BASE=TRUE

LCD_CONN_B_CLK_N

LVDS_B_DATA_P<3>

MAKE_BASE=TRUE

LCD_CONN_B_DATA_N<3>

LCD_CONN_B_DATA_N<2>

LVDS_B_DATA_P<2>

MAKE_BASE=TRUE

LCD_CONN_B_DATA_P<2>

LVDS_B_DATA_N<1>

MAKE_BASE=TRUE

LCD_CONN_B_DATA_N<1>

LCD_CONN_B_DATA_P<1>

LVDS_B_DATA_P<1>

MAKE_BASE=TRUE

MXM_LVDS_B_DATA_N<1>

MXM_LVDS_B_DATA_P<1>

LVDS_IG_B_DATA_N<0>

MXM_LVDS_B_DATA_N<0>

LVDS_B_DATA_N<0>

MAKE_BASE=TRUE

LVDS_B_DATA_P<0>

MAKE_BASE=TRUE

LCD_CONN_B_DATA_N<0>

LCD_CONN_B_DATA_P<0>LCD_CONN_A_DATA_P<0>

LCD_CONN_A_DATA_N<0>

LVDS_A_DATA_P<0>

MAKE_BASE=TRUE

LVDS_A_DATA_N<0>

MAKE_BASE=TRUE

LVDS_A_DATA_P<1>

MAKE_BASE=TRUE

LVDS_A_DATA_N<1>

MAKE_BASE=TRUE

MXM_LVDS_A_DATA_P<0> MXM_LVDS_A_DATA_N<0>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

MXM_LVDS_A_DATA_P<1> MXM_LVDS_A_DATA_N<1>

LCD_CONN_A_DATA_N<1>

LCD_CONN_A_DATA_P<2> LCD_CONN_A_DATA_N<2>

LCD_CONN_A_DATA_P<3> LCD_CONN_A_DATA_N<3>

LVDS_A_DATA_P<2>

MAKE_BASE=TRUE

LVDS_A_DATA_N<2>

MAKE_BASE=TRUE

LVDS_A_DATA_P<3>

MAKE_BASE=TRUE

LVDS_A_DATA_N<3>

MAKE_BASE=TRUE

LCD_CONN_A_CLK_P

LCD_CONN_A_CLK_N

LVDS_A_CLK_P

MAKE_BASE=TRUE

LVDS_A_CLK_N

MAKE_BASE=TRUE

MXM_LVDS_A_DATA_P<2>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

MXM_LVDS_A_DATA_N<2>

LVDS_IG_A_DATA_N<2>

LVDS_IG_A_DATA_P<2>

MXM_LVDS_A_DATA_P<3> MXM_LVDS_A_DATA_N<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_P<3>

MXM_LVDS_A_CLK_N

MXM_LVDS_A_CLK_P

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

MXM_LVDS_DDC_DAT

MAKE_BASE=TRUE

LCD_CONN_DDC_DAT

MAKE_BASE=TRUE

LCD_CONN_DDC_CLK

MXM_PNL_BL_EN

MXM_PNL_BL_PWM

LVDS_IG_BKL_ON

LCD_PANEL_PWR

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MXM_PNL_PWR_EN

LCD_BKL_PWM

MAKE_BASE=TRUE

LCD MUX & CHOKES

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

DLP0NS

90-OHM

NOSTUFF

0

1/16W

5%

402

MF-LF

0

1/16W

5%

402

MF-LF

NOSTUFF

90-OHM DLP0NS

MF-LF

402

5%

1/16W

0

DLP0NS

90-OHM

NOSTUFF

MF-LF

402

5%

1/16W

0

1/16W

5%

402

MF-LF

402

5%

1/16W

0

1/16W

5%

402

MF-LF

NOSTUFF

90-OHM DLP0NS

10K

5%

MF-LF

1/16W

402

NOSTUFF

402

1K

5%

MF-LF

1/16W

IG

1/16W

5%

0

MF-LF

MXM

402

MF-LF

5%

0

1/16W

IG

1K

IG

MF-LF

402

5%

1/16W

402

5%

MF-LF

1/16W

IG

0

1K

IG

MF-LF

402

5%

1/16W

402

5%

MF-LF

1/16W

IG

0

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

CRITICAL

DLP0NS

90-OHM

SM-LF

5%

0

1/16W

IG

2.7K

402

MF-LF

1/16W

5%

MF-LF

402

2.7K

1/16W

5%

1/16W

0

5%

IG

SM-LF

1/16W

0

5%

IG

SM-LF

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

CRITICAL

DLP0NS

90-OHM

MF-LF

402

5%

1/16W

0

DLP0NS

90-OHM

NOSTUFF

0

1/16W

5%

402

MF-LF

0

1/16W

5%

402

MF-LF

NOSTUFF

90-OHM DLP0NS

MF-LF

402

5%

1/16W

0

MF-LF

402

5%

1/16W

0

DLP0NS

90-OHM

NOSTUFF

1/16W

IG

5%

SM-LF

0

1/16W

IG

5%

SM-LF

0

1/16W

5%

402

MF-LF

0

1/16W

5%

402

MF-LF

NOSTUFF

90-OHM DLP0NS

MF-LF

402

5%

1/16W

0

MF-LF

402

5%

1/16W

0

107 90

107 18

107

107 90

90 6

18

85

18

90 6

107 90

107 18

85

107 18

107

85

107 18

85

107 18

85

107 18

85

107 18

107

107 90

107

107 90

107

107 90

107

107 90

107

85

107 18

85

107

107 90

107 90 107 90

107 90

107

85

107 18

85

107 90

107

107 90

107

85

107 18

85

107 18

85

107 18

85

107 18

85

90

85

18

90 18

85

90

Y

B

A

Y

B

A

GND

G

S

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

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8 7 5 4 2 1

518S0685

INTERNAL LCD INTERFACE

Signal aliases required by this page:

IG, MXM

(NONE)

- =PP3V3_S0_VIDEO

- =PP12V_S0_LCD

Power aliases required by this page:

Page Notes

BOM options provided by this page:

PANEL POWER CONTROL

IF NOT BYPASSED, THIS CAN BE USED TO FORCE THE USE OF THE BACKLIGHT ENABLE SIGNAL EVEN IF THE INVERTER DOES NOT TAKE THIS AS AN INPUT

IT MAY BE BYPASSED IF THE PWM SOURCE IS THE MXM

BACKLIGHT CONTROL SUPPORT

PLACE NEAR J9002

THIS AND GATE CIRCUIT PROVIDES BACKLIGHT GLITCH PREVENTION WHEN MCP GLITCHES GPIOS ON POWERUP

90 OF 110

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9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9002

2

1

C9010

4

3

6 5 2 1

Q9000

4

5

3

1

2

U9021

2

1

C9051

2

1

C9050

21

L9050

21

R9080

4

5

3

1

2

U9020

21

R9081

2

1

R9000

21

R9001

21

C9000

21

L9000

2

1

C9020

2

1

C9001

2

1

R9070

2

1

3

Q9001

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP5V_LCD_CONN

VOLTAGE=5V

=PP3V3_S0_VIDEO

LCD_CONN_DDC_DAT

LCD_CONN_A_DATA_N<3> LCD_CONN_A_DATA_P<3> LCD_CONN_B_DATA_N<0> LCD_CONN_B_DATA_P<0>

LCD_CONN_B_DATA_N<1> LCD_CONN_B_DATA_P<1>

LCD_CONN_B_DATA_N<2>

LCD_CONN_A_CLK_N

LCD_CONN_A_DATA_N<2>

LCD_CONN_A_DATA_P<0> LCD_CONN_A_DATA_N<1>

LCD_CONN_A_DATA_N<0>

LCD_CONN_A_CLK_P

LCD_CONN_A_DATA_P<2>

LCD_CONN_A_DATA_P<1>

LCD_CONN_B_DATA_P<2> LCD_CONN_B_CLK_N LCD_CONN_B_CLK_P LCD_CONN_B_DATA_N<3>

LCD_CONN_DDC_CLK

LCD_CONN_B_DATA_P<3>

LCD_BKL_ON

LCD_PWM_GATE1

PEG_RESET_L

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP5V_LCD

VOLTAGE=5V

=PP5V_S0_LCD

LCD_PANEL_PWR

LCD_PWM_FILT

LCD_PWM

LCD_PANEL_PWR_L

LCD_PWM_R

=PP3V3_S0_VIDEO

LCD_BKL_PWM

LCD_PANEL_PWR_L_RC

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

INTERNAL DISPLAY

1/16W

5%

100K

MF-LF

402

SOT23-HF1

2N7002

1/16W

402

5%

MF-LF

100K

MF-LF

29.4K

1/16W

402

1%

X7R

603-1

50V

0.1UF

10%

SM

FERR-250-OHM

10% 16V

10UF

0805

X5R-CERM

50V

CERM

0.001uF

20%

402

CRITICAL

F-RT-SM

20389-Y30E-01

0.001uF

402

CERM

50V

20%

MLB_PNL_PWR

SM

CRITICAL

FDC638P_G

SOT665

IG

TC7SZ08AFEAPE

IG

CERM

0.1UF

20% 10V

402 402

0.1UF

10V CERM

IG

20%

FERR-250-OHM

CRITICAL

SM

1/16W MF-LF

402

0

MXM

5%

TC7SZ08AFEAPE

SOT665

IG

5% 1/16W MF-LF

47

402

6

90 89 6

89

107 89

89

107 89

89 6

87 9

6

89

6

90 89 6

89

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

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A

B

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8 7 5 4 2 1

MAY SHARE THE COMMON PAD BETWEEN R9125 AND R9130

K50 NOTE: PLACE THESE CAPACITORS ATLEAST 1INCH AWAY FROM DP CONNECTOR

DCOX: PLACE AT MXM CONNECTOR IF THERE IS ROOM

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21

C9114

21

C9164

21

C9112

21

C9162

21

C9110

21

C9160

21

C9158

21

C9108

21

C9156

21

C9106

21

C9154

21

C9104

21

C9152

21

C9102

21

C9150

21

C9100

21

R9130

21

R9125

21

R9124

MXM_DP_A_HPD

MXM_DP_A_ML_P<3>

MXM_DP_A_ML_P<2>

DP_IG_ML_P<2>

MXM_DP_A_ML_N<3>

DP_IG_ML_P<3>

DP_IG_ML_N<3>

MXM_DP_A_ML_P<1>

MXM_DP_A_ML_N<2>

DP_IG_ML_N<2>

MXM_DP_A_ML_N<1>

DP_IG_ML_P<1>

DP_IG_ML_N<1>

DP_IG_ML_N<0>

MXM_DP_A_ML_N<0>

DP_IG_ML_P<0>

MXM_DP_A_ML_P<0>

DP_IG_HPD

DP_HPD

DP_ML_P<3>

DP_ML_N<3>

DP_ML_P<2>

DP_ML_N<2>

DP_ML_P<1>

DP_ML_N<1>

DP_ML_P<0>

DP_ML_N<0>

SYNC_MASTER=MASTER

SYNC_DATE=N/A

DP MUX SUPPORT

X5R40210%16V

0.1UF

MXM

IG

0.1UF

X5R40210%16V

0.1UF

MXM

IG

0.1UF

X5R40210%16V

0.1UF

MXM

IG

0.1UF

X5R40210%16V

0.1UF

MXM

IG

0.1UF

X5R40210%16V

MXM

0.1UF

16V 10% 402 X5R

0.1UF

IG

MXM

0.1UF

16V 10% 402 X5R

0.1UF

IG

MXM

0.1UF

16V 10% 402 X5R

0.1UF

IG

MXM

0.1UF

16V 10% 402 X5R

0.1UF

IG

20.0K

402

MF-LF

1/16W

1%

MXM

MF-LF

0

402

5%

1/16W

IG

402

MXM

1/16W

0

5%

MF-LF

84

107 84

107 9

107 84

107 9

107 84

107 9

107 84

107 9

107 84

107 9

107 84

9

94

107 94

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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A

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SYNC_DATE=10/01/2008

SYNC_MASTER=K51

BLANK PAGE

BI

BI BI

BI

D

G S

IN

OUT

D

S G

D

S G

D

G S

IN

D

S G

D

S G

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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Apple Inc.

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A

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TO DP CONNECTOR

STUFF FOR IG SYSTEMS

STUFF FOR MXM SYSTEMS

FOR IG SYSTEMS, Q9300 SWITCHES BETWEEN AC COUPLED AUX AND DC-COUPLED DDC

THE CARD IS RESPONSIBLE FOR SWITCHING DDC SIGNALS ONTO THE AUX PAIR

FOR MXM, Q9350 BYPASSES THE AC COUPLING CAPS

MXM/IG MUX AND AUX/DDC SWITCHING

TO MCP

93 OF 110

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2

1

R9303

21

R9300

1

2

6

Q9300

21

C9300

21

C9301

4

5

3

Q9300

21

R9301

2

1

R9352

2

1

3

Q9351

4

5

3

Q9350

21

C9351

1

2

6

Q9350

21

C9350

2

1

3

Q9301

2

1

R9302

DDC_CA_DET_LS5V_L

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

DDC_CA_DET_LS5V

DP_AUX_CH_C_N

DP_AUX_CH_C_P

MXM_DP_A_AUX_P

MXM_DP_A_AUX_N

DP_CA_DET

MAKE_BASE=TRUE

=PP5V_S0_DP_AUX_MUX

DP_AUXCH_SW_P

DP_AUXCH_SW_N

DP_IG_CA_DET

DISPLAYPORT SUPPORT

SYNC_MASTER=MASTER

SYNC_DATE=N/A

SSM6N15FEAPE

SOT563

IG

0.1UF

X5R

10%

402

16V

X5R

16V 402

10%

0.1UF

IG

SSM6N15FEAPE

SOT563

9

IG

5%

1/16W

33

402

SIGNAL_MODEL=EMPTY

MF-LF

402

100K

MF-LF

5% 1/16W

MXM

SSM3K15FV

SOD-VESM-HF

MXM

SSM6N15FEAPE

SOT563

MXM

0.1UF

X5R

10%

402

16V

MXM

SOT563

SSM6N15FEAPE

MXM

0.1UF

10% 16V X5R 402

100K

402

MF-LF

5% 1/16W

18

94

SSM3K15FV

SOD-VESM-HF

107 94

107 94 107 18

107 18

9

107 84

MF-LF

1/16W

5%

1K

IG

402

MF-LF

SIGNAL_MODEL=EMPTY

402

33

1/16W

5%

IG

93 6

107

IN

OC*

OUT

EN

GND

IN

ML_LANE2P ML_LANE2N RETURN

GND

ML_LANE1N

ML_LANE0N GND ML_LANE1P

ML_LANE0P

GND

AUX_CHP AUX_CHN

DP_PWR

GND

ML_LANE3N

ML_LANE3P

GND

HPD CONFIG1 CONFIG2

SHIELD PINS

IN

IN IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

IN IN

G

S D

G

S D

G

D

S

G

D

S

OUT

SYM_VER-2

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19

10 12

15 17

9

11

3 5

22

21

2

1413

87

1

20

6

4

16 18

J9400

2

1

C9485

2

1

C9481

2

1

C9480

1

3

5

2

4

U9400

4

3 2

1

FL9403

4

3 2

1

FL9402

4

3 2

1

FL9401

4

3 2

1

FL9400

2

1

R9423

1

2

6

Q9441

4

5

3

Q9441

2

1

R9445

2

1

R9444

4

5

3

Q9440

2

1

R9422

2

1

R9442

1

2

6

Q9440

21

L9400

2

1

C9400

10

9

12

3

D9411

2

1

R9425

76

45

3

D9411

52

6

4

3

1

D9400

10

9

12

3

D9410

2

1

R9420

76

45

3

D9410

2

1

R9421

2

1

R9443

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

DP_CA_DET_Q

DP_ML_CONN_N<1>

DP_ML_CONN_P<1>

DP_HPD_Q

DP_ML_CONN_P<0> DP_ML_CONN_N<0>

HDMI_CEC

DP_ML_CONN_N<3>

DP_AUX_CH_C_N

DP_ML_CONN_P<2> DP_ML_CONN_N<2>

DP_AUX_CH_C_P

DP_ML_CONN_P<3>

DP_ML_N<0>

DP_ML_P<2>

=PP3V3_S0_DPCONN

DP_CA_DET_L_Q

DP_CA_DET

DP_HPD_L_Q

DP_HPD

=PP3V3_S0_DPCONN

DP_ML_N<1>

DP_ML_P<0>

DP_ML_N<2>

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM

PP3V3_S0_DPFUSE

=PP3V3_S0_DPCONN

TP_DP_OC

=PP3V3_S0_DPCONN

PM_SLPS3_BUF1_L

DP_ML_P<1>

DP_ML_P<3> DP_ML_N<3>

DisplayPort Connector

SYNC_MASTER=MASTER

SYNC_DATE=N/A

TCM1210-4SM

12-OHM-100MA

TCM1210-4SM

12-OHM-100MA

TCM1210-4SM

12-OHM-100MA

TCM1210-4SM

5%

402

1/16W MF-LF

100K

91

SOT-363

2N7002DW-X-G

SOT-363

2N7002DW-X-G

402

MF-LF

1/16W

5%

10K

1/16W

402

5%

MF-LF

2N7002DW-X-G

SOT-363

MF-LF

5%

1/16W

402

1M

100K

1/16W

1%

402

MF-LF

SOT-363

2N7002DW-X-G

107 91

MF-LF

402

1%

1/16W

100K

SM-1

400-OHM-EMI

603

20%

0.01UF

50V CERM

107 91

SLP2510P8

RCLAMP0524P

CRITICAL

MF-LF

1M

402

1/16W

5%

RCLAMP0524P

CRITICAL

SLP2510P8

SC70-6-1

CRITICAL

RCLAMP0504F

RCLAMP0524P

SLP2510P8

CRITICAL

100K

5%

1/16W

402

MF-LF

93

SLP2510P8

RCLAMP0524P

CRITICAL

100K

402

MF-LF

1/16W

5%

107 91

CRITICAL

MDP-K22

F-ANG-TH1

73 9

6.3V

CRITICAL

X5R 603

10UF

20%

107 91

402

10V CERM

20%

0.1UF

20%

10UF

603

X5R

6.3V

CRITICAL

TPS2051B

SOT23

107

107 93

107

107 93

107

94 6

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MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

FSB 1X Signals

Group 1

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

CPU Signal Constraints

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

Group 0

Group 1

Group 3

Group 2

FSB 4X Signal Groups

FSB (Front-Side Bus) Constraints

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 90 ps. (Tighther than MCP79)

All 4x FSB signals with impedance requirements are 42-ohm single-ended.

FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Intel Design Guide recommends FSB signals be routed only on internal layers.

FSB 4X signals / groups shown in signal table on right.

All 2x/1x/Async FSB signals with impedance requirements are 50-ohm single-ended.

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

FSB Clock Constraints

MCP FSB COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

FSB 2X

Signals

NET_TYPE

SPACING

Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MOST CPU SIGNALS WITH IMPEDANCE REQUIREMENTS ARE 50-OHM SINGLE-ENDED.

SR DG recommends at least 25 mils, >50 mils preferred

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XDP_CPURST_L

CPU_ITPCPU_50S

CPU_27P4S

CPU_VCCSENSE

VR_CPU_VSNS_R_P

CPU_27P4S

CPU_VCCSENSE

VR_CPU_VSNS_R_N

CPU_50S CPU_ITP

CPU_XDP_BPMB<3..0>

CPU_ITPCPU_50S

CPU_XDP_BPM_L<5..0>

CPU_ITPCPU_50S

CPU_XDP_TRST_L

CPU_ITPCPU_50S

CPU_XDP_TCK

CPU_50S CPU_ITP

CPU_XDP_TMS

CPU_ITPCPU_50S

CPU_XDP_TDO

CPU_50S CPU_ITP

CPU_XDP_TDI

CPU_COMP<0>

CPU_COMP

CPU_27P4S

CPU_FERR_L

CPU_50S

CPU_8MIL

CPU_AGTL

CPU_A20M_L

CPU_50S

FSB_1X

FSB_LOCK_L

FSB_50S

FSB_1X

FSB_HIT_L

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_50S

CLK_FSB

FSB_CLK_CPU_P

CLK_FSB_100D CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP_N

FSB_DSTB_42S

FSB_DSTB_L_P<1>

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_L_N<2>

FSB_1X

FSB_50S

FSB_BREQ1_L

FSB_1X

FSB_DBSY_L

FSB_50S

FSB_DRDY_L

FSB_50S

FSB_1X

CPU_AGTL

CPU_50S

CPU_IERR_L

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP_P

CLK_FSB

CLK_FSB_100D

FSB_CLK_MCP_N

FSB_CLK_MCP_P

CLK_FSB_100D

CLK_FSB

MCP_50S

MCP_CPU_COMP_GND

MCP_FSB_COMP

CPU_AGTL

CPU_DPRSTP_L

CPU_50S

CPU_AGTL

CPU_50S

CPU_DPSLP_L

CPU_50S

CPU_AGTL

FSB_CPUSLP_L

CPU_8MIL

CPU_50S

PM_THRMTRIP_L

FSB_50S

FSB_CPURST_L

FSB_1X FSB_1X

FSB_RS_L<2..0>

FSB_50S

FSB_1X

FSB_TRDY_L

FSB_50S

FSB_ADSTB_L<0>

FSB_ADSTB

FSB_ADDR

FSB_50S

FSB_REQ_L<4..0>

FSB_ADDR

FSB_50S

FSB_A_L<16..3>

FSB_1X

FSB_50S

FSB_ADS_L

FSB_DSTB_L_P<2>

FSB_DSTB_42S

FSB_DSTB

FSB_DATA

FSB_DINV_L<2>

FSB_42S

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB_L_N<3>

CPU_AGTL

CPU_50S

CPU_STPCLK_L

MCP_50S

MCP_BCLK_VML_COMP_VDD

MCP_FSB_COMP

CPU_AGTL

CPU_50S

CPU_SMI_L

MCP_BCLK_VML_COMP_GND

MCP_FSB_COMP

MCP_50S

CPU_50S

CPU_AGTL

CPU_PWRGD

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

CPU_BSEL<2..0>

CPU_AGTL

CPU_50S

FSB_1X

FSB_50S

FSB_BREQ0_L

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB_L_P<3>

FSB_42S

FSB_DATA

FSB_DINV_L<3>

FSB_42S

FSB_DATA

FSB_D_L<63..48>

FSB_42S

FSB_DATA

FSB_D_L<47..32>

FSB_DATA

FSB_42S

FSB_D_L<15..0>

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_L_P<0>

FSB_DATA

FSB_42S

FSB_DINV_L<0>

FSB_1X

FSB_50S

FSB_BPRI_L

FSB_1X

FSB_HITM_L

FSB_50S

CPU_AGTL

CPU_INIT_L

CPU_50S

CPU_IGNNE_L

CPU_50S

CPU_AGTL

CPU_INTR

CPU_50S

MCP_50S

MCP_CPU_COMP_VCC

MCP_FSB_COMP

CPU_AGTL

CPU_NMI

CPU_50S

FSB_50S

FSB_ADDR

FSB_A_L<35..17>

FSB_50S

FSB_ADSTB

FSB_ADSTB_L<1>

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_L_N<1>

FSB_42S

FSB_D_L<31..16>

FSB_DATA

FSB_42S

FSB_DATA

FSB_DINV_L<1>

FSB_1X

FSB_50S

FSB_BNR_L

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_L_N<0>

CPU_GTLREF0

CPU_GTLREF

CPU_50S

CPU_GTLREF1

CPU_GTLREF

CPU_50S

CPU_COMP<8>

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_COMP<2>

CPU_27P4S

CPU_COMP

CPU_COMP<3>

CPU_27P4S

CPU_50S

CPU_VID<7..0>

CPU_8MIL

CPU_27P4S

CPU_VCCSENSE

CPU_VCC_PKG_SENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCC_PKG_SENSE_P

CPU_COMP

CPU_COMP<1>

CPU_27P4S

SYNC_DATE=N/A

SYNC_MASTER=MASTER

CPU/FSB Constraints

=50_OHM_SE

=STANDARD

*

=STANDARD

CPU_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=27P4_OHM_SE

0.175 MM0.175 MM

=27P4_OHM_SE

*

CPU_27P4S

=27P4_OHM_SE=27P4_OHM_SE

=STANDARD

CPU_AGTL

?*

0.2 MM

*

CPU_8MIL

?

0.6 MM

?

CPU_COMP

*

=4x_DIELECTRIC

?

CLK_FSB

TOP,BOTTOM

=3x_DIELECTRIC

TOP,BOTTOM

?

FSB_1X

=4x_DIELECTRIC

?

TOP,BOTTOM

FSB_ADSTB

TOP,BOTTOM

=3x_DIELECTRIC

FSB_ADDR

?

TOP,BOTTOM

FSB_DSTB

=5x_DIELECTRIC

?

=3x_DIELECTRIC

*

FSB_DSTB

?

=2x_DIELECTRIC

?*

FSB_DATA

FSB_1X

=STANDARD

* ?

=42_OHM_SE

=1:1_DIFFPAIR

*

=1:1_DIFFPAIR

FSB_DSTB_42S

=42_OHM_SE

=42_OHM_SE =42_OHM_SE

TOP,BOTTOM

=4x_DIELECTRIC

FSB_DATA

?

=2x_DIELECTRIC

?*

FSB_ADSTB

=3x_DIELECTRIC

?

CLK_FSB

*

=42_OHM_SE =42_OHM_SE=42_OHM_SE =42_OHM_SE

FSB_42S

=STANDARD =STANDARD

*

=50_OHM_SE =50_OHM_SE

=STANDARD

FSB_50S

=50_OHM_SE =50_OHM_SE

=STANDARD

*

=2x_DIELECTRIC

TOP,BOTTOM

CPU_AGTL

?

0.2 MM

?*

MCP_FSB_COMP

=STANDARD

?

FSB_ADDR

*

0.6 MM

CPU_GTLREF

* ?

=2:1_SPACING

CPU_ITP

* ?

*

0.6 MM

?

CPU_VCCSENSE

=100_OHM_DIFF

*

CLK_FSB_100D

=100_OHM_DIFF

=50_OHM_SE =50_OHM_SE=50_OHM_SE

MCP_50S

*

=STANDARD =STANDARD

=50_OHM_SE

13

71

13 11

11

14 10

14 13

14 10

14

14 10

10

14 13

14

14 11

50 14 11

14 13 10

14 10

14

14 10

14

14 13 11

50 14 11

14 11

14 10

14

14 10

29 11 10

11

71 12

11

Apple K22 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual