Apple iMAC G5 A1058 SEEDY MLB 051-6772 Rev04 Schematic

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
78
6
5
4
3
ECN
ZONE
REV
DESCRIPTION OF CHANGE
SEEDY
04
ENGINEERING RELEASED
354713
12
CK APPD
DATE
12/07/04
ENG APPD
?
DATE
12/07/04
D
10 11 12
C
B
A
13* 14 16 17 18 21 22 23 24 25* 26 27 28 29 30 31 32 33 34 35 36 37 38 40 44 45 46 48 49 50
PDF
1 2 3 4 5 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
CIRCUIT
1
TABLE OF CONTENTS
2
SYSTEM BLOCK DIAGRAM POWER BLOCK DIAGRAM
3 4
REVISION HISTORY TABLE ITEMS
6
FUNC TEST
7
POWER CONNECTOR / POWER ALIAS SIGNAL ALIAS
8
2.5V VREG
9
1.2V VREG
3.3V/5V PWRON SWITCHING VESTA POWER SMU CPU LOGIC ANALYZER CONNECTOR FAN 0, 1 AND SYSTEM TEMP SENSOR FAN 2 AND HARD DRIVE TEMP SENSOR I2C CONNECTIONS INDICATOR LED / AMBIENT LIGHT SENSOR
1.5V VREG / U3LITE CORE SHASTA CORE U3LITE MISC SHASTA SERIAL PULSAR POWER PULSAR CLOCKS U3LITE APPLE PI NEO APPLE PI CPU STRAPS NEO POWER & BYPASS CPU BYPASS CPU VREG CPU VREG CPU VREG OUTPUT CAPS CPU DIODE CONDITIONER U3LITE MEMORY SERIES TERMINATION DIMMS PARALLEL TERMINATION PARALLEL TERMINATION VTT VREG U3LITE AGP GPU AGP GRAPHICS VREGS
BLOCK
TOP
PROCESSOR
MEMORY
GRAPHICS
* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC
8
67
5
CSACSA
51 52 53 54 55 56 58 59 60 62* 64 73 74* 75* 76 77* 80* 83 84* 86* 87 88* 89* 90 91* 92 94 95* 96*
98* 100* 101* 102*
4
PDF
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
CIRCUIT
GPU CORE POWER GPU FRAME BUFFER FRAME BUFFER TERMINATION GRAPHICS DDR SDRAM A GRAPHICS DDR SDRAM B GPU STRAPS GPU DVI & DACS EXT VGA & TMDS U3LITE HYPERTRANSPORT SHASTA HYPERTRANSPORT HYPERTRANSPORT LA CONNECTORS PCI SERIES TERMINATION SHASTA PCI BOOT ROM AIRPORT EXTREME & BLUETOOTH USB2 PCI SHASTA DISK DISK CONNECTORS SHASTA ETHERNET VESTA ETHERNET PHY ETHERNET CONNECTOR SHASTA FIREWIRE VESTA FIREWIRE PHY FIREWIRE CONNECTORS USB HOST INTERFACE USB DEVICE INTERFACE MODEM CONNECTOR PCM3052A AUDIO CODEC LINE IN AMP LINE OUT AMP SPEAKER AMP AUDIO CONNECTORS AUDIO POWER SUPPLIES
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
DRAFTER
ENG APPD
QA APPD
RELEASE
3
METRIC
MATERIAL/FINISH
NOTED AS
APPLICABLE
DESIGN CK
MFG APPD
DESIGNER
NONE
SIZE
2
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SCH,MLB,SEEDY
DRAWING NUMBER
D
051-6772
BLOCK
GRAPHICS
HT
PCI
DISK
ETHERNET
FIREWIRE
USB
MODEM
AUDIO
SHT
1
REV.
1
04
OF
D
C
B
A
102
FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE
D
U5400, U5401
FRAME
BUFFER A
PAGE 54
U2600
PULSAR
POWER
C
PAGE 26
B
CLOCKS
PAGE 27
HARD DRIVE
FOR DEVELOPMENT ONLY
OPTICAL
78
64-BIT FRAME BUFFER
2.6V/400MHZ
JXXXX
SATA
CONNECTOR
PAGE 83
J8302
SATA DEV
CONNECTOR
PAGE 83
J8301
UATA
CONNECTOR
PAGE 83
J5900, J5901 J5902, J5903
17",20" INVERTER
TMDS
EXT VGA
PAGE 59
U4900
GPU
RV351LE
PAGE 49
U5500, U5501
FRAME
BUFFER B
PAGE 55
SATA/150
1.2V/1.5GHZ
SATA/150
1.2V/1.5GHZ
UATA/133
3.3V/133MHZ
64-BIT FRAME BUFFER
2.6V/400MHZ
6
32-BIT 8X AGP
0.8V/533MHZ
4X = 1.5V I/O = 1.5V
U2900
CPU
NEO 10S
PAGE 29
APPLE PI
PAGE 28
U3
AGP
U3LITE
PAGE
48
MISC
PAGE 24
HYPERTRANSPORT
I2C
PAGE 18
HYPERTRANSPORT
SATA
U2300
SATA2SATA1
UATA
PAGE 80PAGE 80
CORE
PAGE 23
FIREWIREETHERNET
PAGE 84
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
PAGE 88
32-BIT APPLE PI ELASTIC INTERFACE
1.2V/900MHZ
CORE
PAGE 22
PAGE 60
J6400 J6401 J6402
HT DEBUG
PAGE 64
PAGE 62
SHASTA
NCs
PAGE 91
I2S0 I2S2
1394 OHCI (3.3V/98MHz)
8-bit TX/RX
5
64/128-BIT MAIN MEMORY
2.6V/400MHZ
PAGE 37
MAIN MEMORY
8-BIT HYPERTRANSPORT
1.2V/800MHZ
CONTROL = 2.5V
I2S
PAGE 25
I2S1
PAGE 74
PCI
PAGE 25
GPIO/PCI64
SCCBSCCA
4
J4000 J4001
SERIES
TERM
PAGE 38
U7500
BOOTROM
PAGE 75 PAGE 77
32-bit PCI (5V-3.3V/33MHz)
DIMMS
PAGE 40
J7600
AIRPORT EXTREME
CONNECTOR
PAGE 76
J9401
CTL-LESS / SOFT MODEM CONNECTOR
PAGE 94
PAGES 44&45
U7700
USB 2.0
uPD720101
PARALLEL
TERM
321
USB
PAGE 91
PCI
3
U1300
SMU
PAGE 13
U1301
RTC
PAGE 13
12
D
J9210/J9220/J9230
USB
CONNECTORS
PAGE 92
J9240
54
BLUETOOTH CONNECTOR
PAGE 92
C
B
U9500
AUDIO CODEC
U8600
VESTA
GIG ETHERNET
PAGE 86 PAGE 89
A
4 Diff pairs
J8700
ETHERNET CONNECTOR
PAGE 87
8
67
FIREWIRE A
0
1
2 Diff pairs
J9000, J9001
FIREWIRE A CONNECTORS
PAGE 90
5
PCM3052A
LINE IN
AMP
PAGE 97
J9800
LINE IN
CONNECTOR
PAGE 98
PAGE 95
J9802
MIC
CONNECTOR
PAGE 98
S/PDIF
LINE OUT
AMP
PAGE 97
SPEAKER
AMP
PAGE 97
4
OPTICAL OUT J9803
COMBO OUT CONNECTOR
PAGE 98
LINE OUT
J9801
SPEAKER
CONNECTOR
PAGE 98
SYSTEM BLOCK DIAGRAM
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6772
APPLE COMPUTER INC.
3
2
D
NONE
SHT
2
1
REV.
OF
102
A
04
ALIAS
IN
IN IN
IN
LM339A
V+
GND
IN
LM339A
V+
GND
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
20" PANEL POWER
POWER BLOCK DIAGRAM
AUDIO CODEC
PCI BUS
PP5V_ALL
HDD & OPTICAL
PP5V_RUN
PP12V_RUN
20" LCD INVERTER
PP24V_RUN
20" LCD INVERTER
FW CONN
PAGE 7
J700
5V
PAGE 10
SMU
SYS_POWERUP_L
(PWR_GOOD_PP2V5)
(TURN_ON_VTT)
FET SWITCH
(PWR_GOOD_SB_CORE)
SYS_POWERUP_L
POWER SEQUENCE PIN
PP3V3_RUN
POWER CONNECTOR
GPUL
SC1211*4
SC2643VX*1
SWITCHER
PAGE 33
0.8~1.2V
CPU CORE
HP/LINEOUT AMP
LINEAR
LINEAR
PP4V5_RUN_AUDIO
PP5V_RUN_AUDIO
AUDIO CODEC
5V
PAGE 99
4.5V
PAGE 99
LINEAR
PULSAR CORE
PP1V5_PWRON
1.5V
PAGE 50
SHASTA HT
USB CONN
FET SWITCH
PP5V_PWRON
PAGE 11
5V
DDR DIMM
IRU3037CS
SWITCHER
2.59V
RAM VTT
PP2V5_PWRON
PAGE 9
IRU3037CS
U3LITE CORE
LINEAR
AGP BUS
PAGE 50
POWER SW
PP1V5_RUN
1.3V
PP1V25_RAM_VTT
PAGE 46
CPU AVDD
LINEAR
PP2V5_RUN_CPU_AVDD
U3LITE CORE
SWITCHER
PAGE 31
2.8V
1.53V
PAGE 22
RAM TERM
PP2V5_RUN FET SWITCH
GRAPHIC FB
PAGE 9
SMU
FW PHY
LINEAR
PP3V3_PWRON
PAGE 11
3.3V
PAGE 11
PP3V3_ALL
3.3V
IRU3037ACS
PAGE 50
LINEAR
PP1V8_GPU
GPU
ENET PHY USB2 HOST MODEM & BT
RV351
IRU3037ACS
GPU CORE
PAGE 50
1.20V
VESTA CORE
PP1V2_ALL
SWITCHER
FET SWITCH
PAGE 50
PP2V5_GPU_A2VDD
1.2V
PAGE 10
SWITCHER
PAGE 50
PP1V5_VDDC_CT
LINEAR
PAGE 50
LINEAR
PP1V8_TPVDD
GPU GPU
GPU
PP1V2_PWRON
LINEAR
HT BUS
PP1V2_RUN
PAGE 10
FET SWITCH
SHASTA CORE PWRON_SD PWRON_DISK_SB
402
CERM
16V
20%
0.01UF
2
1
C340
10 10
PP2V5_PWRON
402
5%
150K
2
1
R342
100K
5% 1/16W MF-LF 402
2
1
R343
5% 1/16W MF-LF
10K
402
2
1
R341
5% 1/16W MF-LF
10K
402
2
1
R331
PP5V_ALL
PP3V3_ALL
SOI
3
14
9
8
12
U1100
PP3V3_ALL
46
SOI
3
1
7
6
12
U1100
402
5%
100K
21
R330
20% 16V CERM 402
0.01UF
2
1
C330
23
7 6
402
5%
100K
21
R340
3
102
04
051-6772
=PPVCORE_PWRON_SB
TURN_ON_PP1V2_PWRON_L
PWR_GOOD_PP2V5
TP_SMU_PWRSEQ_P1_0
MAKE_BASE=TRUE
TURN_ON_VTT
CPU_AVDD_EN
=PP5V_RUN_CPU
=PULSAR_POWER_DOWN
PULSAR_POWER_DOWN MAKE_BASE=TRUE
SMU_PWRSEQ_P1_4
SMU_PWRSEQ_P1_0
PWR_GOOD_SB_CORE
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P1_1
COMPARE_SB_CORE
RAIL_CTL_NEG
PS_2V_REF
COMPARE_PP2V5
31
8 7
31
6
27
13
13
13
13
13
13
11
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
(P 83) <RADAR 3890225> OPTICAL DRIVE CONNECTOR CHANGED TO 516S0235
MOVED GPU ZENER DIODES TO VREG PAGE SINCE THEY SHOULD BE PLACED NEAR THE VREGS
<RADAR 3849798> REDUCED CAPACITANCE OF C1100 & C1102
CONNECTED GPU POWER AND POWER FILTERS
(P 76) FIXED PCI_CBE_L<1> CONNECTION MORE PHYSICAL & SPACING UPDATES
CHECKIN 02003
(P 76) ADDED STANDOFFS FOR Q85 CARD (PP 16,17) NEW FAN CIRCUIT CAPS (C1603, C1653, C1703)
(P 59) LED 3 NOW DRIVEN FROM FPD_PWR_ON
(P 49) CONNECTED AGPTEST RESISTOR TO VDDP
11/22/04
(P 12) VESTA_ENET_LOWPWR UPDATE
(P 50) <RADAR 3877855> TP_VDD SET TO 1.80V
(P 50) <RADAR 3865344> VDDC_CT SET TO 1.50V
(P 91) <RADAR 3849858> USB CAP COST REDUCTION
(P 56) ADDED PADS FOR STRAPPING RESISTORS TO GPU_GPIO<14>
(PP 10, 22, 34, 50) USED COMPARATOR FOR LOW VOLTAGE RAIL LEDS
REPLACED EMC FERRITES WITH 0 OHM RESISTORS FOR GRAPHICS AND FANS
CONNECTED FRAME BUFFER
11/20/04
(P 62) <RADAR 3849855> SHASTA HT_PLL FILTER COST REDUCTION
(P 25) <RADAR 3849835> NEW SHASTA XTAL
(PP 56, 58) CONNECTED PWM FROM RV351LEP & PUT IN PROTO WORKAROUND
(P 36) CONNECTED NEW CPU DIODE REFERENCE (P 77) USB2 IDESEL - NOW FROM USB2 SIDE (P 56) ADDED BOMOPTIONS FOR MEMORY STRAPS
(P 91) CHANGED USB2 CHIP GROUNDING (P 8) ALIASED VESTA JTAG TO TEST POINT NETS
REMOVED NV18/34 GPU
11/18/04
REMOVED BCM5231 ETHERNET PHY
10/21/04
(P 7) ADDED PLATED HOLE ZH710 FOR TMDS GROUNDING
REMOVED P50 AIRPORT AND Q23 BLUETOOTH CONNECTORS, HOLES, & STANDOFFS
11/16/04
REMOVED EXTERNAL S/PDIF TRANSMITTER
ADDED Q85 AIRPORT & BLUETOOTH CONNECTOR
(PP 16,17) REPLACED FAN CONTROL WITH NEW CIRCUIT
ADDED TEST POINTS TO GRAPHICS FOR EXOR TESTING
CHECKIN 01005
<RADAR 3849743> ADDED RESISTORS TO STUFF AROUND USB FILTERS CHECKIN 01001
CONNECTED GPU GPIOS
ADDED 8MX32 GRAPHICS MEMORY
FRAME BUFFER SWAPS FOR CLEANER ROUTING
(P 5) NEW BOOTROM P/N
(P 76) FINISHED CONNECTING Q85 CONNECTOR
ADDED POWER SEQUENCING FOR GRAPHICS REGULATORS
ADDED REGULATOR FOR GPU TPVDD
(P 90) CHANGED R9090 TO 665 OHM
11/15/04
CHECKIN 01003 <RADAR 3848850> 2.5V VREG COST REDUCTION
<RADAR 3865344> SET GPU VDDC_CT VREG TO 1.55V
<RADAR 3848850> REGULATOR COST REDUCTIONS
<RADAR 3849772> REMOVED OUTPUT CAP ON 1.2V_ALL VREG
<RADAR 3849854> GPU CORE VREG COST REDUCTION
<RADAR 3849820> SHASTA FILTER COST REDUCTION
WHITE LED - CHANGED INDUCTORS TO 0 OHM RESISTORS
ADDED GPU STRAPS
CHECKIN 00009
ADDED GIGABIT ETHERNET CONNECTOR
MASTER PAGE SYNC:
<RADAR 3616348, 3621390> CHANGED FL5900-2 TO 220 OHM
<RADAR 3849806> CHEAPER SMU CRYSTAL
<RADAR 3849622> STUFFED AROUND TMDS FILTERS
11/01/04
CHECKIN 00008
REMOVED 1.6GHZ PROCESSORS CHANGED VOLTAGE SETTING OF 2.5V VREG TO 2.588V FROM 2.62V
11/06/04
ADDED SPACING & PHYSICAL CONSTRAINTS TO FRAME BUFFER
U2850 - REMOVED MAXIM AS AN ALTERNATE
11/04/04
CHECKIN 00003
REMOVED AGP VREG (VR5001)
CHECKIN 00005
GPU CORE POWER UPDATES
CHECKIN 00004
REMOVED GPU VTT VREG
ADDED RV351LE GPU
ADDED 2.5V VREG FOR A2VDD
REVISION HISTORY
ADDED 2.5V LDO FOR VESTA
10/26/04
10/22/04
ADDED VESTA
10/28/04
CHECKIN 00007
11/03/04
DESCRIPTION
REMOVED VESTA CORE REGULATOR
<RADAR 3848831> MOVED SMU RESET BUTTON TO DEVELOPMENT BOM
CHANGED FETS IN GPU CORE FOR COST REDUCTION
REMOVED VESTA ROM
AUDIO 3052A CODEC
ADDED 1.55V VREG FOR GPU VDDC_CT
TIED PPVCORE_NB DIRECTLY TO PP1V5_PWRON (REMOVED R707)
CONNECTED GPU TEMP SENSOR
ADDED AMBIENT LIGHT SENSOR CONNECTOR
ADDED 1.8V GPU VREG
AUDIO COST REDUCTIONS <RADAR 3849747 & 3849751>
ADDED MORE GPU CONSTRAINTS
<RADAR 3849656> STUFFED AROUND RGB FILTERS
<RADAR 3848887> 5V & 3.3V PWRON FET COST REDUCTIONS
<RADAR 3848859> 1.2V, 1.5V RUN FET COST REDUCTIONS
<RADAR 3848846> 2.5V RUN FET COST REDUCTION
CHECKIN 00010
ADDED DEVELOPMENT LEDS TO REGULATORS
11/09/04
<RADAR 3849857> CHEAPER USB2 CRYSTAL
CHANGED SOURCE OF Q1003 TO PP1V2_ALL RGB TERMINATION NOW CONNECTED TO DIGITAL GROUND
<RADAR 3849767> 2.5V VREG COST REDUCTIONS
11/10/04
UPDATED POWER BLOCK DIAGRAM
CHECKIN 01002
MOVED VTT VREG TO 2.5V PWRON TO REDUCE CURRENT THROUGH Q903
1.2V VREG COST REDUCTIONS - Q1002 TO NTD60N02R; C1002/3 TO 10UF CERM
REMOVED ON BOARD POWER SUPPLY TEMP SENSOR
REMOVED CPU VREG 4TH PHASE
11/07/04
CHANGED FW LATE VG CIRCUITRY TO MATCH Q78 & Q86
CHECKIN 00006
REMOVED MICRODASH CONNECTOR
REMOVED FW PORT POWER CIRCUITRY
REMOVED FW802A FW PHY
ADDED FW LATE VG PROTECTION
ADDED 1.2V REGULATOR FOR VESTA CORE
DATE
10/20/04
CHECKIN 00002
CHECKIN 01004
CHECKIN 01006
(P 58) REPLACED THERMAL SENSOR WITH LM63
(P 22) CHANGED Q2250 TO 376S0143
(P 59) TIED UNUSED BUFFER ENABLE PINS HIGH
(P 46) SLEEP SIGNAL TURNS OFF VTT VREG
(P 12) VESTA_ENET_LOWPWR UPDATE
(P 9) ADDED EXTRA 10UF INPUT CAP
ADDED VESTA ETHERNET LOWPWR CIRCUIT
REMOVED EXTERNAL TMDS TRANSMITTER
(P 7) TIED BOTH EI RAILS TO 1.5V
(P 18) <RADAR 3878118> MOVED SMU I2C E BUS
(P 90) FIXED FW PORT NAMING
CHECKIN 01007 / BOM RELEASE REV 02
(P 9) <RADAR 3848846> ADDED PAD FOR 1NF CAP TO GATE OF Q903
ADDED PHYSICAL CONSTRAINTS AUDIO STUFFING CHANGES CHECKIN 02001
CONNECTED GPU TMDS AND VGA
ADDED VOLTAGE, LINE WIDTH, AND NECK WIDTH PROPERTIES FOR GRAPHICS (IN MM)
REPURPOSED 1.2V REGULATOR FOR VESTA AND SHASTA
<RADAR 3849762> MOVED SMU DOWNLOAD CONNECTOR TO DEVELOPMENT BOM
CLONED DESIGN FROM GILA (Q45 A/B) REV G
CHECKIN 02002
ADDED DEVELOPMENT LEDS FOR VESTA ENET
(P 3) CONNECTED SHASTA CORE POWER FOR POWER SEQUENCING
(P 58) ADDED CONSTRAINT SETS (P 59) STUFFED AROUND Q5900 PANEL PWR SEQUENCING
12/02/04
(P 76) TABLED IN NEW STANDOFFS FOR Q85 CARD
CHECKIN 02004
(P 76) NOW HAVE CORRECT SYMBOL FOR STANDOFFS
11/23/04
(P 76) J7650 - NEW TO ALLOW 5MM CONNECTED HEIGHT
CHECKIN 03002
(P 83) REMOVED SECOND SATA CONNECTOR
(P 90) FIXED ALIAS PROBLEM WITH FW_TPB2_PD
<RADAR 3849718, 3849767, 3849854> MADE ON & VISHAY FETS TRUE ALTERNATES
(P 56) ADDED OPTION OF USING PWM FROM SHASTA
(P 16) C1653 - REPLACED WITH LOWER HEIGHT CAP
(P5) ADDED U3L W/ NEW LAMINATE AS ALTERNATE
PROTO RELEASE (REV 3)
(P 90) FIXED FW_CPS SHORT (P 35) REMOVED DS3500 & DS3501
CONVERTED DISCRETES TO LEAD FREE
CHANGED U7700 BACK TO LEADED PART (P 5) REMOVED ORIGINAL U3LITE (NEW LAMINATE ONLY FOR C/D) (P 49) CHANGED GPU TO RV351LEP (338S0231)
12/07/04
CHECKIN 03001
<RADAR 3848846> UPDATE OF 2.5V RUN FET COST REDUCTION
FRAME BUFFER PIN SWAPS
11/08/04
BOM RELEASE REV 01
BOM RELEASE REV 04
051-6772
04
4
102
Preliminary
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_11_HEAD
REFERENCE DESIGNATOR(S)
BOM OPTION
QTY
DESCRIPTION
VALUE VOLT. WATT.
TOL.PART #
PACKAGE
DEVICE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_11_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
TABLE_5_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
TABLE_5_ITEM
TABLE_ALT_ITEM
ALTERNATES
MISC PARTS
PROCESSORS
VOLTAGE
QUALIFIED
ASICS
TABLE ITEMS
1.20V
1.25VWAVE3
WAVE5
1.25VWAVE5
WAVE3
IC,ASIC,SHASTA,V1.1,PBGA
1
343S0283
051-6772
04
5
102
IC,GPUL,DD3,1.8G,BRA
337S2969337S2970
CPU_DD30_1_8GHZ
337S2981
IC,GPUL,DD3,1.8G,BPL
337S2969
CPU_DD30_1_8GHZ
337S2982
IC,GPUL,DD3,1.8G,BRL
337S2969
CPU_DD30_1_8GHZ
42W
337S2969
CPU_DD30_1_8GHZ
1 ?
PROCESSOR
1.8GHZ
IC,GPUL,10S,DD3,1.8G,85C,BPA
CBGA-576-1MM
IC,ASIC,VESTA,V1.3
343S0324
1
U7500
1
341T1667
IC,FLASH,1MX8,3.3V,90NS
MLB1
1
PCB,FAB,MLB
820-1747
1
LBL1
BARCODE LABEL, MLB, Q45
825-6447
343S0321
U3L,NEW LAM,200MM
U3343S0320
1
U3343S0320
IC,U3LITE,NEW LAM,300MM,PBGA
1
SCH1
PCB,SCHEM,MLB
051-6772
PURCH ASSY, SMU BIG
U1300
341T1395
1
HEAT SINK ASSEMBLY 17 IN
603-6015
1
17_INCH_LCD
CRITICAL
MECH17
HEAT SINK ASSEMBLY 20 IN
603-6016
1
CRITICAL
20_INCH_LCD
MECH20
378S0114
KINGBRIGHT LED
LED700,LED702,LED5900
378S0119
Q3310,Q3320,Q3410
MOSFET,N-CH,VISHAY
376S0130376S0204
Q3311,Q3321,Q3411
376S0146376S0207
MOSFET,N-CH,VISHAY
1
062-2082 VPP1
SPEC,VENDOR PACKAGING PROCEDURE
Preliminary
IN
IN
IN
IN
IN
IN
IN
IN IN IN IN IN IN IN IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN IN
IN
IN
IN
IN IN
IN
IN
IN IN IN IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN IN IN IN
IN IN
IN
IN
IN IN
IN
IN IN IN IN IN IN IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
2 TEST POINTS
2 TEST POINTS
2 TEST POINTS
2 TEST POINTS
FUNC TEST
2 TEST POINTS
2 TEST POINTS
2 TEST POINTS
10 TEST POINTS
5 TEST POINTS
5 TEST POINTS
12 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
2 TEST POINTS
GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:
2 TEST POINTS
I307
I337 I338
I344 I345 I346 I347 I348
I349
I350
I354 I355 I356 I357 I358
I359
I360
I361
I362 I363
I364 I365
I371
I372 I373
I374 I375 I376 I377 I378
I379
I380
I381
I382 I383
I384 I385 I386
I387
I388
I389
I390
I391
I392
I393
I394
I395
I396
I397
I398
I399
I400
I401
I402
I403
I404 I405 I406
I407
I408
I428
I429
I430
I431
I432
I433
I434
I435
I436
I437
I438
I439
I440 I441 I442
I443
I444
PP5V_ALL
PP12V_RUN
PP5V_RUN
PP3V3_PWRON
PP5V_PWRON
PP2V5_RUN
PP1V5_RUN
PP1V2_PWRON
PP3V3_RUN
11
7
18 11 10
7
50 34 22 18 11 10
7
83
7
7
83
18 11
58 27 18 11
13
8 7
31
8 7 3
7
33 34 35
22
34 33
33
33
8 7
13
7
7
7
13
8
46 22 11 10
8 9
33 13 11 10
7
13
8
22
9
59 58
59 58
59 58
83 80
83 80
83 80
83 80
83
83 80
83 80
83 80
6
83 80
6
83 80
83
83
83
83
33
8
36
36
36
36 33
36
36 33
59
59
59
59
59
59
59 58
59
59
59
59
59
59
77 76 75 74 73
77 76 74 73
8
76 74
76 74
76 25
77 76 74 73
74 56
8
77 76 74 73
77 76 74 73
77 76 74 73
77 76 74 73
77 76 74 73
76 75 74
76
76 75 74
76 75 74
76
76 75
76
76
92
92
92
92
92
92
92
92
92
94 25
94 25
94 25
94 25
94 25
94 25
94 25
92 91
92 91
25
25
59
59
59
59
59
59
59
59
59
59
59
59
59
7
101
25
75
PP24V_RUN
36 31
I781
I782
I784 I785
I786
I787
I788
I789
I790
I791
I792
I793 I794
I795 I796
I797
I798 I799
I800
I801 I802
I803
I804 I805
I806 I807
I808
I809 I810
101
90
101
101
18 17
18 17
25 18
25 18
36 33 31
36 33 31
83
051-6772
102
6
04
PP5V_ALL
FUNC_TEST=YES
PP12V_RUN
FUNC_TEST=YES
PP5V_RUN
FUNC_TEST=YES
GND
FUNC_TEST=YES
PP3V3_PWRON
FUNC_TEST=YES
PP5V_PWRON
FUNC_TEST=YES
PP2V5_RUN
FUNC_TEST=YES FUNC_TEST=YES
PP1V5_RUN
PP1V2_PWRON
FUNC_TEST=YES
FUNC_TEST=YES
PP3V3_RUN PP24V_RUN
FUNC_TEST=YES
UATA_CS1_L
FUNC_TEST=YES
UATA_STOPUATA_STOP
FUNC_TEST=YES
FUNC_TEST=TRUE
UATA_DASP_L TDIODE_NEG
FUNC_TEST=YES
FUNC_TEST=TRUE
UATA_DD<15..0>
FUNC_TEST=YES
ROM_WP_L
AUDIO_LO_DET_L
FUNC_TEST=YES
SMU_RESET_L
FUNC_TEST=YES
UATA_CS0_L
FUNC_TEST=YES
FUNC_TEST=TRUE
UATA_DA<2..0>
UATA_CSEL_PD
FUNC_TEST=YES
UATA_IOCS16_PU
FUNC_TEST=YES
UATA_DMARQ_R
FUNC_TEST=YES
UATA_RESET_L
FUNC_TEST=YES
ANALOG_RED
FUNC_TEST=YES
U2200_FEEDBACK
FUNC_TEST=YES
U900_FEEDBACK
FUNC_TEST=YES
SYS_POWERFAIL_L
FUNC_TEST=YES
POWER_BUTTON_L
FUNC_TEST=YES
PCI_CLK33M_AIRPORT
FUNC_TEST=YES
FUNC_TEST=TRUE
PCI_CBE_L<3..0>
PCI_SLOTA_REQ_L
FUNC_TEST=YES
FUNC_TEST=TRUE
I2C_SB_SDA
FUNC_TEST=TRUE
KPGND2
FUNC_TEST=TRUE
KPVDD2
FUNC_TEST=TRUE
TMDS_DCC_DAT
FUNC_TEST=TRUE
TMDS_DCC_CLK
FUNC_TEST=TRUE
I2C_SB_SCL
AUD_MIC_IN_N_CONN
FUNC_TEST=TRUE
AUD_MIC_IN_P_CONN
FUNC_TEST=TRUE
FW_VP
FUNC_TEST=TRUE
GND_AUDIO_MIC_CONN
FUNC_TEST=TRUE
I2C_HD_TEMP_SCL
FUNC_TEST=TRUE
I2C_HD_TEMP_SDA
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PCI_AD<31..0>
FUNC_TEST=YES
PP5V_USB2_PORT1_F
PCI_PAR
FUNC_TEST=YES
USB_BT_P
FUNC_TEST=YES
USB2_PORT1_P_F
FUNC_TEST=YES
USB2_PORT3_P_F
FUNC_TEST=YES
USB2_PORT2_N_F
FUNC_TEST=YES
USB2_PORT2_P_F
FUNC_TEST=YES
USB2_PORT3_N_F
FUNC_TEST=YES
I2S1_RESET_L
FUNC_TEST=YES
I2S1_MCLK
FUNC_TEST=YES
I2S1_BITCLK
FUNC_TEST=YES
TP_NB_PM_SLEEP0
NO_TEST=YES
PCI_RESET_L
FUNC_TEST=YES
ROM_ONBOARD_CS_L
FUNC_TEST=YES
PCI_SLOTA_GNT_L
FUNC_TEST=YES
PCI_SLOTA_INT_L
FUNC_TEST=YES
PCI_IRDY_L
FUNC_TEST=YES
PCI_STOP_L
FUNC_TEST=YES
PCI_DEVSEL_L
FUNC_TEST=YES
FUNC_TEST=YES
PP5V_USB2_PORT3_F
ANALOG_BLU
FUNC_TEST=YES
NO_TEST=YES
PLS_CLK_66M_1_R
NO_TEST=YES
PLS_CLK_66M_0_R
EI_CPU1_SYNC
NO_TEST=YES
TP_PROC_TRIGGER_OUT
NO_TEST=YES
SYNCENABLE
NO_TEST=YES
RI_L
NO_TEST=YES
MCP_L
NO_TEST=YES
I2C_SMU_A_SDA_OUT_L
NO_TEST=YES
I2C_SMU_A_SCL_OUT_L
NO_TEST=YES
EI_SE
NO_TEST=YES
EI_QREQ_L
NO_TEST=YES
EI_QACK_L
NO_TEST=YES
EI_CPU1_CLK_P
NO_TEST=YES
EI_CPU1_CLK_N
NO_TEST=YES
CPU1_HTBEN
NO_TEST=YES
CPU_INT_L
NO_TEST=YES
CPU_HRESET_L
NO_TEST=YES
CHKSTOP_L
NO_TEST=YES
NO_TEST=TRUE
EI_NB_TO_CPU_SR_N<0..1>
NO_TEST=TRUE
EI_NB_TO_CPU_SR_P<0..1>
NO_TEST=YES
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_AD<0..43>
NO_TEST=TRUE
EI_NB_TO_CPU_CLK_N
NO_TEST=YES
EI_CPU_TO_NB_SR_P<0..1>
NO_TEST=TRUE
NO_TEST=TRUE
EI_CPU_TO_NB_SR_N<0..1>
EI_CPU_TO_NB_CLK_P
NO_TEST=YES
EI_CPU_TO_NB_CLK_N
NO_TEST=YES
NO_TEST=TRUE
EI_CPU_TO_NB_AD<0..43>
TP_J4000_SJRESET_L
NO_TEST=YES
TP_J4001_SJRESET_L
NO_TEST=YES
U2100_UNUSED
NO_TEST=YES
TP_RAM_MUXEN4
NO_TEST=YES
TP_RAM_CKE_R<3>
NO_TEST=YES
SMU_MANUAL_RESET_L
FUNC_TEST=YES
FUNC_TEST=YES
=PPVCORE_PWRON_SB =PP3V3_ALL_SMU
FUNC_TEST=TRUE
FUNC_TEST=YES
SYS_POWER_BUTTON_L
FUNC_TEST=YES
=PP5V_DISK
FUNC_TEST=YES
=PP12V_DISK
I2S1_DEV_TO_SB_DTI
FUNC_TEST=YES
I2S1_SB_TO_DEV_DTO
FUNC_TEST=YES
I2S1_SYNC
FUNC_TEST=YES
TP_RAM_CKE_R<2>
NO_TEST=YES
TP_RAM_CKE_R<6>
NO_TEST=YES
TP_RAM_CKE_R<7>
NO_TEST=YES
TP_RAM_CS_L_R<2>
NO_TEST=YES
TP_RAM_CS_L_R<3>
NO_TEST=YES
TP_RAM_CS_L_R<10>
NO_TEST=YES
TP_RAM_CS_L_R<11>
NO_TEST=YES
TP_AFN
NO_TEST=YES
TP_AGP_MB_AGP8X_DET_L
NO_TEST=YES
TP_ATTENTION
NO_TEST=YES
TP_DUMMY_A
NO_TEST=YES
TP_DUMMY_B
NO_TEST=YES
TP_FBBCS1_L
NO_TEST=YES
TP_NEC_AMC
NO_TEST=YES
TP_NEC_NANDTEST
NO_TEST=YES
TP_NEC_NTEST1
NO_TEST=YES
TP_NEC_SMC
NO_TEST=YES
TP_NEC_SMI_L
NO_TEST=YES
TP_NEC_SRCLK
NO_TEST=YES
TP_NEC_SRDATA
NO_TEST=YES
TP_NEC_SRMOD
NO_TEST=YES
TP_NEC_TEB
NO_TEST=YES
TP_NEC_TEST
NO_TEST=YES
TP_PLS_CLK_66M_0
NO_TEST=YES
TP_PLS_CLK_66M_1
NO_TEST=YES
TP_PLS_REF_CML
NO_TEST=YES
TP_PLS_TEST1
NO_TEST=YES
TP_PLS_TEST2
NO_TEST=YES
TP_PLS_TEST3
NO_TEST=YES
TP_PSRO1
NO_TEST=YES
TP_PSRO2
NO_TEST=YES
TP_PSYNCOUT
NO_TEST=YES
TP_RAM_MUXEN0
NO_TEST=YES
TP_SATA_CLK25M
NO_TEST=YES
TP_SB_FSTEST
NO_TEST=YES
TP_SB_NC_P7
NO_TEST=YES
TP_SB_NC_P8
NO_TEST=YES
TP_SB_NC_R3
NO_TEST=YES
TP_SB_NC_R4
NO_TEST=YES
TP_SB_NC_R5
NO_TEST=YES
TP_SB_NC_R6
NO_TEST=YES
TP_SB_NC_R7
NO_TEST=YES
TP_SB_NC_R8
NO_TEST=YES
TP_SB_NC_T1
NO_TEST=YES
TP_SB_NC_T2
NO_TEST=YES
TP_SB_NC_T3
NO_TEST=YES
TP_SB_NC_T4
NO_TEST=YES
TP_SB_NC_T5
NO_TEST=YES
TP_SB_NC_T6
NO_TEST=YES
TP_SB_NC_T7
NO_TEST=YES
TP_SB_NC_T8
NO_TEST=YES
TP_SB_NC_U1
NO_TEST=YES
TP_SB_NC_U2
NO_TEST=YES
TP_SB_NC_U3
NO_TEST=YES
TP_SB_NC_U4
NO_TEST=YES
TP_SB_NC_U5
NO_TEST=YES
TP_SB_NC_U6
NO_TEST=YES
TP_SB_NC_V1
NO_TEST=YES
TP_SB_NC_V2
NO_TEST=YES
TP_SB_NC_V3
NO_TEST=YES
TP_SB_NC_V4
NO_TEST=YES
TP_SB_NC_W1
NO_TEST=YES
TP_SB_NC_W3
NO_TEST=YES
TP_SB_NC_Y1
NO_TEST=YES
TP_SB_NC_Y3
NO_TEST=YES
TP_SB_PLLTEST
NO_TEST=YES
TP_USB2_PWREN<0>
NO_TEST=YES
TP_USB2_PWREN<1>
NO_TEST=YES
TP_USB2_PWREN<2>
NO_TEST=YES
TP_USB2_PWREN<3>
NO_TEST=YES
TP_USB2_PWREN<4>
NO_TEST=YES
TP_VREF_CG
NO_TEST=YES
UATA_DMACK_L
FUNC_TEST=YES
FUNC_TEST=YES
USB2_P<3>
FUNC_TEST=YES
USB2_N<3>
USB2_PORT1_N_F
FUNC_TEST=YES
ANALOG_GRN
FUNC_TEST=YES
CORE_ISNS_M
FUNC_TEST=YES
CORE_ISNS_P
FUNC_TEST=YES
FILT_ANALOG_BLU
FUNC_TEST=YES
FILT_ANALOG_GRN
FUNC_TEST=YES
FILT_ANALOG_RED
FUNC_TEST=YES
GND_17_INV
FUNC_TEST=YES
GND_20_INV
FUNC_TEST=YES
GND_CHASSIS_TMDS
FUNC_TEST=YES
INV_17_CUR_HI_F
FUNC_TEST=YES
INV_17_LCD_PWM_F
FUNC_TEST=YES
INV_20_CUR_HI_F
FUNC_TEST=YES
INV_20_LCD_PWM_
FUNC_TEST=YES
MODEM_RING2SYS_L
FUNC_TEST=YES
MON_DETECT
FUNC_TEST=YES
PCI_SLOTA_IDSEL
FUNC_TEST=YES
PP12V_INV
FUNC_TEST=YES
PP24V_INV
FUNC_TEST=YES
PP3V3_DDC
FUNC_TEST=YES
FUNC_TEST=YES
PP5V_USB2_PORT2_F
PPVCC_TMDS
FUNC_TEST=YES
ROM_CS_L
FUNC_TEST=YES
ROM_OE_L
FUNC_TEST=YES
TCKP
FUNC_TEST=YES
TD0M
FUNC_TEST=YES
TD0P
FUNC_TEST=YES
TD1M
FUNC_TEST=YES
TD1P
FUNC_TEST=YES
TD2M
FUNC_TEST=YES
TD2P
FUNC_TEST=YES
TDIODE_NEG_FMAX
FUNC_TEST=YES
TDIODE_POS_FMAX
FUNC_TEST=YES
FUNC_TEST=YES
I2C_TMDS_SDA
UATA_DSTROBE_R
FUNC_TEST=YES
UATA_INTRQ_R
FUNC_TEST=YES
UDASH_RESET_L
FUNC_TEST=YES
FUNC_TEST=YES
VCORE_SENSE_GND
FUNC_TEST=TRUE
CPU_VID_R<5..0>
AIRPORT_CLKRUN_L_PD
FUNC_TEST=YES
UDASH_SDOWN
FUNC_TEST=YES
TCKM
FUNC_TEST=YES
FUNC_TEST=YES
I2C_TMDS_SCL
PP5V_AGP_RL
FUNC_TEST=YES
KPVDD2_FMAX
FUNC_TEST=YES
KPGND2_FMAX
FUNC_TEST=YES
UATA_HSTROBE
FUNC_TEST=YES
FUNC_TEST=YES
SYS_SLEEP
VCORE_SENSE_VOUT
FUNC_TEST=YES
USB_BT_N
FUNC_TEST=YES
ROM_WE_L
FUNC_TEST=YES
FUNC_TEST=YES
SYS_POWERUP_L
RESET_BUTTON_L
FUNC_TEST=YES
PCI_TRDY_L
FUNC_TEST=YES
PCI_FRAME_L
FUNC_TEST=YES
=PP5V_RUN_CPU
FUNC_TEST=YES
PPVCORE_NB
FUNC_TEST=YES
PPVCORE_CPU
FUNC_TEST=YES
PP12V_CPU
FUNC_TEST=YES
30
30
30
30
30
18
18
29
29
29
29
30
29
29
29
29
29
29
29
29
29
29
29
27
29
29
29
29
14
14
28
28
28
27
27
25
29
14
28
28
28
28
28
28
28
28
28
28
24
27
27
14
14
14
14
14
13
13
14
14
14
14
14
14
14
14
8
14
14
14
14
14
14
14
14
14
14
40
40
21
8
8
8
8
8
8
8
8
8
29
48
29
24
24
52
77
77
77
77
77
77
77
77
77
77
27
27
27
27
27
27
29
29
29
8
27
25
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
25
92
92
92
92
92
48
Preliminary
ALIAS
ALIAS
ALIAS
ALIAS
125
ALIAS
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
CHASSIS GND
ALL RAILS
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
SDF700 IS USED FOR CPU HEATSINK MOUNTING
POWER CONN / ALIAS
SILKSCREEN:2
RUN RAILS
SMU RESET
SILKSCREEN:POWER
SILKSCREEN:1
PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .
RESET
ALWAYS ON (TRICKLE)
ONLY ON IN RUN
RTC BATTERY
SILKSCREEN:RUN
805-5664
516S0248 FOXCONN
P/N 518-0159
POWER
GND RAILS
ON IN RUN AND SLEEP
PWRON RAILS
PP5V_RUN
PP3V3_PWRON
PP1V5_PWRON
PP2V5_PWRON
PP1V2_PWRON
PP24V_RUN
PP5V_ALL
PP5V_ALL
PP3V3_RUN
PP2V5_RUN
PP5V_PWRON
PP1V5_RUN
PP5V_RUN
PP3V3_RUN
PP5V_RUN
PP12V_RUN
SM
21
XW700
SM
21
XW701
315R138
1
ZH700
SM
21
XW702
SM
21
XW703
402
CERM
10V
20%
0.1UF
2
1
C704
20% 10V
402
CERM
0.1UF
2
1
C705
PP12V_RUN
SPST
SM
43
21
SW702
5%
1K
402
MF-LF
1/16W
21
R713
SPST
DEVELOPMENT
SM
43
21
SW701
5%
402
1K
1/16W MF-LF
DEVELOPMENT
21
R712
DEVELOPMENT
SPST
SM
43
21
SW700
315R138
1
ZH701
7R4.15
1
ZH702
6.00MM-PTH
1
ZH703
402
5%
1K
21
R702
SHLD-IO-CONN
Q45-TH1
4
32
1
SH700
SOD-123
B0530WXF
2 1
DS700
PP1V2_RUN
74LCX125
CRITICAL
3
14
17
2
U700
402
CERM
10V
20%
0.1UF
2
1
C700
SYS_PWR_BTN_FILT
FERR-EMI-100-OHM
SM
21
L700
SM
FERR-EMI-100-OHM
21
L701
DEVELOPMENT
GREEN
2.0X1.25A 2
1
LED701
2.0X1.25A
GREEN
2
1
LED702
PP3V3_PWRON
5%
MF-LF
330
603
1/10W
21
R700
GREEN
2.0X1.25A 2
1
LED700
F-RT-TH
HM96110-P2
CRITICAL
9
8
7
6
5
4
3
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J700
SM
21
XW704
SM
21
XW705
SM
21
XW706
SM
21
XW707
HSK-NUT-6.5MM
TH
NOSTUFF
1
SDF700
PP12V_RUN
PP24V_RUN
CRITICAL
ST-SM3
PWR-BUTT
2
1
54
3
SW703
PP3V3_RUN
805
1/8W
5%
0
NOSTUFF
21
R720
315R138
1
ZH710
MF-LF
5%
1/10W
330
603
21
R710
10V CERM
20%
0.1UF
402
2
1
C703
1/10W
5%
MF-LF
DEVELOPMENT
330
603
21
R701
PP5V_ALL
CRITICAL
TH
BB10209-A5
1 2
J702
051-6772
102
7
04
VOLTAGE=3.3V
_PP5V_PWRON_USB
_PP3V3_PWRON_BT =PP3V3_PWRON_CPU
=PP5V_PATA
=PP3V3_PWRON_VESTA
SYS_POWERUP_L_BUF
=PP3V3_PWRON_EI
=PPPCI64_PWRON_SB
POWER_BUTTON_L
SMU_MANUAL_RESET_L
=PP1V5_PWRON_NB_AVDD
=PPVCORE_NB
=PPVCORE_PWRON_PULSAR
=PP1V2_ENETFW
PP1V2_VESTA
MIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUE
PP1V2_ALL VOLTAGE=1.2V MIN_NECK_WIDTH=15MIL
PP5V_AUDIO
ITS_RUNNING
=PP5V_AGP
=PP5V_RUN_CPU
=PP3V3_AGP
=PP3V3_RUN_CPU
GND_SYS_PWR_BTN_FILT
RESET_BUTTON_L
SYS_POWER_BUTTON_L
ITS_PLUGGED_IN
POWER_GOOD
=PP1V2_PWRON_SB
=PP3V3_ALL_RTC
MAKE_BASE=TRUE
PP3V3_ALL_RTC
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=3.3V
=PP1V2_PWRON_HT =PP1V2_PWRON_DISK_SB
=PP3V3_SB_PCI
=PP2V5_PWRON_HT
=PP2V5_PWRON_RAM =PP2V5_HT
SYS_POWERUP_L
PP3V3_ALL_BATT
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=3.3V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=3.3V
PP3V3_ALL_BATT_SAFETY
PP3V3_ALL
GND_AUDIO_SPKRAMP
ITS_ALIVE
=PP24V_GRAPHICS
PP12V_AUDIO_CODEC
PP12V_AUDIO_SPKRAMP
=PP12V_AGP =PP12V_RUN_CPU =PP12V_DISK
PP3V3_AUDIO
=PP3V3_PATA
=PP3V3_DISK
PP2V5_GPU
=PP2V5_RUN_CPU =PP2V5_RUN_RAM
=PPVCORE_PULSAR
=PPVCORE_CPU
MAKE_BASE=TRUE
PPVCORE_CPU
=PP3V3_PWRON_SB
=PPPCI32_PWRON_SB
GND_AUDIO
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
=PP5V_DISK
VOLTAGE=0
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
GND_CHASSIS_17_INCH_INVERTER
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL VOLTAGE=0
GND_CHASSIS_20_INCH_INVERTER
=PP3V3_PWRON_USB
_PP3V3_PWRON_MODEM
=PP5V_PWRON_CPU =PP5V_PWRON_RAM
GND_CHASSIS_LED
GND_CHASSIS_RJ45
VOLTAGE=0
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=15MIL
=PP5V_ALL_CPU
MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL
PP3V3_ALL
MIN_NECK_WIDTH=10MIL
=PP3V3_ENETFW
=PP3V3_FW
=PP3V3_ENET
PP3V3_VESTA
=PP3V3_ALL_CPU
=PP3V3_ALL_SMU
=PPVCORE_PWRON_SB
GND_CHASSIS_AUDIO_EXTERNAL MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUE VOLTAGE=0
GND_CHASSIS_USB
GND_CHASSIS_VGA
GND_CHASSIS_FIREWIRE
MIN_NECK_WIDTH=15MIL VOLTAGE=0
MIN_LINE_WIDTH=25MIL
GND_CHASSIS_TMDS
MAKE_BASE=TRUE
GND_CHASSIS_AUDIO_INTERNAL
=PP2V5_PWRON_SB
=PP2V5_ENET
PPVCORE_GPU
=PP1V2_PULSAR
=PP1V2_HT
=PP1V5_AGP
=PP1V2_EI_CPU =PP1V2_EI_NB
=PP3V3_PCI
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
=PPVIO_PCI_USB2
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_ALL
MIN_LINE_WIDTH=12MIL MAKE_BASE=TRUE
MIN_NECK_WIDTH=8MIL
PP3V3_RUN
MAKE_BASE=TRUE
VOLTAGE=24V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=12V MIN_LINE_WIDTH=25MIL MAKE_BASE=TRUE
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.2V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
VOLTAGE=5V
VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
MIN_NECK_WIDTH=10MIL VOLTAGE=1.2V
MAKE_BASE=TRUE MIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUE
MIN_NECK_WIDTH=10MIL
VOLTAGE=2.5V MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUE VOLTAGE=1.5V
VOLTAGE=3.3V MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
VOLTAGE=5V
PP5V_RUN
MIN_NECK_WIDTH=10MIL
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
50 59
35
34 58
33
31
77
22
60
31
56
46
13
102
55
36
35
88
30
76
18
18
48
8
50
13
40
11
59
101
54
32
34
74
13
59 13
23
74
51
50
29
28
75
11
11
8
37
89
59
6
49
7
37
64
10
11
102
59
83
100
52
45
31
33
25
7
83
11
90
87
8
6
102
59
25
50
60
49
18
18
74
11
10
10
92
76
36
83
12
28
23
6
6
28
22
26
86
12 10
101
50
3
48
33
6
6
8
25
13
62
80
74
62
26
60
6
7
100
59
102
100
50
33
6
95
83
83
50
31
44
26
29
6
23
23
102
6
13
6
59
59
91
94
36
46
21
87
36
7
89
89
86
12
36
6
3
101
92
59
90
6
101
23
87
22
26
24
48
14
14
25
77
6
6
6
Preliminary
ALIAS ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
125
125
125
ALIAS
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
MC33465N_30ATR
RESETDELAY
VCC
GND
VOLTAGE DETECTOR
ALIAS ALIAS ALIAS ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
VESTA JTAG
PULL DOWN
SHASTA JTAG
THESE PINS HAVE INTERNAL PULLUPS
CONNECTION
SIGNAL FROM POWER SUPPLY
(SMU_BOOT_EPM)
CONNECTOR
SIGNAL ALIAS
518S0104
PLL LOCK LED
SMU ANALOG VREF
CHKSTOP LED
DIAG LED
2.2V FOR CPU VRM10.
CPU VID<0:5>
NOTE:PULL UP CPU_VID<5>TO
VID CONTROLLED BY SMU
SMU
PCI CLOCKS
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
PULSAR ERROR_L LEDBACKUP SMU RESET CIRCUIT
DOWNLOAD
518-0158
J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP
POWER_GOOD IS A 5V DRIVEN
2K PULLUP INSIDE P/S
POWER_FAIL_L
SDF700 IS ALSO USED FOR HEATSINK MOUNTING
CPU HEATSINK SMT NUTS
1/16W
10K
MF-LF 402
5%
2
1
R825
DEVELOPMENT
402
5%
100
2 1
R826
5%
0
402
21
R802
10K
402
MF-LF
5% 1/16W
2
1
R803
NOSTUFF
10K
5% 1/16W MF-LF 402
2
1
R807
5%
402
1/16W
10K
MF-LF
2
1
R806
402
0
5%
NOSTUFF
21
R828
74LCX125
6
14
47
5
U700
74LCX125
8
14
10
7
9
U700
74LCX125
11
14
13
7
12
U700
402
5%
4.7K
2
1
R870
PP2V5_PWRON
402
5%
10K
2
1
R814
10K
5% MF-LF
402
2
1
R816
5% 1/16W MF-LF
10K
402
2
1
R817
402
10K
5%
2
1
R808
10K
402
5% 1/16W MF-LF
2
1
R809
NOSTUFF
5% 1/16W MF-LF
1K
402
2
1
R827
NOSTUFF
1K
5% MF-LF
402
2
1
R829
NOSTUFF
1K
5% MF-LF
402
2
1
R830
NOSTUFF
1K
5% 1/16W MF-LF 402
2
1
R831
PP3V3_RUN
5%
10K
402
2
1
R804
5%
20K
402
2
1
R811
TH
HSK-NUT-6.5MM
NOSTUFF
1
SDF800
NOSTUFF
TH
HSK-NUT-6.5MM
1
SDF801
NOSTUFF
TH
HSK-NUT-6.5MM
1
SDF803
NOSTUFF
TH
HSK-NUT-6.5MM
1
SDF802
SM
RED
DEVELOPMENT
2
1
D810
6P15R5P4
OMIT
1
ZH804
402
0.01UF
20% 16V CERM
2
1
C880
402
0.01UF
20% 16V CERM
2
1
C881
402
0.01UF
20% CERM
16V
2
1
C882
402
0.01UF
20% 16V CERM
2
1
C883
CERM
16V
20%
0.01UF
402
2
1
C884
402
5%
180
DEVELOPMENT
2
1
R833
RED
SM
DEVELOPMENT
2
1
LED801
2N7002
SOT23-LF
DEVELOPMENT
Q800_D
2
1
3
Q800
180
5%
DEVELOPMENT
2
1
R834
2N3904LF
DEVELOPMENT
Q801_B
2
3
1
Q801
SM
DEVELOPMENT
2N3906
2
3
1
Q802
402
DEVELOPMENT
5%
180
2
1
R835
180
402
DEVELOPMENT
5%
21
R836
GREEN
2.0X1.25A
DEVELOPMENT
2
1
LED802
180
5% 1/16W
DEVELOPMENT
2
1
R837
402
1K
5%
DEVELOPMENT
2
1
R838
2N3904LF
DEVELOPMENT
2
3
1
Q803
180
402
5%
DEVELOPMENT
21
R839
1K
NOSTUFF
5% 1/16W MF-LF 402
2
1
R832
I246
I247
RED
SM
2
1
LED850
2N3904LF
2
3
1
Q850
1K
402
5%
21
R851
PP5V_ALL
402
5%
180
2
1
R850
402
430
5% MF-LF
2
1
R813
5%
4.7K
2
1
R860
402
5% MF-LF
1K
NOSTUFF
1/16W
2
1
R890
402
6.3V
10%
1uF
CERM
NOSTUFF
2
1
C891
NOSTUFF
SM
2
1
3
5
U890
CERM
16V
10%
402
NOSTUFF
0.01UF
2
1
C890
0
5% 1/16W MF-LF
402
21
R810
0.1uF
10V
20%
CERM
402
NOSTUFF
2
1
C800
DEVELOPMENT
M-ST-TH
HC17051
9
87
65
43
2
10
1
J802
1/16W
10K
MF-LF 402
5%
2
1
R840
0
1/16W
402
MF-LF
5%
NOSTUFF
2
1
R805
PP3V3_ALL
F-ST-SM
DEVELOPMENT
U.FL-R_SMT
1
2
3
J800
PP3V3_ALL
1/16W
10K
MF-LF 402
5%
NOSTUFF
2
1
R812
NOSTUFF
SSOT-23
2.5V
3
12
VR801
1%
402
200
NOSTUFF
2
1
R818
805
CERM
10V
20%
2.2UF
NOSTUFF
2
1
C801
603
0.47UF
20% 10V CERM
NOSTUFF
2
1
C802
NOSTUFF
F-ST-SM
BM12B-SRSS-TB
9876543
2
121110
11314
J803
402
0
5%
21
R819
5%
0
402
21
R820
402
5%
0
21
R821
0
5% 1/16W MF-LF
402
21
R822
402
5%
0
21
R823
402
5% MF-LF
0
21
R824
402
5%
DEVELOPMENT
4.7K
2
1
R801
5% 1/16W
402
330
DEVELOPMENT
2
1
R800
PP3V3_RUN
04
8
102
051-6772
RAM_CS_L_R<3>
PPVREF_SMU MAKE_BASE=TRUE
SMU_BOOT_SCLK
SMU_BOOT_CNVSS
SMU_BOOT_TXD
CPU_VID_R<4>
CPU_VID_R<3>
CPU_VID_R<2>
SMU_BOOT_CE
SMU_MANUAL_RESET_L
J802_6
J802_2
SMU_BOOT_RXD
NB_SUSPEND_ACK_L
ALS1_OUT
SMU_MANUAL_RESET_L
=PP3V3_ALL_SMU
=PCI_ROM_RESET_L =PCI_USB2_RESET_L
CPU_VID_R<0>
10 MIL SPACING
SMU_RESET
SYS_WARM_RESET_L
SMU_RESET
SYS_COLD_RESET_L
10 MIL SPACING
CPU_VID_R<5>
FAN_PWM8
RAM_CKE_R<6>
TP_ALS1_OUT
MAKE_BASE=TRUE
TP_ALS0_OUT
MAKE_BASE=TRUE
PCI_RESET_L
MAKE_BASE=TRUE
SYS_SLOT_PWR
RAM_CKE_R<3>
NB_THMO
NB_THMI
MAKE_BASE=TRUE
TP_NB_THMI
MAKE_BASE=TRUE
TP_RAM_CKE_R<3>
MAKE_BASE=TRUE
TP_RAM_MUXEN4
RAM_MUXEN0
PCI_CLK_P4
RAM_CKE_R<7>
GPU_RESET_L
SMU_WARM_RESET_L
MAKE_BASE=TRUE
PCI_AIRPORT_RESET_L
MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
MAKE_BASE=TRUE
TP_RAM_CS_L_R<11>
RAM_CS_L_R<11>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<10>
RAM_CS_L_R<10>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<3>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<2>
RAM_CS_L_R<2>
TP_RAM_MUXEN0
MAKE_BASE=TRUE
RAM_MUXEN4
TP_RAM_CKE_R<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_RAM_CKE_R<6>
TP_RAM_CKE_R<2>
MAKE_BASE=TRUE
RAM_CKE_R<2>
MAKE_BASE=TRUE
TP_THMO
NB_WARM_RESET_L
MAKE_BASE=TRUE
TP_FAN_PWM8
TP_SYS_DRIVE_BAY_INT_L
MAKE_BASE=TRUE
SYS_DRIVE_BAY_INT_L
TP_SYS_DOOR_AJAR_L
MAKE_BASE=TRUE
SYS_DOOR_AJAR_L
MAKE_BASE=TRUE
TP_SYS_SLOT_PWR
MAKE_BASE=TRUE
TP_SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_3
TP_SMU_ONEWIRE
MAKE_BASE=TRUE
SMU_ONEWIRE
MAKE_BASE=TRUE
TP_ALS_GAIN_BOOST
ALS_GAIN_BOOST
ALS0_OUT
MAKE_BASE=TRUE
TP_PCI_CLK_P4
MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
PCI_CLK_P1
MAKE_BASE=TRUE
TP_PCI_CLK_GP1
PCI_CLK_GP1
_PCI_CLK33M_AIRPORT
PCI_CLK_P3
=PCI_CLK33M_USB2
PCI_CLK_GP0
MAKE_BASE=TRUE
PCI_CLK33M_USB2
CPU_VID<4>
CPU_VID<2>
CPU_VID<0>
CPU_VID<5>
CPU_VID<3>
CPU_VID<1>
MAKE_BASE=TRUE
DIAG_LED
DIAG_LED_R
CPU_VID_R<1>
LED850P2
LED850P1
=PP5V_RUN_CPU
NB_SUSPENDACK_L
SYS_SLEEP
SMU_WARM_RESET_L SYS_WARM_RESET_L
=PPVREF_SMU
PP3V3_ALL_SMU_AVCC
Q802_E
HS_SDF803
HS_SDF800 HS_SDF801 HS_SDF802
GND_SMU_AVSS
Q803_B
Q803_C
LED802_1
Q800_G
LED801_1
NB_PMR_OBSV
GND_SMU_AVSS_DAGND
PPVREF_SMU_ADC_REF
SMU_SLEEP
SMU_BOOT_BUSY
Q802_B
PLLLOCK
HS_SDF804
=PP5V_RUN_CPU
POWER_GOOD
SYS_POWERFAIL_L
CHKSTOP_L
MAKE_BASE=TRUE
TP_JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
MAKE_BASE=TRUE
TP_JTAG_SB_TDO
MAKE_BASE=TRUE
TP_JTAG_SB_TDI
JTAG_SB_TCK
JTAG_SB_TMS
JTAG_SB_TDO
JTAG_SB_TDI
JTAG_SB_TRST_L
TP_JTAG_VESTA_TDI
MAKE_BASE=TRUE
TP_JTAG_VESTA_TMS
MAKE_BASE=TRUE
TP_JTAG_VESTA_TCK
MAKE_BASE=TRUE
=JTAG_VESTA_TDI
TP_JTAG_VESTA_TDO
MAKE_BASE=TRUE
SMU_RESET_L
=JTAG_VESTA_TMS
=JTAG_VESTA_TDO
=JTAG_VESTA_TCK
ERROR_LED
CLOCK_ERROR_L
=JTAG_VESTA_TRST_L
MAKE_BASE=TRUE
JTAG_VESTA_TRST_L
46
31
22
31
77
8
11
77
8
8
8
13
74
74
7
10
74
36
7
29
33
33
33
7
7
7
33
25
24
33
56
13
74
33
6
9
13 25
33
6
13
14
13
37
13
13 13
6
6
6
13
6
13
24
13
6
6
75
77
6
8
13
6
13
37
6
13
37
24
24
6
6
37
27 37
49
8
76
6
6
37
6
37
6
6
37
6
37
6
6
6
37
24
13
13
13
13
13
13
27 27
27
76
27
77
27
13
13
13
13
13
13
13
6
3
13
6
8 8
13
13
13
24
36
36
13
13
29
3
7
6
6
25
25
25
25
25
12
6
12
12
12
27
12
Preliminary
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
2.5V VREG
U900_FEEDBACK
2.5V VOLTAGE REGULATOR
IRU3037CS VREF=1.25VDC VOUT=VREF*(R903+R905)/R905=2.588VDC
SET OUTPUT=2.588V FOR FRAMEBUFFER.
NOTE:
PEAK CURRENT OF TOTAL RAILS
9.24A WITHOUT DIMM TERMINATION
12.68A WITH DIMM TERMINATION
HIGH TO ENABLE
805
1/8W
5%
0
21
R902
1% MF-LF
402
10K
2
1
R905
5%
NOSTUFF
1/4W
1.1K
2
1
R904
20%
6.3V ELEC TH-KZJ
1800UF
2
1
C908
CERM
10UF
6.3V
20%
1206
2
1
C901
TH-KZJ
20% ELEC
6.3V
1800UF
2
1
C909
PP5V_PWRON
805
CERM
1UF
20% 25V
2
1
C904
PP5V_PWRON
SOD-123
MBR0520LXXG
2 1
D900
SOD-123
MBR0520LXXG
2 1
D901
MBR0520LXXG
SOD-123
2
1
D902
603
CERM
10V
20%
1UF
2
1
C917
603
5%
2200PF
50V CERM
2
1
C905
805
CERM
25V
20%
1UF
2
1
C916
PP2V5_PWRON
PP2V5_RUN
220PF
25V
5% CERM
402
2
1
C906
1.6UH
CRITICAL
TH
21
L901
IRU3037CS
SOI
2 6
8
3
5
4
1
7
U900
10.7K
1%
402
2
1
R903
603
CERM
0.47UF
20%
10V
2
1
C915
27.4K
1%
402
2
1
R901
56PF
50V CERM 402
5%
2
1
C913
3300PF
603
10% CERM
50V
NOSTUFF
2
1
C907
603
3900PF
5% CERM
50V
2
1
C914
4.7
805
1/8W MF-LF
5%
2
1
R900
402
240
DEVELOPMENT
5%
2
1
R950
GREEN
DEVELOPMENT
2.0X1.25A
2
1
LED900
SO-8
IRF7413
321
4
8765
Q903
PP12V_RUN
2N7002
SOT23-LF
2
1
3
Q940
5% 1/16W
470K
2
1
R940
NOSTUFF
1UF
20% CERM
25V 1206
2
1
C912
NTD60N02R
CASE369
3
1
4
Q901
NTD60N02R
CASE369
3
1
4
Q902
20%
6.3V ELEC TH-KZJ
1800UF
2
1
C902
1800UF
TH-KZJ
ELEC
6.3V
20%
2
1
C903
1800UF
TH-KZJ
ELEC
6.3V
20%
2
1
C910
1206
20%
6.3V
10UF
CERM
2
1
C911
0.001UF
20% 50V CERM 402
NOSTUFF
2
1
C940
051-6772
04
9
102
Q903_GATE
U900_VC
U900_VC_R
U900_FEEDBACK
Q901_GATE
U900_GATE_L
Q902_DRAIN
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
SYS_SLEEP
U900_SS
LED_PP2V5_RUN
R901_P2
U900_VC_D
R904_P2
U900_COMP
U900_GATE_H
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=2.5V
46 22 11 10
8 6 6
Preliminary
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
LM339A
V+
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
PLACE LED1000 NEAR VREG
PP1V2_ALL VOLTAGE REGULATOR
PP1V2_RUN FET SWITCH
PEAK CURRENT ??A
RDSON=?? OHM @ VGS=?? V
PEAK CURRENT ??A
RDSON=0.06 OHM @ VGS=2.5 V
PP1V2_PWRON FET SWITCH
U1000_FEEDBACK
SET OUTPUT=1.2V IRU3037ACS VREF=0.8VDC
<-- NEED TO VERIFY
NOTE:
~3A
VOUT=VREF*(R1003+R1005)/R1005=1.206VDC PEAK CURRENT OF TOTAL RAILS
1.2V VREG
1.6UH
TH
21
L1001
50V 603
CERM
3300PF
10%
NOSTUFF
2
1
C1007
1% MF-LF
402
10K
2
1
R1005
1206
NOSTUFF
1.1K
1/4W
5%
2
1
R1004
1UF
20% CERM
25V 1206
NOSTUFF
2
1
C1012
MBR0520LXXG
SOD-123
2
1
D1002
PP5V_ALL
CERM
10V 603
20%
1UF
2
1
C1017
0.022UF
603
CERM
NOSTUFF
10% 50V
2
1
C1005
SOD-123
MBR0520LXXG
2 1
D1000
SOD-123
MBR0520LXXG
2 1
D1001
0
5%
1/8W
805
21
R1000
805
CERM
20%
1UF
25V
2
1
C1000
25V
5% CERM
402
220PF
2
1
C1006
20% 25V
805
CERM
1UF
2
1
C1004
IRU3037ACS
SOI
2 6
8
3
5
4
1
7
U1000
TH-KZJ
1800UF
6.3V ELEC
20%
2
1
C1009
5.11K
402
1% 1/16W
2
1
R1003
PP1V2_RUN
2N7002DW
SOT-363
4
5
3
Q1004
SOT-363
2N7002DW
1
2
6
Q1004
PP5V_ALL
402
100K
5%
2 1
R1008
PP5V_ALL
SI3446DV
TSOP
4
3 6
521
Q1006
PP1V2_PWRON
2N7002
SOT23-LF
2
1
3
Q1005
5%
402
100K
2 1
R1009
PP5V_ALL
5% CERM
603
50V
3900PF
2
1
C1014
5%
603
50V CERM
68PF
2
1
C1013
0.1UF
20% CERM
16V 603
2
1
C1015
27.4K
1%
402
2
1
R1001
5%
0
402
21
R1012
0
5%
MF
NOSTUFF
21
R1013
PP3V3_ALL
402
5%
100K
2
1
R1014
1/8W
5%
4.7
805
2
1
R1002
NTD60N02R
CASE369
3
1
4
Q1001
CASE369
NTD60N02R
3
1
4
Q1002
1206
6.3V
20%
10UF
CERM
2
1
C1002
1206
6.3V
20%
10UF
CERM
2
1
C1003
SI3446DV
TSOP
4
3 6
5
2
1
Q1003
CERM
6.3V
20%
1206
10UF
2
1
C1001
DEVELOPMENT
SOI
3
2
5
4
12
U1001
5% 1/16W MF-LF
DEVELOPMENT
330
402
2
1
R1050
GREEN
2.0X1.25A
DEVELOPMENT
2
1
LED1000
402
100K
5% 1/16W MF-LF
DEVELOPMENT
2
1
R1051
DEVELOPMENT
402
47K
5% 1/16W MF-LF
2
1
R1052
5%
0
402
DEVELOPMENT
21
R1053
CERM
10V
20%
0.1UF
402
DEVELOPMENT
2
1
C1050
051-6772
04
10
102
U1000_GATE_H
PP1V2_ALL VOLTAGE=1.2V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=15MIL
Q1002_DRAIN
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
U1000_VC_R
U1000_FEEDBACK
PP1V2_ALL
U1000_COMP
TURN_ON_PP1V2_PWRON_L
U1000_VC_D
R1004_P2
Q1001_GATE
U1000_VC
U1000_SS
R1001_P2
Q1006_G
SYS_POWERUP_L
PP1V2_ALL
SYS_SLEEP
Q1005_G
Q1003_G
U1000_GATE_L
PP1V2_RUN_FOR_LED
1V1_REF
PP3V3_RUN
PP5V_RUN
LED_PP1V2_RUN_N
LED_PP1V2_RUN_P
PP3V3_RUN
50
50
34
34
46
22
22
33
22
18
18
13
11
11
18
11
11
9
50
10
11
10
10
10
7
10
8
34
7
7
7
7
7
3
6
7
6
22
6
6
6
Preliminary
D
G
S
LM339A
V+
GND
LM339A
V+
GND
TAB
VOUTVPWR
VCTRL
VOUT
ADJ
SENSE
D
G
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
FET ON IN RUN
5V & 3.3V VREGS
FET ON IN RUN
PP5V_PWRON
Vpwr >= Vout+0.35V
Vctrl >= Vout+1.25V
R2
R1
Iadj=50uA typ
3.30V - 3.45V
Vref=1.250V typ
Vout=Vref(1+R2/R1)+Iadj(R2)
PROCESS SWING
SHUTDOWN -> FLOAT
SLEEP -> FLOAT
RUN -> LOW
FET ON IN SLEEP
FET ON IN SLEEP
SHUTDOWN -> FLOAT
SLEEP -> LOW
RUN -> FLOAT
20% 10V ELEC
100UF
SM
2
1
C1100
SI4467DY
SM-1
CRITICAL
3 2 1
4
8 7 6 5
Q1100
402
5%
100K
21
R1100
SOI
CRITICAL
3
13
11
10
12
U1100
SOI
3
2
5
4
12
U1100
603
1%
47.0K
2
1
R1102
CS5253
SM
CRITICAL
5
6
3
4
1
2
VR1100
100K
5%
402
21
R1103
100K
5%
402
21
R1104
603
1%
124
2
1
R1105
603
1%
210
2
1
R1106
603
CERM
16V
N20P80%
0.1UF
2
1
C1101
SM-1
SI4467DY
3 2 1
4
8 7 6 5
Q1102
20% ELEC
10V
47UF
SM
2
1
C1102
1%
1K
402
2
1
R1107
402
1K
1% 1/16W MF-LF
2
1
R1101
SI3443DV
TSOP
CRITICAL
4
3 6
5
2
1
Q1103
CRITICAL
TSOP
SI3443DV
4
3 6
5
2
1
Q1101
051-6772
04
11
102
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=5V
PP5V_PWRON
RAIL_SLEEP_FET MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
PP5V_ALL
PP3V3_PWRON
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
PP3V3_ALL
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
PP5V_ALL
RAIL_RUN_FET MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
SYS_SLEEP
SYS_POWERUP_L
PP5V_RUN
MIN_NECK_WIDTH=10MIL
3_3V_ALL_ADJ MIN_LINE_WIDTH=20MIL
PP3V3_RUN
PP3V3_ALL
RAIL_CTL_POS
RAIL_CTL_NEG
50
46
34
22
33
22
58
10
13
18
18
11
27
59
11
9
10
10
10
59
18
7
18
11
7
8
7
7
7
11
6
6
6
7
6
6
6
6
6
7
3
Preliminary
G
D
S
VESTA MISC
1 OF 3
PVDDDVDD
AVDDL
AVDD
GND
AGND
OVDD
REGSUP1 REGSEN1 REGCTL1
REGSUP2 REGSEN2 REGCTL2
2.5V_EN
NC
DNC
DNC
DNC
NC
TDO TCK TMS TRST*
TDI
RESET*
GND
VOUT
VIN
NOISE
CONT
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
Ethernet LowPwr
ETHERNET PORTION IN LOW POWER MODE WHEN NOT IN RUN MODE.
Vout = 2.5V @ 150 mA
2.5V LDO
Page Notes
Power aliases required by this page:
NC
BOM options provided by this page:
Controls operating mode of Vesta 1.2V
regulator will be in continuous mode.
N9/N10
Signal aliases required by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
regulator. If both options are off the
NC
N5/N6
Schmitt trigger
L6/M6
(NONE)
L9/M9
Vesta Core / Misc
Reset RC values per
To keep Vesta from being held
Broadcom recommendation
in reset when system is off
R1252 to enable wirespeed feature
NOTE: Reset GPIO is active HIGH
20% 10V CERM 402
0.1uF
2
1
C1210
0.1uF
402
CERM
10V
20%
2
1
C1211
402
CERM
10V
20%
0.1uF
2
1
C1212
20% 10V CERM 402
0.1uF
2
1
C1213
0.1uF
CERM 402
10V
20%
2
1
C1203
0.1uF
402
CERM
10V
20%
2
1
C1202
0.1uF
402
CERM
20% 10V
2
1
C1201
20% 10V CERM 402
0.1uF
2
1
C1200
20% 10V
CERM
402
0.1uF
2
1
C1222
10V
20%
CERM
402
0.1uF
2
1
C1225
20% 10V
CERM
402
0.1uF
2
1
C1221
0.1uF
20% 10V
CERM
402
2
1
C1224
0.1uF
402
CERM
10V
20%
2
1
C1231
20% 10V
CERM
402
0.1uF
2
1
C1230
20% 10V
CERM
402
0.1uF
2
1
C1220
0.1uF
20% 10V
CERM
402
2
1
C1223
0.1uF
402
CERM
10V
20%
2
1
C1243
20% 10V
CERM
402
0.1uF
2
1
C1242
10V
0.1uF
402
CERM
20%
2
1
C1241
0.1uF
402
CERM
10V
20%
2
1
C1240
603
20%
1uF
10V CERM
2
1
C1250
SOT23-LF
2N7002
2
1
3
Q1250
OMIT
BCM5462
FBGA-200
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15
A7
A1
M13
C3
K2
J2
F14
C14
B7B2A2
J1
C15
B15
B1
E9
C9
B9
N10
N9N6N5M9M6L9L6
R12
R3
P11
P10
P5
P4
N8N7M8
M7L8L7
J12
J11
P9P8P7
P6
H12
H11
M3
U8600
402
5%
82K
2
1
R1251
10% X5R
10UF
6.3V 805
2
1
C1208
FERR-EMI-600-OHM
SM
21
L1200
16V
CERM
402
0.01uF
20%
2
1
C1281
402
6.3V
10%
1uF
CERM
2
1
C1280
6.3V X5R 805
10UF
10%
2
1
C1282
MM1572FN
SOT-25A
CRITICAL
5
1
4
2
3
U1280
402
4.7K
5% 1/16W MF-LF
2
1
R1252
100K
5%
2
1
R1262
5% MF-LF
2.0K
402
2
1
R1260
402
6.3V
10%
1uF
CERM
2
1
C1260
2N3904LF
2
3
1
Q1260
5%
1K
402
2
1
R1261
CERM
10V
20%
0.1UF
402
NOSTUFF
2
1
C1261
10212
04
051-6772
=JTAG_VESTA_TRST_L
PP3V3_VESTA
TP_VESTA_DNC_B9
ENETFW_RESET
VESTA_RESET_L
PP3V3_VESTA
PP3V3_VESTA
PP2V5_VESTA
TP_VESTA_REGSEN2
TP_VESTA_REGSUP2
TP_VESTA_REGSEN1
TP_VESTA_REGSUP1
TP_VESTA_REGCTL1
TP_VESTA_2_5V_EN
TP_VESTA_DNC_E9
PP1V2_VESTA_AVDDL
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.2V MIN_NECK_WIDTH=0.25 mm
=JTAG_VESTA_TMS
=JTAG_VESTA_TCK
=JTAG_VESTA_TDO
TP_VESTA_REGCTL2
=JTAG_VESTA_TDI
PP1V2_VESTA
TP_VESTA_DNC_C9
MAKE_BASE=TRUE
VOLTAGE=2.5V
PP2V5_VESTA
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP3V3_VESTA
=PP2V5_ENETFW
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VESTA2V5_NOISE
PP3V3_VESTA
=PP3V3_PWRON_VESTA
VESTA_ENET_LOWPWR
VESTA_ENET_HIGHPWR
12
12
12
12 89
12
8
7
25
7
7
12
8
8
8
8
7
12
7
86
7
7
86
Preliminary
P9[7]
P9[6]
P9[5]
P8[7]
P8[6]
P8[5]
P3[7]
P3[6]
P3[5]
P3[4]
P2[6] P2[7]
P2[4] P2[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[4]
P0[0]
P0[2] P0[3]
P0[1]
P0[7]
P0[6]
P0[5]
P3[3]
P3[2]
P3[1]
P3[0]
P2[3]
P2[2]
P2[1]
P2[0]
P1[5] P1[6] P1[7]
PCNVSS RESET* XOUT
VREF
XIN
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
P10[0] P10[1]
P9[3]
P9[2]
P9[1]
P9[0]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P10[6] P10[7]
P10[2] P10[3] P10[4] P10[5]
VCC
AVSS
VSS
AVCC
SQW/ OUT
VBAT
SDA SCL
X1 X2
GND
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
MASTER: SEEDY
System Management Unit
3.6
2.7
100K/10uF RC filter at SMU pins.
SMU_VREF should be same signal or
circuit, but be aware that this will
7.6
1.5
1.6
1.7
0.6
0.5
Port
0.4
Portable
Alternate Functions
2.6
Port
2.5
Consumer
Port
6.1
6.2
6.0
7.2
7.4
Tower & Server
Y
Y
IOC2 IOC3
SS
Y
Y
Y
Y
Y
Y
Y
Y
IOC5
INT3*
AN22
YYY
YYY
Y
Y
Y
Y
YYY
YYY
Y
Y
N
N
N
(see aliases below)
SS
Y
Y
Y
Y
Y
SYYS
Y Y
Y
Y
Y Y
Y
Y
S
YYYS S
AN26
Y
Y
Y Y Y
Y
YY
Y
Y
Y
Y
Y
S
INT0*
S
Y
Y
Y Y
Y YYYY
Y
S
Y
Y
Y Y
YYNNSS
Y Y
Y
Y
Y
Y
Y
Y Y
Y
Y
Y
YYYY
Y
Y
Y Y
Y
Y
Entry Desktop
Entry Desktop
Desktop
S
Y
Y
Y
Y
Y
Y
Y
Y
S
Y
Y
Y Y
Y Y
Y Y
Y
Y Y
Y
Y
Y N Y
Y
Y Y
Y
Y
Y Y Y Y
Y
Y Y Y
Portable
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
S
Y
Y
Y
S
Y
Y
Y
S
Y
Y
Y
Y
Y
S
Y
S
Y
Y S
Y
Y
Y
Y
Y
S
Y
Y
Y
Y
Y
Y
S
Y
Y Y
Y
Y Y
Y
Y
N
Y
Y
S
S
Y
Y Y
S S Y
Y
N
S S
N
N
N
Consumer
N
N
N
Server
S
Y Y Y Y
Y Y Y
Y
S
Y
Y
Y
Y
S
Y
Y
Y
Y
Y
Y
Y YYY
Y
Y Y
Y
Y
Y
Y
Y Y Y
Y
S
NSS
Y
Y
Y
Y
Y
Y
Y
Y YSY
Y
Y Y Y
Y
Y Y
S
N Y
Y
Y YYYY
S S
SS
S S
Consumer
Y S S
Y
S
Y Y
Y Y Y
N N
Y Y
Y
Y
Y
Y
Y
Y
Y
Y
S
Y
Y
N
N
Y
Y
Y
Y Y
Y
Portable
DesktopYServer
SMU Pull-ups / pull-down
NET_SPACING_TYPE
System Management Unit
DIFFERENTIAL_PAIR
TA1out
S
S
NOTE: Some primary and alternate functions
AC adapter ID.
affect other analog inputs such as
those capacitors are provided on
Caps should connect to GND_SMU_AVSS.
(CPU_SENSE_I/CPU_SENSE_V) requires
TA3out
TA4in
IOC6
Power aliases required by this page:
review the latest SMU specification to ensure missing pull-ups are
TB2in
this page.
SCL
Y
IOC4
Y Y
KI2*
KI0*
AN3
AN2
AN1
Sout3
Y Y
Y Y
Y Y
Y
Y
SCLmm
AN25
INT1*
NMI*
TB1in
AN24
TA1in
TA4out
SDA
AN05
AN07
RXD1
CLK0 RXD0
RTS1*
CLK1
TXD1
RTS0*/
reuire pull-ups that are not. provided on this page. Please.
NC
Real Time Clock
NOTE: CPU current/voltage monitoring
BOM options provided by this page:
ELECTRICAL_CONSTRAINT_SET
- _PP3V3_ALL_SMU
- _PP3V3_ALL_RTC
- _PP3V3_PWRON_SMU
(NONE)
(NONE)
reference used by monitoring
provided on another page.
Sin3
TB0in
(BUSY)
AN0
TA3in
AN21
AN23
AN27
Y
CE*
INT2*
AN04
TA2in
IOC7
CTS0*
AN06
AN20
Y
INT4* INT5*
SDAmm
Y Y S S
Keep crystal subcircuit close to SMU.
S
KI3*
TXD0
AN01
AN03
AN02
AN00
TA2out
CLK3
N = Alternate function
Y = Primary function
S = Spare
Page Notes
- _PPVREF_SMU (SMU AVCC or 2.5V reference) Signal aliases required by this page:
signal (GND_SMU_AVSS). None of
a 100pF capacitor to the SMU AVSS
NOTE: All analog inputs to SMU should have
NOTE: Pinout matches SMU pinout v1.51.
KI1*
Y
CRITICAL
10.000M
11.4X4.7X4.2-SM
21
Y1300
OMIT
M30280F8
QFP-80
10 12
11
77
13
9
79
80
1
2
3
4
5
7
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
32
33
34
35
36
37
38
39
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
68
69
70
71
72
73
74
76
59
60
61
62
63
64
65
66
67
6
75
78
U1300
DS1338U-33
MSOP
2
1
8
3
7
5
6
4
U1301
PP3V3_PWRON
PP3V3_RUN
PP2V5_PWRON
0
NO_SMU_I2C_D
402
5%
21
R1399
MMBD914XXG
3
1
D1310
402
6.3V
10% CERM
1uF
2
1
C1325
402
5%
10K
2
1
R1325
5% 1/16W MF-LF 402
150K
2
1
R1322
CERM
6.3V 402
0.22uF
20%
2
1
C1310
50V
5%
402
CERM
18pF
2
1
C1304
50V
5%
CERM
18pF
402
2
1
C1305
0
5%
402
2
1
R1317
NO STUFF
402
5%
10M
21
R1316
10K
5% MF-LF
2
1
R1327
402
5%
2.0K
21
R1312
5% 1/16W MF-LF
402
2.0K
NO STUFF
21
R1311
402
5%
100K
21
R1313
100K
5% 1/16W MF-LF
402
21
R1310
402
5%
10K
21
R1302
10K
402
5%
21
R1300
5% 1/16W MF-LF
10K
402
12
R1304
402
0.1uF
CERM
20% 10V
2
1
C1309
402
CERM
0.1uF
20% 10V
2
1
C1308
CERM
0.1uF
20% 10V
402
2
1
C1302
402
CERM
0.1uF
20% 10V
2
1
C1301
805
CERM
20%
10uF
6.3V 2
1
C1300
6.3V
10%
1uF
CERM 402
2
1
C1303
4.7
5% 1/16W MF-LF
402
21
R1315
SM
21
XW1300
CRITICAL
SM-1
32.768K
4
1
Y1301
402
5%
10K
21
R1303
04
13 102
051-6772
SYS_SLOT_PWR
TP_SMU_SPARE_P10_0
SYS_RESET_BUTTON_L
SB_SUSPENDACK_L
NB_SUSPENDACK_L
SMU_WARM_RESET_L
SMU_PWRSEQ_P9_6
SB_STOPXTALS_L
I2C_SMU_CPU_SDA_OUT_L
FAN_PWM8
I2C_SMU_B_SCL
SMU_PWRSEQ_P9_5
SYS_COLD_RESET_L
SYS_POWER_BUTTON_L
SMU_SUSPENDREQ_L
SB_TO_SMU_INT_L
CLOCK_RESET_L
SMU_SLEEP
SYS_SLEWING_L
I2C_SMU_CPU_SCL_OUT_L
CPU_HRESET
FAN_RPM1
SYS_LED
FAN_RPM2
SYS_PME_L SMU_QREQ
I2C_SMU_CPU_SCL_IN
FAN_RPM0
I2C_SMU_B_SDA
SMU_BOOT_TXD
SMU_BOOT_RXD
MAKE_BASE=TRUE
SYS_POWERUP_L
CPU_VID<5>
RTC_CLK32K_X2
RTC_CLK32K_X1
=PP3V3_ALL_RTC =PP3V3_ALL_SMU
GND_SMU_AVSS
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=0V
PP3V3_ALL_SMU_AVCC
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=3.3V
=PP3V3_ALL_SMU
GND_SMU_AVSS
SYS_POWER_BUTTON_L
SMU_RESET_L
=PP3V3_ALL_SMU
SMU_BOOT_CNVSS
SYS_POWERFAIL_L
FAN_TACH1
15 MIL SPACING
SMU_CLK10M_XOUT
RTC_CLK32K_X1
RTC_CLK32K_XTAL
15 MIL SPACING
I2C_RTC_SCL
I2C_RTC_SDA
15 MIL SPACING
RTC_CLK32K_X2
SMU_CLK10M_XIN
SMU_CLK10M_XTAL
15 MIL SPACING
I2C_SMU_A_SCL_OUT_L
I2C_SMU_A_SCL_IN
I2C_SMU_D_SCL
SMU_PWRSEQ_P1_2
FAN_RPM4
CPU_BYPASS
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P1_0
SYS_DRIVE_BAY_INT_L
CPU_SENSE_V
CPU_SENSE_I
I2C_SMU_D_SDA
FAN_RPM5 SMU_ONEWIRE
SMU_PWRSEQ_P1_4
SMU_PWRSEQ_P1_3
I2C_SMU_E_SDA I2C_SMU_E_SCL FAN_TACH0
SYS_DOOR_AJAR_L
FAN_TACH2 FAN_TACH3
FAN_TACH5
SMU_TO_SB_INT_L
CPU_TEMP
SMU_CLK10M_XOUT_R
15 MIL SPACING
FAN_RPM3
FAN_TACH4
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SDA_IN
FAN_TACH6
CPU_VID<0>
FAN_TACH8
CPU_VID<2>
FAN_TACH7
CPU_VID<1>
FAN_PWM7
I2C_SMU_CPU_SCL_IN
FAN_PWM6
I2C_SMU_CPU_SDA_IN
SYS_LED_RED
FAN_TACH3
SYS_LED_GREEN
FAN_TACH4
ALS0_OUTFAN_RPM3 ALS1_OUTFAN_RPM4 ALS_GAIN_BOOST
FAN_RPM5
SMU_ACIN
SYS_POWERFAIL_L
SMU_BATT_DET_L
SYS_DRIVE_BAY_INT_L
SYS_LID_OPEN
SYS_DOOR_AJAR_L
SYS_KBDLED
FAN_PWM8
FAN_TACH5
SYS_LED_BLUE DIAG_LED
SMU_CHARGE_BATT
SYS_PME_L
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SYS_COLD_RESET_L
SMU_SLEEP
SYS_POWERUP_L
SYS_RESET_BUTTON_L
=PP3V3_ALL_SMU
CPU_VID<4>
CPU_VID<3>
CPU_VID<2>
CPU_VID<1>
SMU_BOOT_CE
SMU_BOOT_SCLK
SMU_BOOT_BUSY
CPU_VID<0>
I2C_SMU_CPU_SDA_IN
SMU_CLK10M_XOUT
SMU_CLK10M_XIN
SMU_CLK10M_XOUT_R
=PPVREF_SMU
SYS_OVERTEMP_L
SMU_CHARGE_BATT
33
33
13
13
28
33
11
13
36
13
36
13
33
28
11
13
24
13
25
27
77
10
8
33
8
33
13
8
13
18
18
13
77
27
25
24
10
8
27
13
13
13
7
24
13
25
25
18
7
7
13
7
13
7
8
7
8
14
13
13
14
13
13
13
18
18
8
13
13
13
25
25
24
13
13
7
13
7
13
13
13
18
25
8
7
25
8
8
3
25
18
8
18
3
8
6
13
25
27
8
13
18
30
16
21
17
13
28
13
16
18
8
8
6
8
13
13
7
6
8
8 6
8
6
6
6
8
6
16
13
13
18
18
13
13
6
18
18
3
13
30
3
3
8
33
33
18
13
8
3
8
18
18
16
8
17
13
13
25
36
13
13
13
6
18
8
8
8
13
13
21 13
21 13
8
13
8
13
8
13
6
8
8
8
13 21
8
13
13
13
13
8
8
6
7
6
8
8
8
8
8
8
8
8
13
13
13
13
8
16
13
Preliminary
A30B30
A29B29
A28B28
A27B27
A26B26
B25
B24
B23
B22
B21
A25
A24
A23
A22
A21
C30D30
C29D29
C28D28
C27D27
C26D26
C25D25
D22 D23 D24
D21
C24
C23
C22
C21
E30F30
E29F29
E28F28
E27F27
E26F26
E25F25
F24
F23
F22
F21
E24
E23
E22
E21
G30H30
G29H29
G28H28
G27H27
G26H26
H25 G25
G22 G23 G24
H21 H22 H23 H24
G21
H20
H19
H18
H17
H16
H15
H14
H13
H12
H11
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G20
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
E10
E20
E19
E18
E17
E16
E15
E14
E13
E12
E11
E9
E8
E7
E6
E5
E4
E3
E2
E1
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1 B1 A1
A2 A3 A4 A5 A6 A7 A8
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
NC
NC
CPU LOGIC ANALYZER
NC
402
5%
0
DEVELOPMENT
21
R1400
402
5%
0
DEVELOPMENT
21
R1401
5% 402
0
DEVELOPMENT
21
R1402
0
4025%
DEVELOPMENT
21
R1403
NOSTUFF
YFS-30-03-H-08-SB
F-ST-BGA
H9
H8
H7
H6
H5
H4
H30
H3
H29
H28
H27
H26
H25
H24
H23
H22
H21
H20
H2
H19
H18
H17
H16
H15
H14
H13
H12
H11
H10
H1
G9
G8
G7
G6
G5
G4
G30
G3
G29
G28
G27
G26
G25
G24
G23
G22
G21
G20
G2
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G1
F9
F8
F7
F6
F5
F4
F30
F3
F29
F28
F27
F26
F25
F24
F23
F22
F21
F20
F2
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F1
E9
E8
E7
E6
E5
E4
E30
E3
E29
E28
E27
E26
E25
E24
E23
E22
E21
E20
E2
E19
E18
E17
E16
E15
E14
E13
E12
E11
E10
E1
D9
D8
D7
D6
D5
D4
D30
D3
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D2
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D1
C9
C8
C7
C6
C5
C4
C30
C3
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C2
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C1
B9
B8
B7
B6
B5
B4
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J1400
102
14
04
051-6772
EI_CPU_TO_NB_SR_N<1>
EI_CPU1_CLK_P_R
EI_CPU1_CLK_N
EI_NB_TO_CPU_AD<16>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<4>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<0>
CPU1_HTBEN
CPU_HRESET_L
EI_CPU_TO_NB_AD<6> EI_CPU_TO_NB_AD<21> EI_CPU_TO_NB_AD<20> EI_CPU_TO_NB_AD<25> EI_CPU_TO_NB_AD<26> EI_CPU_TO_NB_SR_P<0> EI_CPU_TO_NB_SR_N<0> EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<19>
CPU_INT_L
EI_CPU_TO_NB_AD<15>
=PP1V2_EI_CPU
EI_CPU_TO_NB_AD<8> EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<12> EI_CPU_TO_NB_AD<5> EI_CPU_TO_NB_AD<36> EI_CPU_TO_NB_AD<35> EI_CPU_TO_NB_AD<18> EI_CPU_TO_NB_AD<43> EI_CPU_TO_NB_AD<42> EI_CPU_TO_NB_AD<38> EI_CPU_TO_NB_AD<40> EI_NB_TO_CPU_AD<9> EI_NB_TO_CPU_AD<11> EI_NB_TO_CPU_AD<0>
EI_CPU1_CLK_N
EI_NB_TO_CPU_AD<5>
EI_CPU1_CLK_P
EI_CPU_TO_NB_AD<3> EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<7> EI_CPU_TO_NB_AD<11> EI_CPU_TO_NB_CLK_N EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_AD<17> EI_CPU_TO_NB_AD<14> EI_CPU_TO_NB_AD<24> EI_CPU_TO_NB_AD<28> EI_NB_TO_CPU_AD<14> EI_NB_TO_CPU_AD<12> EI_NB_TO_CPU_AD<18> EI_NB_TO_CPU_AD<19>
EI_CPU1_SYNC CHKSTOP_L
EI_NB_TO_CPU_AD<13> EI_NB_TO_CPU_AD<15> EI_NB_TO_CPU_AD<17> EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<27> EI_NB_TO_CPU_AD<26> EI_NB_TO_CPU_AD<30> EI_NB_TO_CPU_AD<42> EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<40> EI_NB_TO_CPU_AD<10> EI_NB_TO_CPU_AD<39> EI_NB_TO_CPU_AD<36>
EI_NB_TO_CPU_SR_N<0>
RI_L
EI_NB_TO_CPU_SR_P<0>
EI_QREQ_L
I2C_SMU_A_SCL_OUT_L
EI_NB_TO_CPU_AD<1>
EI_NB_TO_CPU_AD<22> EI_NB_TO_CPU_AD<33> EI_NB_TO_CPU_AD<43> EI_NB_TO_CPU_AD<2> EI_NB_TO_CPU_AD<38>
EI_NB_TO_CPU_AD<37>
SYNCENABLE
EI_NB_TO_CPU_SR_N<1>
TP_PROC_TRIGGER_OUT
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_AD<8> EI_NB_TO_CPU_AD<24> EI_NB_TO_CPU_AD<7> EI_NB_TO_CPU_AD<6>
EI_SE
EI_QACK_L
EI_NB_TO_CPU_AD<35>
=PP1V2_EI_NB
EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<32> EI_NB_TO_CPU_AD<23> EI_NB_TO_CPU_CLK_N EI_NB_TO_CPU_CLK_P MCP_L I2C_SMU_A_SDA_OUT_L
=PP1V2_EI_NB
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<16>
EI_NB_TO_CPU_AD<31>
EI_CPU1_CLK_P
EI_CPU1_CLK_N_R
EI_CPU1_SYNC
EI_CPU1_SYNC_R
CPU1_HTBEN
CPU1_HTBEN_R
35 31
30
30
30
30
28
28
29
27
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
30
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
27
29
27
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
27
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
30
29
29 18
29
29
29
29
29
29
29 30
29
29
29
29
29
29 29
29
29
18
29
29
29
29
29
18
18
29
29
29
27
27
28
14
28
28
28 28
28
28
28
28
28
28
28
28
28
28
28
28
28
14
29
28
28
28
28
28
28
28
28
28
28
25
28
18
28
28
28
28
28
28
28
28
28
28
28
28
28
28
14
28
14
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
14
8
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28 28
29 28
28 13
28
28
28
28
28
28
28 29
28 29
28
28
28
28
28 28
28
28
14
28
28
28
28
28
29
13
14
28
28
28
14
14
14
6
27
6
6
6
6 6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6 6
6 6
6 6
6
6
6
6
6
6
6 6
6 6
6
6
6
6
6 6
6
6
7
6
6
6
6
6
6
6
7
6
6
6
6
27
6
27
6
27
Preliminary
SDA SCL
GND
OS
VS+
A2
A1
A0
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
17" SYSTEM FAN 603-5518
I2C ADDR:90(1001000)
OPTICAL TEMP SENSOR
MOTOR CONTROL TACH
12V DC
20" SYSTEM FAN 603-5521
GND
GND
17" CPU FAN 603-5519 20" HD FAN 603-5487
TACH
MOTOR CONTROL
FAN 0
FAN 1
FAN 0, 1 & SYSTEM TEMP
PP3V3_RUN
HF28040-B
M-ST-TH
CRITICAL
4
3
2
1
J1600
10K
1%
402
2
1
R1610
1/16W MF-LF
402
5%
0
21
R1609
10-89-7062
M-ST-TH
CRITICAL
6 5
4
1
J1601
PP3V3_RUN
10K
1% 1/16W MF-LF 402
2
1
R1659
0
1/16W MF-LF
402
5%
21
R1650
NOSTUFF
SOP
LM75
CRITICAL
8
1
2
3
4
5
6
7
U1602
PP3V3_PWRON
NOSTUFF
402
5%
0
21
R1621
402
CERM
16V
20%
0.01UF
2
1
C1660
5%
0
603
21
R1660
603
0
5% 1/10W MF-LF
21
R1661
603
0
5% 1/10W MF-LF
21
R1662
5%
0
603
21
R1663
5%
0
603
21
R1664
CERM
25V
20%
0.1UF
603
NOSTUFF
2
1
C1602
MMBD914XXG
NOSTUFF
31
D1601
1.5K
5% 1/4W MF-LF 1206
2
1
R1605
NTHS5443T1
1206A-03
5
4
87632
1
Q1603
805
5%
1.5K
1/8W
2
1
R1607
MMBD914XXG
3
1
D1602
805
1/8W
5%
0
21
R1608
805
X7R
0.47UF
16V
10%
2
1
C1604
1/8W
5%
1.8K
805
21
R1606
MMBZ5231B
31
DZ1601
PP12V_RUN
1/8W
0
805
5%
NOSTUFF
21
R1604
SOT23-LF
2N7002
2
1
3
Q1602
0.1UF
20% 25V CERM 603
NOSTUFF
2
1
C1601
0
5%
1/8W
805
21
R1603
805
1.0K
5% 1/8W MF-LF
2
1
R1602
2N7002
SOT23-LF
2
1
3
Q1601
805
1/8W
5%
0
21
R1601
1206A-03
NTHS5443T1
5
4
87632
1
Q1653
NOSTUFF
603
0.1UF
20% 25V CERM
2
1
C1652
1/8W
1.5K
5%
805
2
1
R1657
0
5%
1/8W
805
21
R1658
NOSTUFF
MMBD914XXG
31
D1651
16V
0.47UF
X7R 805
10%
2
1
C1654
805
5%
1/8W
1.8K
21
R1656
MMBD914XXG
3
1
D1652
1206
1/4W
5%
1.5K
2
1
R1655
MMBZ5231B
31
DZ1651
NOSTUFF
5%
805
0
1/8W
21
R1654
2N7002
SOT23-LF
2
1
3
Q1652
PP12V_RUN
805
1/8W
5%
0
21
R1653
1/8W
5%
1.0K
805
2
1
R1652
SOT23-LF
2N7002
2
1
3
Q1651
NOSTUFF
603
CERM
25V
20%
0.1UF
2
1
C1651
0
5%
1/8W
805
21
R1651
ELEC
16V
20%
120UF
6.3X11-TH
2
1
C1603
20% 16V ELEC
100UF
6.3X5.8
2
1
C1653
16
102
051-6772 04
F0_GATESLOWDN
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_0_PWR
PP12V_RUN_FAN_1_LCL VOLTAGE=12V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
FAN_0_TACH
FAN_TACH1
FAN_RPM1
FAN_1_CNTL
FAN_1_DRV
F1_DRV
F1_RCFEEDBK
FAN_1_PWR_FILT
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
PP12V_RUN_FAN_1_LC VOLTAGE=12V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
FAN_1_TACH
F1_T2DRAIN
F1_VOLTAGE8R5 F1_GATESLOWDN
FAN_1_TACH_FILT
FAN_1_GND_FILT VOLTAGE=0V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
F0_RCFEEDBK
F0_VOLTAGE8R5
F0_T2DRAIN
F0_DRV
FAN_0_DRV
FAN_0_CNTL
FAN_RPM0
FAN_TACH0
SYS_OVERTEMP_LTEMP_SENSOR_OS
I2C_OPTICAL_SCL
I2C_OPTICAL_SDA
FAN_1_PWR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
27 25
13
13
13
13
13
18
18
Preliminary
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
FAN 2 & HD TEMP
FAN 2
518S0193
I2C ADDR:92(1001001)
GND
+12V DC
20" CPU FAN 603-5459
17" HD FAN 603-5520
REMOTE HARD DRIVE TEMP SENSOR
MOTOR CONTROL
TACH
CRITICAL
M-ST-TH
10-89-7062
6 5
4
1
J1700
PP3V3_RUN
402
1%
10K
2
1
R1709
0
5%
402
MF-LF
1/16W
21
R1700
PP3V3_PWRON
CRITICAL
53261-0498
M-RT-SM
4
3
2
1
6
5
J1701
NTHS5443T1
1206A-03
5
4
87632
1
Q1703
MMBD914XXG
3
1
D1702
CERM
20%
0.1UF
603
NOSTUFF
25V
2
1
C1702
805
1.5K
1/8W
5%
2
1
R1707
805
1/8W
5%
0
21
R1708
805
X7R
0.47UF
16V
10%
2
1
C1704
MMBD914XXG
NOSTUFF
31
D1701
1/8W
5%
1.8K
805
21
R1706
1.5K
5% 1/4W MF-LF 1206
2
1
R1705
MMBZ5231B
31
DZ1701
1/8W
0
805
5%
NOSTUFF
21
R1704
SOT23-LF
2N7002
2
1
3
Q1702
20% 25V CERM 603
NOSTUFF
0.1UF
2
1
C1701
0
5%
1/8W
805
21
R1703
PP12V_RUN
805
1.0K
5% 1/8W MF-LF
2
1
R1702
805
1/8W
5%
0
21
R1701
2N7002
SOT23-LF
2
1
3
Q1701
6.3X11-TH
120UF
20% 16V ELEC
2
1
C1703
102
17
04
051-6772
FAN_2_PWR
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
F2_GATESLOWDN
FAN_TACH2
FAN_RPM2
FAN_2_CNTL
FAN_2_DRV
F2_DRV
F2_T2DRAIN
F2_VOLTAGE8R5
F2_RCFEEDBK
I2C_HD_TEMP_SCL
I2C_HD_TEMP_SDA
FAN_2_TACH
18
18
13
13
6
6
Preliminary
ALIAS
ALIAS
LM339A
V+
GND
LM339A
V+
GND
G
D
S
G
D
S
G
D
S
G
D
S
ALIAS ALIAS
ALIAS ALIAS
ALIAS ALIAS
LM339A
V+
GND
ALIAS ALIAS
ALIAS
ALIAS
ALIAS ALIAS
LM339A
V+
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
PINS 2, 3
PINS 2, 3
I2C ADDR:94??
PINS 7, 8
U5890
GPU TEMP SENSOR
I2C ADDR:92
PINS C1, B1
I2C ADDR:90
PINS 1, 2
OPTICAL TEMP SENSOR
AMBIENT LIGHT SENSOR
J2100
U1602
PINS 26, 27
PULSAR
I2C B BUS
SMU
MASTER U1300
U2600
PINS A20, B20
PINS 18, 19
AUDIO
U9500 / AU300
PINS AA20, Y21
I2C CONNECTIONS
MASTER U1300
U1300
PINS 14,25,23,68
SMU
I2C A BUS
U3
MASTER
OF EACH DIMM
DIMMS
J4000 = A0 J4001 = A2
PINS 91, 92
U3LITE
I2C C BUS
PINS 5, 6
RTC
U1301
MASTER U1300
I2C D & E BUS
U3
PINS C20, B21
U3LITE ’B’
MASTER U1300
PINS 50, 51
U3
U3LITE
CPU JTAG
I2C_CPU_A_SCL
U2900
CPU
MASTER
SMU
USE 576 OHM FOR R1811 IF 5V RAIL IS USED FOR REFERENCE
I2C SB BUS
PINS Y9, AB7
SHASTA
U2300
MASTER
PINS 36-39
PINS C21, E21
PINS 34, 35
U1702
HD TEMP SENSOR
J2100 CAN BE USED AS A SECOND TEMP SENSOR
I2C ADDR:98
SMU OLD ’E’ SMU NEW ’E’
2.0K
5% 1/16W MF-LF
402
2
1
R1812
2.0K
5% 1/16W MF-LF 402
2
1
R1813
PP2V5_PWRON
PP3V3_RUN
1K
5% 1/16W MF-LF 402
2
1
R1814
1K
5%
402
2
1
R1815
5%
2.0K
402
2
1
R1800
402
5%
200
2
1
R1808
402
200
5% 1/16W
2
1
R1810
SOI
3
13
11
10
12
U1800
SOI
3
2
5
4
12
U1800
5% 1/16W
2.0K
2
1
R1801
5%
402
2.0K
2
1
R1818
5%
2.0K
402
2
1
R1819
5%
0
5
6
7
8
4
3
2
1
RP1800
0
5%
NOSTUFF
5
6
7
8
4
3
2
1
RP1801
20% 10V
CERM
402
0.1UF
2
1
C1800
NOSTUFF
402
5%
0
2
1
R1820
NOSTUFF
0
5% 1/16W MF-LF 402
2
1
R1821
0
5% 1/16W MF-LF
402
NOSTUFF
2
1
R1822
NOSTUFF
402
5%
0
2
1
R1823
NOSTUFF
0
5% 1/16W MF-LF
402
2 1
R1824
NOSTUFF
402
5%
0
2 1
R1825
0
5% 1/16W MF-LF
402
2 1
R1826
5% MF-LF
0
402
2 1
R1827
SOT-363
2N7002DW
1
2
6
Q1800
SOT-363
2N7002DW
4
5
3
Q1800
5%
4.7K
402
2
1
R1828
0.1UF
402
CERM
10V
20%
2
1
C1802
5%
402
4.7K
2
1
R1811
402
2.0K
5%
NOSTUFF
2
1
R1830
2.0K
5%
402
NOSTUFF
2
1
R1831
603
0
21
R1832
0
603
NOSTUFF
21
R1833
SOT-363
2N7002DW
4
5
3
Q1801
402
200
5%
2
1
R1817
402
200
5%
2
1
R1816
SOT-363
2N7002DW
1
2
6
Q1801
SOI
3
1
7
6
12
U1800
2.0K
5% 1/16W MF-LF 402
2
1
R1802
402
5%
2.0K
2
1
R1803
NOSTUFF
4.7K
5%
402
2
1
R1809
402
5%
2.0K
2
1
R1804
2.0K
5% 1/16W MF-LF
402
2
1
R1805
PP3V3_PWRON
PP2V5_PWRON
SOI
3
14
9
8
12
U1800
PP3V3_ALL
1/16W MF-LF 402
5%
2.0K
2
1
R1806
1/16W MF-LF
402
5%
2.0K
2
1
R1807
0.1UF
10V 402
CERM
20%
2
1
C1801
04
18
102
051-6772
I2C_RTC_SDA
I2C
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
I2C_SMU_B_SDA
NET_SPACING_TYPE=I2C
SMU_CPU_JTAG_OR_I2C
I2C_SMU_E_SDA
I2C
I2C_SMU_E_SCL
I2C
I2C_CPU_A_SDA_TO_SMU
I2C_CPU_A_SDA
NET_SPACING_TYPE=I2C
I2C_SMU_CPU_SCL_OUT_L MAKE_BASE=TRUE
I2C
I2C_SMU_CPU_SDA_IN MAKE_BASE=TRUE
I2C
I2C_SMU_CPU_SDA_OUT_L
I2C
MAKE_BASE=TRUE
MAKE_BASE=TRUE
I2C_SMU_CPU_SCL_IN
I2C
I2C_SMU_A_SCL_OUT_L MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
I2C_CPU_A_SCL
I2C_NB_B_SDA
I2C
I2C_0V6_REF
NET_SPACING_TYPE=I2C
MAKE_BASE=TRUE
I2C_SMU_A_SDA_IN
PP3V3_PWRON
=PP1V2_EI_CPU
JTAG_CPU_TCK
JTAG_CPU_TMS
JTAG_CPU_TDI
JTAG_CPU_TDO
I2C_SMU_A_SDA_OUT_L MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
I2C_SMU_D_SCL
I2C
I2C_RTC_SCL
I2C
I2C_NB_B_SCL
I2C
I2C_SMU_D_SDA
I2C
I2C_DIMM_SDA I2C_DIMM_SCL
NET_SPACING_TYPE=I2C
MAKE_BASE=TRUE
I2C_NB_C_SCL
MAKE_BASE=TRUE
I2C_NB_C_SDA
NET_SPACING_TYPE=I2C
MIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=12MIL
PP5V_U1800
PP3V3_RUN
PP5V_RUN
PP5V_PWRON
MAKE_BASE=TRUE
I2C_SMU_A_SCL_IN
NET_SPACING_TYPE=I2C
PP3V3_PWRON
I2C_CPU_A_SDA_TO_CPU
NET_SPACING_TYPE=I2C
I2C_CPU_SCL_LS
=PP1V2_EI_NB
NET_SPACING_TYPE=I2C
I2C_SB_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
I2C_SB_SDA
I2C_AUDIO_SDA I2C_AUDIO_SCL
I2C_NB_A_SCL
I2C_NB_A_SDA
I2C_CLOCK_SDA
I2C_OPTICAL_SDA
I2C_CLOCK_SCL
I2C_OPTICAL_SCL
I2C_ALS_SDA I2C_ALS_SCL
I2C_HD_TEMP_SCL
I2C_HD_TEMP_SDA
MAKE_BASE=TRUE
NET_SPACING_TYPE=I2C
I2C_SMU_B_SCL
I2C_GPU_DIODE_SDA I2C_GPU_DIODE_SCL
50
35
34
58
31
22 58
27
30
11
11
27
14
18
29
14
10
10
18
28
13
11
14
30
30
30
30
13
7
7
11
11
14
25
25
17
17
13
13
13
13
29
13
13
13
13
6
29
24
13
6
7
29
29
29
29
6
13
13 24
13
40
40
24
24
6
6
6
13
6
7
6
6
95
95
24
24
27
16
27
16
21
21
6
6
13
58
58
Preliminary
GRN
BLUE
AMB
+
-
+
-
+
-
+
-
D
S
G
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
TABLE_5_ITEM
TABLE_5_ITEM
INDICATOR LED
TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS
PLACE THESE PARTS CLOSE TO SMU IC
CHANGE R2100 VALUE
PLACE THESE PARTS CLOSE TO SMU IC
PWM INPUT FROM SMU
5MV INPUT OFFSET
PWM INPUT FROM SMU
PWM INPUT FROM SMU
100% DUTY CYCLE OF 3V-PP PWM = 0.5V
TO SET LED CURRENT
PLACE THESE PARTS CLOSE TO SMU IC
PWM INPUT FROM SMU
(AND NO STUFF R2132, R2119 & Q2100)
(STUFF WHEN SYS_LED_L = ACTIVE HIGH)
PLACE THESE PARTS CLOSE TO SMU IC
MAX LED CURRENT = 0.5 / R
<-- 17 INCH
<-- 17 INCH
<-- 17 INCH
20 INCH -->
518S0193
AMBIENT LIGHT SENSOR
J2100 CAN BE USED AS A SECOND TEMP SENSOR
PP5V_PWRON
PP5V_PWRON
PLCC
RGB_LED
LATBG66B
AMB-GRN-BLUE
4
3
1
5
2
6
LED2100
LP324
RGB_LED
4
8
9
10
11
U2100
PP5V_PWRON
RGB_LED
1%
402
953K
2
1
R2109
PP5V_PWRON
2N3904LF
RGB_LED
2
3
1
Q2102
25.5
1% MF-LF
402
RGB_LED
2
1
R2100
LP324
RGB_LED
4
14
13
12
11
U2100
1%
1K
402
RGB_LED
2 1
R2112
402
953K
1%
RGB_LED
2
1
R2104
200K
RGB_LED
1%
402
2
1
R2105
20%
0.47UF
603
RGB_LED
CERM
10V
2
1
C2106
RGB_LED
402
0
5%
2 1
R2101
RGB_LED
1%
953K
402
2
1
R2102
PP5V_PWRON
2N3904LF
RGB_LED
2
3
1
Q2108
1%
25.5
RGB_LED
2
1
R2113
RGB_LED
LP324
4
7
6
5
11
U2100
1%
RGB_LED
1K
402
2 1
R2114
RGB_LED
953K
402
1%
2
1
R2110
200K
402
1%
RGB_LED
2
1
R2111
0.47UF
20% 10V
603
RGB_LED
CERM
2
1
C2112
RGB_LED
0
5%
402
2 1
R2115
RGB_LED
402
953K
1%
2
1
R2118
PP5V_PWRON
RGB_LED
2N3904LF
2
3
1
Q2114
1%
25.5
402
RGB_LED
2
1
R2126
LP324
RGB_LED
4
1
2
3
11
U2100
1%
1K
402
RGB_LED
2 1
R2127
953K
1%
402
RGB_LED
2
1
R2116
200K
1%
402
RGB_LED
2
1
R2117
CERM
10V
20%
0.47UF
603
RGB_LED
2
1
C2118
5%
0
RGB_LED
402
2 1
R2130
RGB_LED
0.022UF
402
CERM
16V
20%
2 1
C2101
16V
CERM
402
RGB_LED
20%
0.022UF
21
C2102
20%
0.022UF
402
CERM
16V
RGB_LED
2 1
C2104
0.1UF
20%
RGB_LED
10V
CERM
402
2
1
C2103
5%
402
1K
NOSTUFF
2 1
R2132
PP3V3_PWRON
NOSTUFF
SOT-23
FDV302P
2
1
3
Q2100
400-OHM-EMI
RGB_LED
SM-1
2
1
L2100
RGB_LED
400-OHM-EMI
SM-1
2
1
L2101
400-OHM-EMI
SM-1
RGB_LED
2
1
L2102
220PF
402
CERM
RGB_LED
25V
5%
21
C2105
220PF
RGB_LED
402
5% 25V CERM
2
1
C2107
400-OHM-EMI
SM-1
RGB_LED
21
L2104
220PF
RGB_LED
5%
25V 402
CERM
2 1
C2108
220PF
CERM
402
25V
5%
RGB_LED
2 1
C2109
25V
220PF
5%
CERM
402
WHITE_LED
2 1
C2110
402
WHITE_LED
CERM
5% 25V
220PF
2
1
C2111
WHITE_LED
0
5%
402
2 1
R2107
1%
402
NOSTUFF
953K
2 1
R2119
WHITE_LED
FDV301N
SM
2
1
3
Q2101
SM6
WHITE
2
1
LED2101
PP3V3_PWRON
CRITICAL
53261-0498
M-RT-SM
4
3
2
1
6
5
J2100
PP3V3_PWRON
WHITE_LED
603
0
5% 1/10W MF-LF
21
R2120
603
0
5% 1/10W MF-LF
WHITE_LED
2
1
R2121
1% MF-LF
402
56.2
17_INCH_LCD
2
1
R2103
5%
402
1K
WHITE_LED
2 1
R2106
402
5%
4.7K
WHITE_LED
2
1
R2129
10221
051-6772 04
114S3921
20_INCH_LCD
1
RES, 39.2 OHM, 1%, 402
RES, 18.2 OHM, 1%, 402
114S1821
3
R2100,R2113,R2126
NOSTUFF
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
SYS_DRV_A
MIN_NECK_WIDTH=10MIL
SYS_DRV_K
MIN_LINE_WIDTH=25MIL
SYS_LED_DRV_K MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
SYS_LED_H
I2C_ALS_SCL
I2C_ALS_SDA
U2100_UNUSED
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
G_DRV_K
G_BASE_DRV
MIN_NECK_WIDTH=10MIL
R_DRV_K MIN_LINE_WIDTH=25MIL
B_DRV_K MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
SYS_LED
SYS_GATE
B_BASE_DRV
R_PWM_DC
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
SYS_LED_DRV_C
G_PWM_DC
G_IN_OFFSET
SYS_LED_IN
GND_CHASSIS_LED
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
RGB_LED_A
GND_CHASSIS_LED
B_IN_OFFSET
G_PWM_IN_H
MAKE_BASE=TRUE
SYS_LED_BLUE
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
B_DRV
MIN_LINE_WIDTH=25MIL
B_DRV_FB MIN_NECK_WIDTH=10MIL
R_DRV MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
R_DRV_FB
R_BASE_DRV
MAKE_BASE=TRUE
SYS_LED_RED
R_PWM_IN_H
MAKE_BASE=TRUE
SYS_LED_GREEN
R_IN_OFFSET
B_PWM_DC
B_PWM_IN_H
GND_CHASSIS_LED
MIN_LINE_WIDTH=25MIL
G_DRV
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
G_DRV_FB MIN_NECK_WIDTH=10MIL
21
21
21
18
18
6
13
7
7
13
13
13
7
Preliminary
G
D
S
GND
GND
VDD
(SYM 6 OF 7)
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
LM339A
V+
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
PLACE LED2200 NEAR VREG
1.5V RUN FET
RDSON=0.012 OHM @ VGS=3.5 V
U2200_FEEDBACK
NOTE:
VOUT=VREF*(R2203+R2205)/R2205=1.53VDC
IRU3037CS VREF=1.25VDC
SET OUTPUT=1.5VDC FOR U3LITE CORE
7.73A OF PEAK CURRENT DRAW ON PCORE_NB
U3LITE CORE POWER
IS D2250 NEEDED?
CHECK FETS
10UF
1206
CERM
6.3V
20%
2
1
C2201
1800UF
20%
6.3V ELEC TH-KZJ
2
1
C2209
6.3V ELEC
1800UF
20%
TH-KZJ
2
1
C2208
603
0.5%
10K
2
1
R2205
NOSTUFF
603
20% CERM
10V
1UF
2
1
C2207
NOSTUFF
20%
1UF
1206
CERM
25V
2
1
C2212
PP5V_PWRON
NTD60N02R
CASE369
Q2201
0.022UF
NOSTUFF
603
10%
50V CERM
2
1
C2205
805
0
5%
1/8W
21
R2202
CERM
25V
20%
1UF
805
2
1
C2204
220PF
5% 25V CERM 402
2
1
C2206
PP5V_PWRON
0.1UF
CERM
16V
20%
603
2
1
C2214
20%
805
CERM
25V
1UF
2
1
C2216
25V CERM 805
1UF
20%
2
1
C2217
SOD-123
MBR0520LXXG
2 1
D2200
MBR0520LXXG
SOD-123
2 1
D2201
MBR0520LXXG
SOD-123
2
1
D2202
OMIT
U3LITE
V1.0-300MM
PBGA
R14
T16
T11
U18
U13
U10
V15
K15
V12
K12
L17
L14
M16
M11
N18
N13
P15
P12
R17
W17
W14
AC13
B22
B16
B13
B4
AC7
D25
D19
D10
D7
D2
F22
F16
F13
G27
G23
AE25
G4
H19
H10
J14
J9
K25
K21
K16
K11
K6
AE19
K2
L18
L13
L10
M20
M15
M12
N27
N23
N17
AE10
N14
N9
N8
N4
P19
P16
P11
R18
R13
R10
AE4
T27
T23
T20
T15
T12
T6
T2
U17
U14
U9
AG22
V19
V16
V11
W25
W21
W18
W13
W8
W4
Y20
AG16
Y15
Y12
AA19
AA10
AB27
AB23
AB6
AB2
AC22
AC16
AG13
AG7
U3
CASE369
NTD60N02R
3
1
4
Q2202
TH
1.6UH
21
L2201
NOSTUFF
402
1% 1/16W MF-LF
1.1K
2
1
R2204
SOI
IRU3037CS
2 6
8
3
5
4
1
7
U2200
603
0.5% 1/16W
2.21K
2
1
R2203
1%
27.4K
402
2
1
R2201
3900PF
5% 50V CERM 603
2
1
C2215
CERM
50V
5%
68PF
603
2
1
C2213
PP5V_PWRON
805
1/8W
5%
4.7
2
1
R2200
PP1V5_RUN
NOSTUFF
SMB
10BQ040PBF
21
D2250
NOSTUFF
20%
CERM
0.1UF
10V 402
21
C2250
2N7002
SOT23-LF
2
1
3
Q2251
PP5V_PWRON
100K
402
5%
2 1
R2250
6.3V ELEC
1800UF
20%
TH-KZJ
2
1
C2202
TH-KZJ
20%
1800UF
ELEC
6.3V
2
1
C2203
1206
20% CERM
6.3V
10UF
2
1
C2210
IRF7413
SO-8
321
4
8765
Q2250
5% 1/16W MF-LF
DEVELOPMENT
330
402
2
1
R2260
GREEN
DEVELOPMENT
2.0X1.25A
2
1
LED2200
SOI
DEVELOPMENT
3
1
7
6
12
U1001
DEVELOPMENT
402
0
5% 1/16W MF-LF
21
R2261
402
0.1UF
20% 10V CERM
2
1
C2222
0.1UF
CERM
10V
20%
402
2
1
C2223
402
10V
0.1UF
20% CERM
2
1
C2225
CERM
10V
20%
0.1UF
402
2
1
C2228
402
0.1UF
20% 10V CERM
2
1
C2227
0.1UF
CERM
10V
20%
402
2
1
C2230
0.1UF
CERM 402
20% 10V
2
1
C2229
10V CERM
20%
0.1UF
402
2
1
C2232
20%
402
0.1UF
10V CERM
2
1
C2231
CERM
10V
20%
0.1UF
402
2
1
C2234
402
0.1UF
20% 10V CERM
2
1
C2233
CERM
10V
20%
0.1UF
402
2
1
C2236
402
0.1UF
20% 10V CERM
2
1
C2235
402
CERM
10V
20%
0.1UF
2
1
C2238
0.1UF
402
20% 10V CERM
2
1
C2237
CERM
10V
20%
0.1UF
402
2
1
C2240
CERM 402
0.1UF
20% 10V
2
1
C2239
CERM
10V
20%
0.1UF
402
2
1
C2242
402
0.1UF
20% 10V CERM
2
1
C2243
402
CERM
10V
20%
0.1UF
2
1
C2244
CERM
10V
20%
0.1UF
402
2
1
C2245
CERM
10V
20%
0.1UF
402
2
1
C2246
CERM
10V
20%
0.1UF
402
2
1
C2247
102
22
04
051-6772
Q2201_GATE
U2200_GATE_L
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL
PPVCORE_NB
MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
=PPVCORE_NB
=PPVCORE_NB
U2200_GATE_H
U2200_VC_D
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
Q2202_DRAIN
U2200_VC_R
R2204_P2
U2200_VC
R2201_P2
PPVCORE_GPU
SYS_SLEEP
U2200_SS
U2200_FEEDBACK
U2200_COMP
=PPVCORE_NB
Q5006G
PP3V3_RUN
LED_PP1V5_RUN_P
1V1_REF
PP1V5_RUN_FOR_LED
LED_PP1V5_RUN_N
50
46
34
11
18
10
11
51
9
10
50
22
50
8
22
7
34
6
7
7
6
6
7
6
10
Preliminary
VIO1
POWER
VDDO33
VDDO25
VIO2
VDDP_KL
VDDC
GND
GND
GND
(1 OF 8)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
Master: Link
other Shasta supplies.
- _PP2V5_PWRON_SB
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
different drive timing
PCI, otherwise 3.3V.
Connect _PPPCI32_PWRON_SB to
spec for 5V vs. 3.3V operation.
appropriate PCI bus voltage and
Signal aliases required by this page: (NONE)
(NONE)
BOM options provided by this page:
Power Sequencing:
- _PPVCORE_PWRON_SB (1.2V) NOTE: PCI pads use the VIO supply to meet
characteristics required by the PCI
_PPPCI64_PWRON_SB to same if 64-bit
Must power Shasta VCore rail before any
Page Notes
Power aliases required by this page:
Shasta Core Power
Shasta max (est 06/30/03) current:
VDDPs - 2.5V - 100 mA ( 250 mW) I/O 2.5 - 2.5V - 20 mA ( 60 mW)
Total: 3015 mW
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
ANALOG12 - 1.2V - 600 mA ( 760 mW)
DIGITAL - 1.2V - 950 mA (1175 mW)
For PCI_AD<31..0>
For PCI_AD<63..32>
20% 10V CERM 402
0.1uF
2
1
C2304
10V CERM 402
0.1uF
20%
2
1
C2305
0.1uF
402
CERM
10V
20%
2
1
C2306
20% 10V CERM 402
0.1uF
2
1
C2307
0.1uF
402
20% CERM
10V
2
1
C2308
20% 10V
402
CERM
0.1uF
2
1
C2309
0.1uF
402
CERM
10V
20%
2
1
C2302
0.1uF
402
CERM
10V
20%
2
1
C2301
20% 10V CERM 402
0.1uF
2
1
C2300
0.1uF
402
CERM
10V
20%
2
1
C2314
0.1uF
402
CERM
10V
20%
2
1
C2313
402
20% 10V CERM
0.1uF
2
1
C2312
20% 10V CERM 402
0.1uF
2
1
C2311
402
CERM
20% 10V
0.1uF
2
1
C2310
20% 10V CERM 402
0.1uF
2
1
C2334
0.1uF
402
CERM
10V
20%
2
1
C2333
0.1uF
402
CERM
10V
20%
2
1
C2339
20% 10V CERM 402
0.1uF
2
1
C2338
20% 10V CERM 402
0.1uF
2
1
C2332
0.1uF
402
CERM
10V
20%
2
1
C2331
0.1uF
402
CERM
10V
20%
2
1
C2337
20% 10V CERM 402
0.1uF
2
1
C2336
20% 10V CERM 402
0.1uF
2
1
C2330
0.1uF
402
CERM
10V
20%
2
1
C2335
0.1uF
402
CERM
10V
20%
2
1
C2324
0.1uF
402
CERM
10V
20%
2
1
C2323
20% 10V CERM 402
0.1uF
2
1
C2329
20% 10V CERM 402
0.1uF
2
1
C2328
20% 10V CERM 402
0.1uF
2
1
C2322
CERM
20% 10V
402
0.1uF
2
1
C2321
0.1uF
402
CERM
10V
20%
2
1
C2327
0.1uF
402
CERM
10V
20%
2
1
C2326
0.1uF
402
CERM
10V
20%
2
1
C2320
20% 10V CERM 402
0.1uF
2
1
C2325
20% 10V CERM
0.1uF
402
2
1
C2351
0.1uF
402
10V
20% CERM
2
1
C2350
0.1uF
402
20% 10V CERM
2
1
C2357
20% 10V CERM 402
0.1uF
2
1
C2356
0.1uF
402
CERM
10V
20%
2
1
C2355
CERM 402
0.1uF
10V
20%
2
1
C2362
20% CERM
402
0.1uF
10V
2
1
C2361
0.1uF
10V 402
CERM
20%
2
1
C2360
0.1uF
402
CERM
10V
20%
2
1
C2365
OMIT
BGA
V1.0
SHASTA
Y19
W22
L21
K21
H17
H18
V8
D1
B5
B2
B1
AB6
AB2
AB10
AA3
W4
V7
U9
U12
R2
M1
L7
H1
F8
F4
AA2
AA1
G15
D19
P15
N8
M15
L8
L15
K8
J15
J12
T15
T10
R9
R12
R10
H8
H15
D2
C19
AB22
AB1
W5 W19 U22 U13 U10 T12 R19 P9 P4
AA6
P14 P13 P12 P10 N9 N22 N13 N12 N11 N10
AA10
M2
M14
M13
M12
M11
M10
L9
L16
L14
L13A5L12
L11
L10
K9
K7
K13
K12
K11
K10
J22
A22
J16
J14
J13
J11
J10
H9
H2
F7
F3
E22
A2
A1
U2300
20% 10V CERM 402
0.1uF
2
1
C2303
23 102
051-6772
04
=PP2V5_PWRON_SB
=PPPCI64_PWRON_SB
=PPPCI32_PWRON_SB
=PP3V3_PWRON_SB
=PP2V5_PWRON_SB
=PPVCORE_PWRON_SB
88
88
74
74
25
74
25
7
23
25
23
6
7
7
7
7
7
3
Preliminary
G
D
S
G
D
S
G
D
S
G
D
S
SYS_ISCL0 SYS_ISCA0
SYS_ISCA1
SYS_ISCL1
API_ISCA
API0_ISCL
THMO
DUMMY_A DUMMY_B
PMR_OBSV
IRQ0
THMI
(SYM 7 OF 7)
HRESET*
PURESET* SUSPENDACK* SUSPENDREQ*
CE1_B_TDO
CE1_A_TDI
CE1_LT_TCK
VSP_CLKN
VSP_CLKP
CE1_DI1_TMS CE1_DI2_TRST CE1_RI
CEO_TEST
PM_SLEEP0
CE0_RE
CE0_MC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
LAST MODIFIED: JUNE 10, 04
MASTER: GILA
JTAG_NB_TRST_L
U3LITE MISC
HIGH FOR NORMAL OPERATION
JTAG_NB_TDO JTAG_NB_TMS
JTAG_NB_TDI
JTAG_NB_TCK
U3LITE REQUIRES ALL JTAG SIGNALS
PP3V3_PWRON
PP3V3_PWRON PP2V5_PWRON
PP2V5_PWRON
PP2V5_PWRON
MF-LF
1/16W
5%
4.7K
402
2
1
R2435
20% 10V
402
0.1UF
CERM
2
1
C2400
402
330
MF-LF
1/16W
5%
2
1
R2419
SOT-363
2N7002DW
4
5
3
Q2404
402
330
1/16W
5% MF-LF
2
1
R2420
100
1% MF-LF
402
2
1
R2400
SOT-363
2N7002DW
1
2
6
Q2404
NOSTUFF
2N7002DW
SOT-363
4
5
3
Q2412
NOSTUFF
MF-LF
10K
402
5% 1/16W
2
1
R2438
NOSTUFF
SOT-363
2N7002DW
1
2
6
Q2412
100
1% MF-LF
402
2
1
R2403
5%
10K
402
2
1
R2424
10K
5% 1/16W MF-LF 402
2
1
R2426
5%
10K
402
2
1
R2429
402
10K
5% 1/16W MF-LF
2
1
R2431
5%
10K
402
2
1
R2433
5%
10K
402
2
1
R2436
402
5% 1/16W MF-LF
10K
2
1
R2442
402
10K
5% 1/16W MF-LF
2
1
R2443
5%
10K
402
2
1
R2444
NOSTUFF
5% 1/16W MF-LF 402
4.7K
2
1
R2405
402
5%
0
21
R2406
NOSTUFF
402
5%
0
21
R2408
PBGA
OMIT
U3LITE
V1.0-300MM
P4 R4
J18
J17
C21
C20
E21
B21
D21
D20
E20
D15
Y9
E9
A21
AB28
AC28
AH3
AC2
R25
F20
M26
AA25
V25
AD3
AD5
B20
A20
U3
1%
121
402
2
1
R2402
402
121
1% 1/16W MF-LF
2
1
R2401
603
25V
5% CERM
NOSTUFF
1000PF
2
1
C2401
04
24
102
051-6772
=PP1V2_HT
PMU_SUSPEND_REQ
NB_VSP_CLK_VREF VOLTAGE=0.6V
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VSP_NB_CLK_P
NB_COLD_RESET_L
NB_PU_RESET
SYS_COLD_RESET_L
TP_NB_PM_SLEEP0
NB_MC_PD NB_RE_PD
NB_TEST_PD
NB_RI_PU
NB_SUSPEND_REQ_L
NB_SUSPEND_ACK_L
NB_COLD_RESET_L
NB_WARM_RESET_L
TP_DUMMY_B
TP_DUMMY_A
NB_INT_L
NB_PMR_OBSV
NB_THMI NB_THMO
I2C_NB_A_SCL I2C_NB_A_SDA
I2C_NB_C_SCL I2C_NB_C_SDA
I2C_NB_B_SDA
I2C_NB_B_SCL
NB_SUSPEND_REQ_L
SMU_SUSPENDREQ_L
VSP_NB_CLK_N
JTAG_NB_TCK JTAG_NB_TDI
JTAG_NB_TRST_L
JTAG_NB_TDO JTAG_NB_TMS
28
60
13
25
7
27
24
8
6
24
8
24
8
6
6
25
8
8
8
18
18
18
18
18
18
24
13
27
Preliminary
GND
PLL_49
GND
XTAL_18 PLL_45
GND
VIO PME
PLL_49
VDD
PLL_45
VDD
XGI
XTALS
TEST
PWR_MGT
PCI
GPIO
I2C
I2S2 I2S1 I2S0
(2 OF 8)
PCI1C_BE_4_L PCI1C_BE_5_L PCI1C_BE_6_L PCI1C_BE_7_L
PCI1PAR64_H
XGI_DTI_H
XGI_DTO1_H
XGI_CLK_H
XGI_DTO0_H
PCI1ACK64_L
PCI1REQ64_L
PCI1AD_60_H
PCI1AD_63_H
PCI1AD_62_H
PCI1AD_61_H
PCI1AD_50_H
PCI1AD_52_H PCI1AD_53_H
PCI1AD_51_H
PCI1AD_59_H
PCI1AD_58_H
PCI1AD_57_H
PCI1AD_56_H
PCI1AD_55_H
PCI1AD_54_H
PCI1AD_40_H PCI1AD_41_H PCI1AD_42_H PCI1AD_43_H PCI1AD_44_H
PCI1AD_49_H
PCI1AD_48_H
PCI1AD_47_H
PCI1AD_46_H
PCI1AD_45_H
PCI1AD_39_H
PCI1REQ_5_L
PCI1AD_32_H
PCI1AD_34_H
PCI1AD_38_H
PCI1AD_37_H
PCI1AD_36_H
PCI1AD_33_H
PCI1AD_35_H
PCI1GNT_5_L
PCI1GNT_4_L
PCI1REQ_4_L
PCI1GNT_3_L
PCI1REQ_3_L
XTAL_18XTAL
VDD VDD
FSTEST
XTAL_18_I XTAL_18_O
XTALI XTALO
PLLTEST
TEST_MODE_H
TDI
TCK TMS
TDO
INTRWD_H
I2CDATA_H
I2CCLK_H
PCI_SEL32BIT_H
GPIO_H_3
GPIO_H_2
GPIO_H_1
I2S2SYNC_H
I2S2BITCLK_H
I2S2MCLK_H
I2S2DTO_H
I2S2DTI_H
GPIO_H_0
I2S1DTO_H I2S1MCLK_H I2S1BITCLK_H I2S1SYNC_H
I2S1DTI_H
I2S0BITCLK_H I2S0SYNC_H
I2S0DTI_H I2S0DTO_H I2S0MCLK_H
RESET_L STOPXTALS_L SUSPENDREQ_L SUSPENDACK_L PCI1PME_L
TRST_L
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
MASTER: SEEDY
Shasta Serial / Misc
the audio circuit to provide the
(I2S2_DEV_TO_SB_DTI)
(I2S1_RESET_L)
DO NOT swap between RPAKs
42
I2S2: S/P-DIF
(I2S1_DEV_TO_SB_DTI)
REDUNDANT - NEED TO ADDRESS THIS
I2S0: Audio DAC
I2S1: Soft Modem
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
GPIO
NC
BOM options provided by this page:
Power aliases required by this page:
26
(I2S0_DEV_TO_SB_DTI)
10
7
11
8
17
13 14 15 16
9
12
22 23
27
19
18
20
24 25
(SCCA)(SCCB)
31
33
30
28
34
36 37 38
43
41
44 45
47
46
39 40
53 54
50
51 52
49
48
(I2S2_RESET_L)
29
- _PP3V3_PCI
- _PP2V5_PWRON_SB
(NONE)
NOTE: XGC required for Shasta GPIOs
6
"Slot E" - AD21
21
32
35
Signal aliases required by this page:
- _PP1V2_PWRON_SB
- _PP3V3_PWRON_SB
AUDIO GPIO - see note on right
- PCI_64BIT
- MPIC_NB/MPIC_SB
To SouthBridge ->
From SouthBridge <-
-> From NorthBridge
<- To CPU
necessary pull-ups & pull-downs.
AUDIO GPIOS
NOTE: It is the responsibility of
Re-pin within each RPAK as necessary
REDUNDANT - NEED TO ADDRESS THIS
Selects whether NorthBridge or
Configures Shasta for 64-bit PCI
Page Notes
NorthBridge / SouthBridge MPIC Routing
interrupt controller.
SouthBridge MPIC will be used for
"Slot F" - AD22
PCI 32-bit select
0 = 64-bit PCI & XGC
1 = 32-bit PCI & GPIOs
NOSTUFF
10uF
20%
6.3V 1206
CERM
2
1
C2500
402
CERM
1uF
10%
6.3V
2
1
C2501
402
10%
CERM
1uF
6.3V
2
1
C2511
NOSTUFF
20%
6.3V CERM 1206
10uF
2
1
C2510
NOSTUFF
20%
6.3V CERM 1206
10uF
2
1
C2520
402
CERM
6.3V
10%
1uF
2
1
C2521
NOSTUFF
10uF
CERM 1206
20%
6.3V
2
1
C2530
CERM
402
10%
1uF
6.3V
2
1
C2531
402
5%
10K
2
1
R2500
402
PCI_64BIT
5%
1K
2
1
R2501
1% 1/16W MF-LF 402
200
2
1
R2590
50V
5%
22pF
402
CERM
2
1
C2591
402
CERM
50V
5%
22pF
2
1
C2590
5%
402
4.7K
2
1
R2580
V1.0
BGA
SHASTA
OMIT
Y13
V13
W13
AB12
W14
V15
U15
T9
U7
W2
Y4
W17
W12
Y11
A3
W11
AA11
AB11
U11 V11
W10
E9
Y12
AA12
AA13AB13
U14
W6
U16
AB21
U17
K17
W18
E18
Y20
AA20
AA19
K20
K22
H22
J20
H21
G22
F22
J19
H20
G21
F21
J17
H19
K18
D22
G20
D21
C22
G19
F20
C21
E20
D20
F19
E19
G18
G17
C20
B21
A21
F16
G16
F17
F18
A20
D18
L17
V12
W9
Y7
Y8
AA5
AB4
AA7
V9
AB5
V10
AA8
Y6
U8
Y5
W7
AA4
AB7
Y9
W8
AB3
Y2
V5
V14
U2300
0.1uF
402
CERM
10V
20%
2
1
C2540
10K
5%
63
RP2551
5%
10K
81
RP2550
5%
10K
54
RP2550
10K
5%
72
RP2550
10K
5%
81
RP2551
5%
10K
72
RP2551
10K
5%
54
RP2551
10K
5%
81
RP2552
5%
10K
63
RP2550
5% 1/16W SM-LF
10K
72
RP2552
5%
10K
54
RP2552
5%
10K
63
RP2552
5% 1/16W
10K
72
RP2553
10K
5%
54
RP2553
5% 1/16W SM-LF
10K
81
RP2553
5%
10K
63
RP2553
10K
5%
402
21
R2550
10K
5%
402
21
R2551
402
5%
10K
21
R2552
5% 1/16W MF-LF
10K
402
21
R2553
5% 1/16W MF-LF
10K
402
21
R2556
5% 1/16W MF-LF
10K
402
21
R2557
10K
5%
402
21
R2558
10K
5%
402
21
R2559
402
5%
10K
21
R2564
10K
402
5%
21
R2563
402
5%
1K
21
R2560
5%
402
10K
21
R2561
10K
402
5%
21
R2566
5% 1/16W MF-LF
402
10K
21
R2565
5% 1/16W MF-LF
402
10K
21
R2567
5%
402
10K
21
R2568
NO STUFF
402
5%
1K
21
R2562
10K
5%
NO STUFF
402
21
R2555
1K
5%
402
21
R2554
PP3V3_RUN
402
5%
10K
2
1
R2576
2N3904LF
MPIC_SB
2
3
1
Q2576
5% 1/16W MF-LF
402
10K
MPIC_SB
21
R2575
MPIC_NB
5% 1/16W MF-LF
402
0
2
1
R2579
5% 1/16W MF-LF
MPIC_SB
47
402
21
R2578
5%
33
7
8
6
5
2
1
3
4
RP2510
33 5%
8
7
6
5
1
2
3
4
RP2530
5%
33
6
5
8
7
3
4
1
2
RP2520
3.3
805
1/8W
5%
21
R2505
5%
1/8W
805
3.3
21
R2510
3.3
805
1/8W
5%
21
R2520
1/8W
5%
805
3.3
21
R2530
5%
0
402
21
R2511
18.432M
11.4X4.7X4.2-SM
21
Y2590
25 102
04
051-6772
SB_CLK18M_XTALO
SB_CLK18M_XTALI
I2S0_MCLK I2S0_BITCLK
SB_GPIO46
SB_GPIO49
SB_GPIO51
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL45VDD
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL49VDD
I2S2_BIDIR
I2S2_SYNC
SB_CLK18M_XTALI
SB_CLK18M_XTAL 15 MIL SPACING
15 MIL SPACING
SB_CLK18M_XTALO SB_CLK18M_XTALO_R
15 MIL SPACING
=PP3V3_PWRON_SB
=PP3V3_PWRON_SB
I2S1_RESET_L
MODEM_RING2SYS_L
CPU_SRESET_L
SYS_SLEWING_L
I2S0_TO_DEV
I2S0_MCLK
AUDIO
I2S0_BITCLK_R
I2S0_MCLK_R
PCI_SLOTE_REQ_L PCI_SLOTE_GNT_L
SB_GPIO12
SB_TO_SMU_INT_L
SB_SATABR_RESET_L
SB_GPIO25
SB_GPIO24
SB_GPIO23
PCI_SLOTF_INT_L
PCI_SLOTE_INT_L
PCI_SLOTD_INT_L
PCI_SLOTC_INT_L
PCI_SLOTB_INT_L
PCI_SLOTA_INT_L
AGP_INT_L
UDASH_RESET_L
UDASH_SDOWN
PCI_SLOTF_GNT_L
CPU_SRESET_L
PCI_SLOTF_REQ_L
SYS_OVERTEMP_L
I2S0_RESET_L
ENET_ENERGYDET
SB_GPIO46
SB_GPIO45
SB_GPIO30
ENETFW_RESET
FW_LOWPWR
AUDIO_GPIO_11
AUDIO_EXT_MCLK_SEL
AUDIO_HP_MUTE_L
AUDIO_HP_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_LI_DET_L
AUDIO_LO_DET_L AUDIO_LO_OPTICAL_PLUG_L
AUDIO_GPIO_12
AUDIO_SPKR_MUTE_L
AUDIO_LO_MUTE_L
AUDIO_SPKR_DET_L
SMU_TO_SB_INT_L
NB_TO_SB_INT
SB_GPIO52
SB_GPIO51
SB_GPIO49 SB_GPIO50
SYS_SLEWING_L
SB_GPIO47
I2S1_MCLK
I2S1_TO_DEV
10 MIL SPACING
I2S0_DEV_TO_SB_DTI
I2S0_TO_SB
SB_INT_L
NB_INT_L_R
CPU_INT_L
NB_INT_L
NB_TO_SB_INT
=PP1V2_PWRON_SB
=PP2V5_PWRON_SB
MIN_NECK_WIDTH=15 mil
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTALVDD
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTAL18VDD
I2S2_MCLK_R
I2S2_DEV_TO_SB_DTI
15 MIL SPACING
SB_CLK25M_ATA
SB_CLK25M_ATA
I2S2_BITCLK
SB_CLK18M_XTALO_R
SYS_WARM_RESET_L
JTAG_SB_TDO
PCI_SLOTG_INT_L
PCI_SLOTD_INT_L
PCI_SLOTE_INT_L
PCI_SLOTA_INT_L
PCI_SLOTF_GNT_L
PCI_SLOTE_GNT_L
PCI_SLOTF_REQ_L
PCI_SLOTE_REQ_L
=PP3V3_PCI
=PP3V3_PWRON_SB
SB_CLK25M_ATA
TP_SB_PLLTEST
JTAG_SB_TDI
JTAG_SB_TCK
TP_SB_WATCHDOG
I2C_SB_SDA
MODEM_RING2SYS_L
SB_INT_L
SB_STOPXTALS_L SMU_SUSPENDREQ_L SB_SUSPENDACK_L
I2C_SB_SCL
SYS_PME_L
I2S2_MCLK
I2S2_TO_DEV
10 MIL SPACING
I2S0_SB_TO_DEV_DTO
I2S0_TO_DEV
I2S2_BITCLK
I2S2_BIDIR
I2S0_BIDIR
I2S0_SYNC
I2S2_TO_SB
I2S2_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BIDIR
I2S1_TO_SB
I2S1_DEV_TO_SB_DTI
I2S2_SB_TO_DEV_DTO
I2S2_TO_DEV
I2S0_SB_TO_DEV_DTO_R
I2S0_SYNC_R
I2S1_SB_TO_DEV_DTO_R I2S1_MCLK_R I2S1_BITCLK_R I2S1_SYNC_R
I2S2_SB_TO_DEV_DTO_R
I2S2_BITCLK_R I2S2_SYNC_R
I2S2_SB_TO_DEV_DTO
I2S1_SB_TO_DEV_DTO
I2S1_SYNC
I2S0_SB_TO_DEV_DTO
I2S0_DEV_TO_SB_DTI
I2S2_RESET_L
=PP3V3_PWRON_SB
SB_TEST_MODE_PD
I2S1_TO_DEV
I2S1_SB_TO_DEV_DTO
I2S0_BIDIR
I2S0_BITCLK
SYS_OVERTEMP_L
SB_TO_SMU_INT_L
UDASH_RESET_L
SB_SATABR_RESET_L
FW_LOWPWR
ENETFW_RESET
ENET_ENERGYDET
PCI_SLOTB_INT_L
PCI_SLOTF_INT_L
PCI_SLOTC_INT_L
SB_GPIO12
SB_GPIO24
SB_GPIO30
SB_GPIO23
SB_GPIO25
SB_GPIO45
SB_GPIO47
SMU_TO_SB_INT_L
SB_GPIO50
SB_GPIO52
JTAG_SB_TMS
I2S1_BITCLK
I2S1_BIDIR
JTAG_SB_TRST_L
SB_PCI_SEL32BIT
TP_SB_FSTEST
I2S2_SYNC
I2S0_SYNC
I2S1_DEV_TO_SB_DTI
I2S2_MCLK
I2S1_RESET_L
I2S1_MCLK I2S1_BITCLK
PCI_SLOTG_INT_L
77
74
74
33
27
33
30
88
76
74
74
27
25
25
94
94
30
27
76
30
25
27
94
29
74
77
76
75
25
94
28
94
94
94
94
25
94
25
94
94
94
94
94
102
102
102
23
23
25
25
29
25
102
25
25
25
56
29
16
86
25
89
101
25
25
25
95
14
23
102
27
102
74
77
25
56
74
23
27
18
25
24
18
77
102
95
102
95
102
25
25
102
102
25
25
95
95
23
25
102
16
25
25
89
25
86
25
25
102
95
25
102
25
25
25
77
25
25
25
25
25
25
25
25
25
25
25
7
7
6
6
25
13
25
25
25
25
13
25
25
25
25
25
25
25
25
25
6
49
6
6
25
25
25
13
95
25
25
25
25
12
25
102
102
102
102
102
101
6
101
101
100
98
102
13
25
25
25
25
25
13
25
6
25
25
6
24
25
7
7
25
25
25
25
8
8
25
25
25
6
25
25
25
25
7
7
25
6
8
8
6
6
25
13
13
13
6
13
25
25
25
25
25
6
6
25
25
6
6
25
25
102
7
6
25
13
13
6
25
25
12
25
25
25
25
25
25
25
25
25
25
25
13
25
25
8
6
8
6
25
25
6
25
6
6
6
25
Preliminary
SYM 2 OF 2
VDD33
VDD25 VDD25
VDD_PLL3
VDD_PLL2
VDD_PLL1
C4_VDD
C3_VDD
C2_VDD
VDD_PLL4
VDD_I2C VDD_NBSYNC VDD_PCLK
VDD33_BC VDD33_BC1
VDD_HCLK0
VDD_HSYNC
VDD_HCLK2
VDD_HCLK0
VDD_HCLK1 VDD_HCLK2
VDD_HSYNC
VDD15_HSYNC VDD15_PCLK
VDD_XTAL
VDD_VCLK
VSS_XTAL
VSS_VCLK
VSS_HSYNC
VSS_HCLK2
VSS_HCLK0 VSS_HCLK1 VSS_HCLK2
VSS_HSYNC
VSS_HCLK0
VSS33_BC1
VSS33_BC
VSS33
VSS_PCLK
VSS_NBSYNC
VSS25
VSS25
VSS_I2C
VSS_CML
VSS_PLL4
VSS_PLL3
VSS_PLL2
C2_VSS C3_VSS C4_VSS
VSS_PLL1
C1_VSSC1_VDD
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
PLACE NEAR PIN D10 D12
A8, C5, B4, K10, H12 J11, M11, A1
PINS G12, M12, H3, K1, L5, M9, A11, A9
CAN BE TURNED OFF IN SLEEP
PLACE NEAR PIN D2 D1
PLACE NEAR PIN M3 M2
PLACE NEAR PIN L8 K8
402 CAPS NOT NEEDED
IF 603 CAN BE PLACED CLOSE TO PULSAR
MASTER: GILA
LAST MODIFIED: APR 09, 04
PULSAR POWER
402
5% 1/16W MF-LF
4.7
21
R2601
PP3V3_RUN
PP3V3_PWRON
0.1UF
402
10V
20% CERM
2
1
C2601
MF-LF
1/16W
5%
4.7
402
21
R2603
MF-LF
1/16W
5%
4.7
402
21
R2605
CERM
20% 10V
402
0.1UF
2
1
C2605
180-OHM-1.5A
0603
21
L2601
20%
0.1UF
10V 402
CERM
2
1
C2609
0.1UF
CERM
20% 10V
402
2
1
C2611
180-OHM-1.5A
0603
21
L2603
402
10V
20% CERM
0.1UF
2
1
C2613
180-OHM-1.5A
0603
21
L2605
402
10V
20% CERM
0.1UF
2
1
C2615
180-OHM-1.5A
0603
21
L2607
0.1UF
10V
20% CERM
402
2
1
C2617
402
10V
20% CERM
0.1UF
2
1
C2619
CERM
20% 10V
402
0.1UF
2
1
C2622
402
4.7
5% 1/16W MF-LF
21
R2607
0603
180-OHM-1.5A
21
L2609
402
0.1UF
CERM
20% 10V
2
1
C2620
0.1UF
402
10V
20% CERM
2
1
C2627
CERM
20% 10V
402
0.1UF
2
1
C2628
0.1UF
402
10V
20% CERM
2
1
C2629
0.1UF
402
10V
20% CERM
2
1
C2630
0.1UF
402
10V
20% CERM
2
1
C2651
CERM
20% 10V
402
0.1UF
2
1
C2623
CERM
20% 10V
402
0.1UF
2
1
C2624
CERM
20% 10V
402
0.1UF
2
1
C2625
CERM
20% 10V
402
0.1UF
2
1
C2626
CERM
20% 10V
402
0.1UF
2
1
C2631
CERM
20% 10V
402
0.1UF
2
1
C2632
CERM
20% 10V
402
0.1UF
2
1
C2633
CERM
20% 10V
402
0.1UF
2
1
C2634
CERM
20% 10V
402
0.1UF
2
1
C2635
CERM
20% 10V
402
0.1UF
2
1
C2636
CERM
20% 10V
402
0.1UF
2
1
C2637
CERM
20% 10V
402
0.1UF
2
1
C2638
CERM
0.1UF
20%
402
10V
2
1
C2665
0.1UF
402
10V
20% CERM
2
1
C2667
0.1UF
402
10V
20% CERM
2
1
C2671
CERM
20% 10V
0.1UF
402
2
1
C2640
10V
20%
0.1UF
CERM 402
2
1
C2639
MF-LF
1/16W
5%
4.7
402
21
R2609
2.2UF
6.3V CERM1
20%
603
2
1
C2645
6.3V
2.2UF
20%
603
2
1
C2669
2.2UF
6.3V CERM1
20%
603
2
1
C2603
6.3V
2.2UF
20%
603
2
1
C2607
2.2UF
6.3V CERM1
20%
603
2
1
C2621
FSBGA
OMIT
PULSAR
C12
A3
M2
K8
D1
D12
L12
F11
C2
K12
H10
A7
A4
B7
B11
C10
A6
M5
L7
E2
H2
L2
A12
A1
M3
L8
D2
D10
M12
G12
B2
H12
K10
B4
C5
A8
A9
A11
M9
L5
E1
K1
H3
M11
J11
C9B9
E10E12
M4L3
G1F1
U2600
PP3V3_PWRON
PP3V3_PWRON
PP3V3_PWRON
PP3V3_RUN
359S0076
1
PULSAR, PBGA
051-6772
04
26
102
MIN_LINE_WIDTH=25MIL
VOLTAGE=1.5V
PP1V5_PSL_PLL3
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=1.5V
PP1V5_PSL_PLL4
MIN_NECK_WIDTH=10MIL
=PP1V2_PULSAR
=PPVCORE_PULSAR
=PPVCORE_PULSAR
=PPVCORE_PWRON_PULSAR
=PPVCORE_PWRON_PULSAR
=PP1V2_PULSAR
=PPVCORE_PULSAR
MIN_LINE_WIDTH=25MIL
VOLTAGE=1.5V
PP1V5_PSL_PLL2
MIN_NECK_WIDTH=10MIL
=PP1V2_PULSAR
=PP2V5_PWRON_RAM
=PP2V5_PWRON_RAM
MIN_LINE_WIDTH=25MIL
VOLTAGE=1.5V
PP1V5_PSL_PLL1
MIN_NECK_WIDTH=10MIL
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL
PP3V3_PSL_XTAL
MIN_NECK_WIDTH=10MIL
=PPVCORE_PWRON_PULSAR
46
46
40
40
37
37
26
26
26
26
26
26
26
26
26
26
26
7
7
7
7
7
7
7
7
7
7
7
Preliminary
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