Apple A1150 Schematic Rev12

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

DVT Build - 12/02/2005

Schematic / PCB #’s

Mullet

M1 MLB

12/03/05

412764ENGINEERING RELEASED

12

?

051-6941

12

1

104

SCHEM,MULLET,M1

Table of Contents

N/A

N/A

1

1

Date

(.csa)

SyncContentsPage

42

FireWire Ports

(MASTER)

(MASTER)

46

TITLE=MULLET

ABBREV=DRAWING

LAST_MODIFIED=Fri Dec 2 23:03:42 2005

Page

(.csa)

SyncContents

Date

1

SCH

051-6941

SCHEM,MULLET,M1

CRITICAL

1

PCBF,MULLET,M1

PCB

820-1881 CRITICAL

PCB_THICK

1

PCB

CRITICAL PCB_THIN920-0342

PCBF,MULLET_THIN,M1

43

Internal USB Connections

(MASTER)

(MASTER)

49

44

External USB Connector

(MASTER)

(MASTER)

52

45

Left I/O Board Connector

(MASTER)

(MASTER)

55

46

PCI-E Connections

(MASTER)

(MASTER)

57

47

SMC

10/07/2005

M38

58

48

SMC Support

(MASTER)

(MASTER)

59

49

LPC+ Debug Connector

07/20/2005

M42

60

50

Thermal Sensors

(MASTER)

(MASTER)

61

51

Current & Voltage Sensing

(MASTER)

(MASTER)

62

52

SPI BOOTROM

11/16/2005

M42

63

53

ALS Support

(MASTER)

(MASTER)

64

54

Fan Connectors

(MASTER)

(MASTER)

65

55

Sudden Motion Sensor (SMS)

(MASTER)

(MASTER)

66

56

TPM

11/16/2005

M38

67

57

IMVP6 CPU VCore Regulator

(MASTER)

(MASTER)

75

58

5V / 1.5V Power Supply

(MASTER)

(MASTER)

76

59

2.5V & 1.2V Regulators

(MASTER)

(MASTER)

77

60

1.8V Supply

(MASTER)

(MASTER)

78

61

3.3V / 1.05V Power Supplies

(MASTER)

(MASTER)

79

62

3.3V G3Hot Supply & Power Control

(MASTER)

(MASTER)

80

63

Power Aliases

(MASTER)

(MASTER)

81

64

PBus-In & Battery Connectors

(MASTER)

(MASTER)

82

65

ATI M56 PCI-E

(MASTER)

(MASTER)

84

66

GPU (M56) Core Supplies

(MASTER)

(MASTER)

85

67

ATI M56 Core Power

(MASTER)

(MASTER)

86

68

ATI M56 Frame Buffer I/F

(MASTER)

(MASTER)

87

69

GPU Straps

(MASTER)

(MASTER)

88

70

GDDR3 Frame Buffer A

(MASTER)

(MASTER)

89

71

GDDR3 Frame Buffer B

(MASTER)

(MASTER)

90

72

ATI M56 GPIO/DVO/Misc

(MASTER)

(MASTER)

91

73

ATI M56 Video Interfaces

(MASTER)

(MASTER)

93

74

Internal Display Connectors

(MASTER)

(MASTER)

94

75

External Display Connector

(MASTER)

(MASTER)

97

76

M1 Specific Connectors

(MASTER)

(MASTER)

98

77

LVDS Interface Pull-downs

(MASTER)

(MASTER)

99

78

Revision History

N/A

N/A

100

79

M1 Net Properties

(MASTER)

(MASTER)

104

System Block Diagram

N/A

N/A

2

2

Power Block Diagram

N/A

N/A

3

3

BOM Configuration

N/A

N/A

4

4

Functional / ICT Test

N/A

N/A

5

5

Signal Aliases

N/A

N/A

6

6

CPU 1 OF 2-FSB

M42

11/16/2005

7

7

CPU 2 OF 2-PWR/GND

M42

11/16/2005

8

8

CPU Decoupling & VID

(MASTER)

(MASTER)

9

9

CPU MISC1-TEMP SENSOR

M42

10/07/2005

10

10

CPU ITP700FLEX DEBUG

M42

10/12/2005

11

11

NB CPU Interface

(MASTER)

(MASTER)

12

12

NB PEG / Video Interfaces

(MASTER)

(MASTER)

13

13

NB Misc Interfaces

(MASTER)

(MASTER)

14

14

NB DDR2 Interfaces

(MASTER)

(MASTER)

15

15

NB Power 1

(MASTER)

(MASTER)

16

16

NB Power 2

(MASTER)

(MASTER)

17

17

NB Grounds

(MASTER)

(MASTER)

18

18

NB (GM) Decoupling

(MASTER)

(MASTER)

19

19

NB Config Straps

(MASTER)

(MASTER)

20

20

SB: 1 OF 4

M38

11/16/2005

21

21

SB: 2 of 4

(M38)

09/08/2005

22

22

SB: 3 OF 4

M38

11/16/2005

23

23

SB: 4 OF 4

M38

11/16/2005

24

24

SB Decoupling

M42

11/16/2005

25

25

SB Misc

(MASTER)

(MASTER)

26

26

M1 SMBus Connections

(MASTER)

(MASTER)

27

27

DDR2 SO-DIMM Connector A

(MASTER)

(MASTER)

28

28

DDR2 SO-DIMM Connector B

(MASTER)

(MASTER)

29

29

Memory Active Termination

(MASTER)

(MASTER)

30

30

Memory Vtt Supply

(MASTER)

(MASTER)

31

31

DDR2 VRef

(MASTER)

(MASTER)

32

32

CLOCKS

M42

10/12/2005

33

33

Clock Termination

(MASTER)

(MASTER)

34

34

Mobile Clocking

(MASTER)

(MASTER)

35

37

PATA Connector

(MASTER)

(MASTER)

36

38

ETHERNET CONTROLLER

M42

10/12/2005

37

41

Ethernet Connector

(MASTER)

(MASTER)

38

42

Yukon Power Control

(MASTER)

(MASTER)

39

43

FIREWIRE CONTROLLER

(M42)

08/29/2005

40

44

FireWire Port Power

(MASTER)

(MASTER)

41

45

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SYNC_DATE=N/A

12

System Block Diagram

SYNC_MASTER=N/A

051-6941

2

104

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

5V/1.5V

PM_SLP_S3_L

U8500

PP3V3_S0

NC

3.3V

1.5V

PP3V3_S5

PGOOD

(ISL6269)

S5

3.3V

ENABLE

U7900

?V

PPVCORE_S0_CPU

1.05V

PP1V05_S0

PGOOD

1.05V

U7950

1.2V - 1.0V

PPVCORE_S0_GPU

S0

(ISL6269)

PGOOD

GPU VCore

ENABLE

3.3V

NC

(LTC3412)

S3

PGOOD

1.2V

ENABLE

U7750

1.2V

PP1V2_S3

2.5V

PP2V5_S0

2.5V

PP2V5_S3

NC

(LTC3411)

2.5V
S3

PGOOD

ENABLE

U7700

3.3V

PP3V3_S3

PP5V_S0

5.0V

PP5V_S3

PP1V5_S0

5.0V

PP5V_S5

SMC_PM_G2_ENABLE

NC

(LTC3728)

S5/S0

PGOOD

ENABLES

U7600

5V

1.5V

PM_SLP_S3_L

SMC_PM_G2_ENABLE

PGOOD

VR_PWRGOOD_DELAY

"IMVP6"

S0

(ISL6262)

CPU VCore

U7500

ENABLES

IMVP_PWRGD_IN

IMVP_VR_ON

RSMRST_PWRGD

(ISL6269)

S0

IMVP_PWRGD_IN/ALL_SYS_PWRGD

PM_SLP_S3_L

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S3_LS5V_L

Q8305

Q8310

Q8315

Q8320

ENABLE

ENABLE

J5500

Connector

Inverter

PP1V8_S3

1.8V

NC

1.8V

U7800

S3

ENABLE

(ISL6269)

PGOOD

PM_SLP_S3_L

U3100

0.9V (Vtt)
S0

(BD3533FVM)

PP0V9_S0

0.9V

FWPWR_EN

Q4565

12.6V - 9V

PPBUS_S5_FWPORT

Q8300

Q8330

PP1V2_S0

1.2V

PM_SLP_S3_LS5V_L

PM_SLP_S3_LS5V_L

Q8325

PP1V8_S0

1.8V

5.0V

U8000

3.425V

PP3V42_G3H

(LT3470)

G3Hot

3.425

ENABLE

12.6V - 9V

PPBUS_G3H_B

18.5V - 9V

PPDCIN_G3H

J5500

J8200

LIO Flex

Connector

LIO Power

12.6V - 9V

PPBUS_G3H_A

Connector

PM_SLP_S4_L

SYNC_DATE=N/A

SYNC_MASTER=N/A

3

104

12

051-6941

Power Block Diagram

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

"Better" BOMs

Phantom BOM #’s

"LeMenu Stage #3" Parts

The above stages and build settings are per 8/25 strategy statement.

LeMenu Stage Mappings

"Best" BOMs

Phantom BOMs

BOMOPTION Groups

"LeMenu Stage #1" Parts

The number of parts managed as Le Menu decreases as a project progresses.

"LeMenu Stage #2" Parts

M1,BTR,HY128

M1,BST,SAM256

M1,BST,HY256

M1,BST,HY128

M1,BST,SAM128

M1,BTR,SAM128

Bar Code Label / EEE #’s

Module Parts

VRAM_256_SAMSUNG

333S0350 CRITICAL

U8900,U8950,U9000,U9050

4

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

4

CRITICAL333S0358

VRAM_128_HYNIX

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

4

CRITICAL333S0351

VRAM_256_HYNIX

VRAM_128_SAMSUNG

CRITICAL333S0354

4

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

CRITICAL

1

826-4393

EEE_UNK

[EEE:UNK]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEE:UR8]

EEE_UR8

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL
CRITICAL

[EEE:UR9]

EEE_UR9

1

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

CRITICAL

1

826-4393

[EEE:UNJ]

EEE_UNJ

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

EEE_TYY

CRITICAL

[EEE:TYY]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEE:UNH]

EEE_UNH

BOM3

256SAM,B13,MULLET,M1

075-0138

1

075-0138 CRITICAL

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6941

BOM Configuration

12

104

4

LEMENU_STAGE1

CRITICAL

IC,SMC,HS8/2116

338S0274

1

U5800

U4102

CRITICAL

LEMENU_STAGE1

341S1797

1

IC,EEPROM,SERIAL IIC,8KBIT,SO8

LEMENU_STAGE2,LEMENU_STAGE3

LEMENU_PROTOEVTDVT

PROJ_PVTRAMP

BOOTROM_FINAL,LEMENU_STAGE1,LEMENU_STAGE2

075-0154

128HY,MULLET,M1

GPU_MEM_HYNIX,VRAM_128_HYNIX

075-0138

256SAM,MULLET,M1

GPU_MEM_256M,VRAM_256_SAMSUNG

075-0155

256HY,MULLET,M1

GPU_MEM_256M,GPU_MEM_HYNIX,VRAM_256_HYNIX

ENETPWR_S3AC,GPU_BB_CTL,GPUTHM_A_GPU,HSTHMSNS_HAS,INVERTER_BUF

M1_COMMON1

KBDLED_HAS,LVDS_PD,MEMVREF_S3,MEMVTT_EN_PU,PCB_THICK

M1_COMMON2

RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU,USB_G_OC_PU

M1_COMMON3

U6301

CRITICAL

1

341S1813

IC,EFI,BOOTROM FINAL,M1

BOOTROM_FINAL

1

CRITICAL

IC,EFI,BOOTROM DEVELOPMENT,M1

341S1812

U6301

BOOTROM_DEVEL

LEMENU_PVTRAMP

LEMENU_STAGE3

PROJ_PROTOEVTDVT

BOOTROM_DEVEL,LEMENU_STAGE1

LEMENU_LOCALPROTO

BOOTROM_DEVEL,LEMENU_STAGE1,LEMENU_STAGE2,LEMENU_STAGE3

LEMENU_STAGE3

CRITICAL

1

343S0385

IC,SB,652BGA

U2100

CRITICAL

1

U0700

337S3268

IC,M1 BST,479 BGA

CPU_BST

CRITICAL

LEMENU_STAGE3

1

338S0269

IC,945GM,SOUTHBRIDGE

U1200

CRITICAL

1

U0700

337S3267

IC,M1 BTR,479 BGA

CPU_BTR

341S1789

U6700

1

CRITICAL

IC, TPM, 28-PIN TSSOP

LEMENU_STAGE2

IC,CY28445-5,CLOCK GEN,68PIN QFN

U3301

359S0101

1

CRITICAL

LEMENU_STAGE1

U7530

353S1235

1

IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE

LEMENU_STAGE1

CRITICAL

338S0309 CRITICAL

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

1

U8400

LEMENU_STAGE1

BOM2 075-0171075-0171

1

CRITICAL

LE MENU,MULLET BST,M1

BOM3 075-0155075-0155

1

CRITICAL

256HY,MULLET,M1

BOM3 075-0154

1

075-0154 CRITICAL

128HY,MULLET,M1

BOM3 CRITICAL 075-0156075-0156

1

128SAM,MULLET,M1

BOM2 CRITICAL 075-0140

1

075-0140

LE MENU,MULLET BTR,M1

BOM1

PROJ PTS,MULLET,M1

075-0139075-0139

1

CRITICAL

M1_DEBUG

DEVELOPMENT,ITP,LPCPLUS

M1_COMMON

M1_COMMON1,M1_COMMON2,M1_COMMON3

075-0156

128SAM,MULLET,M1 VRAM_128_SAMSUNG

CPU_BST,LEMENU_PROTOEVTDVT

075-0171

LE_MENU,MULLET_BST,M1

CPU_BTR,LEMENU_PROTOEVTDVT

075-0140

LE_MENU,MULLET_BTR,M1

075-0139

COMMON,M1_COMMON,M1_DEBUG,PROJ_PROTOEVTDVTPROJ_PTS,MULLET,M1

PCBA,MULLET_BST,HY256,M1

075-0139,075-0171,075-0155,EEE_UNJ

630-7402

PCBA,MULLET_BST,SAM256,M1

075-0139,075-0171,075-0138,EEE_TYY

630-7254

PCBA,MULLET_BST,HY128,M1

075-0139,075-0171,075-0154,EEE_UR9

630-7430

PCBA,MULLET_BST,SAM128,M1

075-0139,075-0171,075-0156,EEE_UR8

630-7429

PCBA,MULLET_BTR,SAM128,M1

075-0139,075-0140,075-0156,EEE_UNK

630-7403

PCBA,MULLET_BTR,HY128,M1

075-0139,075-0140,075-0154,EEE_UNH

630-7401

LEMENU_STAGE1

U4101

CRITICAL338S0270

1

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

CRITICAL

LEMENU_STAGE1

U4400

1

IC,FW32306,1394A LINK,BGA,129P

338S0268

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FUNC_TEST

Left I/O Power Connector

Left ALS Connector

Battery Digital Connector

Functional Test Points

2 TPs per

Current Sense Calibration

Other Func Test Points

FUNC_TEST

FUNC_TEST

Thermal Diode Connectors

FUNC_TEST

Camera Connector

Left I/O Data Connector

Fan Connectors

LPC+ Debug Connector

FUNC_TEST

FUNC_TEST

FUNC_TEST FUNC_TEST

EXPOSED_VIA

Misc EXPOSED_VIA Nets

EXPOSED_VIA

EXPOSED_VIA property indicates that the net
should have a via with 10-mil soldermask
opening for use as engineering probe point.

FUNC_TEST

FUNC_TEST property removed
since these test points
are not on the proper side
for Functional Test points.

FUNC_TEST

NO_TEST

NO_TEST

EXPOSED_VIA

Power Supply NO_TESTs

CPU FSB NO_TESTs

8 TPs, 2 with each of above TP pairs

called out separately in these notes.

NOTE: 10 additional GND test points are

Request for at least 10 GND test points

051-6941

12

104

5

SYNC_MASTER=N/A

SYNC_DATE=N/A

Functional / ICT Test

TRUE

GND\g

TRUE

GND\g

TRUE

GND\g

TRUE

GND\g

TRUE

P1V8S3_COMP

TRUE

P1V05S0_FSET

TRUE

GPUVCORE_FSET

TRUE

FSB_A_L<31..3>
FSB_ADS_L

TRUE

TRUE

FSB_BNR_L

TRUETRUE

FSB_DINV_L<3..0>
FSB_DRDY_L

TRUE

TRUE

GPUBBP_ADJ

TRUE

GPUVCORE_COMP

TRUE

FSB_DSTBN_L<3..0>

TRUE

TRUE

FSB_HIT_L

TRUE

P3V42G3H_FB

TRUE

FSB_DBSY_L

TRUE

P1V5S0_RUNSS

TRUE

P1V2S3_RUNSS

TRUE

P1V2S3_RT

TRUE

P3V3S5_COMP

TRUE

P3V3S5_FSET

TRUE

P2V5S3_SHDNRT

TRUE

P5VS5_RUNSS

TRUE

IMVP6_COMP

TRUE

IMVP6_RBIAS

TRUE

P2V5S3_MODE

TRUE

P1V8S3_FSET

TRUE

P1V05S0_COMP

=PP3V3_S5_LPCPLUS

TRUE

TRUE

ACZ_SDATAOUT

SMC_BATT_CHG_EN

TRUE

SMC_BC_ACOK

TRUE

TRUE

=PP1V5_S0_LIO
=PPDCIN_G3H_LIO

TRUE
TRUE

=PP5V_S5_LIO

PP5V_S0_AUDIO

TRUE

PCIE_CLK100M_EXCARD_N

TRUE

TRUE

=PCIE_EXCARD_D2R_N

=SMBUS_BATT_SCL

TRUE

SMC_BS_ALRT_L

TRUE

=SMBUS_BATT_SDA

TRUE

SMC_ADAPTER_EN

TRUE

TRUE

=PCIE_EXCARD_D2R_P

TRUE

=PCIE_EXCARD_R2D_P

=USB2_EXCARD_N

TRUE

=USB2_EXCARD_P

TRUE

=USB2_LT_N

TRUE

=USB2_LT_P

TRUE

ACZ_SYNC

TRUE

SMC_EXCARD_PWR_EN

TRUE
TRUE

LIO_PLT_RESET_L

SMC_EXCARD_CP

TRUE

EXCARD_CLKREQ_L

TRUE

MINI_CLKREQ_L

TRUE

SMC_BATT_TRICKLE_EN_L

TRUE

LIO_P3V3S3_EN

TRUE

TRUE

LIO_DCIN_ISENSE

LIO_BATT_ISENSE

TRUE

SMC_SYS_ISET

TRUE

TRUE

SMC_TDO
SMC_MD1

TRUE

SMC_TRST_L

TRUE

PP5V_S0_AUDIO_PWR

TRUE

=PP3V42_G3H_LIO

TRUE

TRUE

GND_AUDIO_PWR

TRUE

GND_AUDIO

SMC_RX_L

TRUE

SMC_RST_L

TRUE

SMC_TX_L

TRUE

LPC_AD<1>

TRUE

TRUE

ACZ_SDATAIN<0>

=PP5V_S0_LPCPLUS

TRUE

DEBUG_RST_L

TRUE

BOOT_LPC_SPI_L

TRUE

PM_CLKRUN_L

TRUE

LPC_FRAME_L

TRUE

LPC_AD<0>

TRUE

SMC_TMS

TRUE

TRUE

ACZ_BITCLK

PCIE_CLK100M_EXCARD_P

TRUE

TRUE

FSB_ADSTB_L<1..0>

TRUE

TRUE

FSB_D_L<63..0>

TRUE

FSB_BREQ0_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_LOCK_L

TRUE

FSB_HITM_L

TRUETRUE

FSB_DSTBP_L<3..0>

TRUE

DMI_N2S_N<1..0>

TRUE

DMI_N2S_P<1..0>

TRUE

SB_CLK100M_SATA_N

TRUE

SB_CLK100M_SATA_P

FAN_RT_TACH

FAN_LT_PWM
FAN_LT_TACH

FAN_RT_PWM

=PP5V_S0_FAN_LT

TRUE

LPC_AD<3>

PCI_CLK_PORT80_LPC

TRUE

LPC_AD<2>

TRUE

INT_SERIRQ

TRUE

SMC_TDI

TRUE

=PCIE_EXCARD_R2D_N

TRUE

SV_SET_UP

TRUE

SMC_NMI

TRUE

SMC_TCK

TRUE

PM_SUS_STAT_L

TRUE

FWH_INIT_L

TRUE

=SMBUS_ATS_SDA

TRUE

TRUE

=PP3V3_S3_LTALS

TRUE

ALS_GAIN
LTALS_OUT

TRUE

TRUE

RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

=USB2_CAMERA_P

TRUE

=SMBUS_ATS_SCL

TRUE

PM_SYSRST_L

TRUE

SMC_ONOFF_L

TRUE

=PP1V05_S0_REG

TRUE

TRUE

HSTHMSNS_DX_P

=PP5V_S0_ISENSECAL

TRUE

PP1V8_S3_REG

TRUE

PP1V5_S0_REG

TRUE

PPVCORE_S0_GPU

TRUE

PPVCORE_S0_CPU

TRUE

GND_BATT

TRUE

TRUE

LTUSB_OC_L

TRUE

ACZ_RST_L

TRUE

EXCARD_OC_L

SMC_BATT_ISET

TRUE

LIO_P3V3S0_EN_L

TRUE

SYS_ONEWIRE

TRUE

=USB2_CAMERA_N

TRUE

=PP5V_S3_CAMERA

TRUE

=PCIE_MINI_R2D_N

TRUE
TRUE

=PCIE_MINI_R2D_P

TRUE

=PCIE_MINI_D2R_P

TRUE

=PCIE_MINI_D2R_N

TRUE

PCIE_CLK100M_MINI_P

TRUE

=SMBUS_LIO_SMC_SCL

TRUE

PCIE_CLK100M_MINI_N

TRUE

=SMBUS_LIO_SMC_SDA

TRUE

=SMBUS_LIO_SB_SCL

TRUE

=SMBUS_LIO_SB_SDA

TRUE

PCIE_WAKE_L

=PPBUS_G3H_LIO_CONN

TRUE

HSTHMSNS_DX_N

TRUE

ISENSE_CAL_EN

TRUE

56

56

48

56

49

56

56

56

56

56

49

51

79

79

79

79

79

79

79

79

79

48

48

64

47

79

48

48

49

49

49

49

49

79 49

47

49

49

49

79

79

79

79

79

79

79

79

49

49

49

49

49

48

49

76

47

48

63

79

48

48

45

12

12

12

12

12

12

12

12

62

59

62

63

45

47

47

63

63

63

45

46

64

48

64

45

46

46

45

45

45

45

45

47

45

47

45

45

47

62

51

51

47

48

49

49

63

48

48

48

47

45

63

49

47

40

47

47

48

45

45

12

12

12

12

12

12

12

22

22

34

34

63

47

49

47

47

48

46

49

49

48

47

48

43

76

47

76

43

43

26

47

61

45

45

45

47

62

47

43

63 46

46

46

46

45

45

45

45

45

45

37

64

60

61

66

7

7

7

7

7

66

66

7

7

62

7

58

39

59

61

61

59

58

57

57

59

60

61

49

21

45

45

45

45

45

45

34

45

27

47

27

41

45

45

6

6

6

6

21

45

26

45

34

34

45

45

45

45

45

47

47

47

45

45

45

45

47

47

47

21

21

49

26

22

23

21

21

47

21

34

7

7

7

7

7

7

7

14

14

21

21

54

54

54

54

54

21

34

21

23

47

45

23

47

47

23

21

27

63

6

53

50

50

6

27

23

43

51

50

63

63

63

63

64

6

21

6

45

45

45

6

43 45

45

45

45

34

27

34

27

27

27

23

63

50

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"ENET_LOM_DISABLE" are mutually-exclusive.

NOTE: BOM options "USB_G_OC_PU" and

Ethernet Power Management Support

NOTE: NB_CFG<13..12> require test access

Trace deleted to make room for other diffpairs over RAM connector.

USB Port "H" = Reserved (PCI-E Mini Card)

USB Port "E" = ExpressCard

USB Port "B" = Trackpad (Geyser)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "G" = Bluetooth (M13P)

USB Port "C" = Left USB 2.0 Port

USB Port "F" = IR Receiver

USB Port "D" = Camera

Chassis connection to be made at the mounting hole east of the LVDS connector

Chassis connection to be made at the mounting hole northwest of the DVI connector

Chassis connection to be made at the mounting hole southwest of the USB connector

HOLE-VIA-P5RP25

1

ZT0600

HOLE-VIA-P5RP25

1

ZT0601

HOLE-VIA-P5RP25

1

ZT0602

SHLD-SM-LF

OG-503040

3

2

1

SH0600

22

5%
1/16W
MF-LF

402

ENET_LOM_DISABLE

0

21

R0600

37

SYNC_DATE=N/A

SYNC_MASTER=N/A

6

104

12

051-6941

Signal Aliases

=GND_CHASSIS_DVI5

=GND_CHASSIS_DVI3

GND_CHASSIS_DVI_BOT

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI1

=GND_CHASSIS_DVI2
=GND_CHASSIS_DVI4

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V

MAKE_BASE=TRUE

GND_CHASSIS_DVI_TOP

MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_ENET
=GND_CHASSIS_FW_EMI
=GND_CHASSIS_FW_PORT1
=GND_CHASSIS_RTUSB

MAKE_BASE=TRUE

LTUSB_OC_L

=USB_IR_P

USB_F_P

=USB2_LT_N

USB_E_P

=USB2_EXCARD_P
=USB2_EXCARD_N

MAKE_BASE=TRUE

USB_BT_N

USB_BT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_EXCARD_P

=USB2_CAMERA_N

USB2_CAMERA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_CAMERA_P

USB_G_P
USB_G_N

USB_E_N

MAKE_BASE=TRUE

EXCARD_OC_L

USB_E_OC_L

USB_D_OC_L

USB_D_N

=USB2_LT_P

=USB_TRACKPAD_N

MAKE_BASE=TRUE

USB_TRACKPAD_N

MAKE_BASE=TRUE

USB_TRACKPAD_P

=RTUSB_OC_L

RTUSB_OC_L

MAKE_BASE=TRUE

USB_C_N
USB_C_OC_L

USB_C_P

MAKE_BASE=TRUE

UNUSED_USB_B_OC_L

USB_B_OC_L

USB_B_N

USB_B_P

USB_A_OC_L

USB_A_N

USB_A_P

=USB2_RT_N

=USB2_RT_P

USB2_RT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_RT_N

=GND_CHASSIS_LCD1

=GND_CHASSIS_INVERTER

=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD3

GND_CHASSIS_LVDS

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

NC_CPU_A32_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A33_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A34_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A35_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A37_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A38_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A39_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_HFPLL

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE0

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE2

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE4

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_A32_L

TP_CPU_A33_L

TP_CPU_A34_L

TP_CPU_A35_L

TP_CPU_A37_L

TP_CPU_A36_L

TP_CPU_A38_L

TP_CPU_A39_L

TP_CPU_APM1_L

TP_CPU_EXTBREF

TP_CPU_SPARE0

TP_CPU_SPARE2

TP_CPU_SPARE1

TP_CPU_SPARE4

MAKE_BASE=TRUE

UNUSED_USB_D_OC_L

USB_F_N

=USB_BT_N

=USB_IR_N

USB_IR_P

MAKE_BASE=TRUE

USB_IR_N

MAKE_BASE=TRUE

USB_D_P

=USB_TRACKPAD_P

USB2_LT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_LT_N

NC_CPU_EXTBREF

MAKE_BASE=TRUE
NO_TEST=TRUE

TP_CPU_HFPLL

NC_CPU_APM0_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_APM1_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A36_L

MAKE_BASE=TRUE
NO_TEST=TRUE

GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_LCD2

=USB2_CAMERA_P

USB2_EXCARD_N

MAKE_BASE=TRUE

USB_H_P
USB_H_N

TP_USB2_HP

MAKE_BASE=TRUE

TP_USB2_HN

MAKE_BASE=TRUE

TP_CPU_APM0_L

=USB_BT_P

MEM_A_A<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_A<15..14>

MEM_B_A<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_A<15..14>

NB_CFG<4..3>

MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<6>

NB_CFG<8>

MAKE_BASE=TRUE

TP_NB_CFG<8>

NB_CFG<11..10>

MAKE_BASE=TRUE

TP_NB_CFG<11..10>

NB_CFG<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<15..14>

NB_CFG<17>

MAKE_BASE=TRUE

TP_NB_CFG<17>

NB_CFG<13..12>

MAKE_BASE=TRUE

TP_NB_CFG<13..12>

SUS_CLK_SB

MAKE_BASE=TRUE

TP_SB_SUS_CLK

TP_SB_XOR_T5

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_T5

TP_SB_XOR_V3

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_V3

TP_SB_XOR_U5

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_U5

TP_SB_XOR_W3

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_W3

TP_SB_XOR_V4

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_V4

SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

=RTALS_GAIN

MAKE_BASE=TRUE

ALS_GAIN

ENET_CTRL12

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_ENET_CTRL12

ENET_CTRL25

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_ENET_CTRL25

ENET_LOM_DIS_L

SB_GPIO30

48

76

45

45

45

45

43

45

45

43

47

75

75

75

75

75

38

42

42

44

5

76 22

5

22

5

5

5

22

22

22

5

22

22

22

5

43

44

22

22

22

22

22

22

22

22

22

44

44

74

74

74

74

7

7

7

7

7

7

7

7

7

7

7

7

7

7

22

76

76

22

43

7

74

5

22

22

7

76

28

29

14

14

14

14

14

14

14

23

21

21

21

21

21

47

53

5

37

37

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN
IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

A7*

RSVD14
RSVD15

BCLK1

BCLK0

RSVD20

RSVD17
RSVD18
RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1*
BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6
RSVD7
RSVD8

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

RSVD9
RSVD10

SMI*

LINT0
LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30*
A31*

A27*
A28*
A29*

A26*

A25*

A24*

A22*
A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14*
A15*
A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1 ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2
COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52*
D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45*
D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0
BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26*
D27*
D28*

D24*
D25*

D23*

D21*
D22*

D20*

D19*

D18*

D16*
D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF
NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0.1" AWAY

ROUTE TO TP VIA AND

SPARE[7-0],HFPLL:

STUB)

PM_THRMTRIP#
SHOULD CONNECT TO

CPU_PROCHOT_L TO SMC

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".

ICH7-M AND GMCH

LAYOUT NOTE: 0.5" MAX LENGTH

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

PLACE GND VIA W/IN 1000 MILS

TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WITHOUT T-ING (NO

AND CPU VR TO INFORM
CPU IS HOT

1%

54.9

MF-LF
402

1/16W

2

1

R0702

68

1/16W

5%
402

MF-LF

2

1

R0704

1K

MF-LF
402

1%
1/16W

2

1

R0705

2.0K

MF-LF
402

1%
1/16W

2

1

R0706

1%

402

54.9

21

R0719

27.4

21

R0718

1%

402

54.9

21

R0717

27.4

402

21

R0716

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79

12

5

79 12

5

79 12

5

57 21

79 21

79 12

12

57

79 21

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79

12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

34

34

34

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

79 12

79 12

5

79 12

5

79 12

5

79 12

5

79

12

5

79

12

5

79 11

79 11

79 11

79 11

79 11

79 11

11

26 11

10

48 21 14

79 21

79 12 11

79 12

79 12

79 12

79 12

11

7

11

7

11

7

11

10

34

34

79 21

79 21

79 21

79 21

79 21

79 21

21

NOSTUFF

402

0

21

R0730

1/16W

5%
402

MF-LF

1K

NOSTUFF

2

1

R0707

51

1/16W

5%
402

MF-LF

2

1

R0712

402

MF-LF

1/16W

1%

54.9

2

1

R0703

1%

402

54.9

21

R0720

54.9

402

1%

21

R0721

1%

402

54.9

21

R0722

OMIT

CPU

YONAH

BGA

AB6

G2

AB5

C7

A25

A24

AB3

AA6

AC5

D5

A3

B2

V3

T2

N5

M4

AA3

AB2

C24

AA4

C23

D22

AF1

C1

D3

F6

D2

T22

B25

C3

AA1

G3

F4

F3

B1

L5

J3

K2

H2

K3

D21

AC1

AC2

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V4

L2

H1

J1

N2

M1

K5

M3

L4

Y1

W2

J4

Y4

W5

W3

T3

T5

R4

U2

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L1

P2

P5

N3

U0700

OMIT

BGA

YONAH

CPU

D25

C26

D7

D6

AE6

A2

AD26

AE24

Y25

N25

G22

AD23

W24

M24

H23

D24

B5

E5

AC20

V23

M26

J26

G24

K24

E23

AF26

AF22

AF25

AE25

E25

AD21

AE21

AD24

AF23

AE22

AD20

AC25

AB21

AA21

AB22

G25

AC23

AC22

AA24

AC26

Y22

Y26

AA26

Y23

W22

AB25

F23

U22

U25

U23

W25

V26

V24

AB24

AA23

N24

T25

H22

L26

R24

T24

P23

P22

P25

M23

L23

L22

L25

E26

R23

P26

K25

N22

H25

K22

F26

H26

J23

J24

F24

E22

V1

U1

U26

R26

C21

B23

B22

U0700

CPU 1 OF 2-FSB

SYNC_MASTER=M42

7

12

051-6941

104

SYNC_DATE=11/16/2005

FSB_RS_L<0>
FSB_RS_L<1>

XDP_BPM_L<5>

FSB_HITM_L

FSB_HIT_L

FSB_RS_L<2>
FSB_TRDY_L

=PP1V05_S0_CPU

XDP_BPM_L<1>

FSB_DBSY_L

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

XDP_TMS

XDP_TDI

XDP_TCK

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>

FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_ADSTB_L<0>

FSB_REQ_L<2>

FSB_REQ_L<0>
FSB_REQ_L<1>

FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>

FSB_A_L<23>

FSB_A_L<22>
FSB_A_L<24>

FSB_A_L<25>
FSB_A_L<26>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<31>

FSB_A_L<30>
FSB_ADSTB_L<1>

CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L

CPU_STPCLK_L
CPU_NMI

CPU_INTR
CPU_SMI_L

TP_CPU_APM1_L

TP_CPU_APM0_L

TP_CPU_A36_L

TP_CPU_A35_L

TP_CPU_A34_L

TP_CPU_A33_L

TP_CPU_A32_L

TP_CPU_A39_L

TP_CPU_A38_L

TP_CPU_A37_L

TP_CPU_HFPLL

FSB_DEFER_L
FSB_DRDY_L

FSB_BREQ0_L
FSB_IERR_L

CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L

XDP_BPM_L<0>
XDP_BPM_L<2>

XDP_BPM_L<3>
XDP_BPM_L<4>

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L

CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N

PM_THRMTRIP_L

TP_CPU_EXTBREF
TP_CPU_SPARE0

TP_CPU_SPARE3

TP_CPU_SPARE6

TP_CPU_SPARE5

TP_CPU_SPARE4

TP_CPU_SPARE7

FSB_CLK_CPU_P
FSB_CLK_CPU_N

TP_CPU_SPARE2

TP_CPU_SPARE1

FSB_A_L<7>

CPU_GTLREF

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>

FSB_D_L<17>

FSB_D_L<16>
FSB_D_L<18>

FSB_D_L<19>
FSB_D_L<20>

FSB_D_L<22>

FSB_D_L<21>
FSB_D_L<23>
FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>

FSB_DSTBP_L<1>
FSB_DINV_L<1>

CPU_TEST1
CPU_TEST2

CPU_BSEL<1>

CPU_BSEL<0>

FSB_DSTBN_L<1>

CPU_BSEL<2>

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>

FSB_D_L<46>

FSB_D_L<45>

FSB_DSTBP_L<2>

FSB_D_L<47>
FSB_DSTBN_L<2>

FSB_DINV_L<2>
FSB_D_L<48>

FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>

FSB_D_L<53>

FSB_D_L<52>
FSB_D_L<54>

FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_DINV_L<3>

FSB_DSTBN_L<3>
FSB_DSTBP_L<3>

CPU_COMP<0>
CPU_COMP<1>

CPU_COMP<3>

CPU_COMP<2>

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD
FSB_SLPCPU_L
CPU_PSI_L

FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L

63

63

63

63

11

11

11

11

9

9

9

9

8

8

8

8

11

11

11

7

7

7

7

7

7

7

6

6

6

6

6

6

6

6

6

6

6

79

6

6

6

6

6

79 79

79

79

79

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VSS_82
VSS_83
VSS_84
VSS_85

VSS_87

VSS_86

VSS_88
VSS_89
VSS_90

VSS_92

VSS_91

VSS_93
VSS_94
VSS_95

VSS_97

VSS_96

VSS_100

VSS_98
VSS_99

VSS_102

VSS_101

VSS_105

VSS_103
VSS_104

VSS_106
VSS_107

VSS_110

VSS_109

VSS_108

VSS_111
VSS_112

VSS_115

VSS_114

VSS_113

VSS_116
VSS_117
VSS_118

VSS_120

VSS_119

VSS_123

VSS_121
VSS_122

VSS_124
VSS_125

VSS_128

VSS_126
VSS_127

VSS_129
VSS_130

VSS_133

VSS_131
VSS_132

VSS_134
VSS_135

VSS_138

VSS_136
VSS_137

VSS_139
VSS_140
VSS_141

VSS_143

VSS_142

VSS_146

VSS_144
VSS_145

VSS_147
VSS_148

VSS_151

VSS_150

VSS_149

VSS_152
VSS_153

VSS_156

VSS_155

VSS_154

VSS_157
VSS_158
VSS_159

VSS_161

VSS_160

VSS_162

VSS_1
VSS_2
VSS_3

VSS_5

VSS_4

VSS_6
VSS_7
VSS_8

VSS_10

VSS_9

VSS_11
VSS_12

VSS_15

VSS_13
VSS_14

VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

VSS_23

VSS_22

VSS_21

VSS_24
VSS_25

VSS_28

VSS_27

VSS_26

VSS_29
VSS_30

VSS_33

VSS_32

VSS_31

VSS_34
VSS_35

VSS_38

VSS_37

VSS_36

VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

VSS_46

VSS_44
VSS_45

VSS_47
VSS_48

VSS_51

VSS_49
VSS_50

VSS_52
VSS_53

VSS_56

VSS_54
VSS_55

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

VSS_63

VSS_62

VSS_64
VSS_65
VSS_66

VSS_69

VSS_68

VSS_67

VSS_70
VSS_71

VSS_74

VSS_73

VSS_72

VSS_75
VSS_76

VSS_79

VSS_78

VSS_77

VSS_80
VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59
VCC_60

VCC_58

VCC_57

VCC_56

VCC_54
VCC_55

VCC_53

VCC_51
VCC_52

VCC_49
VCC_50

VCC_48

VCC_47

VCC_46

VCC_44
VCC_45

VCC_43

VCC_41
VCC_42

VCC_40

VCC_39

VCC_38

VCC_36
VCC_37

VCC_33

VCC_35

VCC_34

VCC_31
VCC_32

VCC_29
VCC_30

VCC_28

VCC_26
VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18
VCC_19

VCC_17

VCC_16

VCC_15

VCC_13
VCC_14

VCC_12

VCC_10
VCC_11

VCC_8
VCC_9

VCC_7

VCC_6

VCC_5

VCC_3
VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82
VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90
VCC_91
VCC_92

VCC_94

VCC_93

VCC_95
VCC_96
VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12
VCCP_13
VCCP_14

VCCP_16

VCCP_15

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTH

VCCSENSE AND VSSSENSE LINES

LAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE

VID FOR CPU POWER SUPPLY
IF NO USE, NEED PULL-UP OR
PULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

79

9

79

9

79

9

79

9

79

9

79

9

1/16W

1%
402

MF-LF

100

2

1

R0803

79

9

79 57

79 57

100

MF-LF
402

1%
1/16W

2

1

R0802

OMIT

BGA

YONAH

CPU

V22

V5

V2

U24

U21

U6

U3

T26

T23

T4B6

T1

R25

R22

R5

R2

P24

P21

P6

P3

N26

A26

N23

N4

N1

M25

M22

M5

M2

L24

L21

L6

A23

L3

K26

K23

K4

K1

J25

J22

J5

J2

H24

A19

H21

H6

H3

G26

G23

G1

G4

F25

F22

F2

A16

F19

F16

F13

F11

F8

F5

E24

E21

E19

E16

A14

E14

E11

E8

E6

E3

D26

D23

D19

D16

D13

A11

D11

D8

D4

D1

C25

C22

C2

C19

C16

C14

A8

C11

C8

C5

AF24

AF21

AF19

B24

AF16

AF13

AF11

AF8

AF6

AF3

AE26

AE23

AE19

AE16

B21

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

AD13

B19

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

AC11

B16

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

AB8

B13

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

AA5

B11

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

V25

B8

A4

U0700

OMIT

BGA

YONAH

CPU

AE7

AE2

AF2

AE3

AF4

AE5

AF5

AD6

AF7

N21

M21

K21

J21

M6

K6

J6

G21

W21

V21

T6

T21

R6

R21

N6

V6

B26

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

AE17

A20

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

AD12

A18

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

AC7

A17

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

AB9

A15

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

F20

A13

F18

F17

F15

F14

F12

F10

F9

F7

E20

E18

A12

E17

E15

E13

E12

E10

E9

E7

D18

D17

D15

A10

D14

D12

D10

D9

C18

C17

C15

C13

C12

C10

A9

C9

B20

B18

B17

B15

B14

B12

B10

B9

AF20

B7

A7

U0700

CPU 2 OF 2-PWR/GND

SYNC_MASTER=M42

051-6941

12

8

104

SYNC_DATE=11/16/2005

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU
CPU_VID<0>

CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

63

63

63

51

11

51

9

9

9

8

7

8

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

VCCA (CPU AVdd) Decoupling

1x 470uF, 6x 0.1uF 0402

between CPU and NB

1x 10uF, 1x 0.01uF

4x 470uF. 20x 22uF 0805

CPU VCORE VID Connections

Resistors to allow for override of CPU VID
Will probably be removed before production

VCCP (CPU I/O) Decoupling

CPU VCORE HF AND BULK DECOUPLING

NOTE: This cap is shared

6.3V

20%
X5R

805

22uF

2

1

C0906

6.3V

20%
X5R

22uF

805

2

1

C0904

6.3V

20%
X5R

22uF

805

2

1

C0916

6.3V

20%
X5R

22uF

805

2

1

C0914

6.3V

20%
X5R

22uF

805

2

1

C0908

6.3V

20%
X5R

22uF

805

2

1

C0903

6.3V

20%
X5R

22uF

805

2

1

C0907

6.3V

20%
X5R

22uF

805

2

1

C0902

6.3V

20%
X5R

805

22uF

2

1

C0901

6.3V

20%
X5R

805

22uF

2

1

C0913

6.3V

20%
X5R

22uF

805

2

1

C0912

6.3V

20%
X5R

22uF

805

2

1

C0911

6.3V

20%
X5R

22uF

805

2

1

C0919

6.3V

20%
X5R

22uF

805

2

1

C0900

6.3V

20%
X5R

22uF

805

2

1

C0910

0.1UF

CERM
402

20%
10V

2

1

C0936

20%

2.5V
TANT

D2T

470uF-7MOHM

CRITICAL

32

1

C0935

6.3V

20%
X5R

22uF

805

2

1

C0905

6.3V

20%
X5R

22uF

805

2

1

C0909

20%
X5R

22uF

6.3V
805

2

1

C0915

6.3V

20%
X5R

22uF

805

2

1

C0917

0.1UF

CERM
402

20%
10V

2

1

C0937

0.1UF

CERM
402

20%
10V

2

1

C0938

0.1UF

CERM
402

20%
10V

2

1

C0939

0.1UF

CERM
402

20%
10V

2

1

C0940

0.1UF

CERM
402

20%
10V

2

1

C0941

22uF

X5R

20%

6.3V
805

2

1

C0918

20%

D2T

2.5V
TANT

470uF-7MOHM

CRITICAL

3 2

1

C0950

20%

2.5V
D2T

TANT

470uF-7MOHM

CRITICAL

3 2

1

C0952

470uF-7MOHM

20%

2.5V
TANT
D2T

CRITICAL

3 2

1

C0953

470uF-7MOHM

20%

2.5V
TANT
D2T

CRITICAL

3 2

1

C0954

16V

0.01UF

CERM
402

20%

2

1

C0981

X5R

10uF

20%

6.3V
603

2

1

C0980

0

5%
1/16W
MF-LF

402

21

R0996

0

5%
1/16W
MF-LF

402

21

R0995

402

MF-LF

1/16W

5%

0

21

R0993

402

1/16W

5%

0

MF-LF

21

R0994

402

MF-LF

1/16W

5%

0

21

R0991

402

MF-LF

1/16W

5%

0

21

R0992

402

MF-LF

1/16W

5%

0

21

R0990

CPU Decoupling & VID

051-6941

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

12

9

104

IMVP6_VID<6>

CPU_VID<1>

CPU_VID<3>

IMVP6_VID<3>

CPU_VID<5>

IMVP6_VID<5>

CPU_VID<0>

IMVP6_VID<0>

CPU_VID<2>

IMVP6_VID<2>

CPU_VID<4>

IMVP6_VID<4>

CPU_VID<6>

IMVP6_VID<1>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

63 11

63

79

79

79

79

79

79

79

8

63

51

57

8

8

57

8

57

8

57

8

57

8

57

8

57

7

8

8

D+
D-

ALERT*/

THM*

SCLK

SDATA

VDD

GND

THM2*

BI
BI

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACEHOLDER ADT7461A

LAYOUT NOTE:

(TO CPU INTERNAL THERMAL DIODE)

CPU_THERMD_N

LAYOUT NOTE:

CPU ZONE THERMAL SENSOR

ROUTE CPU_THERMD_P AND

10 MIL TRACE

LAYER.

10 MIL SPACING

FOR CPU_THERMD_P AND CPU_THERMD_N ON SAME

ADD GND GUARD TRACE

PLACE U1001 NEAR THE U1200

CRITICAL

MSOP

ADT7461

1

4

7

8

5

3

2

6

U1001

MF-LF

499

1/16W

402

1%

21

R1001

CERM

50V

0.001uF

10%

402

2

1

C1001

27

27

X5R

0.1UF

16V

10%

402

2

1

C1002

7

7

499

1%

MF-LF

402

1/16W

21

R1002

1/16W

5%

402

10K

MF-LF

2

1

R1005

10K

1/16W
402

MF-LF

5%

2

1

R1006

051-6941

12

10

104

SYNC_MASTER=M42

SYNC_DATE=10/07/2005

CPU MISC1-TEMP SENSOR

THRM_CPU_DX_P
THRM_CPU_DX_N

CPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_THRM_SNR

THRM_ALERT_L
THRM_ALERT

SMB_THRM_CLK
SMB_THRM_DATA

50

50

63

OUT
OUT
OUT

OUT

OUT

IN

IN
IN

BI

BI

BI

BI

BI

BI

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)

(AND WITH RESET BUTTON)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

NC

NC

NC

(DBA#)
(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

MF-LF

22.6

1%

1/16W

402

ITP

21

R1100

ITP

402

1%

22.6

1/16W
MF-LF

21

R1102

54.9

1/16W

1%
402

MF-LF

ITP

2

1

R1103

402

X5R

16V

10%

0.1UF

2

1

C1100

1/16W

240

402

MF-LF

5%

2

1

R1104

F-RT-SM

52435-2872

CRITICAL

ITPCONN

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J1101

1/16W
402

54.9

1%
MF-LF

2

1

R1101

680

402

5%
1/16W
MF-LF

2

1

R1106

7

7

7

11

7

11

7

7

79 34

79

7

79

7

79

7

79

7

79

7

79

7

79 12

7

CPU ITP700FLEX DEBUG

SYNC_DATE=10/12/2005

051-6941

12

11 104

SYNC_MASTER=M42

=PP1V05_S0_CPU

FSB_CPURST_L

XDP_BPM_L<0>

XDP_TCK

XDP_TDI

XDP_TDO

=PP3V3_S5_SB_PM

=PP1V05_S0_CPU

XDP_TMS

CPU_XDP_CLK_N

XDP_TRST_L

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

CPU_XDP_CLK_P

ITP_TDO

XDP_DBRESET_L

ITPRESET_L

63

63

11

11

9

63

9

8

26

8

7

23

7

79

BI

BI
BI

OUT

OUT

OUT

BI

BI

BI

BI
BI

BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

BI
BI
BI
BI

BI
BI

OUT

BI

OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI

IN

BI

IN

BI

BI

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM*
HLOCK*

HHIT*

HDSTBP2*
HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1*
HDSTBN2*

HDSTBN0*

HDINV2*
HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP
HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10*
HD11*
HD12*
HD13*
HD14*

HD5*

HD7*
HD8*
HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21*
HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10*
HA11*
HA12*

HADSTB1*

HREQ0*
HREQ1*
HREQ2*
HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI

BI
BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

79

7 5

79

7 5

79

7 5

79 11

7

79

7

79

7

79

7 5

79

7 5

79

7 5

79

7

79

7 5

79

7 5

402

X5R

16V

10%

0.1uF

2

1

C1211

200

1%
1/16W
MF-LF
402

2

1

R1211

100

1%
1/16W
MF-LF
402

2

1

R1210

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7

79

7 5

7

79

7

79

7

79

7

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

34

79

7 5

34

54.9

1%
1/16W
MF-LF

402

2

1

R1220

402

MF-LF

1/16W

1%

24.9

2

1

R1221

221

1%
1/16W
MF-LF
402

2

1

R1225

1%
1/16W
MF-LF
402

100

2

1

R1226

0.1uF

402

X5R

16V

10%

2

1

C1226

402

X5R

16V

10%

0.1uF

2

1

C1236

221

1%
1/16W
MF-LF
402

2

1

R1235

54.9

1%
1/16W
MF-LF

402

2

1

R1230

79

7 5

1%
1/16W
MF-LF
402

100

2

1

R1236

402

MF-LF

1/16W

1%

24.9

2

1

R1231

79

7 5

BGA

NB

945GM

OMIT

W1

U1

Y1

E4

E2

E1

E7

E3

D6

E6

B4

A8

F8

B8

G8

D8

B3

D4

D3

K13

AC5

AA5

T6

K3

AC4

Y5

T7

K4

H8

J9

AB10

U3

W8

J7

C3

A7

K1

K9

G2

AC8

AD4

AD10

AB5

G1

AC6

AD7

AC1

AD9

AD1

AC2

AB3

AC11

AB11

AC9

K2

AB4

AA1

Y8

AA10

AA6

AA2

AA7

AA4

W2

AB8

H3

Y10

W5

Y7

Y3

W3

W4

AA9

AB7

T5

W6

J6

T9

U5

W7

T4

T8

T1

W9

T11

U11

U9

H1

U7

T3

W11

T10

G4

K11

J3

H4

J8

K7

J1

F1

B7

AG1

AG2

C7

F6

C6

J13

C13

B9

E8

F9

G12

F11

G11

E11

C9

D14

C14

H9

A14

C12

B14

B12

F12

G13

E13

A13

A12

C11

A11

D12

F14

J15

H13

J14

D9

G14

J12

H11

U1200

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB CPU Interface

12

12

104

051-6941

FSB_D_L<17>

FSB_DSTBN_L<2>
FSB_DSTBN_L<3>

FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>

FSB_DINV_L<0>

FSB_DSTBN_L<0>

FSB_DINV_L<1>
FSB_DINV_L<2>

NB_FSB_VREF

FSB_D_L<1>
FSB_D_L<2>

FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<3>

FSB_D_L<0>

FSB_D_L<16>

FSB_TRDY_L

FSB_SLPCPU_L

FSB_RS_L<1>

FSB_RS_L<0>

FSB_HITM_L
FSB_LOCK_L

FSB_HIT_L

FSB_DSTBP_L<0>

FSB_DSTBN_L<1>

FSB_DINV_L<3>

FSB_DRDY_L

FSB_DPWR_L

FSB_DEFER_L

FSB_DBSY_L

FSB_CPURST_L

FSB_BREQ0_L

FSB_BPRI_L

FSB_BNR_L

FSB_CLK_NB_N

FSB_CLK_NB_P

NB_FSB_YSWING

NB_FSB_YRCOMP
NB_FSB_YSCOMP

NB_FSB_XSWING

NB_FSB_XSCOMP

FSB_A_L<13>

FSB_ADS_L
FSB_ADSTB_L<0>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<15>

FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<31>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<21>
FSB_A_L<22>

FSB_A_L<17>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>

FSB_ADSTB_L<1>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>

FSB_D_L<30>

FSB_REQ_L<4>

FSB_RS_L<2>

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

NB_FSB_XRCOMP

63

63

63

34

34

34

19

19

19

12

12

12

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF
TV_IRTNA

TV_DACB_OUT
TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK
L_DDC_DATA

EXP_A_COMPI
EXP_A_COMPO

EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8

EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11
EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9
EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15

L_CLKCTLB

L_BKLTEN
L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

IN

OUT

IN

OUT
OUT
OUT
OUT

IN
IN

OUT
OUT
OUT

OUT

IN

OUT

OUT

BI

IN

IN
IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

IN

BI
BI

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

OUT
OUT
OUT

OUT

OUT

OUT

BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#
SDVO_INT#

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:
Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implemented
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

BGA

NB

945GM

OMIT

B19

B18

B16

J20

A19

C18

A16

F29

F28

D30

D29

G30

F30

E27
E26

A37

A36

B35

B34

C37

B37

A33
A32

C32

C33

F32

C35

B38

G25

G26

H29

H30

J30

D32

G23

R40

P36

N40

M36

L40

J36

H40

G36

AB40

AA36

Y40

W36

V40

T36

F40

D36

T40

R36

P40

N36

M40

L36

J40

H36

AC40

AB36

AA40

Y36

W40

V36

G40

F36

R38

P34

N38

M34

L38

J34

H38

G34

AB38

AA34

Y38

W34

V38

T34

F38

D34

T38

R34

P38

N34

M38

L34

J38

H34

AC38

AB34

AA38

Y34

W38

V34

G38

F34

D38

D40

H23

B21

A21

J22

B22

C22

C25

C26

D23

E23

U1200

65

65

402

MF-LF

1/16W

1%

24.9

2

1

R1310

19

65

19

19

19

19

19

19

19

19

19

19

65

19

19

19

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

19

19

19

19

65

19

19

19

19

19

19

19

19

65

19

19

19

19

19

19

19

19

19

19

65

19

19

19

19

19

19

19

19

051-6941

12

104

13

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB PEG / Video Interfaces

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<15>

CRT_BLUE_L

CRT_BLUE

CRT_GREEN_L

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFL

LVDS_VREFH

TP_LVDS_VBG

LVDS_IBG

LVDS_DDC_CLK
LVDS_DDC_DATA

PEG_COMP

PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<11>
PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>
PEG_R2D_C_P<0>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

LVDS_BKLTEN
LVDS_CLKCTLA

LVDS_BKLTCTL

=PP1V5_S0_NB_PCIE

LVDS_CLKCTLB

CRT_VSYNC_R

CRT_HSYNC_R

63 19

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2
RSVD3

RSVD6

RSVD4
RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10
RSVD11
RSVD12
RSVD13

CFG1

CFG0

CFG2
CFG3
CFG4

CFG6

CFG5

CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14

CFG17

CFG16

CFG15

CFG18
CFG19
CFG20

PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*

SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*

NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC0
NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0
SM_CK1
SM_CK2

SM_CK0*

SM_CK3

SM_CK1*
SM_CK2*
SM_CK3*

SM_CKE0
SM_CKE1

SM_CKE3

SM_CS1*
SM_CS2*
SM_CS3*

SMOCDCOMP0
SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0
SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

IN

IN

IN

IN

OUT

OUT

IN
IN

IN

BI
BI
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN

IN
IN
IN
IN
IN
IN

IN
IN
IN
IN

IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC
NC

IPD

IPD

(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)

(H_EDRDY#)

(D_PLLMON1)

(H_PROCHOT#)

(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)

(H_PLLMON1)

(H_PLLMON1#)

(H_PCREQ#)

(VSS_MCHDETECT)

(D_PLLMON1#)

NC
NC
NC

NC

NC

NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

NC
NC
NC
NC
NC

IPU

IPD

IPU

IPU

IPU
IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

NC

NC

IPU

IPU

NC

NC

NC

BGA

NB

945GM

OMIT

AK41

AK1

AV9
AT9

AF10

AL20

AU21

AY20

BA12

BA13

AW21

AY21

AW12

AW13

AY29

BA29

AT20

AU20

AY40

AW40

AY7

AW7

AT1

AR1

AW35

AY35

H27

H28

K30

J19

H7

AF11

AG11

F7

F3

R32

D27

D28

A34

A35

A41

J29

T32

AH34

AH33

G6

H26

F25

G28

B41

BA1

BA2

BA3

BA39

BA40

BA41

C1

A3

A39

A4

A40

AW1

AW41

AY1

AY41

B2

C41

D1

K28

AF33
AG33

AG41

AF37

AE41

AC37

AH41

AG37

AF41

AE37

AG39

AF35

AE39

AC35

AH39

AG35

AF39

AE35

C40
D41

A27
A26

H32

G16

D16

D19

E18

F15

E15

F18

J26

J18

K27

J25

H15

G18

H16

C15

K15

G15

D15

E16

K18

K16

U1200

6

6

20

402

MF-LF

1/16W

5%

100

21

R1430

26

10K

402

5%
MF-LF

1/16W

2

1

R1441

10K

402

5%
1/16W
MF-LF

2

1

R1440

32

0.1uF

402

CERM

10V

20%

2

1

C1416

0.1uF

402

CERM

10V

20%

2

1

C1415

23

48 21

7

48 47

79 57 23

57 26

19

19

22

33

28

29

29

28

28

29

29

28

30 28

30 28

30 29

30 28

30 29

30 28

30 29

30 29

30 28

30 28

30 29

30 29

1/16W

1%

402

MF-LF

80.6

2

1

R1410

1/16W

1%

402

MF-LF

80.6

2

1

R1411

32

34

34

19

19

19

19

22

22

22

22

22

22

22

22

22

5

22

22

22

5

22

5

22

5

22

22

1/16W

5%

402

MF-LF

10K

2

1

R1420

34

34

34

20

20

6

20

6

6

6

6

6

6

20

6

20

6

20

NB Misc Interfaces

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

14

TP_NB_XOR_FSB2_H7

TP_NB_XOR_LVDS_D27

TP_NB_XOR_LVDS_D28

TP_NB_XOR_LVDS_A34

MEM_VREF_NB_1

MEM_VREF_NB_0

MEM_RCOMP

MEM_RCOMP_L

=PP1V8_S3_MEM_NB

MEM_CKE<2>

MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>

MEM_ODT<1>
MEM_ODT<2>

NB_CFG<12>

MEM_CS_L<0>

NB_BSEL<1>

NB_BSEL<0>

NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>

NB_CFG<6>

NB_CFG<5>

NB_CFG<7>

NB_CFG<9>
NB_CFG<10>

NB_CFG<14>

NB_CFG<17>

NB_CFG<16>

NB_CFG<15>

NB_CFG<19>
NB_CFG<20>

PM_BMBUSY_L

PM_THRMTRIP_L
VR_PWRGOOD_DELAY

SDVO_CTRLCLK
SDVO_CTRLDATA
NB_SB_SYNC_L

MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>

MEM_CLK_N<0>

MEM_CLK_P<3>

MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>

MEM_CKE<0>
MEM_CKE<1>

MEM_CKE<3>

MEM_ODT<0>

MEM_ODT<3>

NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

NB_RST_IN_L

NB_CFG<8>

NB_CFG<11>

NB_CFG<13>

NB_CFG<18>

=PP3V3_S0_NB

PM_DPRSLPVR

TP_NB_TESTIN_L

TP_NB_XOR_LVDS_A35

NB_TV_DCONSEL0
NB_TV_DCONSEL1

=PP3V3_S0_NB

NB_CLK_DREFSSCLKIN_P

NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFCLKIN_P

NB_CLK_DREFCLKIN_N

CLK_NB_OE_L

NB_RST_IN_L_R

PM_EXTTS_L

63

63

63

20

20

19

19

19

19

19

19

16

14

19

14

SA_DQ1

SA_DQ0

SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0
SA_DM1
SA_DM2
SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6
SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA1

SA_MA0

SA_MA2
SA_MA3

SA_MA5

SA_MA4

SA_MA6
SA_MA7

SA_MA9

SA_MA8

SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

BI

BI
BI
BI
BI
BI

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

BI
BI
BI

BI

BI
BI
BI
BI

BI BI

BI
BI
BI
BI
BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

SB_DQ1

SB_DQ0

SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0
SB_DM1
SB_DM2
SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6
SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*

SB_MA1

SB_MA0

SB_MA2
SB_MA3

SB_MA5

SB_MA4

SB_MA6
SB_MA7

SB_MA9

SB_MA8

SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

BI
BI
BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

BI

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI
BI

OUT

BI

BI

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

BI

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC

NC

NC

BGA

945GM

NB

OMIT

AY14

AK24

AK23

AW14

AT16

AW17

AU17

AV17

AU16

BA17

BA16

AW16

AV12

AV20

AT17

AU13

AU14

AY16

AH5

AG5

AN3

AP3

AL8

AN8

AM12

AN12

AM21

AM22

AN27

AN28

AU33

AT33

AK32

AK33

AP33

AN35

AH31

AF8

AF4

AH6

AG9

AJ32

AF6

AG4

AF9

AG7

AL2

AN1

AT3

AV2

AN2

AP1

AK35

AW2

AY2

AL5

AT5

AN9

AP9

AK7

AK8

AN7

AK9

AJ36

AL12

AL14

AT12

AT13

AP12

AP13

AR14

AR12

AT21

AP20

AM33

AP24

AL23

AN20

AP21

AL22

AP23

AP26

AM24

AL28

AK28

AM31

AN24

AM26

AL27

AK26

AN33

AM34

AM36

AN38

AP31

AR31

AJ34

AJ35

AH4

AR3

AL9

AM14

AN22

AL26

AM35

AJ33

AY13

BA20

AV14

AU12

U1200

28

28

28

28

28

28

28

28

28

28

28

28

28

28

29

29

29

29

29

29

29

29

28 29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

BGA

945GM

NB

OMIT

AR27

AK18

AK16

AU23

AW27

AV27

AV28

AU27

AT28

AT27

AR28

AY24

AR23

AY27

BA27

AV24

AW24

AY23

AP5

AN5

AT7

AR7

AT10

AR10

AP16

AR16

AP29

AR29

AT35

AU35

AU39

AT39

AM40

AM39

AV41

AT40

AP41

AJ3

AJ5

AK5

AT4

AN41

AK3

AK4

AR5

AV4

AY5

AW5

AY9

AY10

AW4

BA4

AK38

AW10

BA10

AJ8

AK10

AH11

AK13

AN10

AJ9

AH10

AJ11

AJ38

AL15

AP15

AM16

AN17

AN14

AP14

AL19

AM19

AW29

AV29

AR41

AW31

AU31

AU29

AT31

BA33

AY33

AP34

AP35

AU36

BA36

AP39

AP36

AR36

AV36

BA38

AY38

AW38

AR40

AP38

AV38

AU38

AJ37

AK39

AN4

BA5

AH8

AL17

BA31

AT36

AR38

AK36

AR24

AY28

AV23

AT24

U1200

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

30 29

30 29

30 29

28

30 29

30 29

30 29

30 29

30 29

30 29

30 29

30 29

30 29

30 29

28

30 29

30 29

30 29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

30 29

30 29

30 29

28

30 29

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

30 28

30 28

30 28

28

30 28

28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

28

28

28

28

28

28

28

28

28

28

28

28

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB DDR2 Interfaces

051-6941

12

104

15

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_BS<2>
MEM_B_CAS_L

MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<3>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>

MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_BS<2>
MEM_A_CAS_L

MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<2>
MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47
VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37
VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34
VCCAUX_NCTF35

VCCAUX_NCTF32
VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27
VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24
VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42
VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19
VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14
VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7
VSS_NCTF8

VSS_NCTF5
VSS_NCTF6

VSS_NCTF4

VSS_NCTF2
VSS_NCTF3

VSS_NCTF0
VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61
VCC_NCTF62
VCC_NCTF63

VCC_NCTF60

VCC_NCTF57
VCC_NCTF58
VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53
VCC_NCTF54

VCC_NCTF52

VCC_NCTF50
VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46
VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38
VCC_NCTF39

VCC_NCTF36
VCC_NCTF37

VCC_NCTF34
VCC_NCTF35

VCC_NCTF33

VCC_NCTF31
VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18
VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13
VCC_NCTF14

VCC_NCTF11
VCC_NCTF12

VCC_NCTF10

VCC_NCTF8
VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0
VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NCTF balls are Not Critical To Function

These connections can break without

impacting part performance.

Layout Note:
Place near pin BA23

Place near pin BA15

Layout Note:

Layout Note:
Place in cavity

1.05V or 1.5V

1.05V, External Graphics: 1500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, Internal Graphics: 3500mA Max

667MTs 1700mA 3200mA

533MTs 1500mA 2800mA

400MTs 1300mA 2400mA

Speed 1 Channel 2 Channel

1.8V Max Current

BGA

NB

945GM

OMIT

AT6

AV6

AW6

AY6

BA6

AP8

AR8

AT8

AV8

AW8

AT34

AY8

BA8

AK11

AG12

AH12

AJ12

AK12

AH13

AJ13

AJ14

AU34

AJ15

AR15

AT15

AU15

AV15

AW15

AY15

BA15

AH16

AJ16

AV34

AH17

AJ17

AJ18

AJ19

AK19

AP19

AR19

AT19

AU19

AV19

AW34

AW19

AY19

BA19

AK20

AK21

AJ22

AK22

AP22

AR22

AT22

AY34

AU22

AV22

AW22

AY22

BA22

AJ23

BA23

AH24

AJ24

AH25

BA34

AJ25

AH26

AJ26

AR26

AT26

AU26

AV26

AW26

AY26

BA26

AU40

AH27

AJ27

AH28

AJ28

AH29

AJ29

AK29

AL29

AM29

AM30

AM41

AN30

AP30

AR30

AT30

AU30

AV30

AW30

AY30

BA30

AJ1

AV1

AJ6

AK6

AL6

AN6

AP6

AR6

AR34

AT41

AU41

N19

Y19

AA19

AB19

L20

M20

N20

P20

W20

Y20

V32

AB20

AC20

L21

M21

N21

W21

AA21

AC21

L22

M22

W32

N22

P22

W22

Y22

AB22

AC22

L23

M23

N23

P23

Y32

Y23

AA23

AB23

M24

N24

P24

L25

M25

N25

L26

AA32

N26

P26

L27

M27

N27

P27

L28

M28

N28

P28

J33

R28

T28

U28

V28

Y28

AA28

AB28

L29

M29

P29

L33

R29

U29

V29

W29

Y29

AA29

L30

M30

N30

P30

N33

R30

T30

U30

V30

W30

Y30

AA30

M31

N31

P31

P33

R31

T31

V31

W31

AA31

J32

L32

M32

L16

N32

M16

N16

M17

N17

P17

L18

M18

N18

L19

M19

P32

W33

AA33

U1200

402

6.3V
CERM-X5R

0.47uF

20%

2

1

C1610

603

20%
X5R

6.3V

10uF

2

1

C1621

10uF

6.3V
X5R

20%

603

2

1

C1620

945GM

NB

BGA

OMIT

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

U17

Y17

AC17

AE26

AE27

AF23

AG23

AF24

AG24

R15

T15

U15

V15

W15

Y15

AA15

AB15

AF25

AC15

AD15

AE15

AF15

AG15

R16

T16

U16

V16

W16

AG25

Y16

AA16

AB16

AC16

AD16

AE16

AF16

AG16

R17

T17

AF26

V17

W17

AA17

AB17

AD17

AE17

AF17

AG17

R18

AF18

AG26

AG18

R19

AF19

AG19

AF20

AG20

AF21

AG21

AF22

AG22

AF27

AG27

R27

T27

T18

U18

V18

U27

W18

Y18

AA18

AB18

AC18

AD18

T19

U19

V19

AD19

V27

R20

T20

U20

V20

AD20

R21

T21

U21

V21

AD21

W27

R22

T22

U22

V22

AD22

R23

T23

U23

V23

AD23

Y27

R24

T24

U24

V24

W24

Y24

AA24

AB24

AC24

AD24

AA27

R25

T25

U25

V25

W25

Y25

AA25

AB25

AC25

AD25

AB27

R26

T26

U26

V26

W26

Y26

AA26

AB26

AC26

AD26

AC27

AD27

U1200

402

6.3V
CERM-X5R

0.47uF

20%

2

1

C1611

402

6.3V

CERM-X5R

0.47uF

20%

2

1

C1612

402

6.3V
CERM-X5R

20%

0.47uF

2

1

C1613

402

6.3V

CERM-X5R

20%

0.47uF

2

1

C1614

402

6.3V
CERM-X5R

20%

0.47uF

2

1

C1615

NB Power 1

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

16

=PP1V8_S3_MEM_NB

NB_VCCSM_LF1

NB_VCCSM_LF2

NB_VCCSM_LF5

NB_VCCSM_LF4

=PPVCORE_S0_NB

=PPVCORE_S0_NB

=PP1V5_S0_NB_VCCAUX

63

63

63

63

19

19

19

19

14

16

16

17

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25

VTT27

VTT26

VTT28
VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35
VTT36
VTT37

VTT39

VTT38

VTT40
VTT41
VTT42
VTT43
VTT44
VTT45

VTT48

VTT46
VTT47

VTT49
VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58
VTT59
VTT60
VTT61
VTT62

VTT64

VTT63

VTT65
VTT66
VTT67

VTT69

VTT68

VTT70
VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG
VSSA_TVBG

VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0
VCCD_LVDS1

VCCD_TVDAC

VCC_HV1
VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14
VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23
VCCAUX24

VCCAUX22

VCCAUX25
VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30
VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34
VCCAUX35
VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39
VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1900mA Max

40mA Max

See VCCSYNC

150mA Max

120mA Max

45mA Max

45mA Max

50mA Max

50mA Max

10mA Max

24mA Max

20mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

60mA Max

2mA Max

800mA Max

1500mA Max VCC3G/3GPLL

OMIT

BGA

NB

945GM

L14

M14

M1

N1

P1

R1

AB1

D2

M2

N14

P2

R2

M3

N3

P3

R3

M4

N4

P4

M5

P14

N5

P5

R5

A6

M6

P6

R6

M7

N7

P7

R14

M8

N8

P8

R8

M9

N9

P9

M10

N10

P10

T14

R10

M11

N11

P11

R11

L12

M12

N12

P12

R12

V14

T12

U12

V12

W12

Y12

AA12

AB12

L13

M13

N13

W14

R13

T13

U13

V13

W13

Y13

AA13

AB13

AC13

AD13

AB14

AC14

G20

B39

G21

H41

H22

D21

H19

C28

B28

A28

AH2

AH1

AF30

AG30

AH30

AJ30

AK30

AD12

AL30

AE12

AF12

AE13

AF13

Y14

AE14

AF14

AG14

AH14

P15

AC31

AH15

P16

P19

AH19

AH20

AJ20

AH21

AJ21

AH22

AE28

AE31

AF28

AG28

AC29

AD29

AE29

AF29

AG29

AC30

AD30

AE30

AF31

AK31

F20

E20

D20

C20

F19

E19

H20

AF2

A38

AF1

C39

B26

E21

F21

AC33

G41

A30

B30

C30

B25

B23

A23

L41

N41

R41

V41

Y41

AB41

AJ41

U1200

402

CERM-X5R

6.3V

0.47uF

20%

2

1

C1711

20%

0.22uF

6.3V
402

X5R

2

1

C1712

402

6.3V

CERM-X5R

20%

0.47uF

2

1

C1713

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Power 2

051-6941

12

104

17

PP2V5_S0_NB_VCCA_CRTDAC

=PP1V5_S0_NB_VCCAUX

PP1V5_S0_NB_VCCD_QTVDAC

=PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCA_MPLL

=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_DPLLB

GND_NB_VSSA_CRTDAC

GND_NB_VSSA_3GBG

=PP2V5_S0_NB_VCCA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB_VCC3G

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

NB_VTTLF_CAP1

NB_VTTLF_CAP2

NB_VTTLF_CAP3

=PP1V05_S0_NB_VTT

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_LVDS

63 19

63

63

63

63

19

16

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

VSS_1

VSS_0

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7

VSS_9

VSS_8

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17

VSS_19

VSS_18

VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26

VSS_28

VSS_27

VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

VSS_49

VSS_48

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

VSS_73

VSS_72

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79

VSS_82

VSS_80
VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92
VSS_93
VSS_94

VSS_96

VSS_95

VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125

VSS_127

VSS_126

VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135

VSS_137

VSS_136

VSS_138
VSS_139
VSS_140
VSS_141

VSS_143

VSS_142

VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156

VSS_158

VSS_157

VSS_159
VSS_160
VSS_161
VSS_162

VSS_164

VSS_163

VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170

VSS_172

VSS_171

VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269
VSS_270

VSS_268

VSS_266
VSS_267

VSS_265

VSS_264

VSS_263

VSS_261
VSS_262

VSS_260

VSS_259

VSS_258

VSS_256
VSS_257

VSS_255

VSS_254

VSS_253

VSS_251
VSS_252

VSS_250

VSS_248
VSS_249

VSS_247

VSS_246

VSS_245

VSS_243
VSS_244

VSS_242

VSS_241

VSS_240

VSS_238
VSS_239

VSS_237

VSS_236

VSS_235

VSS_233
VSS_234

VSS_232

VSS_231

VSS_230

VSS_228
VSS_229

VSS_227

VSS_225
VSS_226

VSS_224

VSS_223

VSS_222

VSS_220
VSS_221

VSS_219

VSS_218

VSS_217

VSS_215
VSS_216

VSS_214

VSS_213

VSS_212

VSS_210
VSS_211

VSS_209

VSS_207
VSS_208

VSS_205
VSS_206

VSS_204

VSS_202
VSS_203

VSS_201

VSS_200

VSS_199

VSS_197
VSS_198

VSS_196

VSS_195

VSS_194

VSS_192
VSS_193

VSS_191

VSS_190

VSS_189

VSS_187
VSS_188

VSS_186

VSS_184
VSS_185

VSS_183

VSS_182

VSS_180
VSS_181

VSS_273
VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282
VSS_283
VSS_284

VSS_286

VSS_285

VSS_287
VSS_288
VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301
VSS_302

VSS_300

VSS_304

VSS_303

VSS_305
VSS_306
VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312
VSS_313
VSS_314
VSS_315

VSS_317

VSS_316

VSS_318
VSS_319
VSS_320

VSS_322

VSS_321

VSS_323
VSS_324
VSS_325

VSS_327

VSS_326

VSS_328
VSS_329
VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338
VSS_339
VSS_340

VSS_342
VSS_343

VSS_341

VSS_345

VSS_344

VSS_346
VSS_347
VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB

945GM

BGA

OMIT

AF34

AG34

AK34

AN34

D35

F35

G35

H35

J35

L35

AP40

M35

N35

P35

R35

T35

V35

W35

Y35

AA35

AB35

AV40

AH35

AR35

AV35

BA35

B36

C36

AC36

AE36

AF36

AG36

F41

AH36

AN36

AW36

AY36

D37

F37

G37

H37

J37

L37

J41

M37

N37

P37

R37

T37

V37

W37

Y37

AA37

AB37

M41

AH37

AK37

C38

AE38

AF38

AG38

AH38

AM38

AT38

D39

P41

F39

G39

H39

J39

L39

M39

N39

P39

R39

T39

T41

V39

W39

Y39

AA39

AB39

AC39

AJ39

AN39

AR39

AV39

W41

AW39

AY39

AW23

AL24

AU24

BA24

A25

D25

E25

H25

K25

P25

B40

AK25

D26

F26

K26

M26

AN26

B27

C27

F27

G27

AE40

J27

AK27

AM27

AP27

E28

J28

W28

AC28

AD28

AM28

AF40

AP28

AU28

AW28

BA28

A29

B29

C29

E29

G29

K29

AG40

N29

T29

AB29

AN29

AT29

E30

AB30

Y31

AB31

AG31

AH40

AJ31

AN31

AV31

AY31

B32

G32

AB32

AC32

AE32

AF32

AJ40

AG32

AH32

B33

D33

F33

G33

H33

M33

R33

T33

AK40

V33

Y33

AB33

AE33

AR33

AV33

AW33

C34

AC34

AE34

AN40

AA41

AC41

U1200

NB

945GM

BGA

OMIT

AL1

C2

F2

H2

J2

N2

T2

U2

Y2

AB2

AD2

AJ2

AK2

AP2

AR2

AT2

G3

AA3

AC3

AD3

AF3

AG3

AH3

AL3

AV3

AW3

AY3

C4

F4

J4

R4

U4

Y4

AJ4

AL4

AP4

AR4

AY4

AD5

AF5

AV5

B6

H6

K6

N6

U6

Y6

AB6

AD6

AG6

D7

G7

R7

AC7

AF7

AH7

AJ7

AL7

AP7

AV7

BA7

C8

K8

U8

AA8

AD8

AG8

A9

E9

G9

R9

Y9

AB9

AH9

AR9

AW9

BA9

U10

W10

AC10

AG10

AJ10

AL10

AP10

AV10

B11

D11

J11

Y11

AA11

AD11

E12

H12

K12

AC12

AY12

B13

D13

F13

P13

AG13

AL13

AM13

AN13

AR13

AV13

E14

H14

K14

U14

AA14

AD14

AK14

AT14

BA14

A15

B15

L15

M15

N15

AK15

AM15

AN15

C16

F16

J16

AL16

AN16

AV16

AK17

AM17

AP17

AR17

AY17

A18

D18

H18

P18

AH18

C19

G19

K19

W19

AC19

AN19

A20

B20

K20

AA20

AM20

AR20

AW20

C21

H21

J21

K21

P21

Y21

AB21

AL21

AN21

AR21

AV21

BA21

A22

D22

E22

F22

G22

K22

AA22

C23

F23

J23

K23

W23

AC23

AH23

AM23

AN23

AT23

U1200

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Grounds

051-6941

12

104

18

IN

IN

IN

IN

IN

IN
IN
IN

IN

IN
IN
IN

IN

IN

IN

IN

IN
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GMCH CORE PWR 1.05V BYPASS

1500mA Max

1500mA Max
10mA Max?

?mA Max

?mA Max

60mA Max

70mA Max

3200mA Max

24mA Max

100mA Max

?mA Max

800mA Max

3674mA Max

?mA Max
40mA Max

40mA Max?

1500mA Max

2mA Max

1900mA Max

150mA Max

2310mA Max?

Power Interface

These are the power signals that leave the NB "block"

132mA Max

3200mA Max

Rail Totals:

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH LVDS DATA/CLK TX 2.5V PWR)

(MCH LVDS DIGITAL 1.5V PWR)

(MCH LVDS ANALOG 2.5V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

(MCH DISPLAY A PLL 1.5V PWR)

(MCH DISPLAY B PLL 1.5V PWR)

1500mA Max

be close to MCH
on opposite side.

GMCH VCCA_3GPLL FILTER

(PCI-E/DMI ANALOG 1.5V PWR)

10uF caps should

Layout Note: Route to caps, then GND

(3GIO PLL 1.5V PWR)

GMCH VCC3G FILTER

Layout Note:

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Place L and C
close to MCH

Layout Note:

1500mA Max

GMCH VCCA_HPLL FILTER

45mA Max

(HOST PLL 1.5V PWR)

(MCH MEMORY PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

45mA Max

100mA Max

GMCH VCCAUX FILTER
(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

MCH VCCA_3GBG BYPASS

2mA Max

MCH VCC_HV BYPASS
(MCH HV BUFFER 3.3V PWR)

40mA Max

Place on the edge

Layout Note:

(SHARE C0940 470UF)

MCH VTT BYPASS
(MCH FSB 1.05V PWR)

Layout Note:
Place in cavity

800mA Max

0.22uF

X5R

6.3V

20%

402

2

1

C1907

X5R
603

20%

6.3V

10uF

2

1

C1972

220UF

20%

2.5V
POLY
SMB2

2

1

C1970

6.3V

20%
402

X5R

0.22uF

2

1

C1967

6.3V
603

2.2uF

20%
CERM1

2

1

C1966

6.3V

20%
603

CERM

4.7uF

2

1

C1965

63 34 12

63 19 17

63 13

63 19

63 17

63 19 17 16

63 19

19 17

63 19 17

63 19

63 19 17

470uF-7MOHM

20%

2.5V
TANT
D2T

CRITICAL

3 2

1

C1900

63 19

63 19

91nH

1210

21

L1970

0.1uF

402

20%
10V

CERM

2

1

C1916

6.3V

20%

402

X5R

0.22uF

2

1

C1906

10V

20%
402

CERM

0.1uF

2

1

C1915

6.3V

20%
603

X5R

10uF

2

1

C1914

6.3V
402

20%
X5R

0.22uF

2

1

C1905

20%
10V

402

CERM

0.1uF

2

1

C1935

FERR-120-OHM-0.2A

0603

21

L1934

0.1uF

CERM

20%
10V

402

2

1

C1937

402

6.3V

1uF

CERM

10%

2

1

C1904

FERR-120-OHM-0.2A

0603

21

L1936

22uF

X5R
805

20%

6.3V
2

1

C1934

22uF

X5R
805

20%

6.3V

2

1

C1936

6.3V
X5R

20%

603

10uF

2

1

C1903

6.3V

20%

603

X5R

10uF

2

1

C1902

10V

20%
402

CERM

0.1uF

2

1

C1918

10V

20%
402

CERM

0.1uF

2

1

C1976

1.0UH-220MA-0.12-OHM

0805

21

L1975

6.3V

20%
603

X5R

10uF

2

1

C1975

MF-LF

402

0.51

1/16W

1%

21

R1975

10uF

X5R
603

20%

6.3V

2

1

C1971

NB (GM) Decoupling

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

19

=PP1V05_S0_NB_VTT

=PP3V3_S0_NB_VCC_HV

=PP2V5_S0_NB_VCCA_3GBG

=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_PLL

PP1V5_S0_NB_VCCA_MPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_VCCA_HPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_3GPLL_F

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

VOLTAGE=1.5V

PP1V5_S0_NB_VCC3G

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

GND_NB_VSSA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_3G

NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N

TP_NB_VCCA_DPLLB

MAKE_BASE=TRUE

PP1V5_S0_NB_VCCA_DPLLB

MAKE_BASE=TRUE

TP_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_DPLLA

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACA

PP1V5_S0_NB_VCCD_QTVDAC

PP1V5_S0_NB_VCCD_TVDAC

=PP2V5_S0_NB_VCCSYNC

PP2V5_S0_NB_VCCA_CRTDAC
GND_NB_VSSA_CRTDAC

NO_TEST=TRUE

NC_GND_NB_VSSA_LVDS

MAKE_BASE=TRUE

GND_NB_VSSA_LVDS

=PP2V5_S0_NB_VCCA_LVDS

=PP1V5_S0_NB_VCCD_LVDS

=PP2V5_S0_NB_VCC_TXLVDS

=PP1V5_S0_NB_TVDAC

=PPVCORE_S0_NB

=PPVCORE_S0_NB

=PP1V5_S0_NB

=PP1V05_S0_NB_VTT

=PP1V5_S0_NB_3G

=PP1V5_S0_NB_PCIE

=PP1V05_S0_FSB_NB

=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV

=PP2V5_S0_NB_VCCA_3GBG

=PP1V8_S3_MEM_NB

=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_PLL

=PP1V5_S0_NB_3GPLL

=PP1V05_S0_NB_CRT

=PPVCORE_S0_NB

MAKE_BASE=TRUE

TP_CRT_DDC_CLK

CRT_DDC_DATA

MAKE_BASE=TRUE

TP_CRT_DDC_DATA

CRT_DDC_CLK

CRT_IREF

CRT_BLUE_L

CRT_GREEN_L

CRT_RED_L

CRT_BLUE

CRT_GREEN

CRT_RED

=PP1V05_S0_NB_CRT

TV_DACB_OUT
TV_DACC_OUT

TV_DACA_OUT

TV_IRTNA

TV_IREF

TV_IRTNC

TV_IRTNB

LVDS_BKLTEN

MAKE_BASE=TRUE

TP_LVDS_BKLTEN

LVDS_BKLTCTL

MAKE_BASE=TRUE

TP_LVDS_BKLTCTL

LVDS_CLKCTLA

MAKE_BASE=TRUE

TP_LVDS_CLKCTLA

LVDS_CLKCTLB

MAKE_BASE=TRUE

TP_LVDS_CLKCTLB

LVDS_DDC_CLK

MAKE_BASE=TRUE

TP_LVDS_DDC_CLK

LVDS_IBG

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IBG

LVDS_DDC_DATA

MAKE_BASE=TRUE

TP_LVDS_DDC_DATA

LVDS_VREFL

MAKE_BASE=TRUE

TP_LVDS_VREFL

LVDS_VDDEN

MAKE_BASE=TRUE

TP_LVDS_VDDEN

LVDS_VREFH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_VREFH

LVDS_A_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_CLKP

LVDS_A_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_CLKN

LVDS_A_DATA_P<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<2..0>

LVDS_A_DATA_N<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<2..0>

LVDS_B_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_CLKN

LVDS_B_DATA_P<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_DATAP<2..0>

LVDS_B_CLK_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_CLKP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A35

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D27

TP_NB_XOR_LVDS_D28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D28

TP_NB_XOR_LVDS_A35

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A34

SDVO_CTRLDATA

MAKE_BASE=TRUE

TP_SDVO_CTRLDATA

SDVO_CTRLCLK

MAKE_BASE=TRUE

TP_SDVO_CTRLCLK

TP_NB_XOR_LVDS_A34

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<2..0>

=PP1V5_S0_NB_TVDAC

CRT_VSYNC_R

CRT_HSYNC_R

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

LVDS_B_DATA_N<2..0>

TP_NB_XOR_LVDS_D27

63

63 63

63 19

63

63

19 19

19 17

63

63

63

19

19

63

19

19

63

63

17 17

17 16

19

17

17

17

17

17 19

19

14

14

14

14

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

19

16

16

13

13

13

13

13

13

13

13

13

19

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

14

14

14

14

14

19

13

13

13

14

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Internal pull-ups

Internal pull-up

RESERVED

RESERVED

NB_CFG<11>

NB_CFG<10>

High = Mobile CPU

NB_CFG<7>

RESERVED

Internal pull-up

DMI x2 Select

PROBABLY NOT NEEDED

PROBABLY NOT NEEDED

Lane Reversal

NB_CFG<4>

NB_CFG<3>

RESERVED

NB_CFG<13:12>

NB_CFG<14>

NB_CFG<5>

NB_CFG<15>

NB_CFG<16>

NB_CFG<6>

NB_CFG<17>

NB_CFG<18>

NB_CFG<8>

NB_CFG<9>

NB_CFG<19>

NB_CFG<20>

Low = DMIx2

High = DMIx4

Low = RESERVED

High = Normal

PCIE Graphics

RESERVED

CPU Strap

RESERVED

Low = Reversed

Internal pull-up

11 = Normal Operation

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

00 = Partial Clock Gating Disable

RESERVED

Internal pull-up

RESERVED

High = Enabled
Low = Disabled

RESERVED

FSB Dynamic
ODT

or PCIe x1

Low = Only SDVO

High = Both active

945 External Design Spec says reserved

Internal pull-down

Internal pull-down

Internal pull-down

Low = 1.05V

High = 1.5V

Low = Normal

High = Reversed
DMI Lane
Reversal

VCC Select

Interop. Mode

PCIe Backward

402

5%

2.2K

1/16W
MF-LF

NBCFG_DMI_X2

2

1

R2075

2.2K

5%
1/16W
MF-LF
402

NBCFG_DYN_ODT_DISABLE

2

1

R2085

402

1/16W

5%

2.2K

NBCFG_VCC_1V5

MF-LF

2

1

R2058

402

MF-LF

1/16W

5%

2.2K

NBCFG_DMI_REVERSE

2

1

R2059

NBCFG_SDVO_AND_PCIE

402

MF-LF

1/16W

5%

2.2K

2

1

R2060

402

MF-LF

1/16W

5%

2.2K

NO STUFF

2

1

R2077

402

MF-LF

1/16W

5%

2.2K

NBCFG_PEG_REVERSE

2

1

R2079

20

104

12

051-6941

NB Config Straps

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PP3V3_S0_NB

=PP3V3_S0_NB

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<19>

NB_CFG<20>

NB_CFG<16>

NB_CFG<5>

NB_CFG<7>

NB_CFG<9>

63

63

63

20

20

20

19

19

19

14

14

14

14

14

14

14

14

14

14

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN
IN

BI
BI
BI
BI

IN

BI

DDACK*

SATARBIASN
SATARBIASP

SATA_CLKN
SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN
SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0
LAN_TXD1

LAN_RXD1
LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0
LAD1

EE_DOUT
EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY
DDREQ

DD0
DD1

DD3

DD2

DD5

DD4

DD6
DD7
DD8

DD11

DD9

DD10

DD12
DD13
DD14
DD15

DA0
DA1
DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT
OUT

OUT
IN

OUT

IN
IN

IN
IN

OUT
OUT

OUT
OUT

IN
IN

OUT
OUT
OUT

IN
IN
IN

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WEAK INT PU)

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

INTEL HIGH DEFINITION AUDIO

ACZ_SDOUT

ACZ_SYNC

ACZ_BIT_CLK
ACZ_RST#

ACZ_SDIN[0-2]

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

AC ’07

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

NONE

INTERNAL 20K PD

INTERNAL 20K PD ONLY ENABLED IN S3COLD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

NOTE: DD<7> HAS INTERNAL 11.5K PD

(HSTROBE)
(STOP)

20K PD
20K PD
20K PD

(DSTROBE)

< 2 IN OF R2107 W/O STUB

LAYOUT NOTE: R2108 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB

BOM CONSOLIDATION

NOTE: RISING-EDGE TRIGGERED AT CPU

NOTE: KEYBOARD CONTROLLER RESET CPU

POR IS SMC WILL PUT LAN INT’F

NOTE:

INTO RESET STATE TO SAVE PWR.

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTEL CONFIRMS OK TO LEAVE PINS AS NC

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

NOTE: PULLED UP PER INTEL

NOTE: R2110=56 IN CV.
CHANGED TO 54.9 FOR
BOM CONSOLIDATION

NOTE: R2108=56 IN CV.

(WEAK INT PD)

(INT PU)

(INT PU)

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

36

48 14

7

79

7

79

7

79

7

79

7

49 48

5

79

7

79

7

7

79

7

57

7

56 49 47

5

79

7

26

26

26

26

36

36

56 49 47

5

56 49 47

5

56 49 47

5

NOSTUFF

1/16W

MF-LF

0

5%

402

21

R2100

47

NOSTUFF

402

2.2K

5%
1/16W
MF-LF

21

R2101

MF-LF

5%

39

402

1/16W

21

R2195

39

21

R2198

39

21

R2197

39

21

R2196

402

10K

5%
1/16W
MF-LF

2

1

R2199

BGA

SB

ICH7-M

OMIT

AH25

AF24

AF26

AH22

AF23

AG10

AH10

AF18

AE1

AF1

AH6

AG6

AE7

AF7

AH2

AG2

AE3

AF3

AB2

AB1

AA3

AG23
AH24

AB3

AA5

AC3

V7

V6

U7

T5

V4

U5

U3

V3

Y6

AC4

AB5

AA6

AG16

W4

Y5

AF25

AG21
AF22

AG22

AH16

AG24

AG26

Y1
Y2
W3

W1

AH15

AF15

AE15

AF16

AF12

AE12

AC12

AD12

AC13

AD14

AF13

AG13

AC15

AH14

AH13

AF14

AC14

AB13

AE14

AB15

AD16

AE16

AF17

AE17

AH17

AG27

R6

T4

T1

T3

T2

R5

U1

AH28

AE22

U2100

402

10K

5%
1/16W
MF-LF

2

1

R2194

332K

402

1%

1/16W

MF-LF

2

1

R2105

24.9

MF-LF
1/16W

1%

402

21

R2107

402

MF-LF
1/16W

1%

54.9

2

1

R2108

MF-LF
1/16W

402

54.9

1%

21

R2110

79 45

5

79 45

5

79 45

5

79 45

5

79 45

5

36

36

76

76

36

36

76

76

34

5

34

5

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

12

21

104

051-6941

SYNC_MASTER=M38

SYNC_DATE=11/16/2005

SB: 1 OF 4

TP_SB_XOR_V7

TP_SB_XOR_V6

TP_SB_XOR_U7

TP_SB_XOR_Y2

TP_SB_XOR_Y1

TP_SB_XOR_W1

SB_INTVRMEN

=PP1V05_S0_SB_CPU_IO

CPU_FERR_L

SB_A20GATE

CPU_RCIN_L

SATA_C_D2R_P

IDE_PDDACK_L

SATA_RBIAS_N
SATA_RBIAS_P

SB_CLK100M_SATA_N
SB_CLK100M_SATA_P

SATA_C_R2D_C_P

SATA_C_R2D_C_N

SATA_C_D2R_N

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_A_D2R_P

SATA_A_D2R_N

TP_SB_SATALED_L

SB_ACZ_SDATAOUT

TP_SB_ACZ_SDIN1
TP_SB_ACZ_SDIN2

ACZ_SDATAIN<0>

SB_ACZ_SYNC

SB_ACZ_BITCLK

SB_SM_INTRUDER_L

SB_RTC_X1

CPU_THERMTRIP_R

CPU_STPCLK_L

CPU_NMI

CPU_SMI_L

CPU_INTR

CPU_INIT_L

FWH_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L

CPU_DPSLP_L

CPU_A20M_L

TP_CPU_CPUSLP_L

SB_ACZ_RST_L

IDE_PDIOR_L

IDE_IRQ14

IDE_PDIOW_L

IDE_PDIORDY
IDE_PDDREQ

IDE_PDD<0>
IDE_PDD<1>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<7>
IDE_PDD<8>

IDE_PDD<11>

IDE_PDD<9>
IDE_PDD<10>

IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>

IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

ACZ_SYNC

SMC_RCIN_L

=PP1V05_S0_SB_CPU_IO

PM_THRMTRIP_L

ACZ_SDATAOUT

IDE_PDD<6>

=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_GPIO

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

TP_SB_DRQ0_L
TP_SB_GPIO23

LPC_FRAME_L

SB_RTC_X2
SB_RTC_RST_L

ACZ_BITCLK

ACZ_RST_L

PP3V3_S5_SB_RTC

TP_SB_XOR_U3
TP_SB_XOR_U5

TP_SB_XOR_V4
TP_SB_XOR_T5

TP_SB_XOR_W3
TP_SB_XOR_V3

IDE_PDD<2>
IDE_PDD<3>

63

63

25

25 63

63

26

24

24 23

23

25

21

79

79

79

79

21 21

21

24

6

6

6

6

IN

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI
BI

BI
BI

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI2TXN
DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P

USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBP4N

OC0*
OC1*
OC2*
OC3*
OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK
SPI_CS*

SPI_MOSI
SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN
DMI1RXP

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0*
C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE2*
C/BE3*

GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*

PIRQA*
PIRQB*
PIRQC*
PIRQD*

RSVD0
RSVD1
RSVD2
RSVD3

MISC

INT I/F

PCI

(2 OF 6)

BI

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

IN

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

AND PWROK=H

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

BOM NOTE FOR PD ON PCI_GNT3_L:

IR

BT

CF/SD

CAMERA

AIRPORT (MINI-PCIE)

EXTERNAL 2

EXTERNAL 1

EXTERNAL 0

NOTE:

STUFF - A16 SWAP OVERRIDE

(STRAPPED TO TOP-BLOCK SWAP MODE
IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)

SB BOOT BIOS SELECT

GNT4#GNT5#

TO RSVD[1-9]

NOTE: CHANGE SYMBOL

R2210STRAP
11
10
01

STUFF

UNSTUFF

UNSTUFFUNSTUFF

STUFF

UNSTUFF

SPI

PCI

LPC (DEFAULT)

NOTE:

LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

(INT PD)

(INT PD)

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

NOTE: FWH_WP_L NOT USED

R2211

ENABLED ONLY WHEN PCIRST#=0

SB: 2 OF 4

(AKA TP3, INTERNAL 20K PU)

(INT 20K PU)

GNT[0-3]# HAVE INT 20K PU

NO STUFF - DEFAULT

34

40

40 26

40

40

40

40

40

40 26

26

26

26

49 47

5

37

37

46

46

46

46

1/16W

402

24.9

MF-LF

1%

21

R2203

46

46

46

46

46

46

37

37

46

46

46

46

46

46

46

46

46

46

52 47

52 47

52 47

52 47

22

6

6

6

6

6

6

6

6

6

6

6

6

6

34

14

34

14

14

14

14

14

5

14

5

14

5

14

5

14

14

14

14

14

14

14

10K

1/16W
MF-LF

5%
402

USB_G_OC_PU

2

1

R2222

402

22.6

1%
1/16W
MF-LF

21

R2204

1/16W

5%

10K

MF-LF
402

2

1

R2223

10K

5%
1/16W
MF-LF
402

2

1

R2225

402

MF-LF

1/16W

10K

5%

2

1

R2226

40

10K

5%
1/16W
MF-LF
402

2

1

R2299

OMIT

BGA

SB

ICH7-M

D2
D1

N3

N4

M2

M1

L5

L4

K2

K1

J3

J4

H2

H1

G3

G4

F2

F1

P5
P2

P6

R2

P1

R27

N27

L27

J27

G27

E27

R28

N28

L28

J28

G28

E28

T24

P25

M25

K25

H25

F25

T25

P26

M26

K26

H26

F26

B3

A2

C3

E5

D4

D5

C4

D3

C25
D25

AE27

AE28

AC27

AC28

AD24

AD25

AA27

AA28

AB25

AB26

W27

W28

Y25

Y26

U27

U28

V25

V26

U2100

SB

BGA

ICH7-M

OMIT

F14

F15

B10

F21

AH8

AG8

AE9

AD9

AH4

AG4

AD5

AE5

A13

E13

C17

C16

D7

B19

C26

E11

B5

C5

B4

A3

C9

B18

A9

E10

AH20

A7

G7

F8

F7

G8

D8

C8

A14

F13

D17

D16

E7

F16

A12

C15

D12

C12

B15

C14

A15

A17

E17

A18

E16

D6

E6

F18

B6

C7

A6

A8

B9

D9

E9

F10

F11

A10

A16

A11

D11

C11

E12

G13

G15

C13

B12

D14

E14

C18

E18

U2100

47

MF-LF

1/16W

5%

10K

402

2

1

R2200

402

MF-LF

1/16W

5%

10K

USB_C_OC_PU

2

1

R2250

10K

5%
1/16W
MF-LF
402

USB_E_OC_PU

2

1

R2251

USB_D_OC_PU

MF-LF

1/16W

5%

10K

402

2

1

R2255

MF-LF
402

1/16W

5%

10K

2

1

R2298

40

MF-LF

402

5%

10K

1/16W

2

1

R2205

402

10K

MF-LF

5%

1/16W

NOSTUFF

2

1

R2206

MF-LF
1/16W

10K

402

5%

2

1

R2207

VOLTAGE=0V

1/16W
MF-LF

5%

1K

402

2

1

R2211

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40 26

26

26

26

40 26

14

36

26

26

26

26

40 26

40 26

40 26

26

40 26

40 26

051-6941

104

22

12

PCI_PME_FW_L

=PP3V3_S0_SB

SPI_SI

SPI_CE_L

SB_GPIO30

PCI_REQ2_L

BOOT_LPC_SPI_L

PCI_C_BE_L<2>

SPI_SCLK

PCI_STOP_L

PCI_REQ3_L

PCI_REQ1_L

PCI_REQ0_L

PCI_AD<1>

PCI_AD<6>

USB_E_OC_L

SB_GPIO29

TP_SB_XOR_AE9
TP_SB_XOR_AG8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AH8

TP_SB_XOR_AE5

TP_SB_XOR_AD9

TP_SB_XOR_AH4

TP_SB_XOR_AG4

TP_SB_XOR_AD5

INT_PIRQD_L

USB_H_P

SPI_SO

SPI_ARB

USB_C_OC_L
USB_D_OC_L

USB_B_OC_L

USB_A_OC_L

USB_C_OC_L

=PP3V3_S5_SB_IO

PP1V5_S0_SB_VCC1_5_B

SB_GPIO31

PCIE_F_R2D_C_P

PCIE_F_R2D_C_N

PCIE_F_D2R_P

PCIE_F_D2R_N

PCIE_E_R2D_C_P

PCIE_E_R2D_C_N

PCIE_E_D2R_P

PCIE_E_D2R_N

PCIE_D_R2D_C_P

PCIE_D_R2D_C_N

PCIE_D_D2R_P

PCIE_D_D2R_N

PCIE_C_R2D_C_P

PCIE_C_R2D_C_N

PCIE_C_D2R_P

PCIE_C_D2R_N

PCIE_B_R2D_C_P

PCIE_B_R2D_C_N

PCIE_B_D2R_P

PCIE_B_D2R_N

PCIE_A_R2D_C_P

PCIE_A_R2D_C_N

PCIE_A_D2R_P

PCIE_A_D2R_N

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_N<1>
DMI_S2N_P<1>

DMI_N2S_N<2>
DMI_N2S_P<2>

SB_CLK100M_DMI_N

SB_GPIO29
SB_GPIO30

USB_E_N

USB_H_N

USB_G_P

USB_G_N

USB_F_P

USB_F_N

USB_E_P

USB_D_P

USB_D_N

USB_C_P

USB_C_N

USB_B_P

USB_B_N

USB_A_P

USB_A_N

DMI_N2S_P<3>
DMI_S2N_N<3>
DMI_S2N_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

USB_RBIAS_PN

SB_CLK100M_DMI_P

DMI_IRCOMP_R

INT_PIRQC_L

INT_PIRQB_L

INT_PIRQA_L

PCI_C_BE_L<3>

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

PCI_AD<25>

PCI_AD<24>

PCI_AD<23>

PCI_AD<22>

PCI_AD<21>

PCI_AD<20>

PCI_AD<19>

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_AD<0>

PCI_SERR_L

PCI_LOCK_L

PCI_PAR

PCI_CLK_SB

PCI_IRDY_L

PCI_FRAME_L

PCI_TRDY_L

PLT_RST_L

TP_PCI_PME_L

PCI_RST_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_C_BE_L<1>

PCI_C_BE_L<0>

SB_GPIO2
SB_GPIO3
SB_GPIO4
ODD_PWR_EN_L

TP_SB_RSVD9

NB_SB_SYNC_L

SB_GPIO31

USB_A_OC_L

USB_E_OC_L

USB_B_OC_L

USB_D_OC_L

=PP3V3_S5_SB_USB

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_GNT2_L

PCI_GNT3_L

TP_PCI_GNT4_L

63

22

22

22

22

22

22

22

25

22

22

22

22

25

6

6

22

6

6

6

6

6

63

24

22

22

6

22

6

6

6

63

IN

IN

IN

IN

OUT

OUT
OUT
OUT

OUT

IN

IN

BI
BI

OUT
OUT

OUT
IN

IN

BI

IN

IN

BI

IN

IN
IN

IN

OUT

BI

BI

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3*
SLP_S4*
SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25
GPIO35
GPIO38
GPIO39

SMBCLK
SMBDATA
LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR
SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ
THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

HI = PRESENT
LO = NOT PRESENT

SV_SET_UP IS LINDACARD DETECT

NOTE:

NOTE:
SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F
IN RESET STATE TO SAVE PWR

DEF=GPI

DEF=GPI

DEF=GPI

OD

(INT 20K PU)

NOTE FOR GPIO25:

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

LAYOUT NOTE:

(INT WEAK PD)

NOTE: RESERVED FOR FUTURE

NOT USED

NOTE FOR R2323 (DEF=NOSTUFF)
SB WILL DISABLE TCO TIMER

STRAPPING @ PWROK RISING:
SYSTEM REBOOT FEATURE

RESERVED FOR MOBILE
AZALIA DOCKING INT’F

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

47

47

47

79 57 14

62 47 41

62 47 39

48 47

6

34

34

27

27

33

33

56 49 48 47

5

47 26

5

14

56 49 47 40

5

45 37

5

47

56 49 47

5

26

47

47

26

23

100

21

R2302

100

21

R2303

100

21

R2305

36

36

48 47

23

47

NOSTUFF

402
5%

MF-LF

1/16W

10K

2

1

R2306

10K

402
5%

MF-LF

1/16W

2

1

R2307

402

1/16W
MF-LF

5%

10K

2

1

R2308

5%

MF-LF

1/16W

0

402

NOSTUFF

2

1

R2309

402
5%

MF-LF

1/16W

10K

2

1

R2310

1/16W
MF-LF

5%

NOSTUFF

402

10K

2

1

R2311

10K

1/16W
MF-LF

5%

402

2

1

R2313

402

NOSTUFF

0

1/16W
MF-LF

5%

2

1

R2314

33

402

10K

1/16W
MF-LF

5%

2

1

R2316

402

10K

1/16W
MF-LF

5%

2

1

R2317

10K

402

1/16W
MF-LF

5%

2

1

R2318

10K

1/16W
MF-LF

5%

402

2

1

R2319

402
5%

MF-LF

1/16W

10K

2

1

R2320

1/16W

5%

10K

SM-LF

5678

4321

RP2300

5%

402

MF-LF

1/16W

100K

21

R2399

1/16W
MF-LF

5%

402

1K

2

1

R2398

5%

MF-LF

1/16W

8.2K

402

2

1

R2397

MF-LF
5%

1/16W

10K

402

2

1

R2396

8.2K

1/16W
MF-LF

402
5%

2

1

R2395

OMIT

BGA

SB

ICH7-M

F20

AD22

C21

AF20

A22

C20

A27

A19

A25

B25

B22

C22

F22

D23

B24

AH21

Y4

A28

AA4

C23

A26

C19

E20

E21

AC18

AC21

AE20

AD20

AE19

AH19

AD21

U2

AC19

AG18

E23

B21

A21

D20

R3

AF19

AF21

AH18

AC20

AC22

E22

R4

E19

F19

B23

A20

AB18

B2

AC1

U2100

402

10K

5%
1/16W
MF-LF

2

1

R2390

402

1/16W
MF-LF

5%

10K

2

1

R2388

MF-LF

402
5%

1K

1/16W

NO_REBOOT_MODE

2

1

R2323

NOSTUFF

10K

1/16W
MF-LF
402
5%

2

1

R2326

NOSTUFF

5%

MF-LF

1/16W
402

10K

2

1

R2327

5%
402

8.2K

1/16W
MF-LF

2

1

R2343

47

SB: 3 OF 4

SYNC_DATE=11/16/2005

SYNC_MASTER=M38

051-6941

104

23

12

SMC_RUNTIME_SCI_L
SMC_EXTSMI_L

PM_THRM_L

SB_GPIO26

SMB_ALERT_L

PM_CLKRUN_L

PCIE_WAKE_L
INT_SERIRQ

=PP3V3_S5_SB

SMB_DATA

SB_SPKR

PM_BMBUSY_L

PM_STPCPU_L

FWH_MFG_MODE

TP_AZ_DOCK_RST_L

PM_STPPCI_L

PATA_PWR_EN_L

=PP3V3_S5_SB

SATA_C_PWR_EN_L

=PP3V3_S0_SB_GPIO

CRB_SV_DET

SMC_WAKE_SCI_L

SMS_INT_L

PATA_PWR_EN_L

SMC_SB_NMI

=PP3V3_S0_SB_GPIO

BIOS_REC

FWH_MFG_MODE

=PP3V3_S5_SB

CRB_SV_DET

TP_SB_GPIO38

TP_SB_GPIO6

IDE_RESET_L

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB

VR_PWRGD_CK410

TP_AZ_DOCK_EN_L

BIOS_REC

PM_SUS_STAT_L
PM_SYSRST_L

PM_RI_L

SMLINK<0>
SMLINK<1>

SMB_LINK_ALERT_L

SATA_C_PWR_EN_L

SB_CLK100M_SATA_OE_L

TP_SB_GPIO25_DO_NOT_USE

SV_SET_UP

PM_LAN_ENABLE

PM_PWRBTN_L

PM_DPRSLPVR

PM_BATLOW_L

PM_SB_PWROK

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

SUS_CLK_SB

SB_CLK14P3M_TIMER

SB_GPIO37

SB_CLK48M_USBCTLR

SB_GPIO21
SB_GPIO19

SATA_C_DET_L

SMB_CLK

PM_RSMRST_L

SV_SET_UP

63

63

63

63

63

63

63

63

49

49

25

25

23

23

25

25

26

25

23

23

23

23

23

23

23

21

23

21

23

23

23

23

23

11

23

23

5

5

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB CORE

VCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCCSUS3_3

VCC1_5_A

VCC1_5_A

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CODEC IC’S CONSIDERED SO FAR ARE 3.3V

DEPENDING ON VIO OF AZALIA INTERFACE

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V

NOTE:

VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE

CHANGE SYMBOL TO 1.05

CHANGE SYMBOL TO 1.05

S0 OR S3 IF NOT

S3 IF INTERNAL LAN IS USED

NOTE FOR VCCLAN_3_3:

0 0

OMIT

BGA

ICH7-M

SB

AE21

AE18

AE13

AE11

AE8

AE4

AE2

AD23

AD19

AD15

AD11

AD8

AD7

AD4

AD3

AD1

AC11

AC9

AC5

AC2

AB28

AB27

AB24

AB21

AB19

AB16

AB14

AB11

AB6

AB4

AA26

AA25

AA24

AA1

Y28

Y27

Y24

Y3

W26

W25

W24

W6

V28

V27

V24

V15

V13

V2

U26

U25

U24

U17

U16

U15

U14

U13

U12

U4

T17

T16

T15

T14

T13

T12

T6

R18

R17

R16

R15

R14

R13

R12

R11

R1

P28

P27

P24

P17

P16

P15

P14

P13

P12

P4

P3

N26

N25

N24

AH27

AH23

AH12

AH7

N18

AH3

AH1

AG25

AG20

AG17

AG14

AG11

AG7

AG3

AG1

N17

AF28

AF27

AF11

AF8

AF4

AF2

AE25

AE24

N16

N15

N14

N13

N12

N11

N6

N5

N2

N1

M28

M27

M24

M17

M16

M15

M14

M13

M12

M5

M4

M3

L26

L25

L24

L15

L13

K28

K27

K24

J26

J25

J24

J5

J2

J1

H28

H27

H24

H5

H4

H3

G26

G25

G24

G21

G18

G14

G9

G6

G5

G2

G1

F28

F27

F12

F5

F4

F3

E15

E8

E4

E2

E1

D24

D21

D18

D13

D10

C27

C6

C2

B28

B26

B20

B17

B14

B11

B8

B1

A23

A4

U2100

OMIT

BGA

SB

ICH7-M

C1

K6

K5

K4

K3

G19

D22

D19

C24

E3

N7

M7

M6

L7

L6

L3

L2

L1

A24

P7

R7

G20

C28

K7

AD2

W5

W7

W2

V1

V5

Y7

AA2

AG28

AG15

AG12

AD18

AD13

AC16

AB20

AB12

G16

AA7

G12

G11

F9

D15

C10

B7

B16

B13

A5

AG19

AH11

B27

U6

AD27

AD26

AC26

AC25

Y23

Y22

W23

AC24

W22

V23

V22

U23

U22

T28

T27

T26

T23

T22

AC23

R26

R25

R24

R23

R22

P23

P22

N23

N22

M23

AB23

M22

L23

L22

K23

K22

J23

J22

H23

H22

G23

AB22

G22

F24

F23

E26

E25

E24

D28

D27

D26

AD28

AA23

AA22

AB10

AH5

AG5

AF6

AF5

AE6

AD6

J7

J6

H7

H6

A1

AC8

AB8

G17

F17

T7

AC7

AC17

AB17

AH9

AG9

AF9

AF10

AE10

AD10

AC10

AB9

AC6

AB7

P11

M18

M11

L18

L17

L16

L14

V18

L12

V17

V16

V14

V12

V11

U18

U11

T18

T11

P18

L11

AH26

AE26

AE23

F6

AD17

G10

U2100

SB: 4 OF 4

SYNC_DATE=11/16/2005

SYNC_MASTER=M38

12

24

104

051-6941

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ARX

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3

=PP1V05_S0_SB_CPU_IO

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_VCCLAN3_3

=PPVCORE_S0_SB

PP5V_S5_SB_V5REF_SUS

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

63

26

63

63

63

63

63

63

63

25

25

63

63

25

63

25

63

63

25

25

63

63

25

25

25

25

24

21

25

25

24

25

24

25

25

25

24

21

25

25

25

25

22

NC NC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCDMIPLL BYPASS

PLACE C2520 NEAR PIN E3 OF SB

PLACEMENT NOTE:
PLACE C2503 < 2.54MM OF PIN AD17 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2504 < 2.54MM OF PIN F6 OF SB

PLACEMENT NOTE:

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

ICH V5REF_SUS BYPASS

(ICH SUSPEND 3.3V PWR)

ICH VCCSUS3_3 BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)

ICH VCC1_5_A/ARX BYPASS

ICH VCC3_3 BYPASS

PLACE C2509 NEAR PIN B27 OF SB

PLACEMENT NOTE:

ICH VCC3_3 BYPASS

(ICH RTC 3.3V PWR)

ICH VCCRTC BYPASS

V5, W2, OR W7

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

3.56MM ON PRIMARY NEAR PIN AD2

ICH VCC_PAUX/VCCLAN3_3 BYPASS
(ICH LAN I/F BUFFER 3.3V PWR)

PLACEMENT NOTE:
PLACE CAPS NEAR PINS
AB8 AND AC8 OF SB

ICH USB/VCCSUS3_3 BYPASS
(ICH SUSPEND USB 3.3V PWR)

PLACE CAPS NEAR PINS
K3 ... N7 OF SB

PLACE C2520 NEAR PIN C1 OF SB

NEAR PINS D28, T28, AD28

PLACEMENT NOTE:

ICH VCC1_5_A/ATX BYPASS

(ICH IO BUFFER 3.3V PWR)

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

ICH VCCSATAPLL BYPASS
(ICH SATA PLL 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH V_CPU_IO BYPASS
(ICH CPU I/O 1.05V PWR)

ICH IDE/VCC3_3 BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH PCI I/O 3.3V PWR)

A24 ... G19 AND P7 OF SB

DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS A5 ... G16

(ICH IO BUFFER 3.3V PWR)

3.56MM ON PRIMARY NEAR PIN AG9

3.56MM ON PRIMARY NEAR PIN AG5

PLACEMENT NOTE:

PLACEHOLDER
FOR 270UF

PLACE CAPS NEAR PINS

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE:

PLACEMENT NOTE:

SB: 4 OF 4

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH V5REF BYPASS

PLACEMENT NOTE:

ICH CORE/VCC1_05 BYPASS
(ICH CORE 1.05V PWR)

PLACEMENT NOTE:
PLACE CAP UNDER SB NEAR PINS V1,

3.56MM ON PRIMARY NEAR PIN U6

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

(ICH SUSPEND 3.3V PWR)

ICH VCCSUS3_3 BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

ICH VCC1_5A BYPASS
(ICH LOGIC&IO 1.5V PWR)

(ICH USB CORE 1.5V PWR)

3.56MM ON PRIMARY NEAR PINS A1 ... J7

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB CORE/VCC1_5_A BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AH11

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

(ICH IDE I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH DMI PLL 1.5V PWR)

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2500 & C2505-07 < 2.54MM OF SB

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

(ICH INTEL HDA CORE 3.3V PWR)

ICH VCC3_3/VCCHDA BYPASS

PLACE CAPS AT EDGE OF SB

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACE < 2.54MM OF SB ON

ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)

20%

220UF

POLY

2.5V
SMB2

2

1

C2500

X5R

16V

10%

0.1UF

402

2

1

C2510

0

402

0.1UF

10%
16V
X5R

2

1

C2512

0

1

5%

1/10W
MF-LF

603

21

R2500

4.7UF

20%

6.3V
CERM
603

2

1

C2524

0.1UF

10%
16V
X5R
402

2

1

C2522

BAT54DW

SOT-363

5

6

1

D2502

BAT54DW

SOT-363

2

3

4

D2502

1206

0.28-OHM

21

L2507

0.1UF

402

10%
16V
X5R

2

1

C2503

0

X5R

16V

10%

0.1UF

402

2

1

C2504

0

5%

MF-LF

1/16W

402

10

21

R2501

100-OHM-EMI

SM-3

21

L2500

0

0.1UF

10%
16V
X5R
402

2

1

C2505

X5R

16V

10%

0.1UF

402

2

1

C2506

0.1UF

16V

10%
X5R

402

2

1

C2507

0.01UF

10%
16V
CERM
402

2

1

C2501

603

10UF

20%

6.3V
X5R

2

1

C2508

0

10%
16V
X5R
402

0.1UF

2

1

C2509

0

X5R
402

16V

10%

0.1UF

2

1

C2511

0

0.1UF

402

X5R

16V

10%

2

1

C2517

0

0.1UF

10%
16V
X5R
402

2

1

C2513

0

0

402

6.3V
CERM

10%

1UF

2

1

C2514

0

0.1UF

10%
16V
X5R
402

2

1

C2520

402

X5R

16V

10%

0.1UF

2

1

C2515

0

0

CASE-C2

POLY

20%

2.5V

330UF

2

1

C2516

5%

1/16W

402

MF-LF

100

2

1

R2502

1UF

10%

6.3V
CERM
402

2

1

C2502

402

0.1UF

10%
16V
X5R

2

1

C2518

0

X5R

16V

10%

0.1UF

402

2

1

C2519

0

0.1UF

10%
16V

402

X5R

2

1

C2521

0

X5R

16V

10%

0.1UF

402

2

1

C2523

0

0.1UF

X5R

16V

10%
402

2

1

C2525

0

X5R

16V

10%

0.1UF

402

2

1

C2526

X5R

16V

10%

0.1UF

402

2

1

C2527

X5R

16V

10%

0.1UF

402

2

1

C2528

402

0.1UF

10%
16V
X5R

2

1

C2529

0

402

0.1UF

10%
16V
X5R

2

1

C2530

402

0.1UF

10%
16V
X5R

2

1

C2534

0

402

0.1UF

10%
16V
X5R

2

1

C2531

402

0.1UF

10%
16V
X5R

2

1

C2532

0

402

0.1UF

10%
16V
X5R

2

1

C2533

051-6941

104

25

12

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_B

=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ATX

=PPVCORE_S0_SB

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP1V05_S0_SB_CPU_IO

=PP1V5_S0_SB_VCCUSBPLL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

=PP3V3_S0_SB_VCC3_3_IDE

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S0_SB_VCCLAN3_3

PP3V3_S5_SB_RTC

=PP5V_S5_SB

=PP3V3_S0_SB

=PP3V3_S5_SB

=PP5V_S0_SB

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_SB_V5REF

VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

63

63

63

63

63

26

24

63

63

63

63

24

63

63

63

25

63

25

25

63

63

25

63

63

63

63

24

63

63

22

25

24

24

24

21

24

24

24

24

24

25

24

24

24

24

24

24

24

24

24

21

63

22

23

63

24

24

BI

BI

IN

IN

IN

IN

BI
BI

BI

BI
BI

BI
BI

OUT

OUT

IN

IN

OUT

IN

OUT

IN

SYM_1

NCNC

IN

OUT

OUT

BI
BI
BI
BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Unbuffered

518S0226

NC

NC

RTC Battery Connector

SB RTC Crystal Circuit

it provides a set of pads
on the board to short or
to solder a reset button.

1G00 used as small & cheap inverter

100-ohm on NB page

Linda Card represents 3 loads

Buffered

NC?
NC?

Silk: "SYS RST"

Is this the best part to use?

LIO represents X loads (2?)

This part is never stuffed,

NCNC

fault protection for RTC battery.

NOTE: R2607 and D2600 form the double-

Initial resistor values are based on CRB,
but may change after characterization.

Platform Reset Connections

22

40 22

22

22

22

40 22

22

22

22

MF-LF

5%

402

1/16W

20K

21

R2600

22

40 22

22

22

21

0.1UF

402

CERM

10V

20%

2

1

C2611

23

402

CERM

6.3V

10%

1UF

2

1

C2605

57 14

57

33

100K

MF-LF

402

5%

1/16W

OMIT

2

1

R2698

11

7

1M

402

MF-LF

1/16W

5%

2

1

R2606

47 23

5

MF-LF

10K

402

5%

1/16W

2

1

R2697

402

5%

MF-LF

1/16W

1K

12

R2607

50V

5%

402

CERM

12pF

21

C2608

12pF

CERM

402

5%

50V

21

C2609

32.768K

SM-2

CRITICAL

31

42

Y2600

0

402

MF-LF

1/16W

5%

21

R2610

10M

402

MF-LF

1/16W

5%

2

1

R2609

CERM

0.1UF

20%
10V

402

2

1

C2680

100K

5%
1/16W
MF-LF
402

2

1

R2680

402

0

MF-LF

1/16W

5%

21

R2681

100

402

MF-LF

1/16W

5%

21

R2683

0

1/16W

5%

MF-LF

402

21

R2684

0

402

MF-LF

1/16W

5%

21

R2685

0

5%
1/16W
MF-LF

402

21

R2687

0

402

MF-LF

1/16W

5%

21

R2682

22

CRITICAL

F-RT-SM

88460-0201

2

1

4

3

J2600

402

ITP

5%
1/16W
MF-LF

1K

21

R2696

MC74VHC1G00

SC70-5

5

4

1

2

3

U2603

MC74VHC1G08

SC70

5

4

1

2

3

U2680

SC70

MC74VHC1G08

5

4

1

2

3

U2601

BAT54DW

SOT-363

2

5

3

6

4

1

D2600

62 47

402

MF-LF

1/16W

5%

1.8K

2

1

R2611

0.1UF

402

CERM

10V

20%

2

1

C2607

23

402

MF-LF

1/16W

5%

10K

2

1

R2612

10K

5%
1/16W
MF-LF
402

2

1

R2622

8.2K

21

R2623

8.2K

21

R2624

8.2K

21

R2625

8.2K

21

R2626

8.2K

21

R2627

8.2K

21

R2628

8.2K

21

R2629

8.2K

21

R2630

8.2K

21

R2631

8.2K

21

R2632

8.2K

21

R2633

8.2K

21

R2634

8.2K

21

R2636

21

8.2K

21

R2637

8.2K

21

R2638

8.2K

21

R2639

8.2K

21

R2640

8.2K

21

R2641

8.2K

21

R2642

402

6.3V

10%
CERM

1UF

2

1

C2610

40 22

40 22

40 22

40 22

40 22

40 22

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

26

051-6941

12

104

SB Misc

PLT_RST_BUF_L

TPM_LRESET_L

ENET_RST_L

MAKE_BASE=TRUE

PLT_RST_L

MAKE_BASE=TRUE
VOLTAGE=3.3V

PP3V3_G3C_SB_RTC_D

SB_GPIO4

SB_GPIO2
SB_GPIO3

INT_PIRQD_L

INT_PIRQB_L
INT_PIRQC_L

PCI_REQ3_L
INT_PIRQA_L

PCI_REQ2_L

PCI_REQ1_L

PCI_REQ0_L

PCI_LOCK_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_SERR_L

PCI_STOP_L

PCI_TRDY_L

PCI_IRDY_L

PCI_FRAME_L

=PP3V3_S0_SB_PCI

PP3V3_S5_SB_RTC

=PP3V42_G3H_SB_RTC

VOLTAGE=3.3V

PPVBATT_G3C_RTC_R

=PP3V3_S0_SB_PM

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

PM_SB_PWROK

=PP3V3_S0_RSTBUF

VR_PWRGD_CK410_L

MAKE_BASE=TRUE

=PP3V3_S0_SB_PM

MAKE_BASE=TRUE

PM_SYSRST_L

XDP_DBRESET_L

SB_SM_INTRUDER_L

LIO_PLT_RESET_L

SB_RTC_X1

SB_RTC_X1_R

SB_RTC_X2

DEBUG_RST_L

SMC_LRESET_L

PEG_RESET_L

NB_RST_IN_L

=PP3V3_S5_SB_PM

VR_PWRGD_CK410

CK410_PD_VTT_PWRGD_L

SB_RTC_RST_L

PPVBATT_G3C_RTC

VOLTAGE=3.3V

25

63

24

63

63

45

49

23

56

37

63

21

63

26

63

26

5

21

21

5

47

65

14

11

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SO-DIMM "B"

(Write: 0xA0 Read: 0xA1)

SMC

SO-DIMM "A"

SMC

U2 - Keyboard Controller

U1 - Trackpad Controller

Trackpad I2C Connections:

M35 - TMP105

(Write: 0x70 Read: 0x71)

(Write: 0x72 Read: 0x73)

Left I/O SMBus Connections:

(Write: 0x92 Read: 0x93)

(Address determined by ARP)

ExpressCard Slot

Left I/O Board

(See Table)

SMC "0" SMBus Connections

(MASTER)

SMC "A" SMBus Connections

(MASTER)

U5800

SMC "Battery A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

SMC "Battery B" SMBus Connections

J8250

U5800

(MASTER)

Ambient Thermal

Right-Side Temp

ADT7461: U6150

GPU Temp

TMP105: J4930

U5800

J2800

Clock Chip

(Write: 0xD2 Read: 0xD3)

CY28445-5: U3301

U2100

(MASTER)

MAX6695: U6100

(Write: 0x98 Read: 0x99)

(Write: 0x30 Read: 0x31)

J4900

(Write: 0x90 Read: 0x91)

Left ALS - TSL2561

(Write: 0x92 Read: 0x93)

SMC

(Write: 0x90 Read: 0x91)

LIO - TMP105

(MASTER)

SMC

U5800

SMC "B" SMBus Connections

(See Table)

J5400

ADT7461: U1001

CPU Temp

(Write: 0x98 Read: 0x99)

(See Table)

Left Temp - TMP105

(Write: 0x52 Read: 0x53)

ICH7-M

Left I/O Board

Left I/O SMBus Connections:

J5500

(See Table)

(Write: 0xA4 Read: 0xA5)

J2900

Trackpad

J4900

(MASTER)

U5800

Battery

(Write: 0x90 Read: 0x91)

Right Temp - TMP105

Top-Case SMBus Connections:

Top-Case

ICH7-M SMBus Connections

(Write: 0x16 Read: 0x17)

MF-LF

402

1/16W

5%

4.7K

2

1

R2700

MF-LF
402

5%
1/16W

4.7K

2

1

R2701

1/16W

5%

402

MF-LF

4.7K

2

1

R2780

1/16W

5%

402

MF-LF

4.7K

2

1

R2781

100K

5%
1/16W

402

MF-LF

2

1

R2791

100K

1/16W

5%

402

MF-LF

2

1

R2790

402

MF-LF

1/16W

5%

4.7K

2

1

R2761

5%

1/16W

402

MF-LF

4.7K

2

1

R2760

1/16W
MF-LF
402

5%

4.7K

2

1

R2771

1/16W

402

MF-LF

5%

4.7K

2

1

R2770

402

MF-LF

1/16W

5%

4.7K

2

1

R2751

MF-LF

402

5%

1/16W

4.7K

2

1

R2750

M1 SMBus Connections

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

104

27

12

051-6941

=SMBUS_BATT_SDA

=I2C_TRACKPAD_SDA

=I2C_TRACKPAD_SCL

=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA

=SMBUS_LIO_SB_SCL
=SMBUS_LIO_SB_SDA

SMB_THRM_DATA

=SMBUS_LIO_SMC_SCL

=SMBUS_TOPCASE_SCL

SMB_THRM_CLK

=SMBUS_LIO_SMC_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

SMB_A_S3_DATA

SMB_A_S3_CLK

=SMBUS_TOPCASE_SDA

SMB_BSB_DATA

=SMBUS_GPUTHMSNS_SDA

SMB_CLK
SMB_DATA

=I2C_SODIMMA_SCL

SMB_CK410_DATA

SMB_CK410_CLK

=SMBUS_ATS_SDA

SMB_0_S0_DATA

SMB_0_S0_CLK

=SMBUS_GPUTHMSNS_SCL

=SMBUS_RSTHMSNS_SDA

=SMBUS_RSTHMSNS_SCL

SMB_BSB_CLK

SMB_BSA_DATA

SMB_BSA_CLK

=SMBUS_BATT_SCL

SMBUS_SMC_BSB_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_BSB_SCL

=PP3V3_S0_SMBUS_SMC_BSB

=I2C_SODIMMA_SDA

=SMBUS_ATS_SCL

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_B_S0

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

=PP3V42_G3H_SMBUS_SMC_BSA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUE

SMBUS_SB_SDA

MAKE_BASE=TRUE

SMBUS_SB_SCL

=PP3V3_S0_SMBUS_SB

64

45

45

45

45

43

64

43

5

43

43

29

29

5

5

10

5

43

10

5

47

47

47

47

43

47

50

23

23

28

33

33

5

47

47

50

50

50

47

47

5

63

28

5

63

63

63

63

63

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42
DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1
VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"Lower" (surface-mount) slot

by another page.

The reference voltage must be provided

NOTE: This page does not supply VREF.

Page Notes

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

NC

Power aliases required by this page:

(NONE)

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V8_S3_MEM

- =PPSPD_S0_MEM (2.5V - 3.3V)

516S0382

NC

NC

NC

NC

ADDR=0xA0(WR)/0xA1(RD)

(For return current)

DDR2 Bypass Caps

NC

0.1uF

CERM
402

20%
10V

2

1

C2813

0.1uF

CERM
402

20%
10V

2

1

C2812

10UF

X5R
603

20%

6.3V

2

1

C2809

0.1uF

CERM
402

20%
10V

2

1

C2811

10UF

X5R
603

20%

6.3V

2

1

C2808

0.1uF

CERM
402

20%
10V

2

1

C2810

0.1uF

CERM
402

20%
10V

2

1

C2819

0.1uF

CERM
402

20%
10V

2

1

C2818

0.1uF

CERM
402

20%
10V

2

1

C2817

0.1uF

CERM
402

20%
10V

2

1

C2816

0.1uF

CERM
402

20%
10V

2

1

C2821

0.1uF

CERM
402

20%
10V

2

1

C2820

0.1uF

CERM
402

20%
10V

2

1

C2815

0.1uF

CERM
402

20%
10V

2

1

C2814

0.1uF

CERM
402

20%
10V

2

1

C2800

DDR2-SODIMM-DUAL

F-RT-SM

CRITICAL

109A

24A

21A

18A

15A

12A

196A

193A

190A

187A

184A183A

178A177A

172A

9A

171A

168A

165A

162A161A

156A155A

150A149A

145A

144A

139A

138A

133A

132A

128A127A

122A121A

78A

8A

77A

72A71A

66A65A

60A59A

54A53A

3A

48A47A

42A41A

40A39A

34A33A

28A27A

2A1A

199A

112A111A

104A103A

96A95A

88A87A

82A

118A117A

81A

195A
197A

200A

198A

110A

108A

114A

163A

120A

83A

69A

50A

115A

119A

80A

84A
86A

116A

204

203

202

201

186A
188A

167A
169A

146A
148A

129A
131A

68A
70A

49A
51A

29A
31A

11A
13A

25A

23A

16A

14A

194A

192A

182A

180A

6A

191A

189A

181A

179A

176A

174A

160A

158A

175A

173A

4A

159A

157A

154A

152A

142A

140A

153A

151A

143A

141A

19A

136A

134A

126A

124A

137A

135A

125A

123A

76A

74A

17A

64A

62A

75A

73A

63A

61A

58A

56A

46A

44A

7A

57A

55A

45A

43A

38A

36A

22A

20A

37A

35A

5A

185A

170A

147A

130A

67A

52A

26A

10A

79A

166A

164A

32A

30A

113A

85A

106A

107A

91A
93A

92A
94A

97A 98A
99A

100A

101A

89A 90A

105A

102A

J2800

2.2uF

20%

603

CERM1

6.3V

2

1

C2801

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

DDR2 SO-DIMM Connector A

051-6941

12

104

28

MEM_VREF

MEM_A_DM<0>

MEM_CLK_P<1>

=PP1V8_S3_MEM

=PPSPD_S0_MEM

=PP1V8_S3_MEM

=PP1V8_S3_MEM

MEM_A_DQ<2>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQS_N<3>

MEM_A_DQ<23>

MEM_A_CAS_L
MEM_CS_L<1>

MEM_ODT<0>

MEM_A_RAS_L

MEM_A_A<0>

MEM_A_A<11>

MEM_A_DQ<31>

MEM_A_DQ<24>

MEM_A_DQ<29>

MEM_A_DQ<17>

MEM_A_DM<2>

MEM_A_DQ<22>

MEM_A_DQ<1>

MEM_A_BS<1>

MEM_CKE<1>

MEM_A_DQ<14>

MEM_A_DQ<11>

MEM_A_DQ<5>
MEM_A_DQ<4>

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MEM_A_DQ<6>

MEM_A_DQ<19>
MEM_A_DQ<18>

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MEM_A_DQ<20>
MEM_A_DQ<16>

MEM_A_DQ<25>

MEM_A_DM<3>

MEM_A_DQ<27>
MEM_A_DQ<30>

MEM_CKE<0>

MEM_A_BS<2>

MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>

MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>

MEM_A_A<10>
MEM_A_BS<0>
MEM_A_WE_L

MEM_A_DQ<7>

MEM_ODT<1>

MEM_A_DQ<35>
MEM_A_DQ<39>

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>

MEM_A_DQ<37>
MEM_A_DQ<33>

MEM_A_DM<7>

MEM_A_DQ<58>

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>

MEM_A_DQ<41>
MEM_A_DQ<46>

MEM_A_DQ<51>
MEM_A_DQ<50>

MEM_A_DM<6>

MEM_A_DQ<53>
MEM_A_DQ<48>

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

MEM_A_DQ<8>

MEM_CLK_P<0>
MEM_CLK_N<0>

MEM_A_DQ<0>

MEM_A_DQ<21>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<7>
MEM_A_A<6>

MEM_A_A<4>
MEM_A_A<2>

MEM_CS_L<0>

MEM_A_A<13>

MEM_A_DQ<38>
MEM_A_DQ<34>

MEM_A_DM<4>

MEM_A_DQ<32>
MEM_A_DQ<36>

MEM_A_DQ<40>
MEM_A_DQ<42>

MEM_CLK_N<1>

MEM_A_DM<5>

MEM_A_DQ<47>

MEM_A_DQ<54>

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

MEM_A_DQ<52>
MEM_A_DQ<49>

DIMM_OVERTEMP_L

MEM_A_DQ<44>

MEM_A_DQS_P<3>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<3>

MEM_A_DQ<9>

MEM_A_DQ<15>

MEM_A_DM<1>

MEM_A_DQ<10>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<59>

MEM_A_DQ<61>

MEM_A_DQ<43>
MEM_A_DQ<45>

MEM_A_DQ<55>

MEM_A_DQ<60>

MEM_A_DQ<57>

MEM_A_DQ<62>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQS_N<7>

MEM_A_DQ<56>

63

63

63

32

29

63

29

29

30

30

30

30

30

30

30

30 30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

48

29

15

14

28

29

28

28

15

15

15

15

15

15

14

14

15

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

27

27

15

14

14

15

15

6

6

15

15

15

15

14

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

29

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0*
DQS0
VSS6
DQ2
DQ3

DQ8
DQ9
VSS10
DQS1*
DQS1

DQ10
DQ11
VSS14

VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS21
DQ18
DQ19
VSS23
DQ24
DQ25
VSS25
DM3
NC1
VSS27
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
VDD10
NC/ODT1
VSS31
DQ32
DQ33
VSS33
DQS4*
DQS4
VSS36

DQ35
VSS38

DQ41
VSS40
DM5
VSS41

VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQS6*

VSS49
DQ50

VSS51
DQ56

VSS53
DM7
VSS55
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD

DM6

DQ55

DQ61

DQ46
DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14
DQ15

VSS15

VSS17

DQ20
DQ21

VSS19

NC0
DM2

VSS22

DQ22
DQ23

VSS24

DQ28

DQ29
VSS26
DQS3*

DQS3
VSS28

DQ30

DQ31
VSS30

NC/CKE1

VDD1

NC/A15
NC/A14

VDD3

A11

A7
A6

VDD5

A4
A2
A0

VDD7

BA1

RAS*

S0*
VDD9
ODT0

NC/A13

VDD11

NC3

VSS32

DQ36
DQ37

VSS34

DM4

VSS35

DQ38
DQ39

VSS37

DQ44
DQ45

VSS39
DQS5*

DQS5

VSS42

VSS44

DQ52
DQ53

VSS46

CK1
CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54
DQS7*

DQS7

VSS56

DQ62
DQ63

VSS58

SA0

SA1

DQ5
VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"Upper" (thru-hole) slot

516-0140

NOTE: This page does not supply VREF.
The reference voltage must be provided
by another page.

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

Page Notes

NC

Signal aliases required by this page:

(NONE)

Power aliases required by this page:

- =PP1V8_S3_MEM

- =PPSPD_S0_MEM (2.5V - 3.3V)

BOM options provided by this page:

NC

NC

NC

NC

NC

DDR2 Bypass Caps

(For return current)

Resistor prevents pwr-gnd short

ADDR=0xA4(WR)/0xA5(RD)

10V

0.1uF

CERM
402

20%

2

1

C2913

10V

0.1uF

CERM
402

20%

2

1

C2912

6.3V

20%
603

X5R

10UF

2

1

C2909

10V

0.1uF

CERM
402

20%

2

1

C2911

6.3V

20%
603

X5R

10UF

2

1

C2908

10V

0.1uF

CERM
402

20%

2

1

C2910

10V

0.1uF

CERM
402

20%

2

1

C2919

10V

0.1uF

CERM
402

20%

2

1

C2918

0.1uF

CERM
402

20%

10V

2

1

C2917

10V

0.1uF

CERM
402

20%

2

1

C2916

10V

0.1uF

CERM
402

20%

2

1

C2921

0.1uF

10V

CERM
402

20%

2

1

C2920

10V

0.1uF

CERM
402

20%

2

1

C2915

10V

0.1uF

CERM
402

20%

2

1

C2914

402

MF-LF

1/16W

5%

10K

2

1

R2900

CRITICAL

DDR2-SODIMM-DUAL

F-RT-TH1

109B

24B

21B

18B

15B

12B

196B

193B

190B

187B

184B183B

178B177B

172B

9B

171B

168B

165B

162B161B

156B155B

150B149B

145B

144B

139B

138B

133B

132B

128B127B

122B121B

78B

8B

77B

72B71B

66B65B

60B59B

54B53B

3B

48B47B

42B41B

40B39B

34B33B

28B27B

2B1B

199B

112B111B

104B103B

96B95B

88B87B

82B

118B117B

81B

195B
197B

200B

198B

110B

108B

114B

163B

120B

83B

69B

50B

115B

119B

80B

84B
86B

116B

202

201

186B
188B

167B
169B

146B
148B

129B
131B

68B
70B

49B
51B

29B
31B

11B
13B

25B

23B

16B

14B

194B

192B

182B

180B

6B

191B

189B

181B

179B

176B

174B

160B

158B

175B

173B

4B

159B

157B

154B

152B

142B

140B

153B

151B

143B

141B

19B

136B

134B

126B

124B

137B

135B

125B

123B

76B

74B

17B

64B

62B

75B

73B

63B

61B

58B

56B

46B

44B

7B

57B

55B

45B

43B

38B

36B

22B

20B

37B

35B

5B

185B

170B

147B

130B

67B

52B

26B

10B

79B

166B

164B

32B

30B

113B

85B

106B

107B

91B
93B

92B
94B

97B 98B
99B

100B

101B

89B 90B

105B

102B

J2900

0.1uF

CERM
402

20%
10V

2

1

C2900

2.2uF

20%

603

CERM1

6.3V

2

1

C2901

104

29

051-6941

12

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

DDR2 SO-DIMM Connector B

MEM_VREF

=PPSPD_S0_MEM

SODIMM_A_SA1

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DQ<48>
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

=PPSPD_S0_MEM

MEM_B_DQ<15>

MEM_B_DM<1>

MEM_B_DQ<14>

MEM_B_DQS_N<0>

MEM_B_DQ<21>

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

MEM_B_DQ<23>

MEM_B_DQ<29>
MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_CKE<2>

MEM_B_BS<2>

MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>

MEM_B_A<3>
MEM_B_A<1>

MEM_B_A<10>
MEM_B_BS<0>
MEM_B_WE_L

MEM_B_CAS_L
MEM_CS_L<3>

MEM_ODT<3>

MEM_B_DQ<36>
MEM_B_DQ<33>

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>

MEM_B_DQ<34>
MEM_B_DQ<35>

MEM_B_DQ<40>
MEM_B_DQ<41>

MEM_B_DM<5>

MEM_B_DQ<43>

MEM_B_DQ<54>
MEM_B_DQ<51>

MEM_B_DM<6>

MEM_B_DQ<52>
MEM_B_DQ<49>

MEM_B_DQ<42>

MEM_B_RAS_L

MEM_CS_L<2>

MEM_ODT<2>

MEM_B_A<13>

MEM_B_DQ<37>

MEM_B_DM<4>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQ<46>

MEM_CLK_N<2>

MEM_B_DQ<55>

MEM_B_DQ<32>

MEM_B_DQ<12>

MEM_B_DM<2>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<28>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_A<11>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_BS<1>

MEM_B_DQ<9>

MEM_B_DQ<11>

MEM_B_DQ<19>

MEM_B_DM<3>

MEM_B_A<14>

MEM_CKE<3>

MEM_B_A<5>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQ<61> MEM_B_DQ<57>

MEM_B_DQ<60> MEM_B_DQ<56>

MEM_B_DM<7>

MEM_CLK_P<2>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<58>
MEM_B_DQ<59>

MEM_B_DQ<8>

MEM_B_DQS_P<0>

DIMM_OVERTEMP_L

MEM_B_DQ<22>

MEM_B_DQ<18>

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DM<0>

MEM_CLK_P<3>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<5>

MEM_B_DQ<7>

MEM_B_DQ<26>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_A<15>

MEM_B_DQ<27>

=PP1V8_S3_MEM

MEM_B_DQ<20>

=PP1V8_S3_MEM

=PP1V8_S3_MEM

MEM_B_DQ<0>

MEM_CLK_N<3>

MEM_B_DQ<1>

63

63

63 63

63

32

29

29

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

48

29 29

29

28

28

15

15

15

27

27

28

15

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

14

14

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

14

14

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

6

14

15

15

15

15

15

15

15 15

15 15

15

14

15

15

15

15

15

15

28

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

6

15

28

15

28

28

15

14

15

IN

IN

IN
IN
IN

IN

IN

IN

IN

IN
IN
IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Ensure CS_L and ODT resistors are close to SO-DIMM connector

One cap for each side of every RPAK, one cap for every two discrete resistors

402

10V

20%
CERM

0.1uF

2

1

C3051

0.1uF

402

CERM

10V

20%

2

1

C3053

0.1uF

CERM

10V

20%

402

2

1

C3052

CERM

0.1uF

20%
10V

402

2

1

C3050

20%
10V
CERM
402

0.1uF

2

1

C3055

0.1uF

402

CERM

10V

20%

2

1

C3057

20%
10V
CERM
402

0.1uF

2

1

C3059

0.1uF

20%
CERM

402

10V

2

1

C3058

402

CERM

10V

20%

0.1uF

2

1

C3056

0.1uF

402

CERM

10V

20%

2

1

C3054

0

1

2

3

5

4

6

7

8

9

10

11

12

13

0

2

1

29 15

29 15

29 15

29 15

29 15

SM-LF

1/16W

5%

56

63

RP3058

56

SM-LF

1/16W

5%

54

RP3058

56

SM-LF

1/16W

5%

72

RP3032

5%

SM-LF

1/16W

56

81

RP3032

1/16W

SM-LF

5%

56

72

RP3052

56

5%

1/16W

SM-LF

81

RP3050

56

5%

1/16W

SM-LF

81

RP3054

1/16W

5%

SM-LF

56

81

RP3056

5%

1/16W

SM-LF

56

81

RP3005

SM-LF

1/16W

5%

56

54

RP3056

SM-LF

1/16W

5%

56

72

RP3058

SM-LF

1/16W

5%

56

81

RP3058

SM-LF

1/16W

5%

56

54

RP3054

SM-LF

1/16W

5%

56

63

RP3054

SM-LF

1/16W

5%

56

81

RP3052

SM-LF

1/16W

5%

56

72

RP3054

SM-LF

1/16W

5%

56

63

RP3052

SM-LF

1/16W

5%

56

54

RP3050

SM-LF

1/16W

5%

56

63

RP3050

SM-LF

1/16W

5%

56

72

RP3005

SM-LF

1/16W

5%

56

72

RP3050

SM-LF

1/16W

5%

56

63

RP3056

1/16W

5%

SM-LF

56

72

RP3056

SM-LF

1/16W

5%

56

54

RP3052

1/16W5%MF-LF

402

56

21

R3000

402

MF-LF

5%

1/16W

56

21

R3002

5%

MF-LF

402

1/16W

56

21

R3001

5%

MF-LF

402

1/16W

56

21

R3003

56

5%

1/16W

SM-LF

54

RP3005

56

SM-LF

1/16W

5%

54

RP3030

56

5%

1/16W

SM-LF

63

RP3030

56

SM-LF

1/16W

5%

81

RP3010

56

SM-LF

1/16W

5%

72

RP3010

5%

1/16W

SM-LF

56

72

RP3034

5%

1/16W

SM-LF

56

81

RP3030

5%

1/16W

SM-LF

56

63

RP3032

5%

1/16W

56

SM-LF

72

RP3030

5%

1/16W

56

SM-LF

63

RP3005

5%

1/16W

56

SM-LF

81

RP3034

5%

1/16W

SM-LF

56

54

RP3034

5%

1/16W

56

SM-LF

54

RP3032

SM-LF

5%

1/16W

56

81

RP3036

5%

1/16W

56

SM-LF

63

RP3034

5%

1/16W

56

SM-LF

63

RP3036

56

SM-LF

1/16W

5%

54

RP3036

56

SM-LF

1/16W

5%

72

RP3036

56

SM-LF

1/16W

5%

54

RP3010

56

5%

1/16W

SM-LF

63

RP3010

402

MF-LF

5%

1/16W

56

21

R3010

56

1/16W5%MF-LF

402

21

R3011

402

MF-LF

5%

1/16W

56

21

R3012

402

MF-LF1/16W

56

5%

21

R3013

0

1

0

1

1

0

2

0

1

2

3

4

5

6

7

10

11

9

8

13

12

29 28 14

29 28 14

28 15

28 15

28 15

28 15

28 15

2

3

2

3

20%
10V
CERM
402

0.1uF

2

1

C3039

0.1uF

20%
CERM

402

10V

2

1

C3038

20%
10V
CERM
402

0.1uF

2

1

C3033

402

20%
10V
CERM

0.1uF

2

1

C3032

402

CERM

10V

20%

0.1uF

2

1

C3031

CERM

0.1uF

20%
10V

402

2

1

C3030

0.1uF

10V

20%

402

CERM

2

1

C3011

0.1uF

402

20%
10V
CERM

2

1

C3010

20%
CERM

402

0.1uF

10V

2

1

C3007

0.1uF

402

CERM

10V

20%

2

1

C3005

20%
10V
CERM
402

0.1uF

2

1

C3002

402

CERM

10V

20%

0.1uF

2

1

C3000

0.1uF

402

CERM

10V

20%

2

1

C3037

402

CERM

10V

20%

0.1uF

2

1

C3036

20%
10V
CERM
402

0.1uF

2

1

C3035

0.1uF

402

CERM

10V

20%

2

1

C3034

0

1

2

3

29 28 14

30

104

12

051-6941

Memory Active Termination

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MEM_B_A<13..0>

MEM_B_BS<2..0>

MEM_CS_L<3..0>

MEM_CKE<3..0>

MEM_A_BS<2..0>

MEM_A_A<13..0>

MEM_ODT<3..0>

MEM_B_WE_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_B_CAS_L

MEM_B_RAS_L

=PP0V9_S0_MEM_TERM

63

VREF

VTT

GND

VTT_IN

EN

VTTS

VDDQ

VCC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(NONE)

(NONE)

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

- =PP5V_S0_MEMVTT

- =PP1V8_S0_MEMVTT

- =PP0V9_S0_MEMVTT_LDO

Page Notes

Okay to turn off 5V and
leave 1.8V powered in S3.

DDR2 Vtt Regulator

If power inputs are not S0,
MEMVTT_EN can be used to
disable MEMVTT in sleep.

6.3V

20%
X5R

603

10uF

2

1

C3101

CRITICAL

MSOP-8

BD3533FVM

3

7

8

4

5 6

1

2

U3100

MEMVTT_EN_PU

1K

402

MF-LF

1/16W

5%

2

1

R3100

6.3V
SMC-LF

POLY

20%

150UF

C3105

603

X5R

20%

10uF

6.3V

2

1

C3102

CERM1

20%

6.3V

2.2uF

603

2

1

C3104

220

5%
1/16W
MF-LF

402

2 1

R3104

10%
16V
X5R

0.1uF

402

2

1

C3103

6.3V

10%

1uF

CERM
402

2

1

C3100

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Memory Vtt Supply

051-6941

12

104

31

=PP1V8_S0_MEMVTT

MEMVTT_EN

MEMVTT_VREF

=PP5V_S0_MEMVTT

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP1V8_S0_MEMVTT_VDDQ

=PP0V9_S0_MEMVTT_LDO

63

63

63

V+

V-

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL

MAX4236EUTT

SOT23-6-LF

2

6

5

1

4

3

U3200

62

20%

0.1UF

402

10V

CERM

2

1

C3200

CERM

402

220pF

25V

5%

2

1

C3205

10K

1/16W

1%

402

MF-LF

2

1

R3206

10K

MF-LF

402

1%

1/16W

2

1

R3205

100K

MEMVREF_S3

MF-LF

402

5%

1/16W

2

1

R3202

5%
1/16W
MF-LF

402

0

MEMVREF_S0

2 1

R3203

32

104

12

051-6941

DDR2 VRef

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MEMVREF_SHDN_L

=PP3V3_S3_MEMVREF

=MEMVREF_EN

MEM_VREF
MEM_VREF_NB_0
MEM_VREF_NB_1

MEMVREF_UNBUF

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V

=PP1V8_S3_MEMVREF

MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0.9V

MIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

MEMVREF_OUT

29

63

28

14

14

63

VTT_PWRGD*/PD

DOT96T/27MHZ_NON-SPREAD

SRCT_0/LCD100MT

CPUC2_ITP/SRCC_10

VDD48

XIN

VDD_PCI1

VDD_SRC0

VDD_REF

VDD_SRC1

VDD_SRC2

VDD_SRC3

REF1/FCTSEL0

REF0/FSC

FSA/48M

DOT96C/27MHZ_SPREAD

CLKREQ_8*

SRCT_8

SRCC_8

SRCT_7

SRCC_7

CLKREQ_6*

CPUT2_ITP/SRCT_10

IREF

SDATA

SCLK

VSS_REF

VSS_PCI1

VSS_PCI0

VSS_CPU

VSS48

VSS_SRC

PCIF1

PCI1

SRCT_5

THRML_PAD

PCI4

PCI2

FSB

CLKREQ_4*

SRCC_5

SRCC_4
SRCT_4

SRCT_3

CLKREQ_3*

SRCC_3

SRCC_2
SRCT_2

SRCC_1

CLKREQ_1*

SRCT_1

SRCC_0/LCD100MC

CPUC1
CPUT1

CPUC0
CPUT0

PCI_STP*
CPU_STP*

SRCC_6

CLKREQ_5*

SRCT_6

PCIF0/ITP_SEL

PCI5/FCTSEL1

PCI3

XOUT

VDDA
VSSA

VDD_PCI0

VDD_CPU

IN
IN

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT
OUT
OUT
OUT

IN

BI

OUT

IN

BI

BI

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT
OUT

OUT
OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(FW PCI 33MHZ)

(FOR PCI-E CARD)

NEED TO CHECK CAP VALUE

(ICH7M USB 48MHZ)

(FROM CPU VCORE PWR GOOD)

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

(GIGA LAN PCI-E 100 MHZ )

(WIRELESS PCI-E 100 MHZ )

(FROM GMCH CLK_REQ*)

(FROM ICH7 GPIO35)

(ICH7M DMI 100 MHZ )

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?

(GPU PCI-E 100 MHZ )

(INT PU)

(INT PU)

(EACH POWER PIN PLACED ONE 0.1UF)
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

(SMC LPC 33MHZ)

(TPM LPC 33MHZ)

(ICH SATA 100 MHZ)

(INT PU)

FCTSEL0

SRCC0
SRCC0
SRCC0

SRCT0

100MT_SSTDOT96C

TBD

SPREAD

27M

SPREAD

27M NON

OFF LOW

11

1

10

0 0

FCTSEL1

100MC_SST

PIN 11PIN 10

PIN 7
DOT96T
DOT96T DOT96C

SRCT0
SRCT0

* FOR INT. GRAPHIC SYSTEM

* FOR EXT. GRAPHIC SYSTEM

PIN 6

(INT PU)

(INT PU)

(INT PD)

(INT PU)

(INT PD)

(NOT USED )

(CPU HOST 133/167MHZ)

(INT PU)

(SIGNAL NAME WILL BE CHANGED POST

PROTO TO REMOVE 100M FROM SIGNAL NAME)

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

(ITP HOST 133/167MHZ)

(GMCH HOST 133/167MHZ)

(FROM ICH7 GPIO20 STPCPU* )

(FROM ICH7 GPIO18 STPPCI* )

(GMCH G_CLKIN 100 MHZ )

(INT PD)

(ICH7M,SIO,LPC REF. 14.318MHZ)

(INT PU)

0

(PORT80 LPC 33MHZ)

(ICH7M PCI 33MHZ)

(ICH SM BUS)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(NO USED)

603

NOSTUFF

X5R

10UF

20%

6.3V

2

1

C3309

FERR-120-OHM-1.5A

0402

21

L3302

0.1UF

10%
X5R

16V
402

2

1

C3305

16V
X5R
402

10%

0.1UF

2

1

C3306

16V
X5R

0.1UF

10%
402

2

1

C3307

0.1UF

10%
402

16V
X5R

2

1

C3308

CY284455

CRITICAL

QFN

OMIT

50

51

2

39

31

52

66

62

46

5

38

35

28

17

12

49

67

61

43

3

69

33

29

26

23

21

18

15

13

10

32

30

27

24

22

19

16

14

11

48

47

53

54

1

68

56

65

64

63

58

57

40

8

4

6

7

37

42

45

36

41

44

55

34

25

60

20

59

9

U3301

23

23

34

34

34

34

34

34

34

34

34

34

34

34

34

34

34

34

50V
402

CERM

5%

18pF

2

1

C3390

50V

5%
CERM

402

18pF

2

1

C3389

34

27

MF-LF

1%

475

402

1/16W

2

1

R3300

20%

10UF

6.3V
X5R
603

2

1

C3312

16V

0.1UF

402

X5R

10%

2

1

C3311

34

34

34

34

402

10%
16V
X5R

0.1UF

2

1

C3304

X5R

16V
402

0.1UF

10%

2

1

C3303

0.1UF

10%
16V
X5R
402

2

1

C3302

402

X5R

16V

0.1UF

10%

2

1

C3301

1UF

6.3V
CERM

10%
402

2

1

C3310

10UF

603

6.3V

20%
X5R

2

1

C3316

10%
X5R

16V
402

0.1UF

2

1

C3315

FERR-120-OHM-1.5A

0402

21

L3301

1UF

10%
CERM

6.3V
402

2

1

C3314

402

MF-LF

1/16W

5%

2.2

21

R3302

402

1/16W

5%

MF-LF

1

21

R3303

603

6.3V

20%

10UF

X5R

2

1

C3317

MF-LF

402

2.2

5%

1/16W

21

R3304

34

34

34

34

34

34

10K

5%
MF-LF

402

1/16W

2

1

R3301

34

34

34

34

34

34

34

CRITICAL

5X3.2-SM

14.31818

21

Y3301

12

051-6941

33

104

SYNC_DATE=10/12/2005

CLOCKS

SYNC_MASTER=M42

CK410_PCIF0_CLK

CK410_PCI1_CLK

CK410_FSB_TEST_MODE

CK410_SRC1_N

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK410_VDD48

VOLTAGE=3.3V

=PP3V3_S0_CK410

CK410_SRC2_P
CK410_SRC3_N

CK410_PCI3_CLK

CK410_SRC6_P

CK410_SRC6_N

CK410_SRC7_N
CK410_SRC7_P

CK410_SRC8_N

=PP3V3_S0_CK410

CK410_SRC4_N
CK410_SRC4_P

CK410_SRC5_N

SB_CLK100M_SATA_OE_L

CK410_SRC_CLKREQ3_L

SMB_CK410_CLK

CK410_CPU2_ITP_SRC10_N

CK410_LVDS_N
CK410_LVDS_P

CK410_CPU1_N

CK410_SRC3_P

CK410_SRC2_N

CK410_SRC_CLKREQ1_L

CK410_PCI2_CLK

CK410_REF1_FCTSEL0

CK410_CLK14P3M_TIMER

=PP3V3_S0_CK410

CK410_CPU0_P

CK410_SRC_CLKREQ6_L

CLK_NB_OE_L

CK410_SRC5_P

SMB_CK410_DATA

CK410_IREF

CK410_PCIF1_CLK

CK410_PCI5_FCTSEL1

PP3V3_S0_CK410_VDD_CPU_SRC

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK410_VDD_REF

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

PP3V3_S0_CK410_VDD_PCI

CK410_CPU1_P

PM_STPPCI_L
PM_STPCPU_L

CK410_CPU0_N

CK410_CPU2_ITP_SRC10_P

CK410_USB48_FSA

CK410_PD_VTT_PWRGD_L

CK410_DOT96_27M_P

CK410_DOT96_27M_N

CK410_SRC_CLKREQ8_L

CK410_SRC8_P

CK410_PCI4_CLK

PP3V3_S0_CK410_VDDA

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

CK410_SRC1_P

CK410_XTAL_IN
CK410_XTAL_OUT

63

63

63

34

34

34

33

33

33

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

OUTOUT

OUT

BI

BI

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED

Yukon CLK OE*

(Yukon PCI-E 100MHZ)

(GPU 27MHz Spread / Non-Spread)

(GPU PCI-E Graphics 100MHz)

(TO MCH FS_B)

(FROM CPU FS_B)

(FROM CPU FS_C)

0

FS_B

166M

CPUFS_C
0
0 0

0

0

0 0
0

0

1

1 1
1
1 1
1 1
1 1 1

100M
333M

0
0

1#

#

400M

133M
200M

266M

FS_A

(CPU HOST 133/167MHZ)

(GMCH HOST 133/167MHZ)

(GMCH G_CLKIN 100MHZ)

(ICH7M DMI 100MHZ)

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY

(ICH7M 14.318MHZ)

(TO MCH FS_C)

RESERVED

(FROM CPU FS_A)

(ICH7M SATA 100MHZ)

(PORT80 LPC 33MHZ)
(TO ICH7M PCI 33MHZ)

(TO ICH7M USB 48MHZ)

NEED TO CHECK THE BSEL PULLS

(TO MCH FS_A)

(WIRELESS PCI-E MINI 100MHZ)

GPU CLK OE*

(ITP HOST 133/167MHZ)

(TO SMC PCI 33MHZ)

(TO TPM PCI 33MHZ)

(TO FIREWIRE PCI 33MHZ)

(ExpressCard Slot)

49.9

MF-LF

402

1%

1/16W

ITP

21

R3441

402

1/16W

1%

MF-LF

71.5

21

R3402

33

33

33

33

MF-LF

1%

402

1/16W

121

21

R3418

1%

402

MF-LF

1/16W

121

21

R3419

33

33

33

33

69 34

69 34

402

MF-LF

1/16W

5%

33

21

R3422

33

5%
1/16W
MF-LF

402

21

R3423

34 14

34 14

33

33

33

MF-LF

402

5%

1/16W

21

R3465

MF-LF

402

1/16W

33

5%

21

R3426

33

33 37 34

37 34

34 22

33

MF-LF

5%

1/16W

402

21

R3428

5%

1/16W

33

MF-LF

402

21

R3427

33

33

1/16W

5%

402

33

MF-LF

21

R3429

33

MF-LF

402

5%

1/16W

21

R3430

1/16W

5%

402

MF-LF

33

21

R3433

MF-LF

5%

402

1/16W

33

21

R3432

33

33

33

33

40

56

47

22

45 34

5

45 34

5

5%
MF-LF

402

1/16W

33

21

R3435

5%

402

MF-LF

1/16W

33

21

R3434

33

49.9

MF-LF

402

1%

1/16W

21

R3408

33

49.9

MF-LF

402

1%

1/16W

21

R3436

49.9

MF-LF

402

1%

1/16W

21

R3437

49

5

1/16W

5%

MF-LF

33

402

21

R3463

33

34 22

10K

MF-LF
402

5%
1/16W

2

1

R3467

10K

MF-LF
402

5%
1/16W

2

1

R3466

49.9

MF-LF

402

1%

1/16W

21

R3431

1/16W

5%

402

MF-LF

1K

2

1

R3469

1/16W

5%

402

MF-LF

1K

21

R3468

1/16W

5%

402

MF-LF

1K

21

R3472

1/16W

5%

402

MF-LF

1K

2

1

R3470

1/16W

5%

402

MF-LF

1K

21

R3471

33

1/16W

5%

402

MF-LF

1K

2

1

R3473

1/16W

5%

402

MF-LF

1K

21

R3475

1/16W

5%

402

MF-LF

1K

21

R3474

33

33

23

49.9

MF-LF

402

1%

1/16W

21

R3406

34 21

5

34 21

5

33

MF-LF

402

5%

1/16W

21

R3478

MF-LF

402

5%

1/16W

33

21

R3477

33

1/16W

1%

402

MF-LF

49.9

21

R3439

33

1/16W

5%

402

MF-LF

1K

NOSTUFF

2

1

R3480

1/16W

1%

402

MF-LF

49.9

21

R3481

1/16W

1%

402

MF-LF

49.9

21

R3482

1/16W

5%

402

MF-LF

33

21

R3476

1/16W

5%

402

MF-LF

0

21

R3450

7

7

1/16W

5%

402

MF-LF

0

21

R3453

1/16W

5%

402

MF-LF

1K

NOSTUFF

2

1

R3454

49.9

MF-LF

402

1%

1/16W

21

R3407

7

1/16W

5%

402

MF-LF

0

21

R3451

1/16W

5%

402

1K

NOSTUFF

MF-LF

2

1

R3452

45 34

5

45 34

5

1/16W
MF-LF

5%

402

33

21

R3499

5%

402

1/16W

33

MF-LF

21

R3498

33

34 12

33

49.9

MF-LF

402

1%

1/16W

21

R3495

49.9

MF-LF

402

1%

1/16W

21

R3496

33

33

MF-LF

402

1/16W

33

5%

21

R3493

5%

33

402

1/16W
MF-LF

21

R3494

65 34

65 34

49.9

MF-LF

1%

1/16W

402

21

R3490

34 12

49.9

MF-LF

402

1%

1/16W

21

R3491

33

33

33

34

7

5%

1K

1/16W

402

MF-LF

21

R3486

5%

1K

MF-LF

1/16W

402

21

R3485

34

7

79 34 11

79 34 11

402

33

MF-LF

1/16W

5%

21

R3411

49.9

MF-LF

402

1%

1/16W

ITP

21

R3440

33

MF-LF

402

5%

1/16W

21

R3413

402

MF-LF

1/16W

5%

33

ITP

21

R3415

1/16W

1%

402

MF-LF

49.9

21

R3438

49.9

MF-LF

402

1%

1/16W

21

R3404

49.9

MF-LF

402

1%

1/16W

21

R3442

33

402

5%
1/16W
MF-LF

21

R3412

1/16W

5%

402

MF-LF

33

21

R3414

49.9

MF-LF

402

1%

1/16W

21

R3403

1/16W

1%

402

MF-LF

71.5

21

R3405

1/16W

1%

402

MF-LF

49.9

21

R3400

1/16W

402

MF-LF

5%

33

ITP

21

R3416

1/16W

5%

402

MF-LF

33

21

R3417

1/16W

5%

402

MF-LF

2.2K

21

R3401

33

33

33

Clock Termination

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

34

104

12

051-6941

CK410_DOT96_27M_P

CK410_DOT96_27M_N
CK410_27M_SPREAD

MAKE_BASE=TRUE

CK410_27M_NONSPREAD

MAKE_BASE=TRUE

CK410_SRC3_P

MAKE_BASE=TRUE

TP_CK410_SRC7N

PCI_CLK_PORT80_LPC

CK410_SRC6_P

CK410_CPU2_ITP_SRC10_N

CK410_SRC_CLKREQ3_L

CK410_SRC2_P

SB_CLK100M_DMI_N

PCIE_CLK100M_MINI_P

CK410_SRC5_P

CK410_SRC6_N

NB_CLK100M_GCLKIN_P

ENET_CLK100M_PCIE_P

PEG_CLK100M_GPU_P

CK410_SRC7_P

=PP3V3_S0_CK410

=PP1V05_S0_FSB_NB

CK410_PCI5_FCTSEL1

SB_CLK14P3M_TIMER

CK410_REF1_FCTSEL0

CPU_BSEL_R<2>

MAKE_BASE=TRUE

TP_CK410_LVDSN

CK410_SRC1_P

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_P

CK410_SRC4_P

CK410_SRC8_P

CK410_SRC8_N

SB_CLK100M_DMI_P

SB_CLK100M_SATA_N

CPU_BSEL<2>

ENET_CLK100M_PCIE_N

CK410_SRC3_N

CPU_BSEL<1>

NB_BSEL<1>

CPU_BSEL_R<1>

CK410_CLK14P3M_TIMER

CPU_BSEL<0>

CPU_BSEL_R<0>

NB_BSEL<2>

CK410_USB48_FSA

CK410_FSB_TEST_MODE

NB_BSEL<0>

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

FSB_CLK_CPU_P

CK410_CPU0_P

FSB_CLK_CPU_N

CK410_CPU0_N

CK410_CPU1_P FSB_CLK_NB_P

FSB_CLK_NB_N

CK410_CPU2_ITP_SRC10_P

CPU_XDP_CLK_N

PCIE_CLK100M_MINI_N

NB_CLK100M_GCLKIN_N

SB_CLK100M_DMI_N

SB_CLK100M_DMI_P

CPU_XDP_CLK_N

CPU_XDP_CLK_P

FSB_CLK_NB_P

FSB_CLK_NB_N

FSB_CLK_CPU_P

FSB_CLK_CPU_N

ENET_CLK100M_PCIE_P

ENET_CLK100M_PCIE_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_N

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

PCIE_CLK100M_EXCARD_N

PEG_CLK100M_GPU_N

CK410_SRC1_N

MAKE_BASE=TRUE

TP_CK410_LVDSP

CK410_LVDS_P

MAKE_BASE=TRUE

TP_CK410_SRC7P

MAKE_BASE=TRUE

TP_CK410_PCI4_CLK

CK410_PCI4_CLK

PCI_CLK_SB

CK410_PCIF0_CLK

CK410_PCI1_CLK

PCI_CLK_FW

CK410_PCI2_CLK

PCI_CLK_TPM

CK410_PCI3_CLK

SB_CLK48M_USBCTLR

PEG_CLK100M_GPU_N

PEG_CLK100M_GPU_P

CK410_LVDS_N

CK410_SRC_CLKREQ8_L

CK410_SRC_CLKREQ1_L

CK410_SRC7_N

MINI_CLKREQ_L

MAKE_BASE=TRUE

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

CK410_SRC_CLKREQ6_L

CK410_SRC5_N

PCI_CLK_SMC

CK410_PCIF1_CLK

CK410_SRC4_N

CK410_SRC2_N

CK410_CPU1_N

CPU_XDP_CLK_P

SB_CLK100M_SATA_P

GPU_CLK27MSS_IN

GPU_CLK27MGPU_CLK27M

GPU_CLK27MSS_IN

63

63

63

34

45

45

34

34

79

79

45

45

34

34

63

19

34

34

19

19

34

34

34

34

34

34

34

34

37

37

34

34

34

34

21

21

65

65

45

45

69

69

33

33

12

5

5

12

12

22

22

11

11

12

12

7

7

34

34

5

5

14

14

5

5

34

34

33

33

5

5

33

34

34

NC7

NC6

NC5

NC4

NC2
NC3

OUT

VDD

NC0
NC1

VIO

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Is this the best part to use?

NC

NC

NC

NC

NC

NC

NC

NC

NC?

NC?

TPM Crystal Circuit

SMC G3Hot Oscillator

CRITICAL

32.768K

SM-2

31

42

Y3720

MF-LF

1/16W

0

402

5%

21

R3721

10M

NO STUFF

MF-LF

402

5%

1/16W

2

1

R3720

32.768KHZ-9-3.6V

CRITICAL

SG-3040LC-SM

1

12

7

11

10

9

8

5

4

3

2

6

U3750

0.1uF

20%

402

CERM

10V

2

1

C3751

FERR-EMI-100-OHM

SM

21

L3750

6.3V
603

CERM

20%

4.7uF

2

1

C3750

402

22

MF-LF

1/16W

5%

21

R3750

15pF

50V

CERM

402

5%

21

C3720

15pF

CERM

402

5%

50V

21

C3721

37

104

12

051-6941

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

Mobile Clocking

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP3V42_G3H_SMC_CLK_F

VOLTAGE=3.425V

TPM_XTALO_R

TPM_XTALI

TPM_XTALO

=PP3V42_G3H_SMC_CLK

MAKE_BASE=TRUE

SMC_SUS_CLK

SMC_CLK32K_SUSCLK_R

SMC_CLK32K_SUSCLK

56

56

63

47

IN

BI

BI

BI

BI

BI

IN

BI

BI

BI

IN

IN

IN
IN

OUT

G

D

S

IN

BI
BI
BI
BI

BI
BI
BI
BI

IN

OUT

OUT

IN

OUT
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ODD to keep SB GPIO <= 3.3V

Counters 10K pull-up to 5V in

(UATA_CS0*)

(UATA_HSTROBE)
(UATA_DSTROBE)

NC

(UATA_CS1*)

from ball of SB

Place within 12.7mm

Placement note

(UATA_STOP)

IDE (ODD) Connector

516S0335

Indicates disk presence

21

21

21

21

21

21

23

1/16W

100

402

MF-LF

5%

2

1

R3850

M-ST-SM1-LF

CRITICAL

9

8

7

6

50

5

49
48
47
46
45
44
43
42
41
40

4

39
38
37
36
35
34
33
32
31
30

3

29
28
27
2625

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3800

1%

24.9

1/16W
MF-LF
402

2

1

R3860

21

21

21

21

21

21

21

1/16W

402

MF-LF

NO STUFF

4.7K

5%

2

1

R3801

402

4.7K

MF-LF

5%

1/16W

2

1

R3802

6.2K

MF-LF
402

5%
1/16W

2

1

R3803

47

33K

MF-LF
402

5%
1/16W

2

1

R3810

BGA

CRITICAL

FDZ293P

B3
B2
B1
A3
A2

A1

C3
C2
C1

Q3820

1/16W

5%

402

MF-LF

10K

2

1

R3820

22

21

21

21

21

21

21

21

21

21

21

21

21 21

21

0.22uF

402

X5R

6.3V

20%

21

C3821

10K

MF-LF

402

5%

1/16W

2

1

R3821

1/16W
MF-LF

402

5%

15K

2

1

R3811

SYNC_MASTER=(MASTER)

104

38

12

051-6941

PATA Connector

SYNC_DATE=(MASTER)

=PP3V3_S0_IDE

IDE_PDIOW_L

SMC_ODD_DETECT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=5V

PP5V_S0_IDE_ODD

IDE_PDDREQ
IDE_PDIOR_L
IDE_PDIORDY

IDE_PDD<3>

IDE_IRQ14

ODD_PWR_EN_L_RC

IDE_PDD<0>

=PP5V_S0_IDE

IDE_PDD<13>

ODD_PWR_EN_L

SATA_RBIAS

MAKE_BASE=TRUE

TP_SATA_A_R2DN

MAKE_BASE=TRUE

TP_SATA_A_D2RN

MAKE_BASE=TRUE

SATA_A_D2R_N

TP_SATA_A_D2RP

MAKE_BASE=TRUE

SATA_A_D2R_P

TP_SATA_A_R2DP

MAKE_BASE=TRUE

SATA_A_R2D_C_P

SATA_C_DET_L

SATA_A_R2D_C_N

IDE_PDD<4>

IDE_PDCS3_L

IDE_PDA<1>

IDE_PDDACK_L

IDE_PDD<15>

IDE_PDD<14>

IDE_PDD<11>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<8>

IDE_PDD<1>

IDE_PDD<2>

IDE_PDD<5>

IDE_PDD<6>

IDE_PDD<7>

IDE_PDA<0>

IDE_PDCS1_L

IDE_PDA<2>

SATA_RBIAS_P
SATA_RBIAS_N

IDE_PDD<12>

IDE_RESET_L

63

63

21

21

21

23

21

21

21

OUT
OUT

AVDDL0

AVDDL4

AVDD

THRML_PAD

VDDO_TTL0

AVDDL6

VDDO_TTL1

RX_N

TESTMODE

TSTPT

LINK*

LED_LINK10/100*
LED_LINK1000*

LED_ACT*

RSET

CTRL25
CTRL12

HSDACN

HSDACP

SWITCH_VAUX

SWITCH_VCC

VMAIN_AVLBL

VAUX_AVLBL

LOM_DISABLE*

XTALO

XTALI

SPI_DO

SPI_CLK

SPI_CS

SPI_DI

VPD_CLK

VPD_DATA

MDIP3
MDIN3

MDIN2

MDIP2

MDIN1

MDIP1

MDIN0

MDIP0

WAKE*

REFCLKN

TX_N

VDDO_TTL3

VDDO_TTL2

VDDO_TTL4

VDD0

VDD1

VDD3

VDD2

VDD6

VDD5

VDD4

VDD7

AVDDL1

AVDDL2

AVDDL5

VDD25

PERST*

REFCLKP

RX_P

AVDDL3

TX_P

PU_VDDO_TTL0
PU_VDDO_TTL1

TEST

TEST

TWSI

SPI

MAIN CLK

PCI EXPRESS

ANALOG

MEDIA

LED

E2

WC*

NC0

NC1

VCC

VSS

SCL

SDA

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

IN
IN

IN

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TRACE LENGTH <12MIL

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101

NO PULL-UP NEEDED

PLACE C4113 AND C4112 WITHIN

PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

SCHEME MATCHES DOC MVL100258-01

PLACE C4110 AND C4111 WITHIN
12 MIL OF U4101 PIN 49 AND 50

PLACE C4107 NEAR U4101 AVDD

PLACE C4140 NEAR U4102 VCC

SCHEME MATCHES DOC MVL100258-01

PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

SCHEME MATCHES DOC MVL100258-01

NC

NC

2. DO NOT ROUTE UNDER CRYSTAL

NC

NC
NC

NC

NC

NC

NC

1. KEEP ENET_XTALI AND ENET_XTALO

ASF IS UNAVAILABLE ON 8053

PLACE RESISTORS CLOSE TO U4101

OPTIONAL EXTERNAL LDO

NC
NC

INTERNAL PULL-UP

NC

12 MIL OF U2100 E27 AND E28

27pF

50V
CERM

5%

402

2

1

C4151

5%

4.7K

1/16W

MF-LF

402

21

R4122

4.7K

MF-LF

5%

402

1/16W

21

R4123

6

6

402

16V
X5R

10%

0.1UF

2

1

C4101

CRITICAL

OMIT

QFN

88E8053

14

15

6

41

38

47

614540

8

1

58484439336413

7

2

12

49
50

29

65

46

11

9

34

35

36

37

54
53

16

55
56

43

42

5

30

26

20

17

31

27

21

18

10

63

62

60

59

24
25

4
3

57525132282219

23

U4101

16V

10%

0.1UF

402

X5R

2

1

C4140

SO8

CRITICAL

M24C08

OMIT

7

4

8

5

6

2
1

3

U4102

22

1/16W

1%

4.87K

MF-LF

402

21

R4102

22

0.1UF

X5R
402

10%
16V

2

1

C4107

38

38

38

38

38

38

38

38

402

10%
16V
X5R

0.1UF

21

C4110

16V

10%

0.1UF

402

X5R

21

C4111

10%

0.1UF

402

16V

X5R

21

C4112

402
X5R
16V
10%

0.1UF

21

C4113

402

MF-LF

1%

49.9

1/16W

2

1

R4106

402

1%
1/16W
MF-LF

49.9

2

1

R4117

402

MF-LF

1/16W

49.9

1%

2

1

R4118

1%

49.9

1/16W
MF-LF
402

2

1

R4119

402

1/16W

1%
MF-LF

49.9

2

1

R4120

MF-LF

49.9

402

1%
1/16W

2

1

R4103

402

MF-LF

1/16W

1%

49.9

2

1

R4104

402

MF-LF

1/16W

1%

49.9

2

1

R4105

50V

10%

402

CERM

0.001UF

2

1

C4116

402

10%

0.001UF

50V
CERM

2

1

C4118

0.001UF

CERM

10%

402

50V

2

1

C4117

402

50V

10%
CERM

0.001UF

2

1

C4115

402

CERM

6.3V

10%

1UF

2

1

C4100

FERR-120-OHM-1.5A

0402

21

L4100

4.7K

5%
1/16W
MF-LF
402

2

1

R4131

402

MF-LF

1/16W

5%

4.7K

2

1

R4130

4.7K

1/16W

402

5%

MF-LF

21

R4101

0.001UF

CERM

10%
50V

402

2

1

C4105

X5R

10%

0.1UF

402

16V

2

1

C4104

402

0.1UF

X5R

10%
16V

2

1

C4103

10%

0.1UF

X5R
402

16V

2

1

C4102

0.001UF

402

CERM

50V

10%

2

1

C4106

402

16V

0.1UF

X5R

10%

2

1

C4128

0.001UF

10%
402

50V
CERM

2

1

C4133

50V
402

CERM

0.001UF

10%

2

1

C4134

402

CERM

0.001UF

10%
50V

2

1

C4131

10%

0.001UF

CERM
402

50V

2

1

C4132

16V

10%
X5R

402

0.1UF

2

1

C4127

10%
X5R

402

16V

0.1UF

2

1

C4126

16V
402

X5R

0.1UF

10%

2

1

C4129

16V

10%
402

X5R

0.1UF

2

1

C4130

402

CERM

10%
50V

0.001UF

2

1

C4139

0.001UF

50V
CERM
402

10%

2

1

C4138

16V

0.1UF

X5R
402

10%

2

1

C4137

402

10%
X5R

0.1UF

16V

2

1

C4136

402

X5R

0.1UF

10%
16V

2

1

C4135

34

34

26

45
23

5

25.0000M

SM-3.2X2.5MM

CRITICAL

3 1

4 2

Y4101

22

22

27pF

402

CERM

50V

5%

2

1

C4150

12

051-6941

104

SYNC_MASTER=M42

SYNC_DATE=10/12/2005

ETHERNET CONTROLLER

41

ENET_XTALO

ENET_XTALI

=PP1V2_S3_ENET

ENET_MDI_P<2>
ENET_MDI_N<2>

ENET_MDI_P<3>
ENET_MDI_N<3>

ENET_MDI_P<1>

PCIE_A_R2D_N

=PP3V3_S3_ENET

ENET_MDI_P<0>

PP2V5_S3_ENET_AVDD

MIN_NECK_WIDTH=0.22MM

MIN_LINE_WIDTH=0.4MM

VOLTAGE=2.5V

ENET_VPD_DATA

ENET_PU_VDD_TTL0

=ENET_VMAIN_AVLBL

ENET_MDI_N<0>

ENET_VPD_CLK

ENET_VPD_DATA

=PP3V3_S3_ENET

ENET_RST_L

ENET_CLK100M_PCIE_N

ENET_CLK100M_PCIE_P

ENET_PU_VDD_TTL1

PCIE_A_D2R_C_P

=PP2V5_S3_ENET

PCIE_WAKE_L

ENET_PU_VDD_TTL1

=PP3V3_S3_ENET

ENET_RSET

ENET_LOM_DIS_L

PCIE_A_R2D_P

ENET_PU_VDD_TTL0

ENET_MDI1

PCIE_A_R2D_C_N

ENET_MDI0

PCIE_A_R2D_C_P

ENET_MDI3

=PP3V3_S3_ENET

PCIE_A_D2R_C_N

PCIE_A_D2R_N

PCIE_A_D2R_P

=PP3V3_S3_ENET

ENET_VPD_CLK

ENET_CTRL25
ENET_CTRL12

=PP1V2_S3_ENET

ENET_MDI_N<1>

ENET_MDI2

63

63

63

63

63

63 63

37 37

38

37

37

62

37

37

37

37

63

37

37

6

37

37

37

37

37

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BOM options provided by this page:

Place close to connector

514-0277

Short shielded RJ-45

PHYSICAL

PROVIDED

ELECTRICAL_CONSTRAINT_SET

Place one cap at each pin of transformer

NET_TYPE

SPACING

Page Notes

Power aliases required by this page:

(NONE)

Signal aliases required by this page:

(NONE)

- =PP2V5_ENET

BY

ETHERNET

PHY

Transformers should be
sides of the board

- =GND_CHASSIS_ENET

mirrored on opposite

1/16W

NO STUFF

5%

MF-LF

0

402

21

R4210

1uF

6.3V

10%
CERM

402

2

1

C4203

1uF

6.3V

10%
CERM

402

2

1

C4202

100pF

CERM
1808

10%
3KV

1 2

C4204

1/16W

5%

402

MF-LF

75

2

1

R4203

1/16W

5%

402

MF-LF

75

2

1

R4202

1/16W

5%

402

MF-LF

75

2

1

R4201

1/16W

5%

402

MF-LF

75

2

1

R4200

6.3V
402

1uF

10%
CERM

2

1

C4201

1uF

CERM

6.3V

10%

402

2

1

C4200

XFR-SM

CRITICAL

1000BT-824-00275

13
125

4

98

7

6

3

2

16

15

14

11

10

1

T4200

XFR-SM

1000BT-824-00275

CRITICAL

13
125

4

98

7

6

3

2

16

15

14

11

10

1

T4201

37

37

37

37

37

37

37

37

37

6

CRITICAL

JM36113-P2054-7F

F-RT-TH-RJ45

8

7

6

5

4

3

2

1

12

11

10

9

J4200

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Ethernet Connector

104

051-6941

42

12

ENETCONN_P<3>

ENET_100D

ENETCONN

ENETCONN_P<2>

ENET_MDI_P<0>

ENET_MDI_P<3>

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

ENET_CTAP_COMMON

ENET_MDI_N<3>

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_MDI_P<1>

ENET_MDI_N<0>

ENET_100D

ENETCONN

ENETCONN_N<2>

ENET_100D

ENETCONN

ENETCONN_P<3>

ENET_100D

ENETCONN

ENETCONN_P<0>

ENET_100D

ENETCONN

ENETCONN_N<0>

ENET_100D

ENETCONN

ENETCONN_N<1>

ENET_100D

ENETCONN

ENETCONN_N<3>

ENET_100D

ENETCONN

ENETCONN_P<1>

ENET_CTAP1

ENET_CTAP3

ENET_CTAP2

ENETCONN_N<3>

ENETCONN_N<1>

ENETCONN_N<2>

ENETCONN_P<2>

ENETCONN_N<0>

=GND_CHASSIS_ENET

ENET_MDI_N<1>

PP2V5_S3_ENET_AVDD

ENETCONN_P<0>

ENETCONN_P<1>

ENET_CTAP0

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

G

D

S

N-CHN

S

D

G

P-CHN

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)

Allows powering Yukon down during battery sleep to save power

1.2V enable has pull-up to 3.3V

When ENETPWR_S3 BOMOPTION is active:

When ENETPWR_S3AC BOMOPTION is active:

State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS

State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS

S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 3.3V (2.5V OFF) 0V (1.2V OFF)
S5 AC 0V 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
S5 Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
G3H Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

S0 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S5 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
G3H 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

Yukon Power Control

5%
1/16W
MF-LF
402

470K

2

1

R4302

2N7002DW-X-F

SOT-363

4

5

3

Q4304

MF-LF

100K

1/16W

5%

402

2

1

R4304

0

ENETPWR_S3AC

402

MF-LF

1/16W

5%

21

R4300

0

402

MF-LF

1/16W

5%

ENETPWR_S3

2

1

R4301

SC70-6

FDG6332C_NL

1

2

6

Q4300

FDG6332C_NL

SC70-6

4

5

3

Q4300

2N7002

SOT23-LF

2

1

3

Q4302

SOT-363

2N7002DW-X-F

1

2

6

Q4304

402

5%
1/16W
MF-LF

100K

2

1

R4305

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Yukon Power Control

051-6941

12

104

43

P1V2S3_RUNSS

PM_SLP_S3BATT

FWPWR_EN_L_OR_GND

PM_SLP_S4_L

=PP3V3_S3AC_FET

=PP3V3_S3_P3V3S3AC

PPVIN_S3_P2V5S3_SVIN

PM_SLP_S3BATT_L

=P2V5S3_EN_L

MAKE_BASE=TRUE

P2V5S3_EN_L

=PPBUS_G3H_S3AC

FWPWR_EN_L

62

59

47 5 23

63 63

59

59

63

41

BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI

BI
BI
BI

BI

BI

BI

BI
BI

BI

BI
BI

BI

BI

BI

BI
BI

BI
BI
BI

BI

BI

BI

BI

BI

BI
BI
BI
BI
BI
BI

BI
BI

BI

OUT
IN

IN

OUT
OUT

BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI

MPCI_ACTN_323

TPB0_P

TPBIAS0

PCI_AD12

RESET*

TPBIAS2

PCI_RST*
PCI_INTA*
PCI_PME*

PCI_AD21

PCI_AD31

XO

XI

R1

R0

TPA0_N

TPA0_P

TPB0_N

TPBIAS1

TPA1_P

TPB1_P

TPA1_N

TPA2_P
TPA2_N
TPB2_P
TPB2_N

MODE_A

MODE_420

TEST0
TEST1
PTEST

SE
SM

VSS21

VSS22

VSS20

VSS18

VSS19

VSS16

VSS15

VSS17

VSS13

VSS14

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VSS0

VSSA0

VSSA1

VSSA3

VSSA4

VSSA2

VDDA4

VDDA5

VDDA3

VDDA2

VDDA1

VDDA0

VDD0

VDD2

VDD1

VDD3

VDD4

VDD7

VDD9

PCI_VIOS

PCI_AD0

PCI_AD2

PCI_AD4
PCI_AD5

PCI_AD3

PCI_AD6

PCI_AD9
PCI_AD10

PCI_AD8

PCI_AD11

PCI_AD14
PCI_AD15

PCI_AD13

PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20

PCI_AD23

PCI_AD22

PCI_AD25

PCI_AD28

PCI_AD26

PCI_AD29
PCI_AD30

PCI_CBE2*

PCI_CBE1*

PCI_CBE0*

PCI_CBE3*

PCI_PAR
PCI_FRAME*
PCI_IRDY*
PCI_TRDY*
PCI_DEVSEL*
PCI_STOP*
PCI_IDSEL

PCI_REQ*
PCI_GNT*
PCI_PERR*
PCI_SERR*

PCI_CLK
CLKRUN*

VDD5

PCI_AD27

PCI_AD24

VDD6

PCI_AD1

TPB1_N

PC0

PC2

CONTENDER

CARDBUSN

PCI_AD7

PC1

BI

BI

BI

BI
BI

BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NEED TO CHECK CRYSTAL LOAD CAPACITANCE

6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L

6/20/2005 - BGA VERSION OF FW323-06 ADDED

PAGE HISTORY

6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE

FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS

INPUT

PAGE NOTES

6/22/2005 - CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT

OUTPUT

6/22/2005 - REMOVED C4421 - REDUNDANT

FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS

INPUT/OUTPUT

PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE

PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL

PCI_REQ3_L - PCI REQUEST TO SB

PCI_RST_L - PCI RESET FROM SB
FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER

PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)

INT_PIRQD_L - INTERRUPT TO SB

6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE

6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)

6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)

PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,
PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L
FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS

6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)

5/19/2005 - FIRST REVISION OF PAGE

7/26/2005 - CONNECTED PIN E10 TO GND

=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)
=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)
PCI_GNT3_L - PCI GRANT FROM SB

DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)
SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)

PLACE ONE CAP PER TWO PINS STARTING WITH C4424 ON VDD0

PLACE ONE CAP PER TWO PINS STARTING WITH C4416 ON VDDA0

0.001A DURING SLEEP

MODE FOR EXTERNAL LINK

LOW = PCI OPERATION

LOW = NOT BUS MANAGER

MANUFACTURING TEST PINS

CONNECT TO VDD FOR 3.3V OPERATION

THIS IS FROM ICH-7M

SPEC RECOMMENDS 2.49K

197S0178 3.2MMX2.5MM

6.3V

20%

603

X5R

10UF

2

1

C4416

1/16W

1%

402

MF-LF

2.49K

2

1

R4452

10V

20%

402

CERM

0.1UF

2

1

C4428

10V

20%

402

CERM

0.1UF

2

1

C4426

10V

20%

402

CERM

0.1UF

2

1

C4422

10V

20%

402

CERM

0.1UF

2

1

C4418

16V

10%

402

X5R

0.1UF

2

1

C4429

16V

10%

402

X5R

0.1UF

2

1

C4425

16V

10%

402

X5R

0.1UF

2

1

C4417

16V

10%
402

X5R

0.1UF

2

1

C4420

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

26 22

26 22

26 22

26 22

26 22

26 22

26 22

56

49 47 23

5

26 22

22

34

26 22

22

1/16W

5%

402

MF-LF

390

21

R4400

42

42

42

42

22

6.3V

20%

603

X5R

10UF

2

1

C4424

0402

600-OHM-300MA

21

L4400

42

42

42

42

42

42

CRITICAL

OMIT

BGA

FW32306

B5

A5

D5D7D9

E9

E13

F8F7F6

F4E5E4

D4

N13

K9

K8

C3

J10

J9J5H8

H7

H6G8G7G6G1

B2

A1

D6A8A7

B13

A13

D10

A2

H13

L13

K7K6K5N2N1

G4

C13

D8

B8

D13
D12

B12
A12

B10
A10

C11
C12

A11
B11

A9
B9

C1

C2

B3

A3

B4

A6

B7

A4

G13

N7

M7

N9

F1

E2

F2

M8

N10

M6

D2

L2

E1

N6

N8

G2

L1

L3

M9

K12

M13

L12

K10

K13

J12

J13

H1

H4

H12

H2

J1

J2

K1

J4

K2

M1

K4

N3

M2

H10

M3

N4

N5

M4

N11

M10

N12

M11

M12

L11

G10

F10

F12

F13

E12

E10

B6

M5

G12

D1

B1

U4400

1/16W

5%

402

MF-LF

510K

2

1

R4420

42

42

42

42

42

1/16W

5%

402

MF-LF

100

21

R4432

SM

21

XW4400

1/16W

5%

402

MF-LF

22

2

1

R4431

24.576MHZ

CRITICAL

SM-3.2X2.5MM

31

42

Y4403

CERM

50V
402

5%

22pF

2

1

C4411

5%

402

CERM

50V

22pF

2

1

C4412

10V

20%

402

CERM

0.1UF

2

1

C4430

10V

20%

402

CERM

0.1UF

2

1

C4432

SYNC_MASTER=(M42)

SYNC_DATE=08/29/2005

FIREWIRE CONTROLLER

051-6941

12

104

44

FW_XO

FW_XI

FW_A_TPA_P

FW_A_TPB_P

PCI_IRDY_L

VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

GND_FW_VSSA

GND_FW_VSSA

PCI_RST_L

FW_PCI_RST_L
INT_PIRQD_L

PCI_CLK_FW
PM_CLKRUN_L

PCI_PERR_L
PCI_SERR_L

PCI_GNT3_L

PCI_REQ3_L

PCI_STOP_L

PCI_DEVSEL_L

PCI_TRDY_L

PCI_FRAME_L

PCI_C_BE_L<3>

PCI_PAR

PCI_C_BE_L<1>

PCI_C_BE_L<0>

PCI_AD<31>

PCI_AD<28>
PCI_AD<29>
PCI_AD<30>

PCI_AD<26>
PCI_AD<27>

PCI_AD<25>

PCI_AD<23>
PCI_AD<24>

PCI_AD<22>

PCI_AD<21>

PCI_AD<20>

PCI_AD<18>

PCI_AD<15>

PCI_AD<17>

PCI_AD<16>

PCI_AD<13>
PCI_AD<14>

PCI_AD<10>
PCI_AD<11>
PCI_AD<12>

PCI_AD<8>
PCI_AD<9>

PCI_AD<6>
PCI_AD<7>

PCI_AD<5>

PCI_AD<3>
PCI_AD<4>

PCI_AD<2>

PCI_AD<1>

PCI_AD<0>

FW_PC0

FW_C_TPB_N

FW_C_TPB_P

FW_C_TPA_P
FW_C_TPA_N

FW_C_TPBIAS

FW_B_TPB_N

FW_B_TPB_P

FW_B_TPA_P
FW_B_TPA_N

FW_B_TPBIAS

FW_A_TPB_N

FW_A_TPBIAS

FW_A_TPA_N

FW_PCI_IDSEL

PCI_AD<19>

=PP3V3_S3_FW

PP3V3_S3_FW_AVDD

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=3.3V

FW_PWRON_RST_L

=PP3V3_S3_PCI

FW_R1

FW_R0

FW_XO_R

PCI_C_BE_L<2>

PCI_PME_FW_L

40

40

63

63

OUT

GND

OUT

VIN+ VIN-

V+

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

is running or on AC.

Enables port power when machine

Port Power Switch

- =PPBUS_S0_FWPWRSW (system supply for bus power)

50V/V

1A = 1V

- =PP3V3_S0_FWPORTPWRSW

BOM options provided by this page:
(NONE)

Power aliases required by this page:

Signal aliases required by this page:

- =FWPWR_PWRON (see related text note below)

Page Notes

FireWire Port Current Sense

402

MF-LF

330K

5%
1/16W

2

1

R4566

16V

20%
402

0.01uF

CERM

2

1

C4565

1/16W

5%

402

470K

MF-LF

2

1

R4565

CRITICAL

SMB

B340XF

21

D4565

NDS9407

CRITICAL

SOI-LF

3
2
1

4

8
7
6
5

Q4565

1uF

CERM

402

10%

6.3V
2

1

C4595

51

SOT23-5

INA194

CRITICAL

43

5 1

2

U4595

0.5%
1W

0612

MF

0.02

21

R4570

2N7002DW-X-F

SOT-363

4

5

3

Q4560

SOT-363

2N7002DW-X-F

1

2

6

Q4560

MINISMDC

1.1A-24V

CRITICAL

21

F4565

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

FireWire Port Power

12

051-6941

45

104

FWPWR_IOUT

=PP3V3_S0_FWISENS

=PPBUS_S5_FW_FET

VOLTAGE=12.6V

PPBUS_S5_FW_FET_D_R

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPBUS_S5_FW_FET_D

PPBUS_S5_FWPWRSW_F

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PM_SLP_S3_L

SMC_ADAPTER_EN

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

FWPWR_EN_L_DIV

=PPBUS_S5_FWPWRSW

FWPWR_EN_L

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

48

62

47

47

45

63

63

23

5

63

39

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"Snapback" & "Late VG" Protection

(TPB-)

- =PPFW_PORT1

NOTE: FireWire TPA/TPB pairs are NOT

514-0255

the necessary aliases to map the

(TPB+)

(TPA+)
(TPA-)

(PPFW_PORT1_VP)

1394b implementation based on Apple

Signal aliases required by this page:

FireWire TPA/TPB pairs to their

BOM options provided by this page:

(NONE)

(NONE)

FireWire Design Guide (FWDG 0.6, 5/14/03)

appropriate connectors and/or to

NOTE: This page is expected to contain

BY

PAGE

PHY

SPACING

NET_TYPE

PHYSICAL

properly terminate unused signals.

PROVIDED

ELECTRICAL_CONSTRAINT_SET

- =PP3V3_S5_FWLATEVG

- =GND_CHASSIS_FW_PORT1

Power aliases required by this page:

Page Notes

provide the appropriate constraints

Termination

Cable Power

Single-port system sets PC=0

(GND_FW_PORT1_VG)

to apply to entire TPA/TPB XNets.

FW Power Class Strap

Place close to FireWire PHY

assumed that FireWire PHY page will

2nd TPA/TPB pair unused

Late-VG Protection Power

3rd TPA/TPB pair unused

constrained on this page. It is

1394A

PORT 1

SM-1

400-OHM-EMI

21

L4690

330

5%

1/16W

402

MF-LF

21

R4690

SM

FERR-250-OHM

21

L4620

402

50V

20%
CERM

0.001uF

2

1

C4624

SOT-363

BAV99DW-X-F

3

5

4

DP4620

0.001uF

CERM

402

50V

20%

2

1

C4621

603

50V

20%
CERM

0.01uF

2

1

C4625

20%

CERM

0.01uF

16V
402

2

1

C4626

SOT-363

BAV99DW-X-F

3

5

4

DP4621

0.001uF

CERM

20%
50V

402

2

1

C4623

BAV99DW-X-F

SOT-363

6

2

1

DP4620

0.001uF

402

20%

CERM

50V

2

1

C4620

BAV99DW-X-F

SOT-363

6

2

1

DP4621

CERM

402

20%
50V

0.001uF

2

1

C4622

6.3V

10%
402

0.33uF

CERM-X5R

2

1

C4650

1/16W

56.2

MF-LF

402

1%

2

1

R4651

56.2

MF-LF
402

1%
1/16W

2

1

R4650

56.2

MF-LF

402

1%

1/16W

2

1

R4653

MF-LF
402

1%
1/16W

56.2

2

1

R4652

MF-LF

1%

1/16W

4.99K

402

2

1

R4654

CERM
402

5%
25V

220pF

2

1

C4654

F-RT-TH-LF

1394A

CRITICAL

1

2

5

6

3

4

10987

J4620

CRITICAL

SM1

260-OHM-330MA

3

21

4

FL4620

CRITICAL

SM1

260-OHM-330MA

3

21

4

FL4621

0.001uF

CERM

402

10%
50V

2

1

C4692

CRITICAL

MMBZ5227B

SOT23

3

1

D4690

10V

0.1uF

CERM

402

20%

2

1

C4691

1/16W

5%

402

MF-LF

0

21

R4699

051-6941

12

46

104

FireWire Ports

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PP3V3_S5_FWLATEVG_R_F

FW_PORT1_TPB_P

FW_PORT1_TPB_N

FW_PORT1_TPB_FL_N

FW_PORT1_TPB_FL_P

FW_PORT1_TPA_N

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPFW_PORT1_VP

=PPFW_PORT1

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_S5_FWLATEVG_R_F

FW_TPA0_C

=GND_CHASSIS_FW_PORT1

MAKE_BASE=TRUE

NC_FW_B_TPBIAS

NO_TEST=YES

FW_PORT1_TPA_FL_N

FW

FW_110D

FW_A_TPBIAS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_S5_FWLATEVG_R

=PP3V3_S5_FWLATEVG

FW_PC0

FW_C_TPB_N

FW_C_TPB_P

NO_TEST=YES

MAKE_BASE=TRUE

NC_FW_C_TPAP

FW_A_TPA_P
FW_A_TPA_N

FW_PORT1_TPB_N

MAKE_BASE=TRUE

FW_PORT1_TPB_FL_N

FW

FW_110D

FW_C_TPA_P

FW_B_TPB_N

FW_PORT1_TPA_FL_P

FW

FW_110D

FW_PORT1_TPB_FL_P

FW_110D

FW

FW_PORT1_TPA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_PORT1_TPA_P

FW_B_TPA_P

FW_B_TPBIAS

FW_B_TPA_N FW_C_TPA_N

=GND_CHASSIS_FW_EMI

MAKE_BASE=TRUE

FW_PORT1_TPB_P

NC_FW_B_TPAN

NO_TEST=YES

MAKE_BASE=TRUE

NO_TEST=YES

MAKE_BASE=TRUE

NC_FW_B_TPBP

NC_FW_B_TPBN

NO_TEST=YES

MAKE_BASE=TRUE

NC_FW_C_TPBN

NO_TEST=YES

MAKE_BASE=TRUE

NC_FW_C_TPBP

NO_TEST=YES

MAKE_BASE=TRUE

FW_B_TPB_P

NC_FW_B_TPAP

MAKE_BASE=TRUE
NO_TEST=YES

NC_FW_C_TPAN

NO_TEST=YES

MAKE_BASE=TRUE

MAKE_BASE=TRUE
NO_TEST=YES

NC_FW_C_TPBIAS

FW_C_TPBIAS

FW_A_TPB_N

FW_A_TPB_P

FW_PORT1_TPA_P

FW_PORT1_TPA_FL_N

FW_PORT1_TPA_FL_P

42

42

42

42

42

42

63

42

6

42

40

63

40

40

40

40

40

42

42

40

40

42

42

42

42

40

40

40 40

6

42

40

40

40

40

42

42

42

BI BI

BI

OUT

OUT

BI BI

BI

IN

OUT

SYM_VER-2

SYM_VER-2

BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Top-Case Connector

516S0350

Connector shield

(40 AWG)

(28 AWG)

Twin-Ax Pair 2

Standard wires

Connector shield

(40 AWG)

518S0371

Camera Connector

Twin-Ax Pair 1

M-ST-SM

QT500166-L020

CRITICAL

9

87

65

43

2

1615

1413

1211

10

1

J4900

6

27

27

51 48 47

5

48 47

F-RT-SM

CAMERA-M1-CUS

CRITICAL

6

5

4

3

2

1

8

7

J4931

6

27

27

53

53

SC-75

RCLAMP0502B

CRITICAL

2

1

3

D4900

0402

FERR-220-OHM

21

L4931

0402

FERR-220-OHM

21

L4930

SM

165-OHM

CRITICAL

4

32

1

FL4936

SM

165-OHM

CRITICAL

4

32

1

FL4935

6 5

6 5

27

5

27

5

SC-75

RCLAMP0502B

CRITICAL

NO STUFF

2 1

3

D4930

50V

20%

402

CERM

0.001uF

NO STUFF

PLACEMENT_NOTE=Place next to J4931 pin 7

2

1

C4931

50V

20%
402

CERM

0.001uF

NO STUFF

PLACEMENT_NOTE=Place next to J4931 pin 8

2

1

C4930

051-6941

12

104

49

Internal USB Connections

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

SMBUS_ATS_SCL_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_CAMERA

VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

USB2_CAMERA_N_F
USB2_CAMERA_P_F
SMBUS_ATS_SDA_F

=SMBUS_ATS_SDA

=PP5V_S3_CAMERA

=USB2_CAMERA_N

=USB2_CAMERA_P

=SMBUS_ATS_SCL

=USB_TRACKPAD_N

SMC_LID

KBDLED_ANODE

=I2C_TRACKPAD_SCL

=SMBUS_TOPCASE_SCL

=SMBUS_TOPCASE_SDA

=I2C_TRACKPAD_SDA

SMC_ONOFF_L

=USB_TRACKPAD_P

KBDLED_RETURN

=PP3V3_S3_TOPCASE
=PP3V42_G3H_LIDSWITCH
=PP5V_S3_TOPCASE

63

5

63

63

63

SYM_VER-2

BI

BI

OUT

VBUS

D-

D+

GND

PAD

THRML

GND

OUT_2

OUT_1

OUT_0

OC*

EN*

IN_0
IN_1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Right USB Port

Place L5200, L5205 and L5206 across moat

514S0115

Port Power Switch

CRITICAL

165-OHM

SM

4

32

1

L5200

FERR-250-OHM

SM

21

L5205

6.3V

20%

B2

POLY

100UF

2

1

C5296

10uF

CERM

805-1

6.3V

20%

2

1

C5295

CERM

20%

6.3V

10uF

805-1

2

1

C5290

10V

20%
402

CERM

0.1UF

2

1

C5291

402

16V

CERM

20%

0.01uF

2

1

C5205

0.01uF

20%

402

16V

CERM

2

1

C5206

SM

FERR-250-OHM

21

L5206

6

6

6

F-RT-SM-USB-RGT1

UAR2X

CRITICAL

8

7

6

5

4

3

2

1

J5200

CRITICAL

RTUSB_ESD

SC-75

RCLAMP0502B

2 1

3

D5200

TPS2051

CRITICAL

MSOP

9

6

7

8

5

3

2

1

4

U5290

0

402

MF-LF

1/16W

5%

21

R5292

402

CERM-X5R

6.3V

20%

NO STUFF

0.47uF

2

1

C5292

External USB Connector

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

52

=RTUSB_OC_L

RTUSB_OC_L_RC

MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

PP5V_S3_RTUSB_ILIM

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm

GND_RTUSB

=GND_CHASSIS_RTUSB

USB2_RT_F_N
USB2_RT_F_P

=USB2_RT_N

=USB2_RT_P

=RTUSB_EN

=PP5V_S3_RTUSB

PP5V_S3_RTUSB_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm

6

62

63

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

516S0361

NC

Place XW5515 at 5V switcher

Left I/O Board Connector

(Input from LIO)

Place XW5500 at 5V switcher

Place XW5505 at 5V switcher

(2 Amps)

(500 mA)

Place XW5510 at 5V switcher

NCNC

(2 Amps)

(500 mA)

NC

CRITICAL

F-ST-SM

QT510806-L111-7F

9

84

8382

81

80

8

79

7877

7675

7473

7271

70

7

69

6867

6665

6463

6261

60

6

59

5857

5655

5453

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J5500

SM

21

XW5500

SM

21

XW5505

SM

21

XW5510

SM

21

XW5515

55

104

12

051-6941

Left I/O Board Connector

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=SMBUS_LIO_SB_SDA

=USB2_LT_P

=USB2_LT_N

LIO_PLT_RESET_L

LIO_P3V3S3_EN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=5V

PP5V_S0_AUDIO

EXCARD_OC_L

SMC_BATT_TRICKLE_EN_L

LIO_DCIN_ISENSE

=PCIE_MINI_R2D_P

=PCIE_MINI_R2D_N

=PCIE_MINI_D2R_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

=SMBUS_LIO_SB_SCL

=USB2_EXCARD_N

=SMBUS_LIO_SMC_SCL

=SMBUS_LIO_SMC_SDA

PCIE_WAKE_L

ACZ_SYNC

ACZ_SDATAIN<0>

ACZ_SDATAOUT

SMC_BC_ACOK

SMC_SYS_ISET

LIO_BATT_ISENSE

MINI_CLKREQ_L

EXCARD_CLKREQ_L

SMC_BATT_CHG_EN

SMC_ADAPTER_EN

SYS_ONEWIRE

=PP5V_S0_AUDIO_XW

SMC_BATT_ISET

LIO_P3V3S0_EN_L

SMC_EXCARD_CP

LTUSB_OC_L

=PPDCIN_G3H_LIO

=PP3V42_G3H_LIO

=PP1V5_S0_LIO

=USB2_EXCARD_P

=PCIE_MINI_D2R_P

ACZ_BITCLK

=PP5V_S5_LIO

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

=PCIE_EXCARD_D2R_N

=PCIE_EXCARD_R2D_P

ACZ_RST_L

=PCIE_EXCARD_R2D_N

=PCIE_EXCARD_D2R_P

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

GND_AUDIO

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=5V

PP5V_S0_AUDIO_PWR

GND_AUDIO_PWR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=0V

SMC_EXCARD_PWR_EN

48

48

48

37

79

79

79

48

48

47

48

48

79

79

27

6

6

26

62

6

47

51

46

46

46

34

34

27

6

27

27

23

21

21

21

47

47

51

34

34

47

41

47

47

62

47

6

63

63

63

6

46

21

63

34

34

46

46

21

46

46

47

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

63

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PCI-E x1 Port "F" = Unused

PCI-E x1 Port "E" = Unused

PCI-E x1 Port "D" = Unused

PCI-E x1 Port "C" = ExpressCard

PCI-E x1 Port "B" = PCI-E Mini Card

PCI-E x1 Port "A" = Ethernet (Yukon)

Place caps close to SB

Place caps close to SB

402

X5R

16V

10%

0.1uF

21

C5710

402

X5R

16V

10%

0.1uF

21

C5711

402

X5R

16V

10%

0.1uF

21

C5721

402

X5R

16V

10%

0.1uF

21

C5720

57

104

12

051-6941

PCI-E Connections

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PCIE_F_R2D_C_P

PCIE_B_R2D_C_P

PCIE_B_D2R_N

MAKE_BASE=TRUE

TP_PCIE_F_R2DN

=PCIE_MINI_D2R_P
=PCIE_MINI_D2R_N

=PCIE_MINI_R2D_N

=PCIE_MINI_R2D_P

PCIE_B_R2D_C_N

PCIE_MINI_R2D_C_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_MINI_D2R_N

PCIE_B_D2R_P

MAKE_BASE=TRUE

PCIE_MINI_D2R_P

MAKE_BASE=TRUE

PCIE_MINI_R2D_C_P

=PCIE_EXCARD_R2D_P

=PCIE_EXCARD_R2D_N

=PCIE_EXCARD_D2R_P
=PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

PCIE_C_R2D_C_P

PCIE_C_R2D_C_N

PCIE_C_D2R_N

PCIE_C_D2R_P

TP_PCIE_D_D2RP

MAKE_BASE=TRUE

TP_PCIE_D_D2RN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_PCIE_D_R2DN

MAKE_BASE=TRUE

TP_PCIE_D_R2DP

PCIE_D_D2R_P
PCIE_D_D2R_N

PCIE_D_R2D_C_N

PCIE_D_R2D_C_P

PCIE_E_R2D_C_P
PCIE_E_R2D_C_N

PCIE_E_D2R_N

PCIE_E_D2R_P

MAKE_BASE=TRUE

TP_PCIE_E_R2DP

MAKE_BASE=TRUE

TP_PCIE_E_R2DN

TP_PCIE_E_D2RN

MAKE_BASE=TRUE

TP_PCIE_E_D2RP

MAKE_BASE=TRUE

PCIE_F_R2D_C_N

PCIE_F_D2R_N

PCIE_F_D2R_P

MAKE_BASE=TRUE

TP_PCIE_F_R2DP

TP_PCIE_F_D2RN

MAKE_BASE=TRUE

TP_PCIE_F_D2RP

MAKE_BASE=TRUE

45

45

45

45

45

45

45

45

22

22

22

5

5

5

5

22

22

5

5

5

5

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12
P13
P14
P15

P17

P31/LAD1

P30/LAD0

P32/LAD2
P33/LAD3

P36/LCLK
P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45
P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*

P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*

P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5

P84/IRQ3*/TXD1
P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2
PB3
PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5
PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD

PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15

PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3

PB0/LSMI*
PB1/LSCI

PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

VCC

VCC

AVCC

XTAL
EXTAL

AVCC

VCC

MD1
MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT
OUT

BI

OUT

IN

IN

IN

OUT

IN

BI

IN

BI

OUT

OUT

IN

IN

OUT

OUT

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN

IN

IN

OUT

IN

IN

IN
OUT
OUT
OUT
OUT

BI

BI
BI
BI
BI
BI
BI

OUT
OUT

OUT
OUT
OUT

IN

IN

IN
IN

OUT

IN

IN

OUT

OUT

IN

OUT
OUT

IN

IN

OUT
OUT

BI
BI
BI
BI

IN
IN
IN

OUT

OUT
OUT

BI

IN
IN
IN
IN

BI

BI

IN
IN

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

THEY ARE SET BY SOFTWARE TO BE
DRIVEN OUTPUTS ALWAYS SO THEY

LAYOUT NOTE:
PLACE C5807 NEAR PIN F1

VCL IS INTERNAL RAIL

PLACE R5899 AND C5820 NEAR SMC PIN N14,N15

SMC

LAYOUT NOTE:

UNUSED PINS HAVE THE FORMAT

CAN BE LEFT NO-CONNECTED.

SMC_XXX WHERE XXX IS THE PORT NUMBER.

805

20%

6.3V
X5R

22UF

2

1

C5802

56 49 48 23

5

49 48

5

51 48 43

5

402

0.47UF

20%

6.3V
CERM-X5R

2

1

C5807

10V

0.1UF

20%
CERM

402

2

1

C5803

0.1UF

20%
CERM

10V
402

2

1

C5820

5%

1/16W

4.7

402

MF-LF

21

R5899

0.1UF

20%
10V
CERM
402

2

1

C5804

SM

21

XW5800

23

57

402

10V

20%

0.1UF

CERM

2

1

C5805

23

23

48

62 26

6

23

20%
10V
CERM
402

0.1UF

2

1

C5806

51

51

51

51

51

51

51

51

64 48

5

48 45

5

49 48

5

49 48

5

52 22

52 22

48 45 41

5

62

BGA

OMIT

SMC_H8S2116

G2

H1

H2

J4

J3

J1

J2

K4

B6

A6

C6

D6

B7

A7

C7

P15

N13

R15

P14

R14

P13

R13

N12

J13

J12

K14

K13

K12

L15

L14

L13

F2

G4

G1

C1

D3

C2

B1

C3

D5

B5

A5

D7

A8

C8

D8

B9

A9

C9

D9

F14

E13

E15

E14

E12

D15

D14

D13

C15

D12

C14

B15

B14

A15

C13

B12

U5800

OMIT

SMC_H8S2116

BGA

B3

D4

C4

K2

F3

E1

R7

P7

M8

R8

P8

N9

R9

P9

N5

P5

R5

M6

N6

R6

P6

M7

L2

L4

M1

M2

M3

M10

N10

R10

P10

N11

R11

P11

M11

H12

H13

H15

H14

G12

G13

G15

G14

D11

A12

C11

B11

A11

D10

A10

B10

N1

M4

N2

R1

N3

R2

P3

R3

U5800

BGA

SMC_H8S2116

OMIT

A2

D2

B4

A4

A13

B13

F13

F12

R4

P4

D1

F1

A1

J15

P1

P2

E3

F4

K1

E2

B2

L1

R12

P12

M15

M14

N15

N14

U5800

BGA

SMC_H8S2116

OMIT

L12

M13

M12

N7

M5

N4

L3

N8

M9

H4

K3

E4

B8

A3

C5

C10

C12

A14

F15

J14

K15

H3

G3

U5800

48 45

5

48 45

5

27

48

MF-LF

5%
402

1/16W

10K

2

1

R5809

49

5

49

5

MF-LF
402

5%

10K

1/16W

2

1

R5801

1/16W

5%

10K

MF-LF
402

2

1

R5802

NOSTUFF

402

MF-LF

1/16W

5%

0

2

1

R5803

10K

MF-LF

5%
1/16W

402

2

1

R5898

26 23

5

56 48

48 14

48 45

5

23

23

23

51

5

36

48 45

5

45

5

23

48

54

54

48

48

48

48

54

54

55

55

48

55

53

53

48

49 48

5

48

49 48

5

49 48

5

49 48

5

48 43

48

45

5

48

45

5

48

52 22

27

27

27

27

27

27

48

48

76

6 5

48 23

55

49 22

5

48

22

52 22

48

23

48

48

21

48

48

48

48

48

48

48

56 49 21

5

56 49 21

5

56 49 21

5

56 49 21

5

56 49 21

5

26

34

56 49 23

5

48

53

27

62 41 23

62 39 23

48 23

35

27

27

48

48

56 49 40 23

5

051-6941

12

58

104

SMC_SYS_VSET

SMC_BATT_ISET

SMC_LID

SMC_PF1

SMS_ONOFF_L

SMS_X_AXIS
SMS_Z_AXIS

SMC_ANALOG_ID
SMC_NB_ISENSE
SMC_MEM_ISENSE

SMC_BS_ALRT_L

SMS_INT_L

SMC_CPU_ISENSE

SPI_SI

SMC_FAN_2_CTL

SMC_EXCARD_OC_L

SMC_PM_G2_EN

SMC_P22

SMC_XTAL
SMC_EXTAL

PP3V3_AVCC_SMC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

=PP3V3_S5_SMC

KBC_MDE

ALS_LEFT

SMC_MD1

PP3V3_AVREF_SMC

SMC_PROCHOT

SMC_TRST_L

SMC_NMI

GND_SMC_AVSS

SPI_ARB

SMC_XDP_TDO_3_3

SMC_SYS_LED_16B

GND_SMC_AVSS

=PP3V3_S5_SMC

SMC_CPU_INIT_3_3_L

SMC_P23

SMC_BC_ACOK

SMC_FWE

ALS_RIGHT

SMS_Y_AXIS

SMC_FAN_3_TACH

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_P21

SMC_BATT_TRICKLE_EN_L

SMC_P20

SMC_BATT_CHG_EN

SMC_P26

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS

SMC_SYS_ISET

SMC_BATT_VSET

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

SMB_0_S0_DATA

SMC_CPU_VSENSE

SMC_ADAPTER_EN

SMC_PF0

SPI_CE_L
SMC_XDP_TCK_3_3

SMC_CPU_RESET_3_3_L

SMC_GPU_ISENSE
SMC_DCIN_ISENSE

SMC_EXCARD_CP

SMC_VCL

=PP3V3_S5_SMC

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

SMC_RST_L

ALS_GAIN

SMC_THRMTRIP

SMC_XDP_TRST_L

PM_SYSRST_L

SMC_SUS_CLK

SPI_SCLK
SPI_SO

SMC_PROCHOT_3_3_L

SMC_GPU_VSENSE
SMC_PBUS_VSENSE

SMC_BATT_ISENSE
SMC_FWIRE_ISENSE

SMC_EXCARD_PWR_EN

ISENSE_CAL_EN

SMC_EXTSMI_L

SMC_RX_L

SMC_XDP_TCK

SMC_XDP_TMS
SMB_BSB_DATA

SMC_TPM_PP

SMC_FAN_3_CTL

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_0_TACH

PM_BATLOW_L

SYS_ONEWIRE

PM_THRM_L

PM_EXTTS_L

SMC_TPM_RESET_L

BOOT_LPC_SPI_L

SMC_RCIN_L

SMC_P27

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
PCI_CLK_SMC
INT_SERIRQ

SMC_TPM_GPIO
PM_CLKRUN_L
PM_SUS_STAT_L
SC_TX_L
SC_RX_L

SMC_ONOFF_L

SMB_BSB_CLK

SMC_WAKE_SCI_L

PM_PWRBTN_L

IMVP_VR_ON

PM_RSMRST_L

SMC_SB_NMI

RSMRST_PWRGD

ALL_SYS_PWRGD

PM_LAN_ENABLE
SMC_RSTGATE_L

SMB_0_S0_CLK

SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK

SMC_SYS_KBDLED

SMC_SYS_LED

SMC_TX_L

53

53

63

51

51

63

63

48

49

48

48

48

48

48

48

48

48

47

5

48

47

47

47

48

48

48

48

48

47 48

G

D

S

G

D

S

IN

OUT

GND

IN

OUT

V-

V+

V-

V+

OUT

NC

CD

GND

OUT

VDD

OUT

OUT

G

D

S

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

5V Comp threshold set to 4.480V (89.6%)

ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)

SMC AVREF Supply

SMC 3.3V to 1.05V Level Shifting

Debug Power Button

Silk: "PWR BTN"

Reports when 5V S5 and 3.3V S5 are in regulation

SMC PWRGD Circuit

1.71V Reference

NOTE: R5965 acts as 10K pull-up for PGOOD signal

System (Sleep) LED Circuit

SMC Crystal Circuit

NC

SMC Reset Button / Brownout Detect

Silk: "SMC RST"

1.05V Mid-Reference

SMC 1.05V to 3.3V Level Shifting

0.1uF

CERM

402

20%
10V

2

1

C5900

SMC_TPM_GPIO1

0

5%

MF-LF

1/16W

402

21

R5990

SMC_TPM_GPIO2

0

5%
1/16W
MF-LF

402

21

R5991

2N7002DW-X-F

SOT-363

1

2

6

Q5995

2N7002DW-X-F

SOT-363

4

5

3

Q5995

402

1/16W

DEVELOPMENT

MF-LF

0

5%

21

R5992

1/16W

DEVELOPMENT

MF-LF

0

5%

402

21

R5993

0.1uF

CERM

402

20%
10V

2

1

C5977

1K

MF-LF

402

5%

1/16W

2

1

R5971

5%

402

6.2K

1/16W
MF-LF

2

1

R5970

0.47uF

6.3V

20%
CERM-X5R

402

2

1

C5965

0.01uF

20%
16V
CERM
402

2

1

C5967

6.3V

20%
X5R

10uF

603

2

1

C5966

SOT23-3

REF3133

CRITICAL

21

3

VR5965

0.1uF

10V

20%
402

CERM

2

1

C5960

10K

MF-LF

402

1%

1/16W

2

1

R5961

MF-LF

402

1%

1/16W

10K

2

1

R5962

5%

402

MF-LF

10K

1/16W

2

1

R5965

61 47

LMC7211

SM-LF

2

5

1

3

4

U5977

SM-LF

LMC7211

2

5

1

3

4

U5960

0

1/16W

5%

MF-LF

402

21

R5994

1/16W
MF-LF

SMC_TPM_PP

5%

402

0

21

R5995

402

MF-LF

5%

1/16W

10K

21

R5931

402

10K

1/16W5%MF-LF

21

R5932

100K

402

MF-LF

5%

1/16W

21

R5933

10K

1/16W5%MF-LF

402

21

R5934

402

MF-LF

5%

1/16W

10K

21

R5935

100K

5%

MF-LF

402

1/16W

21

R5936

2.0K

402

MF-LF

5%

1/16W

21

R5937

402

MF-LF

5%

1/16W

100K

21

R5938

402

MF-LF

5%

1/16W

10K

21

R5939

10K

1/16W

5% 402

MF-LF

21

R5940

4025%

1/16W

10K

MF-LF

21

R5941

10K

1/16W

5% 402

MF-LF

21

R5942

10K

1/16W5%MF-LF

402

21

R5943

10K

1/16W5%MF-LF

402

21

R5944

402

MF-LF

5%

1/16W

10K

21

R5945

1/16W5%MF-LF

402

10K

21

R5946

470K

402

MF-LF

5%

1/16W

21

R5947

10K

1/16W5%MF-LF

402

21

R5948

402

MF-LF

5%

1/16W

10K

21

R5930

62

20.00MHZ

5X3.2-SM

CRITICAL

2

1

Y5920

SOT23-5

RN5VD30A-F

CRITICAL

2

1

4

3

5

U5900

10K

1/16W

1%

402

MF-LF

2

1

R5964

16.2K

MF-LF
402

1%
1/16W

2

1

R5963

CERM
402

0.0022uF

10%
50V

2

1

C5969

402

MF-LF

5%

1/16W

10K

21

R5980

10K

1/16W5%MF-LF

402

21

R5981

10K

1/16W5%MF-LF

402

21

R5982

402

MF-LF

5%

1/16W

100K

21

R5983

402

MF-LF

5%

1/16W

100K

21

R5984

49 47

5

1/16W

5%

402

MF-LF

1K

2

1

R5900

OMIT

0

MF-LF
603

5%
1/10W

2

1

R5901

MF-LF
603

5%

OMIT

0

1/10W

2

1

R5910

51 48 47 43

5

2N7002

SOT23-LF

2

1

3

Q5952

2N3906

SOT23-LF

2

3

1

Q5950

100

MF-LF
402

5%
1/16W

2

1

R5950

2.2K

MF-LF

402

5%

1/16W

2

1

R5951

47

4.7K

MF-LF

402

5%

1/16W

2

1

R5952

76

50V

5%

402

15pF

CERM

21

C5920

15pF

5%

50V

CERM

402

21

C5921

10%
16V

0.01UF

CERM

402

2

1

C5901

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

59

051-6941

12

104

SMC Support

SMC_TX_L

TPM_GPIO2

TPM_GPIO1

SMC_RX_L

TPM_PP

SMC_TPM_GPIO

SC_RX_L

SMC_TPM_PP

SMC_EXCARD_OC_L

SC_TX_L

SMC_PROCHOT_3_3_L

CPU_PROCHOT_L

=PP3V3_S0_SMC_LS

VOLTAGE=0.46V

P0V46_SMC_LSREF

SMC_PF1

MAKE_BASE=TRUE

TP_SMC_PF1

SMC_PF0

TP_SMC_PF0

MAKE_BASE=TRUE

SMC_P27

TP_SMC_P27

MAKE_BASE=TRUE

SMC_P26

TP_SMC_P26

MAKE_BASE=TRUE

SMC_P23

TP_SMC_P23

MAKE_BASE=TRUE

SMC_P22

TP_SMC_P22

MAKE_BASE=TRUE

SMC_P21

MAKE_BASE=TRUE

TP_SMC_P21

SMC_P20

MAKE_BASE=TRUE

TP_SMC_P20

SMC_XDP_TRST_L

MAKE_BASE=TRUE

TP_SMC_XDP_TRST_L

SMC_XDP_TDO_L

TP_SMC_XDP_TDO_L

MAKE_BASE=TRUE

SMC_XDP_TMS

MAKE_BASE=TRUE

TP_SMC_XDP_TMS

SMC_XDP_TCK

MAKE_BASE=TRUE

TP_SMC_XDP_TCK

SMC_FAN_3_CTL

MAKE_BASE=TRUE

TP_SMC_FAN_3_CTL

SMC_FAN_3_TACH

TP_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_FAN_2_TACH

TP_SMC_FAN_2_TACH

MAKE_BASE=TRUE

SMC_FAN_2_CTL

TP_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_SYS_VSET

MAKE_BASE=TRUE

TP_SMC_SYS_VSET

SMC_BATT_VSET

MAKE_BASE=TRUE

TP_SMC_BATT_VSET

SMC_SYS_LED

MAKE_BASE=TRUE

TP_SMC_SYS_LED

SMC_ANALOG_ID

TP_SMC_ANALOG_ID

MAKE_BASE=TRUE

SMC_MEM_ISENSE

SMC_P1V8S3_ISENSE

MAKE_BASE=TRUE

PM_EXTTS_L

MAKE_BASE=TRUE

DIMM_OVERTEMP_L

SMC_NB_ISENSE

SMC_P1V05S0_ISENSE

MAKE_BASE=TRUE

SMC_CPU_INIT_3_3_L

MAKE_BASE=TRUE

FWH_INIT_L

SMC_RST_L

SMC_MANUAL_RST_L

=PP3V3_S5_SMC

SMC_EXTAL

SMC_XTAL

SMC_SYS_LED_16B

SYS_LED_L_VDIV

SYS_LED_ANODE

SYS_LED_L

=PP5V_S3_SYSLED

SYS_LED_ILIM

=P3V3S5_PGOOD

P5VS5_COMP_POS

P1V71_SMC_REF

P5VS5_PGOOD

MAKE_BASE=TRUE

RSMRST_PWRGD

=PP3V42_G3H_SMC_PWRGD

PP5V_S5

SMC_ONOFF_L

SMC_THRMTRIP

SMC_PROCHOT

PM_THRMTRIP_L

CPU_PROCHOT_L

=PP3V42_G3H_SMCVREF

MIN_NECK_WIDTH=0.2 mm

PP3V3_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V

=PP3V3_S3_TPM
=PP3V3_S3_SMS

SMS_INT_L
SMC_TPM_RESET_L

SMC_ONOFF_L
SMC_LID
SMC_FWE
SMC_TX_L
SMC_RX_L
SYS_ONEWIRE

SMC_BATT_TRICKLE_EN_L

SMC_EXCARD_CP
PM_SUS_STAT_L
PM_SLP_S5_L

EXCARD_OC_L

GND_SMC_AVSS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=0V

SMC_BC_ACOK

SMC_CASE_OPEN

SMC_ADAPTER_EN

SMC_BATT_CHG_EN

SMC_XDP_TDO_3_3

SMC_CPU_RESET_3_3_L

SMC_TCK

SMC_XDP_TCK_3_3

=PP3V3_S5_SMC

SMC_TDI

SMC_TDO

SMC_BS_ALRT_L
SMC_TMS

51

56

49

49

48

49

49

49

47

48

48

49

63

21

47

48

48

47

47

47

47

45

53

47

45

47

49

63

49

49

64

49

47

47

48

47 29

21

48

14

48

63

63

47

56

43

47

47

47

45

45

45

23

47

6

51

45

41

45

47

48

47

47

47

47

5

56

56

5

56

47

47

47

47

47

47

7

63

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47 51

14 28

47 51

5

47

47

47

63

63

63

47

47

7

7

63 47

56

55

23

47

5

43

47

5

5

5

5

5

5

23

5

47

5

47

5

5

47

47

5

47

47

5

5

5

5

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(GPIO15)

NC

516S0384

NC

NCNC

QT500306-L021-9F

M-ST-SM

LPCPLUS

CRITICAL

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J6000

LPC+ Debug Connector

SYNC_DATE=07/20/2005

SYNC_MASTER=M42

051-6941

12

104

60

=PP3V3_S5_LPCPLUS

=PP5V_S0_LPCPLUS
FWH_INIT_L
PCI_CLK_PORT80_LPC

LPC_AD<2>
LPC_AD<3>

INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L

SV_SET_UP

LPC_AD<0>

LPC_AD<1>

BOOT_LPC_SPI_L

LPC_FRAME_L

PM_CLKRUN_L

SMC_TMS

DEBUG_RST_L

SMC_TRST_L

SMC_TDO

SMC_MD1

SMC_TX_L

56

56

56

56

56

48

56

56

56

47

48

47

47

47

47

48

48

48

48

47

47

47

47

40

48

48

48

63

63

21

34

21

21

23

23

47

47

47

47

47

23

21

21

22

21

23

47

26

47

47

47

47

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

SMBDATA

SMBCLK
ALERT*

OT2*

DXP2

OT1*

DXN

DXP1

GND

VCC

BI

BI

D+
D-

ALERT*/

THM*

SCLK

SDATA

VDD

GND

THM2*

SYM_1

SYM_1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Right-Side/Fin Stack Thermal Sensor

Place near speaker hole

Placement note:

518S0226

NC

NC

Placement note:

Place in between VRAM

518S0226

NC

NC

Placement note:

Place near GPU center

Minimize stubs

Layout note:

Place U6150 below and to the

Placement note:

GPU / Heat Pipe Thermal Sensor

left of the speaker hole.

NC

NC

NC

these R’s and R1001 & R1002

Minimize stubs between

Layout note:

programatically unstuff those parts to stuff these.

Placement note:

Place near CPU center

CPU Back-Up Thermal Diode

R1001 / R1002 are not currently BOMOPTIONed. Can not

to U6100 as possible

Keep all 4 XWs as close

Placement note:

UMAX

MAX6695AUB

CRITICAL

1

9
7

10

5

6

4

2
3

8

U6100

HSTHMSNS_HAS

402

CERM

50V

10%

0.0022uF

2

1

C6120

SM

21

XW6120

SM

21

XW6121

SM

21

XW6111

GPUTHM_A_GPU

402

MF-LF

1/16W

5%

0

2

1

R6110

GPUTHM_A_GPU

402

MF-LF

1/16W

5%

0

2

1

R6111

1/16W

GPUTHM_A_DIODE

MF-LF

5%

402

0

21

R6115

0

5%
1/16W
MF-LF

402

GPUTHM_A_DIODE

21

R6116

SOT23

2N3904LF

2

3

1

Q6115

SM

21

XW6110

5%
1/16W
MF-LF

402

0

CPUTHM_DIODE

21

R6190

CPUTHM_DIODE

402

0

5%
1/16W
MF-LF

21

R6191

SOT23

2N3904LF

2

3

1

Q6190

10K

MF-LF
402

5%
1/16W

2

1

R6152

27

27

1/16W

5%

402

MF-LF

10K

2

1

R6151

MSOP

ADT7461

CRITICAL

1

4

7

8

5

3

2

6

U6150

0.1UF

X5R
402

10%
16V

2

1

C6150

0.001UF

CERM
402

20%
50V

2

1

C6160

1%

499

402

MF-LF

1/16W

21

R6160

1%

499

MF-LF

402

1/16W

21

R6161

10V

20%
402

CERM

0.1uF

2

1

C6100

CRITICAL

88460-0201

F-RT-SM

2

1

4

3

J6120

88460-0201

F-RT-SM

CRITICAL

2

1

4

3

J6160

1/16W

5%

402

MF-LF

47

21

R6100

50V

0.0022uF

CERM

402

10%

2

1

C6110

116S0004 1

RES,0,1/16W,0402

C6120

HSTHMSNS_NOT

Thermal Sensors

61

104

12

051-6941

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

GPUTHMSNS_DX_A_N

CPUTHMSNS_DIO_N

THRM_CPU_DX_N

THRM_CPU_DX_P

CPUTHMSNS_DIO_P

GPUTHMSNS_DXP1

GPUTHMSNS_DXP2

PP3V3_S0_GPUTHMSNS_R

GPUTHMSNS_DXN

=SMBUS_GPUTHMSNS_SDA
=SMBUS_GPUTHMSNS_SCL

=PP3V3_S0_RSTHMSNS

RSTHMSNS_THM_L

RSTHMSNS_ALERT_L

=SMBUS_RSTHMSNS_SCL
=SMBUS_RSTHMSNS_SDA

=PP3V3_S0_GPUTHMSNS

HSTHMSNS_DX_P

ATI_TDIODE_N

ATI_TDIODE_P

GPUTHMSNS_DX_A_P

GPUTHMSNS_DX_A_DIO_P

GPUTHMSNS_DX_A_DIO_N

HSTHMSNS_DX_N

RSFSTHMSNS_D_P

RSFSTHMSNS_D_N

RSFSTHMSNS_D_R_P
RSFSTHMSNS_D_R_N

10

10

27

27

63

63

5

72

72

5

5

5

IN

OUT

G

S D

D

S

G

N-CHN

S

D

G

P-CHN

G

D

S

N-CHN

S

D

G

P-CHN

G

D

S

OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

OUT

IN

OUT

IN

OUT

IN

OUT

G

D

S

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Place RC close to SMC

Rthevanin = 4573 ohms

PBUS Voltage Sense Enable & Filter

Place RC close to SMC

SMC_ONOFF_L is low (power button

Enables PBUS VSense divider when

Enables PBUS VSense divider when high.

1.8V S3 (Memory) Current Sense Filter

Switches in fixed load on power supplies to calibrate current sense circuits

Place short near U0700 center

1.0A / 1.8W

CPU Voltage Sense / Filter

Place RC close to SMC Place RC close to SMC

Place RC close to SMC Place RC close to SMC

1.05V S0 (NB) Current Sense Filter

Place RC close to SMC

Place RC close to SMC

1.2A / 1.44W 1.05A / 1.1W

FireWire Current Sense Filter

GPU Current Sense Filter

Place RC close to SMC

Battery Current Sense Filter

Place RC close to SMC

Current Sense Calibration Circuit

Place short near U8400 center

CPU Current Sense Filter

This half of Q6216 acts as a
diode to keep Q6215 from
pulling SMC_ONOFF_L low.

DCIN Current Sense Filter

GPU Voltage Sense / Filter

pressed or driven low by SMC)

between PBUS and 3.42V

as a level-shifter

This half of Q6216 acts

R5808 is pull-up

47

5

470K

5%
1/16W
MF-LF
402

2

1

R6228

402

MF-LF

1/16W

5%

100K

2

1

R6227

1%
1/16W
MF-LF

402

100K

2

1

R6215

47

27.4K

1%
1/16W
MF-LF

402

2

1

R6285

6.3V

0.22UF

402

X5R

20%

2

1

C6285

5.49K

402

MF-LF

1/16W

1%

2

1

R6286

2N7002DW-X-F

SOT-363

4

5

3

Q6216

2N7002DW-X-F

SOT-363

1

2

6

Q6216

FDG6332C_NL

SC70-6

1

2

6

Q6229

FDG6332C_NL

SC70-6

4

5

3

Q6229

FDG6332C_NL

SC70-6

1

2

6

Q6215

FDG6332C_NL

SC70-6

4

5

3

Q6215

47

0.22UF

20%

6.3V
X5R
402

2

1

C6259

1%
1/16W
MF-LF

402

4.53K

21

R6259

47

1/16W

4.53K

402

MF-LF

1%

21

R6270

6.3V

0.22UF

402

X5R

20%

2

1

C6270

57 47

20%
X5R

402

0.22UF

6.3V

2

1

C6275

1%
1/16W
MF-LF

402

4.53K

21

R6275

66

47

6.3V

0.22UF

402

X5R

20%

2

1

C6280

4.53K

402

MF-LF

1/16W

1%

21

R6280

45

5

45

5

1%
1/16W
MF-LF

402

4.53K

21

R6290

20%
X5R

402

0.22UF

6.3V

2

1

C6290

47

48

20%
X5R

402

0.22UF

6.3V

2

1

C6240

1%
1/16W
MF-LF

402

4.53K

21

R6240

61 48

6.3V

0.22UF

402

X5R

20%

2

1

C6235

4.53K

402

MF-LF

1%

1/16W

21

R6235

60

47

20%
X5R

402

0.22UF

6.3V

2

1

C6230

1%
1/16W
MF-LF

402

4.53K

21

R6230

41

SM

21

XW6259

47

4.53K

402

MF-LF

1/16W

1%

21

R6209

402

X5R

6.3V

20%

0.22UF

2

1

C6209

SM

21

XW6209

1206

MF-LF

1/4W

1%

1.00

2

1

R6220

470K

5%
1/16W
MF-LF

402

2

1

R6229

CRITICAL

FDC796N

SUPERSOT-6

65321

4

7

Q6220

1206

MF-LF

1/4W

1%

1.00

2

1

R6221

SUPERSOT-6

CRITICAL

FDC796N

65321

4

7

Q6221

1.82

1%

1/4W

MF-LF

1206

2

1

R6222

FDC796N

CRITICAL

SUPERSOT-6

65321

4

7

Q6222

1.00

1%

1/4W

MF-LF

1206

2

1

R6223

SUPERSOT-6

CRITICAL

FDC796N

65321

4

7

Q6223

Current & Voltage Sensing

62

104

12

051-6941

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PP3V42_G3H_PBUSVSENS

SMC_ONOFF_L

PBUSVSENS_PWRBTN_L

SMC_FWIRE_ISENSE

P1V05S0_IOUT

CPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

=PP1V05_S0_REG

P1V05S0_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

=PPVCORE_S0_GPU

GPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

=PPVCORE_S0_CPU

GND_SMC_AVSS

=PPVCORE_S0_GPU

GND_SMC_AVSS

SMC_CPU_VSENSE

SMC_GPU_VSENSE

CPUVSENSE_IN

GPUVSENSE_IN

GND_SMC_AVSSGND_SMC_AVSSGND_SMC_AVSS

SMC_P1V05S0_ISENSE

SMC_P1V8S3_ISENSE

P1V8S3_IOUT

SMC_GPU_ISENSE

GPUVCORE_IOUT

SMC_CPU_ISENSE

CPUVCORE_IOUT

GND_SMC_AVSS

SMC_BATT_ISENSELIO_BATT_ISENSE

GND_SMC_AVSS

SMC_DCIN_ISENSEFWPWR_IOUT

=PPVCORE_S0_CPU

GND_SMC_AVSS

LIO_DCIN_ISENSE

P1V8S3_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

=PP1V8_S3_REG

GND_SMC_AVSS

ISENSE_CAL_EN_LS5V

ISENSE_CAL_EN_L

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN

=PBUSVSENS_EN

PPBUS_G3H

PBUSVSENS_EN_L

VOLTAGE=12.6V

PPBUS_G3H_VSENSE

SMC_PBUS_VSENSE

GND_SMC_AVSS

48

72 63

53

72

53

53 53 53

53 53

63

53

53

53

47

63 67 51

51

67

51

51 51 51

51 51

51

51

51

51

43

61 63

9

48

63

48

48 48 48

48 48

9

48

63

48

63

48

63

5

5

51

8

47

51

47

47 47 47

47 47

8

47

60

47

5

62

63

47

SCK

SO

WP*

SI

VDD

CE*

HOLD*

VSS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM

ICH7M AND TEKOA(LAN CHIP)

R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH

402

CERM

10V

20%

0.1UF

2

1

C6312

1/16W

402

5%

MF-LF

3.3K

2

1

R6301

402

3.3K

5%
1/16W
MF-LF

2

1

R6302

22pF

402

CERM

5%
50V

2

1

C6301

MF-LF

402

5%

1/16W

47

21

R6307

402

22pF

50V

5%
CERM

2

1

C6308

5%
CERM

50V
402

22pF

2

1

C6309

402

MF-LF

47

5%

1/16W

21

R6303

47

1/16W
MF-LF

5%

402

21

R6306

22pF

402

CERM

5%
50V

2

1

C6311

OMIT

CRITICAL

16MBIT

SST25VF016B

SOI

3

4

8

2

5

6

7

1

U6301

402

5%

10K

1/16W

MF-LF

21

R6308

NOSTUFF

10K

5%
1/16W
MF-LF

402

21

R6309

63

SPI BOOTROM

051-6941

12

104

SYNC_MASTER=M42

SYNC_DATE=11/16/2005

=PP3V3_S5_ROM

SPI_SO_R

SPI_SI_RSPI_SCLK

SPI_SCLK_R

SPI_SI

SPI_SO

SPI_CE_L

SPI_HOLD_L

SPI_WP_L

47 47

47

47

63

22 22

22

22

V+

V-

G

D

S

IN

OUT

NC

CNTRL

THRML_PAD

VDD

SW

AGNDPGND

FB

VOUT

IN

IN

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Left ALS circuit has 1K series-R

Left ALS Filter

Keyboard LED Driver

NC

NC

Right ALS Circuit

RTALS_OP_IN and RTALS_OP_COMP need to be matched

MAX4236EUTT

SOT23-6-LF

CRITICAL

2

6

5

1

4

3

U6405

CERM

402

20%
10V

0.1UF

2

1

C6405

120K

MF-LF
402

5%
1/16W

2

1

R6406

0.22UF

X5R
402

20%

6.3V

2

1

C6406

15.0K

MF-LF
402

1%
1/16W

2

1

R6407

1K

MF-LF

402

1%

1/16W

2

1

R6408

MF-LF

402

1%

1/16W

1K

21

R6401

BS520EOF

TH

CRITICAL

2

1

PD6400

5.1M

MF-LF

402

5%

1/16W

2

1

R6400

0.01UF

CERM

20%
16V

402

2

1

C6400

2N7002

SOT23-LF

2

1

3

Q6408

6

47

4.53K

MF-LF

402

1%

1/16W

21

R6410

0.22UF

X5R

20%

6.3V
402

2

1

C6410

MM3120

LLP

CRITICAL

8

197

5

6 4

3

2

U6450

22uH

3.8x3.8x1.5MM

CRITICAL

21

L6450

1uF

CERM

402

10%

6.3V

2

1

C6450

KBDLED_NOT

10K

MF-LF

402

5%

1/16W

2

1

R6451

MF-LF

5%

1/16W

KBDLED_HAS

10K

402

2

1

R6452

47

0.22uF

20%
25V
X5R
603

2

1

C6455

25.5

805

1%
1/8W
MF-LF

2

1

R6455

43

43

47

6.3V

20%

402

X5R

0.22UF

2

1

C6430

1/16W

1%

402

MF-LF

3.48K

21

R6430

ALS Support

64

104

051-6941

12

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=RTALS_GAIN

RTALS_OP_COMP

=PP3V3_S3_RTALS

ALS_RT_OUT

ALS_RIGHT

GND_SMC_AVSS

RTALS_OP_IN

RTALS_PHOTODIODE

RTALS_GAIN_L

SMC_SYS_KBDLED

=PP3V3_S0_KBDLED

KBDLED_RETURN

KBDLED_ANODE

KBDLED_SW

=PP5V_S0_KBDLED

GND_SMC_AVSS

LTALS_OUT

ALS_LEFT

53

53

51

51

48

48

76

63

47

63

63

47

5

G

S D

G

S D

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Left Fan

518S0293518S0293

NC

NC

NC

NC

Right Fan

1/16W

47K

402

MF-LF

5%

2

1

R6550

5%
1/16W
MF-LF

402

47K

21

R6555

402

MF-LF

1/16W

5%

47K

2

1

R6560

47K

402

MF-LF

1/16W

5%

21

R6565

402

MF-LF

5%

1/16W

100K

2

1

R6551

CRITICAL

SM-2MT-LF

4

3

2

1

6

5

J6550

SM-2MT-LF

CRITICAL

4

3

2

1

6

5

J6560

2N7002DW-X-F

SOT-363

4

5

3

Q6560

100K

1/16W

5%

MF-LF

402

2

1

R6561

SOT-363

2N7002DW-X-F

1

2

6

Q6560

Fan Connectors

12

051-6941

104

65

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

FAN_RT_TACHFAN_LT_TACH

=PP5V_S0_FAN_LT

SMC_FAN_0_TACH

SMC_FAN_0_CTL

=PP3V3_S0_FAN_LT

FAN_LT_PWM

SMC_FAN_1_CTL

FAN_RT_PWM

SMC_FAN_1_TACH

=PP3V3_S0_FAN_RT

=PP5V_S0_FAN_RT

63

5 5

5

47

47

63

5

47

5

47

63

63

OUTPUTY

OUTPUTZ

DNC

RSVD

TEST

SELF

PS

PARITY

RSVD

RSVD

RSVD

GND PAD

THRML

OUTPUTX

VDD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

M1 placement: Bottom-side

placed on board bottom-side:

placed on board top-side:

1

Desired orientation when Desired orientation when

+X

+Z (dn)

+Y

Top-through View

Package Top

1

+Y

+Z (up)

+X

NC

NC

0.1uF

CERM
402

20%
10V

2

1

C6620

QFN

KXM52-2050

CRITICAL

8

15

10

11

7

6

4

9

5 14

13

2

123

1

U6620

402

1/16W

5%
MF-LF

10K

1

2

R6621

10K

MF-LF

402

5%

1/16W

2

1

R6620

0.033UF

X7R
402

20%
10V

2

1

C6605

10V

20%
402

X7R

0.033UF

2

1

C6606

10V

20%
402

X7R

0.033UF

2

1

C6604

66

104

12

051-6941

Sudden Motion Sensor (SMS)

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

SMS_Z_AXIS

=PP3V3_S3_SMS

SMS_X_AXIS
SMS_Y_AXIS

SMS_ONOFF_L

SMS_ACC_SELFTEST

63

47

48

47

47 47

IN

BI

BI
BI

LAD1
LAD2

LCLK
LFRAME*
LRESET*
LPCPD*
SERRIRQ

LAD0

CLKRUN/GPIO*

PP/GPIO
GPIO_EXPRESS_00
GPIO/SM_DAT
GPIO/SM_CLK

XTALI/32K_IN

TESTBI/BADD/GPIO

TESTI

3V0
3V1
3V2

3VSB

VNC

VBAT

XTALO

GND2

GND3

GND0

GND1

LAD3

BI

BI

IN

IN

BI

IN
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

BASE ADDR = 0X4E/4F

GPIO2

TESTBI/BADD

1/8W (R6704/R6705) IS USED FOR NOW

SINCE CURRENT OF VSB IS NOT YET ON SPEC,

NOTE:

PLACE R6702-03 WHERE ACCESSIBLE

LAYOUT NOTE:

PLACE WHERE ACCESSIBLE

LAYOUT NOTE:

BASE ADDR = 0X2E/2F

NC

NC

NC

CLKRUN*

GPIO

PP

NC

VDD
VDD
VDD

VSB

NC
NC

GND

(INT PD)

49 48 47 23

5

49 47 23

5

402

X5R

16V

10%

0.1UF

2

1

C6700

0.1UF

402

X5R

16V

10%

2

1

C6701

0.1UF

10%
16V
X5R
402

2

1

C6702

49 47 21

5

0.1UF

10%
16V
X5R
402

2

1

C6703

NOSTUFF

0

5%
1/16W
MF-LF
402

2

1

R6700

49 47 21

5

OMIT

TSSOP

TPM

14

13

3
12

8

9

27

7

16
28

22

21

17

20

23

26

6
1
2

25

18

11

4

15

5

24

19

10

U6700

MF-LF

1/16W

5%

10K

402

2

1

R6702

NOSTUFF

5%
1/16W
MF-LF

10K

402

2

1

R6703

49 47 40 23

5

805

MF-LF

1/8W

5%

0

21

R6704

NOSTUFF

805

MF-LF

1/8W

5%

0

2

1

R6705

0

5%

MF-LF

1/16W

402

21

R6798

MF-LF

5%

0

NOSTUFF

1/16W

402

21

R6799

49 47 21

5

26

48 47

49 47 21

5

34

49 47 21

5

TPM

SYNC_DATE=11/16/2005

SYNC_MASTER=M38

051-6941

12

67

104

SMC_TPM_RESET_L

TPM_LRESET_L

TPM_RST_L

TPM_BADD

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>

PCI_CLK_TPM
LPC_FRAME_L

PM_SUS_STAT_L
INT_SERIRQ

=PP3V3_S0_TPM

TPM_XTALO

TPM_XTALI

PM_CLKRUN_L

=PP3V3_S3_TPM

=PP3V3_S0_TPM

LPC_AD<3>

TPM_GPIO2

TPM_GPIO1

TPM_PP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=3.3V

PP3V3_TPM_3VSB

63

63

63

56

35

35

48

56

48

48

48

TPAD

VSS

BOOT2

BOOT1

PHASE1

UGATE1

LGATE1

PGND1

ISEN1

UGATE2

PHASE2

LGATE2

PVCC

VDDVIN

PGND2

VID6
VID5
VID4

VID2

VID3

VID1
VID0

ISEN2

VSUM

OCSET

VO

DROOP

DFB

VSEN

RTN

DPRSTP*
DPRSLPVR
PSI*
PGD_IN

3V3
CLK_EN*

PGOOD

VR_ON

NTC

VR_TT*

SOFT

RBIAS

VDIFF

FB2
FB
COMP
VW

NC

IN

IN

IN
IN

OUT
IN
OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU VCore Current Sense

<Rc>

Vout = Gain * ((2.1 mV/A * Iload) + Voffset)

(IMVP6_FB)

(IMVP6_VO)

(IMVP6_NTC)

0 1 1 2-Phase CCM

1 1 0 1-Phase DCM

Vout @ 36A = 2.44V-2.60V

Gain = Rc / (Ra + Rb)
Voffset worst-case ~2.3mV (+/- ~1A offset)

Voffset = (Vdrp_offset * Kdroop) + Vamp_offset

<Rc>

<Ra + Rb>

(IMVP6_VO)

(IMVP6_VSUM)

<Ra>

(IMVP6_ISEN2)

<Rb>

(IMVP6_PHASE2)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

These caps for Q7500

36A max output

Vout = Variable

(Inductors limit)

These caps for Q7550

(IMVP6_VW)

(GND)

(GND_IMVP6_SGND)

(GND_IMVP6_SGND)

(IMVP6_COMP)

(GND)

DPRSLPVR DPRSTP* PSI* Operation Mode

0 1 0 1-Phase CCM
1 0 1 1-Phase DCM

402

CERM

NO STUFF

10%

0.0022UF

50V

2

1

C7501

402

CERM

10%
50V

NO STUFF

0.0022UF

2

1

C7502

402

10K

MF-LF

1/16W

1%

21

R7505

20%

402

X5R

6.3V

0.22UF

21

C7505

3.65K

MF-LF

1%

603

1/10W

2

1

R7506

147K

1%
1/16W

402

MF-LF

2

1

R7532

402

16V

0.01uF

20%

CERM

2

1

C7532

402

0.1uF

X5R

10%
16V

2

1

C7531

QFN

OMIT

ISL6262

9

19

21

14

5

44

18

20

43
42
41
40
39
38
37

13

22

27

35

49

7

15

4

31

2

28

34

1

29

33

3

8

6

25

30

32

23

24

12
11

16

46
45

17

10

47

26

36

48

U7530

MF-LF

402

1.82K

1%

1/16W

2

1

R7535

1/16W
MF-LF

1%

402

3.57K

2

1

R7537

0.0047uF

25V

10%

402

CERM

2

1

C7537

1%

MF-LF

402

1/16W

182K

2

1

R7534

50V

10%
402

CERM

330pF

2

1

C7535

25V
X5R
603

0.22uF

20%

2

1

C7500

603

X5R

25V

0.22uF

20%

2

1

C7550

MF-LF

1%
1/16W

402

9.31K

2

1

R7542

1%

402

MF-LF

1/16W

3.92K

21

R7540

402

MF-LF

1K

1%
1/16W

2

1

R7541

180pF

50V

5%

402

CERM

2

1

C7540

499

MF-LF

1%

1/16W

402

21

R7545

21

7

79 23 14

7

62

26

47

26 14

LFPAK

HAT2165H

CRITICAL

321

4

5

Q7501

HAT2165H

CRITICAL

LFPAK

321

4

5

Q7502

HAT2168H

CRITICAL

LFPAK

321

4

5

Q7500

22uF

X7R

1210

20%
16V

2

1

C7510

1210

16V
X7R

20%

22uF

2

1

C7511

20%

22uF

1210

X7R

16V

2

1

C7512

402

10K

1/16W
MF-LF

1%

21

R7555

CRITICAL

LFPAK

HAT2168H

321

4

5

Q7550

0.22UF

20%

402

X5R

6.3V

21

C7555

MF-LF

1%

3.65K

603

1/10W

2

1

R7556

CRITICAL

HAT2165H

LFPAK

321

4

5

Q7552

0.0022UF

CERM

10%
50V

402

NO STUFF

2

1

C7552

CRITICAL

HAT2165H

LFPAK

321

4

5

Q7551

0.0022UF

10%
50V
CERM
402

NO STUFF

2

1

C7551

1uF

10%
402

6.3V
CERM

2

1

C7530

MF-LF

1/16W

5%

10

402

21

R7530

X7R

1210

20%
16V

22uF

C7513

402

MF-LF

1/16W

1%

2.0K

NO STUFF

2

1

R7536

1%

1.40K

1/16W
402

MF-LF

2

1

R7533

CERM

50V

470pF

10%
402

2

1

C7533

6.3V
402

0.22uF

X5R

20%

2

1

C7544

11K

1/16W

1%

402

MF-LF

2

1

R7543

MF-LF

402

1/16W

1%

30.1K

21

R7593

MF-LF

1/16W

402

1%

30.1K

21

R7591

603

X5R

10%

1uF

16V

2

1

C7528

4.7uF

CERM

6.3V

20%

603

2

1

C7529

402

1/16W
MF-LF

10

5%

21

R7531

1/16W

5%

10

402

MF-LF

21

R7528

CERM

16V

10%

0.01uF

402

2

1

C7546

1/16W

402

1%

4.02K

MF-LF

2

1

R7547

402

MF-LF

1/16W

1%

499

2

1

R7544

20%

6.3V
X5R
402

0.22UF

2

1

C7541

10%

CERM

402

0.0068uF

25V

2

1

C7580

NO STUFF

0.001uF

50V

10%

402

CERM

2

1

C7542

MF-LF

1/16W

402

1%

2.61K

2

1

R7548

402

0.047uF

CERM

16V

10%

2

1

C7543

MF-LF

1/16W

1

5%

402

2

1

R7507

5%
1/16W
MF-LF

1

402

2

1

R7557

NO STUFF

CERM

10%
16V

0.01uF

402

2

1

C7581

10%
16V

0.01uF

CERM

402

2

1

C7582

1/16W
MF-LF

5%

402

0

21

R7581

5%
1/16W
MF-LF

402

0

21

R7582

MF-LF

1/16W

1%

1M

402

21

R7598

SOT23-5

LMV2011MF

2

5

1

4

3

U7595

1/16W

402

MF-LF

1M

1%

21

R7592

51

1uF

402

10%

6.3V
CERM

2

1

C7595

0603-LF

CRITICAL

10KOHM-5%

2

1

R7549

402

CERM

10%
50V

470pF

21

C7598

10%
50V

CERM

470pF

402

21

C7592

402

390pF

10%
50V
CERM

2

1

C7534

CRITICAL

SMB

B340LBXF

2

1

D7500

CRITICAL

B340LBXF

SMB

2

1

D7550

470K

402

CRITICAL

2

1

R7546

22uF

1210

X7R

16V

20%

C7563

1210

22uF

X7R

16V

20%

2

1

C7562

22uF

16V

1210

X7R

20%

2

1

C7561

22uF

X7R

1210

20%
16V

2

1

C7560

CRITICAL

SM-PCC

0.36uH

21

L7505

CRITICAL

0.36uH

SM-PCC

21

L7555

MF-LF

402

1/16W

0

5%

21

R7594

402

CERM

10V

20%

NO STUFF

0.1uF

2

1

C7594

SM

2 1

XW7530

IMVP6 CPU VCore Regulator

051-6941

12

75

104

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

IMVP6_ISEN2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

IMVP6_PHASE1

IMVP_DPRSLPVR

PM_DPRSLPVR

VR_PWRGOOD_DELAY

IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>

IMVP6_VID<0>

CPU_DPRSTP_L

VR_PWRGD_CK410_L

IMVP6_VID<3>

IMVP6_VID<1>

IMVP6_VID<2>

IMVP6_COMP_RC

IMVP_VR_ON

IMVP_PWRGD_IN

IMVP6_NTC_R

IMVP6_RBIAS

IMVP6_SOFT

IMVP6_NTC

IMVP6_COMP

IMVP6_FB

IMVP6_VDIFF_RC

IMVP6_VDIFF

IMVP6_FB2

=PP3V3_S0_IMVP6

=PPVIN_S0_IMVP6

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PPVIN_S0_IMVP6_R

VOLTAGE=12V

=PP5V_S0_IMVP6

IMVP6_VR_TT

IMVP6_VO_R

IMVP6_UGATE1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

IMVP6_ISEN1

=PPVIN_S0_IMVP6

=PPVOUT_S0_IMVP6_REG

CPUISENS_POS

IMVP6_LGATE1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

IMVP6_LGATE2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

IMVP6_DROOP

=PP3V3R5V_S0_CPUISENS

CPUVCORE_IOUT

CPU_VCCSENSE_N

CPU_VCCSENSE_P

IMVP6_DROOP

IMVP6_PHASE2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

IMVP6_BOOT2

IMVP6_BOOT1

IMVP6_VW

GND_IMVP6_SGND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_IMVP6_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

PP5V_S0_IMVP6_VDD

MIN_NECK_WIDTH=0.25 mm

IMVP6_UGATE2

MIN_LINE_WIDTH=0.5 mm

IMVP6_DFB

CPU_PSI_L

IMVP6_VO

IMVP6_OCSET

IMVP6_VSUM

CPUISENS_NEG

IMVP6_VSEN_N

IMVP6_VSEN_P

CPUISENS_NEG_RC

63

63

79

79

79

9

9

9

9

9

9

9

5

5

63

57

63

57

63

57

63

8

8

57

79

79

NC4

NC3

NC2

NC1

EXTVCC

FCB

INTVCC

PGOOD

3_3VOUT

RUN_SS2

ITH2

RUN_SS1

ITH1

SW1

TG1

BOOST1

BG1

PLLIN

SENSE1+
SENSE1-

VOSENSE1

BOOST2

TG2

BG2

SW2

PLLFLTR

SENSE2+

VOSENSE2

SENSE2-

THRML_PAD

SGND

PGND

VIN

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

5V S0 FET

<Ra>

8A max output
(L7620 limit)

Vout = 4.98V

NC

NC
NC
NC

NC

NC

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

<Rb>

Vout = 1.49V
8A max output
(L7660 & Q7660 limit)

If unconnected, powers up with VIN.

5V S3 FET

<Rb>

NOTE: Be aware of pull-ups to VIN on these signals.

Connect to RUNSS pins to control outputs.

CRITICAL

CMDSH-3

SOD-323

2

1

D7624

1uF

CERM

402

10%

6.3V

2

1

C7605

16V

10%

402

0.01uF

CERM

2

1

C7607

22uF

20%
16V
X7R
1210

2

1

C7640

1/16W

5%

402

MF-LF

1M

2

1

R7630

0.1uF

20%
CERM

402

10V

2

1

C7630

22K

5%
1/16W

402

MF-LF

2

1

R7625

50V

10%

402

470pF

CERM

2

1

C7625

50V

5%

402

47pF

CERM

2

1

C7626

10

402

1/16W
MF-LF

5%

2

1

R7600

10%
X5R

603

1uF

16V

2

1

C7600

CRITICAL

QFN

LTC3728LXC

91

33

14

26

15

6

11

1230

1328

2

27

19

32

29

16

10

8

5

20

4

21

17

18

7

U7600

CRITICAL

CMDSH-3

SOD-323

2

1

D7664

10V

20%
402

CERM

0.1uF

2

1

C7670

CERM

50V

10%

402

470pF

2

1

C7665

100pF

CERM

402

5%

50V

2

1

C7666

10K

MF-LF

402

5%

1/16W

2

1

R7665

CERM

50V

0.001uF

402

10%

2

1

C7662

470pF

50V

10%

402

CERM

2

1

C7627

52.3K

1/16W

402

MF-LF

1%

2

1

R7627

25V
402

X7R

1000pF

NO STUFF

10%

2

1

C7628

10K

1/16W
MF-LF

402

1%

2

1

R7628

IHLP2525CZ-SM

CRITICAL

2.2uH-14A

21

L7660

MF-LF

39.2K

1/16W

1%

402

2

1

R7668

NO STUFF

25V

10%
402

X7R

1000pF

2

1

C7668

34.0K

1/16W

1%
MF-LF

402

2

1

R7667

470pF

CERM

402

10%
50V

2

1

C7667

MF-LF

1/16W

5%

402

1M

2

1

R7670

402

6.3V

10%

1uF

CERM

2

1

C7602

603

6.3V

20%

4.7uF

CERM

2

1

C7601

MF-LF
402

5%
1/16W

30K

2

1

R7603

1K

MF-LF
402

5%
1/16W

2

1

R7604

0.01uF

CERM
402

10%
16V

2

1

C7604

22uF

20%
16V
X7R
1210

2

1

C7641

22uF

20%
16V
X7R

1210

2

1

C7680

X7R

22uF

20%
16V

1210

2

1

C7681

MF-LF
402

1/16W

0

5%

2

1

R7664

MF-LF

0

402

5%

1/16W

2

1

R7624

FDC796N

SUPERSOT-6

CRITICAL

65321

4

7

Q7660

B240-X-F

SMB

CRITICAL

2

1

D7621

SUPERSOT-6

FDC796N

CRITICAL

65321

4

7

Q7620

SUPERSOT-6

FDC796N

CRITICAL

65321

4

7

Q7621

NO STUFF

10%
25V
X7R
402

1000pF

2

1

C7661

402

0.1uF

CERM

10V

20%

2

1

C7664

805

X5R

6.3V

20%

22uF

2

1

C7690

805

X5R

6.3V

20%

22uF

2

1

C7691

20%
10V
CERM
402

0.1uF

2

1

C7624

NO STUFF

402

X7R

25V

10%

1000pF

2

1

C7621

10%

CERM

50V

0.001uF

402

2

1

C7622

20%

CRITICAL

SMC-LF

POLY

6.3V

150uF

2

1

C7652

20%

22uF

6.3V
X5R
805

2

1

C7650

X5R
805

22uF

20%

6.3V

2

1

C7651

1/16W

5%

402

MF-LF

0

P5VP1V5_SKIP

2

1

R7606

0

MF-LF
402

P5VP1V5_CONT

5%
1/16W

2

1

R7607

SM

21

XW7600

402

0.1uF

X5R

16V

10%

2

1

C7620

3.9K

402

MF-LF

1/16W

5%

2

1

R7620

402

X5R

16V

10%

0.1uF

2

1

C7623

1%

402

MF-LF

1.33K

1/16W

2

1

R7623

402

0.1uF

X5R

16V

10%

2

1

C7660

1%

402

1/16W
MF-LF

3.65K

2

1

R7660

10%
16V
X5R
402

0.1uF

2

1

C7663

1%

909

402

MF-LF

1/16W

2

1

R7663

CASE-D2E-LF

330uF

CRITICAL

POLY

20%

2.5V-ESR9V

2

1

C7692

CRITICAL

IRF7832PBF

SO-8

321

4

8765

Q7661

SM5

4.7uH

CRITICAL

21

L7620

1%

1.21K

MF-LF

1/16W

402

2

1

R7669

1%

1.21K

MF-LF

1/16W
402

2

1

R7629

22uF

805

X5R

6.3V

20%

2

1

C7617

22uF

805

X5R

6.3V

20%

2

1

C7616

0.0022uF

402

CERM

50V

10%

21

C7615

FDC638P

SM-LF

4

3

6
5
2
1

Q7615

100K

5%
1/16W
MF-LF

402

21

R7615

FDC638P

SM-LF

4

3

6
5
2
1

Q7610

0.0022uF

402

CERM

10%
50V

21

C7610

MF-LF

1/16W

5%

402

100K

21

R7610

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

5V / 1.5V Power Supply

051-6941

12

104

76

=PP5V_S5_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P5VS5_SW

=PPVIN_S5_P5VP1V5

=PP5V_S5_P5VP1V5_VCC

=P5VS3_EN_L

P5VS5_VOSNS

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm

GND_P5VP1V5_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P5VS5_SNS_N

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P5VS5_SNS_P

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_BOOST_RC

=PP1V5_S0_REG

P1V5S0_VOSNS
P1V5S0_ITH

=P5VP1V5_PGOOD

P5VS5_RUNSS

PP5V_S5_P5VP1V5_INTVCC

MIN_LINE_WIDTH=0.6 mm

P5VS5_BOOST_RC

MIN_NECK_WIDTH=0.25 mm

P5VS5_TG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P5VS5_BOOST

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V5S0_SNS_R_N

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V5S0_SW

P5VP1V5_FCB

P5VS0_EN_L_RC

=PP5V_S3_FET

=P5VS0_EN_L

=PP5V_S0_FET

=PP5V_S0_P5VS0

P5VS3_EN_L_RC

=PP5V_S3_P5VS3

PP5V_S5_P5VP1V5_INTVCC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_TG

P1V5S0_ITH_RC

P5VS5_ITH_RC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V5S0_BG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V5S0_SNS_R_P

P1V5S0_RUNSS

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=12V

MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_P5VP1V5_R

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5V

PP5V_S5_P5VP1V5_INTVCC

MIN_LINE_WIDTH=0.6 mm

P5VP1V5_FSEL

P5VS5_ITH

MIN_LINE_WIDTH=0.6 mm

P5VS5_BG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V5S0_BOOST

P5VP1V5_FSEL

62

63

63

63

62

63

62

5

58

63

62

63

63

63

58

58

58

58

PVINSVIN

SHDN/RT
SYNC/MODE

SW
VFB
ITH

PGOOD

PGND SGND

SW

SGND PGND

PAD

THERM

SVIN PVIN

PGOOD

VFB

ITH
SYNC/MODE

RUN/SS

RT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Rb>

(Switcher limit)

2.5A max output

Vout = 1.205V

(Switcher limit)

1.25A max output

Vout = 2.52V

<Ra>

1.2V S3 Regulator

<Ra>

<Rb>

<Rc>

Vout = 0.8V * (1 + Ra / (Rb + Rc))

Vout = 0.8V * (1 + Ra / Rb)

1.2V S0 FET

2.5V S0 FET

2.5V S3 Regulator

Mode

Continuous

If unconnected, powers up with PVIN.

Connect RUNSS off-page to control

NOTE: Be aware of pull-up on this signal.

Burst Continuous

LTC3411

CRITICAL

MSOP-LF

9

2

4

7

1

3

6

8

5

10

U7700

CERM

100pF

402

5%

50V

2

1

C7703

4.99K

MF-LF

402

1%

1/16W

2

1

R7706

0.0033uF

CERM
402

10%
50V

2

1

C7704

2.2uH-1.32A

CDRH4D18-SM

CRITICAL

21

L7700

22pF

5%

CERM

402

50V

2

1

C7706

10K

1/16W

1%
MF-LF

402

2

1

R7707

4.7K

MF-LF
402

1%
1/16W

2

1

R7708

805

X5R

22uF

20%

6.3V

2

1

C7709

1uF

CERM
402

10%

6.3V

2

1

C7701

1/16W

5%

402

MF-LF

10

21

R7700

10UF

603

X5R

6.3V

20%

2

1

C7700

MF-LF
402

1%

324K

1/16W

2

1

R7705

1M

MF-LF

402

5%

1/16W

2

1

R7704

1/16W

5%

402

MF-LF

1M

2

1

R7701

SM

21

XW7700

6.3V

20%
805

X5R

22uF

2

1

C7756

6.3V

20%

805

X5R

22uF

2

1

C7755

22uF

X5R
805

20%

6.3V

2

1

C7752

805

22uF

X5R

6.3V

20%

2

1

C7751

50V

5%

402

CERM

22pF

2

1

C7750

1/16W

1%

402

MF-LF

47.0K

2

1

R7750

MF-LF

402

1%

1/16W

61.9K

2

1

R7751

SM-LF

CRITICAL

1.0UH-3.48A

21

L7750

MF-LF

402

1%

1/16W

30.9K

2

1

R7752

CRITICAL

TSSOP-LF

LTC3412

4

17

6

15

14

11

10

1

8

7

5

16

9

2

13

12

3

U7750

SM

21

XW7750

309K

MF-LF
402

1%
1/16W

2

1

R7754

50V

470pF

CERM

402

10%

2

1

C7757

1/16W

5%

402

MF-LF

0

NO STUFF

2

1

R7755

5.1M

1/16W

5%

402

MF-LF

2

1

R7757

0

MF-LF
402

5%
1/16W

2

1

R7756

CERM

402

5%

50V

22pF

2

1

C7754

MF-LF

402

1%

1/16W

8.25K

2

1

R7753

CERM
402

10%
50V

0.0022uF

2

1

C7753

SI3446DV

TSOP-LF

4

36

5

2

1

Q7720

50V

0.0022uF

10%

CERM

402

2

1

C7720

402

5%
1/16W
MF-LF

100K

21

R7720

TSOP-LF

SI3446DV

4

36

5

2

1

Q7770

10%
50V

402

0.0022uF

CERM

2

1

C7770

5%
1/16W
MF-LF

0

402

21

R7770

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

2.5V & 1.2V Regulators

12

051-6941

77

104

=PPVIN_S3_P1V2S3

P1V2S3_RT

P1V2S3_VFB_DIV

P1V2S3_ITH_RC

P1V2S3_RUNSS

P1V2S3_MODE

P1V2S3_ITH

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=0V

GND_P1V2S3_SGND

P2V5S3_SHDNRT
P2V5S3_MODE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=0V

GND_P2V5S3_SGND

=PPVIN_S3_P2V5S3

=P2V5S3_EN_L

=PP2V5_S0_P2V5S0

=PP2V5_S0_FET

=P1V2S0_EN

P1V2S0_EN_RC

=PP1V2_S0_P1V2S0

=PP1V2_S0_FET

=P2V5S0_EN

P2V5S0_EN_RC

=P1V2S3_PGOOD

MIN_NECK_WIDTH=0.25 mm

P2V5S3_SW

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V2S3_SW

P1V2S3_VFB

=PP1V2_S3_REG

P2V5S3_VFB

=PP2V5_S3_REG

P2V5S3_ITH_RC

=P2V5S3_PGOOD

P2V5S3_ITH

PPVIN_S3_P2V5S3_SVIN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

39

63

5

5

5

5

63

39

63 63

62

63 63

62

62

63

63

62

39

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD
COMP

FSET

ISEN

FB
VO

BOOT

VIN

THRML

PAD

VCC

OUT

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1.8V S3 Current Sense

(Q7820 limit)

17A max output

Vout = 0.6V * (1 + Ra / Rb)

<Rb>

(P1V8S3_FB)

R7894 and R7897

<Ra>

NC

close to inductor

Placement Note:

Keep C7890, R7890,

1.8V S0 FET

Vout = 1.83V

20%

2.5V-ESR9V

CASE-D2E-LF

POLY

330uF

2

1

C7842

1/16W
MF-LF

402

3.32K

1%

2

1

R7821

1.62K

MF-LF

402

1%

1/16W

2

1

R7822

1.0uH-20.5

SM1

CRITICAL

3

2

1

L7820

LFPAK

HAT2168H

CRITICAL

321

4

5

Q7820

CRITICAL

B340LBXF

SMB

2

1

D7820

3.01K

1/16W

1%

402

MF-LF

21

R7810

6.3V

2.2UF

603

CERM1

20%

2

1

C7802

603

CERM1

2.2UF

20%

6.3V

2

1

C7800

603

10%

1uF

16V
X5R

2

1

C7801

CRITICAL

QFN

ISL6269

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U7800

15PF

CERM

402

5%

50V

2

1

C7807

64.9K

MF-LF
402

1%
1/16W

2

1

R7808

50V

10%

0.0022uF

402

CERM

2

1

C7808

MF-LF

0

5%

1/16W

NO STUFF

402

2

1

R7804

1/16W

5%

402

MF-LF

0

2

1

R7805

57.6K

MF-LF
402

1%
1/16W

2

1

R7806

0.01UF

CERM

402

10%
16V

2

1

C7806

22uF

X7R

16V
1210

20%

2

1

C7831

1210

X7R

16V

22uF

20%

2

1

C7830

22uF

20%
X5R

6.3V
805

2

1

C7840

805

6.3V
X5R

22uF

20%

2

1

C7841

CASE-D2E-LF

330uF

20%

2.5V-ESR9V
POLY

2

1

C7843

1000pF

402

X7R

25V

10%

NO STUFF

2

1

C7822

402

10%

1000pF

X7R

25V

NO STUFF

2

1

C7821

SM

21

XW7800

22uF

20%
X7R

16V
1210

2

1

C7833

16V
X7R
1210

20%

22uF

2

1

C7832

402

NO STUFF

MF-LF

1/16W

5%

0

2

1

R7802

LFPAK

HAT2165H

CRITICAL

321

4

5

Q7822

HAT2165H

LFPAK

CRITICAL

321

4

5

Q7821

51

1uF

CERM
402

10%

6.3V

2

1

C7895

10%

CERM

402

470pF

50V

2 1

C7898

1/16W

1%

1M

MF-LF

402

21

R7898

LMV2011MF

SOT23-5

2

5

1

4

3

U7895

50V

CERM

10%

402

470pF

2 1

C7892

1%

1M

1/16W
MF-LF

402

21

R7892

10KOHM-5%

CRITICAL

0603-LF

2

1

R7897

1%

1K

402

1/16W
MF-LF

2

1

R7896

20.0K

MF-LF

402

1/16W

1%

21

R7893

1/16W

20.0K

402

MF-LF

1%

21

R7891

NO STUFF

1/16W
MF-LF

402

1K

1%

21

R7894

1uF

402

CERM

6.3V

10%

2 1

C7890

649

1%

MF-LF

402

1/16W

2

1

R7890

SUPERSOT-6

FDC796N

6
5
3
2
1

4

7

Q7845

22uF

6.3V
805

X5R

20%

2

1

C7847

20%

6.3V
805

22uF

X5R

2

1

C7846

402

CERM

50V

10%

0.0022uF

2

1

C7845

5%
1/16W
MF-LF

402

0

21

R7845

X5R

0.22uF

402

6.3V

20%

2

1

C7809

0

5%
1/16W
MF-LF

402

2

1

R7809

402

CERM

10%

0.0022uF

50V

NO STUFF

2

1

C7820

5%

NO STUFF

0

1/16W
MF-LF
402

2

1

R7820

402

MF-LF

1/16W

5%

470K

2

1

R7846

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

1.8V Supply

051-6941

78

104

12

MIN_NECK_WIDTH=0.25 mm

P1V8S3_UG

MIN_LINE_WIDTH=0.6 mm

=PP1V8_S3_REG

P1V8S3_FB

=PP3V3R5V_S3_P1V8ISENS

P1V8ISENS_POS

P1V8S3_IOUT

P1V8ISENS_NEG

P1V8ISENS_NTC

=PP5V_S3_P1V8S3

P1V8S3_ISEN

P1V8S3_COMP

=PP1V8_S0_FET

GND_P1V8S3_SGND

P1V8ISENS_RC

P1V8S3_COMP_R

PP5V_S3_P1V8S3_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

P1V8S3_FSET

P1V8S3_LG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P1V8S3_FB_RC

P1V8S3_BOOT

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V8S3_BOOT_R

MIN_NECK_WIDTH=0.25 mm

P1V8S3_FCCM

=P1V8S3_EN

=P1V8S3_PGOOD

=P1V8S0_EN

P1V8S0_EN_RC

=PP1V8_S0_P1V8S0

=PPVIN_S3_P1V8S3

=PPBUS_S0_P1V8S0

P1V8S3_PHASE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

63 51

63

63

5

63

5

62

62

62

63

63

63

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

OUT

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD
COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

G

D

S

G

D

S

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4.5A max output

3.3V S3 FET

Vout = 3.32V

<Rb>

<Ra>

3.3V S0 FET

(L7920 limit)

3.3V S5 Regulator

1.05V S0 Regulator

(Q7970 & L7970 limit)

10A max output

Vout = 1.05V

Placement Note:

Keep C7990, R7990,
R7994 and R7997
close to inductor

NC

<Ra>

(P1V05S0_FB)

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

1.05V Current Sense

Vout = 0.6V * (1 + Ra / Rb)

603

X5R

10%

1uF

16V

2

1

C7951

QFN

ISL6269

CRITICAL

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U7950

50V

5%

402

CERM

15PF

2

1

C7957

CERM

402

20%
16V

0.01uF

2

1

C7958

MF-LF
402

1%
1/16W

30.9K

2

1

R7958

1/16W

5%
MF-LF

0

NO STUFF

402

2

1

R7954

0

MF-LF
402

5%
1/16W

2

1

R7955

57.6K

1%

402

MF-LF

1/16W

2

1

R7956

16V

10%
402

CERM

0.01UF

2

1

C7956

SO-8

CRITICAL

IRF7832PBF

321

4

8765

Q7971

POLY

20%

330uF

CASE-D2E-LF

2.5V-ESR9V

2

1

C7989

22uF

X7R

16V

20%
1210

2

1

C7982

MBRS140XXG

SMB

CRITICAL

2

1

D7920

20%
X7R

16V
1210

22uF

2

1

C7930

NO STUFF

1/16W
MF-LF
402

5%

0

2

1

R7902

NO STUFF

402

0

MF-LF

5%
1/16W

2

1

R7952

50V

470pF

CERM

10%

402

2 1

C7998

1uF

CERM
402

10%

6.3V

2

1

C7995

402

MF-LF

1/16W

1M

1%

21

R7998

LMV2011MF

SOT23-5

2

5

1

4

3

U7995

50V

470pF

402

CERM

10%

2 1

C7992

402

MF-LF

1/16W

1M

1%

21

R7992

CRITICAL

0603-LF

10KOHM-5%

2

1

R7997

402

MF-LF

1/16W

1K

1%

2

1

R7996

1%

1/16W

402

MF-LF

20.0K

21

R7993

10%

6.3V
CERM

402

1uF

2 1

C7990

MF-LF

1%

1/16W

20.0K

402

21

R7991

1%

1K

402

MF-LF

1/16W

NO STUFF

21

R7994

1%

1/16W

402

MF-LF

649

2

1

R7990

51

0

402

5%
1/16W
MF-LF

21

R7949

20%
16V

0.01uF

NO STUFF

402

CERM

2

1

C7949

402

10%
25V
CERM

0.0047uF

2

1

C7920

0

1/16W
MF-LF

402

5%

2 1

R7920

402

CERM

10%

0.0047uF

25V

21

C7947

SM-LF

FDC638P

4

3

6
5
2
1

Q7947

402

MF-LF

1/16W

5%

100K

21

R7947

0.0022uF

402

CERM

50V

10%

21

C7945

SM-LF

FDC638P

4

3

6
5
2
1

Q7945

402

MF-LF

1/16W

5%

100K

21

R7945

5%

0

1/16W
MF-LF

402

2

1

R7909

0.22uF

402

X5R

6.3V

20%

2

1

C7909

0

5%
1/16W
MF-LF

402

2

1

R7959

20%

6.3V
X5R
402

0.22uF

2

1

C7959

402

CERM

10%

0.0022uF

50V

NO STUFF

2

1

C7970

402

MF-LF

1/16W

0

5%

NO STUFF

2

1

R7970

1210

22uF

20%
X7R

16V

2

1

C7980

1210

16V
X7R

20%

22uF

2

1

C7981

3.01K

MF-LF

402

1%

1/16W

21

R7910

SMC-LF

POLY

20%

150uF

6.3V

2

1

C7942

603

2.2UF

CERM1

20%

6.3V
2

1

C7902

10%
25V
X7R
402

NO STUFF

1000pF

2

1

C7921

SM

21

XW7900

2.2UF

CERM1

603

20%

6.3V

2

1

C7900

10%
X5R

1uF

603

16V

2

1

C7901

ISL6269

QFN

CRITICAL

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U7900

10%

470pF

CERM

402

50V

2

1

C7907

0.022uF

CERM-X5R

10%
16V

402

2

1

C7908

NO STUFF

MF-LF

1/16W

5%

0

402

2

1

R7904

51.1K

402

MF-LF

1/16W

1%

2

1

R7908

1/16W

5%

402

MF-LF

0

2

1

R7905

1/16W

57.6K

MF-LF

1%

402

2

1

R7906

16V

10%
402

CERM

0.01UF

2

1

C7906

22uF

805

6.3V
X5R

20%

2

1

C7941

805

22uF

20%

6.3V
X5R

2

1

C7940

3.32K

MF-LF

402

1%

1/16W

2

1

R7921

MF-LF

402

1%

1/16W

732

2

1

R7922

FDC796N

SUPERSOT-6

CRITICAL

65321

4

7

Q7920

4.7uH

CRITICAL

IHLP

21

L7920

SUPERSOT-6

CRITICAL

FDC796N

65321

4

7

Q7921

2.2UF

CERM1

603

20%

6.3V
2

1

C7952

20%

22uF

X5R

6.3V
805

2

1

C7986

805

22uF

20%

6.3V
X5R

2

1

C7985

1/16W

1%

402

MF-LF

3.32K

2

1

R7971

1/16W

1%

MF-LF

4.42K

402

2

1

R7972

SM

1.53uH

CRITICAL

3

2

1

L7970

CRITICAL

SUPERSOT-6

FDC796N

65321

4

7

Q7970

402

MF-LF

1%

1/16W

2.8K

21

R7960

1000pF

402

X7R

25V

10%

NO STUFF

2

1

C7971

SM

21

XW7950

2.2UF

CERM1

603

20%

6.3V
2

1

C7950

051-6941

79

104

12

SYNC_DATE=(MASTER)

3.3V / 1.05V Power Supplies

SYNC_MASTER=(MASTER)

=PPVIN_S5_P3V3S5

P1V05S0_IOUT

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_UG

P3V3S5_FSET

=PPVIN_S0_P1V05S0

P1V05ISENS_NTC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE

P1V05S0_PHASE

P1V05ISENS_RC

P1V05S0_FB

=PP1V05_S0_REG

P1V05ISENS_NEG

P1V05ISENS_POS

=PP3V3R5V_S0_P1V05ISENS

P1V05S0_FB_RC

P3V3S5_FCCM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_S5_P3V3S5_VCC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_S0_P1V05S0_VCC

P1V05S0_FCCM

=P1V05S0_PGOOD

=P1V05S0_EN

GND_P1V05S0_SGND

P1V05S0_FSET

P1V05S0_COMP

=PP5V_S0_P1V05S0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_LG

P1V05S0_COMP_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

P1V05S0_BOOT

P1V05S0_ISEN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_UG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V05S0_BOOT_R

=PP5V_S5_P3V3S5

=PP3V3_S5_REG

GND_P3V3S5_SGND

P3V3S5_FB_RC

P3V3S5_FB

=P3V3S0_EN_L

P3V3S0_EN_L_RC

=PP3V3_S0_FET

=PP3V3_S0_P3V3S0

P3V3S5_BOOT

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P3V3S5_PHASE

P3V3S5_BOOT_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P3V3S5_COMP

=P3V3S5_EN

=P3V3S5_PGOOD

=P3V3S3_EN_L

P3V3S5_EN_RC

P3V3S5_LG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

P3V3S3_EN_L_RC

=PP3V3_S3_FET

P3V3S5_COMP_R

P3V3S5_ISEN

=PP3V3_S3_P3V3S3

63 51

63

5

63

5

63

62

62

5

5

63

63

63

62

63

63

5

62

48

62

63

63

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

G

D

S

V-

V+

OUT

THRML

V2V1

RST*

V3
V4
VADJ1
VADJ2

GND

PAD

IN

G

D

S

G

D

S

OUT

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

IN

IN

IN

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

State

Soft-Off (S5)

Sleep (S3)

Run (S0)

Battery Off (G3Hot)

0

1

1
1

SMC_PM_G2_ENABLE

0
0

1

1

PM_SLP_S4_L

0

0

0

1

PM_SLP_S3_L

(Switcher limit)

200mA max output

Vout = 3.425

<Ra>

<Rb>

NC

Vout = 1.25V * (1 + Ra / Rb)

before enabling GPU VCore to support
removing ethernet power in battery sleep.

Ensure 1.2V and 2.5V S3 supplies are up

by ethernet power control circuit.

2.5V S3 and 1.2V S3 supplies are controlled

5V Enable has pull-up to PBUS

(PM_SLP_S3_L)

(P5VS5_PGOOD)

(PM_SLP_S4_L)

PowerPlay is changing

deassert while GPU

GPU core voltage.

Need to ensure that

Power Control Signals

LTC2908 sources 6uA at 5.0V

and 3.3V level-shifter.

R8075 serves as pull-down

1.5V Comp threshold set to 1.32V (88%)

Reports when 5V S0, 3.3V S0, 2.5V S0, 1.8V S0, 1.2V S0 and 0.9V S0 are in regulation

LTC2908 threshold is 95% (4.75V, 3.135V, 2.375V, 1.71V, 1.14V, 0.86V)

Other S0 Rails PWRGD Circuit

ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)
NOTE: R8065 acts as 10K pull-up for PGOOD signal

Reports when 1.5V S0 and 1.05V S0 are in regulation

1.5V / 1.05V PWRGD Circuit

0.89V Reference

ISL6269 PGOOD does not

1.8V Enable has pull-up to PBUS

Unused PGOOD Signals

3.3V rise after VCore is up.

GPU requires 1.2V, 1.8V, 2.5V and

1.5V Enable has pull-up to PBUS

TSOT23-8

CRITICAL

LT3470

3

51

2

4

8

6

7

U8000

0

402

5%
1/16W
MF-LF

NO STUFF

21

R8060

2N7002DW-X-F

SOT-363

4

5

3

Q8056

10uF

X5R

1206

10%
25V

2

1

C8000

22uF

X5R
805

20%

6.3V

2

1

C8015

200K

MF-LF
402

1%
1/16W

2

1

R8011

1/16W

5%

402

MF-LF

10K

2

1

R8065

10V

20%

402

CERM

0.1uF

2

1

C8060

SM-LF

LMC7211

2

5

1

3

4

U8060

SC70

MC74VHC1G08

5

4

1

2

3

U8080

402

CERM

10V

0.1UF

20%

2

1

C8080

57

10V

20%
402

CERM

0.1uF

2

1

C8071

LLP

LTC2908

CRITICAL

8

6

3

7

45

9

2

1

U8070

1/16W

1%

402

MF-LF

549K

2

1

R8076

1/16W

1%

402

MF-LF

4.99K

2

1

R8063

1/16W

1%

402

MF-LF

27.4K

2

1

R8061

1/16W

1%

402

MF-LF

10K

2

1

R8064

1/16W

1%

402

MF-LF

10K

2

1

R8062

10V

20%
402

CERM

0.1uF

2

1

C8070

124K

1/16W

1%

402

MF-LF

2

1

R8072

100K

1/16W

1%

402

MF-LF

2

1

R8073

61

1/16W

1%

402

MF-LF

68.1K

2

1

R8074

1/16W

1%

402

MF-LF

100K

2

1

R8075

1/16W

5%

402

MF-LF

10K

2

1

R8051

1/16W

5%

402

MF-LF

10K

2

1

R8050

SOT-363

2N7002DW-X-F

1

2

6

Q8057

SOT-363

2N7002DW-X-F

1

2

6

Q8050

47 26

1/16W

5%

402

MF-LF

100K

2

1

R8054

SOT-363

2N7002DW-X-F

4

5

3

Q8057

348K

MF-LF
402

1%
1/16W

2

1

R8010

5%

402

MF-LF

10K

1/16W

2

1

R8055

SOT-363

2N7002DW-X-F

1

2

6

Q8055

2N7002DW-X-F

SOT-363

4

5

3

Q8055

CRITICAL

33uH

CDPH4D19F-SM

21

L8010

2N7002DW-X-F

SOT-363

4

5

3

Q8059

470K

MF-LF
402

5%
1/16W

2

1

R8059

2N7002DW-X-F

SOT-363

1

2

6

Q8059

SOT-363

2N7002DW-X-F

4

5

3

Q8050

66

22pF

CERM

402

5%

50V

2

1

C8010

1/16W

5%

402

100K

MF-LF

2

1

R8056

47 41 23

1/16W

5%

402

MF-LF

100K

2

1

R8057

47 39 23

1/16W

5%

402

MF-LF

100K

2

1

R8058

48

47

0.22uF

X5R
402

20%

6.3V
2

1

C8005

59

59

MF-LF
402

5%
1/16W

10K

2

1

R8053

10K

MF-LF
402

5%
1/16W

2

1

R8052

12

051-6941

80

104

3.3V G3Hot Supply & Power Control

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MAKE_BASE=TRUE

P2V5S3_P1V2S3_PGOOD

=PP3V42_G3H_PWRCTL

=PP5V_S5_PWRCTL

PM_SLP_S3_LS5V_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

P3V3S0_EN_L

=P1V8S3_PGOOD

TP_P1V8S3_PGOOD

MAKE_BASE=TRUE

=P5VP1V5_PGOOD

TP_P5V_P1V5_PGOOD

MAKE_BASE=TRUE

=P1V8S0_EN

MAKE_BASE=TRUE

P1V8S0_EN

=P2V5S0_EN
=P1V2S0_EN

=P3V3S0_EN_L

MAKE_BASE=TRUE

PM_SLP_S3_LS5V

=P1V05S0_PGOOD

S0PGOOD_1V2_DIV
S0PGOOD_0V9_DIV

P1V5S0_COMP_POS

P1V0_P1V5PG_REF

P1V5S0_PGOOD

IMVP_PWRGD_IN

ALL_SYS_PWRGD

=PP3V3_S5_P1V5PG

PP5V_S0

S0PGOOD_PWROK

PP3V3_S0

MAKE_BASE=TRUE

P1V5P1V05S0_PGOOD

=PP3V3_S0_ALLSYSPG

PP1V8_S0

PP2V5_S0

PP1V2_S0
PP0V9_S0

PP1V5_S0

=GPUVCORE_PGOOD

MAKE_BASE=TRUE

P5VS5_PGOOD

=P2V5S3_PGOOD
=P1V2S3_PGOOD

SMC_PM_G2_EN

SMC_PM_G2_EN_L

=P3V3S5_EN

LIO_P3V3S3_EN

=RTUSB_EN

=P1V8S3_EN

=P5VS3_EN_L

=P3V3S3_EN_L

MAKE_BASE=TRUE

GPUVCORE_EN

=GPUVCORE_EN

PM_SLP_S3

=PBUSVSENS_EN

=MEMVREF_EN

=ENET_VMAIN_AVLBL

=P1V05S0_EN

LIO_P3V3S0_EN_L

=P5VS0_EN_L

MAKE_BASE=TRUE

PM_SLP_S4_L

MAKE_BASE=TRUE

PM_SLP_S4_LS5V

PM_SLP_S3_L

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

P5VS5_RUNSS

=PP5V_S5_PWRCTL

P1V5S0_RUNSS

=PP3V42_G3H_REG

P3V42G3H_FB

MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

=PPVIN_G3H_P3V42G3H

P3V42G3H5_BOOST

63

63

45

45

63

58

63

58

62

62

60

58

60

59

59

61

63

63

63

63

63

63

63

63

63

61

5

44

60

58

61

66

51

32

37

61

5

58

62

5

62

5

63

5

63

JUMPER

JUMPER

JUMPER

JUMPER

JUMPER

JUMPER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"S3AC" rail is ON in S3 on AC, OFF in S3 on battery

OPEN

PLACEMENT_NOTE=Place on top-side of board

21

XW8115

PLACEMENT_NOTE=Place on top-side of board

0

MF-LF

1/8W

5%

805

21

R8133

PLACEMENT_NOTE=Place on top-side of board

OPEN

21

XW8133

PLACEMENT_NOTE=Place on top-side of board

OPEN

21

XW8150

OPEN

PLACEMENT_NOTE=Place on top-side of board

21

XW8119

OPEN

PLACEMENT_NOTE=Place on top-side of board

21

XW8118

OPEN

PLACEMENT_NOTE=Place on top-side of board

21

XW8125

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

Power Aliases

104

051-6941

12

81

=PP3V42_G3H_REG

PP1V8_S3_REG

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE

PP2V5_S3

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.6 mm

=PP1V5_S0_SB_VCCUSBPLL

=PP1V8_S3_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0_GPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PP1V8_S3

VOLTAGE=1.8V

PP1V8_S0

VOLTAGE=1.8V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP2V5_S0

MIN_NECK_WIDTH=0.25 mm

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S3_P3V3S3AC
=PP3V3_S3_RTALS

=PP3V3_S0_FET

=PP3V3_S0_CK410

=PP3V3_S0_DDC_DVI
=PP3V3_S0_DDC_LCD

=PP3V3_S3_TOPCASE
=PP3V3_S3_LTALS

=PP3V3_S3_BT

=PP3V3_S3_SMS

=PP3V3_S3_TPM

=PP3V3_S3_SMBUS_SMC_A_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=3.425V

PP3V42_G3H

=PP3V42_G3H_PWRCTL

MIN_NECK_WIDTH=0.25 mm

PP3V3_S5

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_S3_P3V3S3

=PP3V3_S0_P3V3S0

=PP3V42_G3H_LIO

=PP3V3_S5_LPCPLUS

=PP3V3_S5_SMC

=PP3V3_S3AC_FET

=PP3V3_S3_ENET

=PPVIN_S5_P3V3S5

=PPVIN_S0_IMVP6

=PPVIN_S5_P5VP1V5

=PPBUS_G3H_S3AC

=PP3V3_S5_SB

=PP1V5_S0_NB_PCIE

=PP3V42_G3H_PBUSVSENS

=PP1V8_S0_FET

=PP2V5_S3_REG

=PP1V8_S0_FB_VDD
=PP1V8_S0_FB_VDDQ

=PP1V8_S0_P1V8S0

=PP2V5_S3_ENET
=PP2V5_S0_P2V5S0

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S3_FET

=PP3V3_S0_LCD

=PPVIN_S3_P2V5S3

=PP3V3_S5_FWLATEVG

=PP3V3_S5_P1V5PG

=PP3V3_S5_ROM

=PP3V3_S5_REG

=PP3V3_S5_SB_USB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB_IO

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V42_G3H_LIDSWITCH

=PP3V42_G3H_SMC_CLK

=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMC_PWRGD

=PP3V42_G3H_SMCVREF

=PP1V05_S0_REG

=PP1V05_S0_FSB_NB

=PP1V05_S0_CPU

=PP0V9_S0_MEM_TERM

=PP1V05_S0_NB_VTT

=PP0V9_S0_MEMVTT_LDO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PP0V9_S0

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.38 mm

PP3V3_S5_REG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.22 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.2V

PP1V2_S3

VOLTAGE=1.2V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PP1V2_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

PPVCORE_S0_GPU

PP2V5_S3_REG

MIN_NECK_WIDTH=0.3 mm
MAKE_BASE=TRUE

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.6 mm

=PP1V2_S3_REG

=PP1V2_S0_PCIE_GPU_VDDR

=PP1V5_S0_CPU
=PP1V5_S0_NB
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_LIO

=PP1V8_S3_MEM
=PP1V8_S3_MEM_NB
=PP1V8_S3_MEMVREF
=PP1V8_S0_MEMVTT

=PP1V8R2V0_S0_FB_GPU

=PP2V5_S0_NB_VCCA_3GBG
=PP2V5_S0_GPU
=PP2V5_S0_GPU_PVDD
=PP2V5_S0_GPU_VDD25
=PP2V5_S0_GPU_VDDC_CT

=PPVCORE_S0_GPU
=PPVCORE_S0_GPU_BBP

=PPVIN_G3H_P3V42G3H

=PP1V2_S0_FET

=PP1V5_S0_REG

=PP2V5_S0_FET

=PPVCORE_S0_GPU_REG

=PPDCIN_G3H_LIO

=PPVCORE_S0_SB

=PPVCORE_S0_NB

=PP1V05_S0_SB_CPU_IO
=PP1V05_S0_PHYSSEC

=PP1V2_S0_P1V2S0

=PP1V2_S3_ENET

PPDCIN_G3H

VOLTAGE=18.5V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_NB_CRT

=PP1V2_S0_PCIE_GPU

=PP1V2_S0_GPU_VDDPLL

=PP1V2_S0_PCIE_GPU_PVDD

PP1V5_S0_REG

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

PP5V_S5_REG

MIN_NECK_WIDTH=0.3 mm
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5V

=PPFW_PORT1

=PPBUS_S5_FW_FET

=PP5V_S5_SB
=PP5V_S5_P3V3S5
=PP5V_S5_P5VP1V5_VCC
=PP5V_S5_LIO
=PP5V_S5_PWRCTL

=PP5V_S3_P1V8S3

=PP5V_S3_P5VS3

=PP5V_S3_RTUSB

=PP5V_S0_GPUVCORE

=PP5V_S0_P5VS0

=PP5V_S0_P1V05S0

=PP5V_S3_SYSLED
=PP5V_S3_CAMERA

=PP5V_S5_REG

PPBUS_S5_FW_FET

VOLTAGE=33V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.5 mm

=PPBUS_S5_FWPWRSW

=PPBUS_G3H_LIO_CONN

=PPVIN_S3_P1V8S3
=PPVIN_S0_P1V05S0
=PPVIN_S0_GPUVCORE
=PPBUS_S0_INVERTER
=PPBUS_S0_P1V8S0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPBUS_G3H

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.22 mm

MIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

PP3V3_S3AC

MAKE_BASE=TRUE

PP1V05_S0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP5V_S3_FET

VOLTAGE=5V

PP5V_S5

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_S0

=PP5V_S0_IDE

=PP5V_S0_DVI_DDC

=PP5V_S0_HDD
=PP5V_S0_IMVP6
=PP5V_S0_INVERTER

=PP5V_S0_FAN_LT

=PP5V_S0_SB

=PP5V_S0_MEMVTT

=PP5V_S0_KBDLED

=PP5V_S0_FAN_RT

=PP5V_S0_LPCPLUS
=PP5V_S0_AUDIO_XW

=PP5V_S0_GPUBBCTL

=PP5V_S0_ISENSECAL

=PP5V_S0_FET

=PP5V_S3_IR
=PP5V_S3_TOPCASE

VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S3

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP1V5_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0

=PP3V3_S3_MEMVREF

=PPVOUT_S0_IMVP6_REG

=PPVOUT_S0_GPUBBP_LDO

=PNVOUT_S0_GPUBBN_REG

=PPVCORE_S0_CPU

=PPBB_S0_GPU

=PNBB_S0_GPU

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

MAKE_BASE=TRUE

PPBB_S0_GPU

VOLTAGE=1.9V

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=-0.7V

PNBB_S0_GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP3V3_S0

PP3V3_S0_GPU

VOLTAGE=3.3V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_S0_IMVP6

=PP3V3_S0_IDE

=PP3V3_S0_INVERTER
=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB

=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_PM

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0_SB_VCC3_3

=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_TPM

=PP3V3_S0_KBDLED

=PP3V3_S0_VGASYNC

=PP3V3_S0_THRM_SNR

=PP3V3_S0_RSTHMSNS

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SB

=PP3V3_S0_RSTBUF

=PP3V3_S0_SMBUS_SMC_BSB

=PP3V3_S0_SMC_LS

=PP3V3_S0_FAN_LT

=PP3V3_S0_ALLSYSPG

=PP3V3_S0_FAN_RT
=PP3V3_S0_FWISENS
=PP3V3R5V_S0_CPUISENS

=PP3V3R5V_S0_P1V05ISENS

=PP3V3R5V_S0_GPUISENS

=PP3V3R5V_S0_P1V8ISENS
=PPSPD_S0_MEM

=PP3V3_S0_GPUBBP

=PP3V3_S0_GPU

=PP3V3_S0_GPU_VDDR3

=PP3V3_S0_GPUBBN

=PP3V3_S0_GPU_GPIOS
=PP1V8R3V3_S0_GPU_VDDR4
=PP1V8R3V3_S0_GPU_VDDR5

=PPVIN_S3_P1V2S3

=PP3V3_S3_FW
=PP3V3_S3_PCI
=PP3V3R5V_S3_P1V8ISENS

MIN_LINE_WIDTH=0.5 MM

PP3V3_S3

VOLTAGE=3.3V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

GND

MIN_NECK_WIDTH=0.2 mm

11

26

61

34

9

19

19

72

25

51

20

72

25

60

25

34

76

55

56

45

49

48

25

19

71

71

23

51

19

8

19

9

17

19

25

25

25

25

45

29

16

68

19

67

45

25

19

24

45

43

64

25

25

54

49

51

9

19

19

25

25

23

25

25

25

25

29

69

62

5

24

51

62

62

24

39

53

61

33

75

74

43

5

76

48

48

27

62

61

61

5

5

47

39 37

61

57

58

39

23

13

51

60

59

70

70

60

37

59

27

61

74

59

42

62

52

61

22

11

22

24

43

35

26

48

48

5

12

7

30

17

31

62

62

5

59

65

8

19

19

19

19

19

16

17

25

24

24

24

24

5

28

14

32

31

67

17

73

72

72

72

51

66

62

59

58

59

66

5

24

16

21

59

37

19

65

72

65

5

42 41

25

61

58

5

62

60

58

44

66

58

61

48

5

58

41

5

60

61

66

74

60

51

24

24

58

48

62

36

75

76

57

74

5

25

31

53

54

5

45

66

5

58

76

43

62

32

57

66

66

8

67

67

5

62

57

36

74

14

17

24

22

21

26

26

24

24

24

24

56

53

75

10

50

50

27

27

27

26

27

48

54

62

54

41

57

61

66

28

66

66

72

66

69

72

72

59

40

40

60

OUT

BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0368

518S0293

Battery Connector (Digital Signals)

NC

NC

Left I/O Power Connector

48

47

5

27

5

27

5

CRITICAL

SM-2MT-LF

4

3

2

1

6

5

J8250

CRITICAL

M-RT-SM

87438

6

5

4

3

2

1

J8200

5%
1/16W
MF-LF
402

10

2

1

R8250

051-6941

12

104

82

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PBus-In & Battery Connectors

SMC_BS_ALRT_L

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

GND_BATT

=PPBUS_G3H_LIO_CONN

63 5 5

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PCIE_PVSS

PCIE_VDDR_12

PCIE_PVDD_12

PCIE_VSS

(1.2V)

(1.2V)

PCIE_VSS

(2 OF 7)

PCI EXPRESS POWER & GROUND

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

OUT

PCIE_REFCLKP
PCIE_REFCLKN

PERST*
PERST*_MASK

PCIE_TEST

PCIE_RX15N

PCIE_RX14P

PCIE_RX13N

PCIE_RX12N

PCIE_RX12P

PCIE_RX1P

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P

PCIE_TX2N

PCIE_TX1N

PCIE_TX2P

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8N

PCIE_TX8P

PCIE_TX9P

PCIE_TX10P

PCIE_TX9N

PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13N

PCIE_TX13P

PCIE_TX14N

PCIE_TX14P

PCIE_TX15N

PCIE_TX15P

PCIE_CALRP
PCIE_CALRN

PCIE_CALI

PCIE_RX1N

PCIE_RX2N

PCIE_RX2P

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6N

PCIE_RX6P

PCIE_RX7N

PCIE_RX7P

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX13P

PCIE_RX14N

PCIE_RX0N

PCIE_RX0P

PCIE_RX15P

PCI-EXPRESS BUS INTERFACE

(1 OF 7)

OUT

OUT

OUT

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100mA

NC

2000mA

13

X5R 402

0.1uF

16V10%

21

C8481

402

0.1uF

X5R16V10%

21

C8482

13

13

0.1uF

40216V10% X5R

21

C8479

402

0.1uF

X5R16V10%

21

C8480

13

13

402

0.1uF

X5R16V10%

21

C8477

402X5R16V10%

0.1uF

21

C8478

13

13

402

0.1uF

X5R16V10%

21

C8475

402

0.1uF

X5R16V10%

21

C8476

13

13

402

0.1uF

X5R16V10%

21

C8473

402

0.1uF

X5R16V10%

21

C8474

13

40210% 16V X5R

0.1uF

21

C8420

13

402

0.1uF

X5R16V10%

21

C8471

402

0.1uF

X5R16V10%

21

C8472

13

13

402

0.1uF

X5R16V10%

21

C8469

402

0.1uF

X5R16V10%

21

C8470

13

13

402

0.1uF

X5R16V10%

21

C8467

10%

0.1uF

16V X5R 402

21

C8421

402

0.1uF

X5R16V10%

21

C8468

13

13

402

0.1uF

X5R16V10%

21

C8465

402

0.1uF

X5R16V10%

21

C8466

13

13

402

0.1uF

X5R16V10%

21

C8463

402

0.1uF

X5R16V10%

21

C8464

13

10% 16V X5R

0.1uF

402

21

C8450

13

402

0.1uF

X5R16V10%

21

C8461

402

0.1uF

X5R16V10%

21

C8462

13

13

402

0.1uF

X5R16V10%

21

C8459

402

0.1uF

X5R16V10%

21

C8460

13

13

402

0.1uF

X5R16V10%

21

C8457

10% 16V X5R 402

0.1uF

21

C8451

0.1uF

402X5R16V10%

21

C8458

MF-LF

1/16W
402

1%

562

2

1

R8496

1%

2.0K

MF-LF
402

1/16W

2

1

R8495

1.47K

1%

402

MF-LF

1/16W

2

1

R8497

BGA

M56P

OMIT

R24

AL27

AK32

R23

AK31

AK30

AK29

AK26

AJ32

AJ30

AJ29

AJ28

AJ26

AH29

P30

AH27

AH26

AH24

AG31

AG29

AG26

AG25

AF30

AF29

AF28

P29

AF26

AE29

AE27

AE26

AD31

AD29

AD26

AD25

AC30

AC29

P28

AC28

AC26

AC24

AC23

AB29

AB27

AB26

AB23

AA31

AA29

P26

AA26

AA25

AA23

Y30

Y29

Y28

Y26

Y24

W29

W27

P25

W26

W24

V31

V29

V26

V25

V24

U30

U29

U28

P24

U26

U24

T29

T27

T26

T24

R31

R29

R26

R25

N30

N24

AM27

AL32

AL31

AL30

AL29

N29

N28

N27

AM31

AM30

AM29

AM28

N26

N25

W23

V23

U23

P23

N23

U8400

CERM

1uF

6.3V
402

10%

2

1

C8402

10% 16V X5R

0.1uF

402

21

C8448

402

CERM

10%

6.3V

1uF

2

1

C8401

10%

6.3V

CERM

402

1uF

2

1

C8407

10% 16V X5R

0.1uF

402

21

C8449

10%

6.3V

CERM

402

1uF

2

1

C8413

1uF

402

CERM

6.3V

10%

2

1

C8406

1uF

402

CERM

6.3V

10%

2

1

C8411

10%

6.3V
CERM

402

1uF

2

1

C8412

20%
X5R

805

6.3V

22uF

2

1

C8400

22uF

6.3V
805

X5R

20%

2

1

C8410

10% 16V X5R

0.1uF

402

21

C8446

22uF

6.3V
805

X5R

20%

2

1

C8405

200-OHM-EMI

0402

2

1

L8400

10% 16V X5R

0.1uF

402

21

C8447

10% 16V X5R

0.1uF

402

21

C8444

10% 16V X5R

0.1uF

402

21

C8445

10% 16V X5R

0.1uF

402

21

C8442

10% 16V X5R

0.1uF

402

21

C8443

10% 16V X5R

0.1uF

402

21

C8440

10% 16V X5R

0.1uF

402

21

C8441

10% 16V X5R

0.1uF

402

21

C8438

10% 16V X5R 402

0.1uF

21

C8439

10% 16V X5R

0.1uF

402

21

C8436

10% 16V X5R

0.1uF

402

21

C8437

10% 16V X5R

0.1uF

402

21

C8434

10% 16V X5R

0.1uF

402

21

C8435

10% 16V X5R

0.1uF

402

21

C8432

10% 16V X5R

0.1uF

402

21

C8433

10% 16V X5R

0.1uF

402

21

C8430

10% 16V X5R 402

0.1uF

21

C8431

10% 16V X5R

0.1uF

402

21

C8428

10% 16V X5R

0.1uF

402

21

C8429

10% 16V X5R

0.1uF

402

21

C8426

10% 16V X5R

0.1uF

402

21

C8427

16V X5R

0.1uF

40210%

21

C8424

10% 16V X5R

0.1uF

402

21

C8425

0.1uF

10% X5R 40216V

21

C8422

10% 16V X5R

0.1uF

402

21

C8423

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

34

34

26

10% 16V X5R

0.1uF

402

21

C8455

10% 16V X5R

0.1uF

402

21

C8456

13

M56P

BGA

OMIT

AF24

AG24

AA27
Y27

AB28
AA28

AC25
AB25

AD27
AC27

AE28
AD28

AF25
AE25

AG27
AF27

AH28
AG28

AJ25
AH25

R27
P27

T28
R28

U25
T25

V27
U27

W28
V28

Y25
W25

AK27
AJ27

AA24

Y31
W31

AA32

Y32

AB30
AA30

AC31
AB31

AD32
AC32

AE30
AD30

AF31
AE31

AG32
AF32

AH30
AG30

P31
N31

R32
P32

T30
R30

U31
T31

V32
U32

W30
V30

AJ31
AH31

AL28
AK28

AD24
AE24

AB24

U8400

13

13

13

402

0.1uF

X5R16V10%

21

C8485

402

0.1uF

X5R16V10%

21

C8486

13

13

402

0.1uF

X5R16V10%

21

C8483

402

0.1uF

X5R16V10%

21

C8484

13

051-6941

SYNC_DATE=(MASTER)

12

104

84

ATI M56 PCI-E

SYNC_MASTER=(MASTER)

=PP1V2_S0_PCIE_GPU

PEG_D2R_C_P<15>

PEG_D2R_C_P<14>

PEG_D2R_C_P<13>

PEG_D2R_C_P<12>

PEG_D2R_C_P<11>

PEG_D2R_C_P<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<8>

PEG_D2R_C_P<7>

PEG_D2R_C_P<6>

PEG_D2R_C_P<5>

PEG_D2R_C_P<4>

PEG_D2R_C_P<3>

PEG_D2R_C_P<2>

PEG_D2R_C_P<1>

PEG_D2R_C_P<0>

PEG_D2R_N<15>

PEG_D2R_N<14>

PEG_D2R_P<15>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_P<10>

PEG_D2R_N<10>

PEG_D2R_P<9>

PEG_D2R_N<9>

PEG_D2R_N<8>

PEG_D2R_P<8>

PEG_D2R_N<7>

PEG_D2R_P<7>

PEG_D2R_N<6>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_N<1>

PEG_D2R_P<1>

PEG_D2R_N<0>

PEG_D2R_P<0>

PEG_D2R_C_N<15>

PEG_D2R_C_N<14>

PEG_D2R_C_N<13>

PEG_D2R_C_N<12>

PEG_D2R_C_N<11>

PEG_D2R_C_N<10>

PEG_D2R_C_N<9>

PEG_D2R_C_N<8>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_N<3>

PEG_D2R_C_N<1>

PEG_D2R_C_N<0>

GPU_PCIE_CALRN

PEG_R2D_C_N<15>

PEG_CLK100M_GPU_N

PEG_RESET_L

PEG_CLK100M_GPU_P

PEG_R2D_C_P<15>

PEG_R2D_C_N<12>

PEG_R2D_C_P<13>

PEG_R2D_C_P<12>

PEG_R2D_C_N<11>

PEG_R2D_C_P<11>

PEG_R2D_C_N<10>

PEG_R2D_C_P<10>

PEG_R2D_C_N<9>

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_P<6>

PEG_R2D_C_N<4>

PEG_R2D_C_P<4>

PEG_R2D_C_N<3>

PEG_R2D_C_P<3>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_N<1>

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_P<15>

PEG_R2D_P<14>

PEG_R2D_P<13>

PEG_R2D_P<12>

PEG_R2D_P<11>

PEG_R2D_P<10>

PEG_R2D_P<9>

PEG_R2D_P<8>

PEG_R2D_P<7>

PEG_R2D_P<6>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_R2D_P<2>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_N<15>

PEG_R2D_N<14>

PEG_R2D_N<13>

PEG_R2D_N<12>

PEG_R2D_N<10>

PEG_R2D_N<11>

PEG_R2D_N<7>

PEG_R2D_N<8>

PEG_R2D_N<9>

PEG_R2D_N<5>

PEG_R2D_N<6>

PEG_R2D_N<3>

PEG_R2D_N<2>

PEG_R2D_N<1>

PEG_R2D_N<0>

GPU_PCIE_CALI

GPU_PCIE_CALRP

PEG_R2D_C_N<14>

PEG_R2D_C_P<14>

PEG_R2D_C_N<13>

=PP1V2_S0_PCIE_GPU_PVDD

PP1V2_S0_PCIE_GPU_PVDD_F

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

PEG_R2D_C_P<5>

PEG_R2D_N<4>

PEG_D2R_C_N<2>

=PP1V2_S0_PCIE_GPU_VDDR

PEG_R2D_C_P<9>

PEG_R2D_P<5>

PEG_D2R_N<12>

63

63

63

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD
COMP

FSET

ISEN

FB
VO

BOOT

VIN

THRML

PAD

VCC

PG
EN

VIN

ADJ

VOUT

GND

G

D

S

OUT

G

D

S

G

D

S

G

D

S

CAP-

FB

OUT

SHDN_L

CAP+

LIN/SKIP_L

IN

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Vout = (1.58V /) 1.50V

Req = Rb || Rc

Vout(low) = 0.59V * (1 + Ra/Rb)

<Rc>

B13: Vout = 1.08V / 1.00V

B24: Vout = 1.10V / 0.95V

17A max output
(Q8520 limit)

(GPUVCORE_FB)

Keep C8590, R8590,
R8594 and R8597

<Ra>

Vout(low) = 0.6V * (1 + Ra / Rb)

Placement Note:

GPU VCore Supply

close to inductor

GPU VCore Current Sense

Ra = Vin / 50 uA

Back-Bias Negative Supply

Vout = -0.50V
125mA max output
(Regulator limit)

Vout = -Vin * Rb / Ra
Recommended values:

Rb = -Vout / 50 uA

<Ra>

<Rb>

Back-bias negative supply provides VSS - 0.5V when active.
When inactive, provides VSS to BBN pins.

NC

satisfy BBP FET Vgs (where Vs = 1.2V)

(LDO limit)

<Ra>

<Rb>

180mA max output

When inactive, provides VDDC to BBP pins.

For proper M56 power sequence, this

Vin must be > 2.8V

SI3446DV max Vgs is 1.6V

Pull-up voltage must be high enough to

NOTE: BBP tracks VDDC based on GPU voltage GPIO.

pull-up must be powered before VCore

Vout(high) = 0.59V * (1 + Ra/Req)

Req = Rb || Rc

Vout(high) = 0.6V * (1 + Ra / Req)

Back-bias positive supply provides VDDC + 0.5V when active.

Back-Bias Positive Supply

<Rb>

<Rc>

330uF

POLY

CASE-D2E-LF

20%

2.5V-ESR9V

2

1

C8542

3.01K

1/16W
MF-LF

1%

402

2

1

R8521

5.11K

1%

MF-LF

1/16W

402

2

1

R8522

1210

X7R

20%
16V

22uF

2

1

C8532

CRITICAL

1.0uH-20.5

SM1

3

2

1

L8520

LFPAK

HAT2168H

CRITICAL

321

4

5

Q8520

SMB

B340LBXF

CRITICAL

2

1

D8520

HAT2165H

LFPAK

CRITICAL

321

4

5

Q8522

1/16W

1%

3.01K

402

MF-LF

21

R8510

CERM1

2.2UF

6.3V

20%
603

2

1

C8502

6.3V

CERM1

20%
603

2.2UF

2

1

C8500

603

16V

10%
X5R

1uF

2

1

C8501

QFN

ISL6269

CRITICAL

8

1

2

14

17

12

15

16

10

11

9

7

3

6

4

5

13

U8500

CERM

402

50V

15pF

5%

2

1

C8507

MF-LF
402

1%
1/16W

150K

2

1

R8508

10%
402

50V

CERM

470pF

2

1

C8508

1/16W

0

MF-LF

5%

402

2

1

R8504

NO STUFF

MF-LF
402

5%
1/16W

0

2

1

R8505

1/16W

1%

402

MF-LF

57.6K

2

1

R8506

16V

10%

402

CERM

0.01UF

2

1

C8506

X7R

22uF

1210

20%
16V

2

1

C8531

20%

22uF

16V
X7R
1210

2

1

C8530

6.3V

20%
X5R

805

22uF

2

1

C8540

22uF

X5R

20%

6.3V
805

2

1

C8541

LFPAK

HAT2165H

CRITICAL

321

4

5

Q8521

SM

21

XW8500

NO STUFF

10%

402

X7R

1000pF

25V

2

1

C8522

NO STUFF

1000pF

X7R

10%
25V

402

2

1

C8521

22uF

X5R
805

20%

6.3V
2

1

C8556

22uF

X5R

20%

6.3V
805

2

1

C8557

1/16W
MF-LF
402

1%

24.9K

2

1

R8555

16.2K

1/16W

1%

402

MF-LF

2

1

R8556

16V

10%

402

CERM

0.01UF

2

1

C8555

FAN2558

SOT23-6-LF

CRITICAL

61

4

2

3 5

U8550

CERM1

603

2.2uF

6.3V

20%

2

1

C8551

330uF

20%

2.5V-ESR9V
CASE-D2E-LF

POLY

2

1

C8543

12.4K

402

1%

MF-LF

1/16W

21

R8523

NO STUFF

1/16W

5%
MF-LF

0

402

2

1

R8502

1/16W

5%

402

MF-LF

10K

2

1

R8560

2N7002

SOT23-LF

2

1

3

Q8570

100K

MF-LF

5%

1/16W

402

2

1

R8570

CERM
402

16V

10%

0.01uF

2

1

C8570

GPU_BB_CTL

0

MF-LF

402

5%

1/16W

21

R8561

50V

470pF

402

CERM

10%

2 1

C8598

51

402

50V

470pF

CERM

10%

2 1

C8592

402

MF-LF

1M

1%

1/16W

21

R8598

LMV2011MF

SOT23-5

2

5

1

4

3

U8595

402

1M

1%

MF-LF

1/16W

21

R8592

1uF

CERM
402

10%

6.3V

2

1

C8595

20.0K

MF-LF

402

1/16W

1%

21

R8593

20.0K

1%

MF-LF

402

1/16W

21

R8591

1/16W
MF-LF

402

1%

649

2

1

R8590

1%

1K

402

MF-LF

1/16W

NO STUFF

21

R8594

CERM

10%

402

1uF

6.3V

2 1

C8590

10KOHM-5%

CRITICAL

0603-LF

2

1

R8597

402

MF-LF

1/16W

1K

1%

2

1

R8596

NO STUFF

1%
1/16W

174K

402

MF-LF

2

1

R8554

0.1uF

402

10%
16V
X5R

2

1

C8523

5%
1/16W
MF-LF

402

10K

2

1

R8524

0

402

MF-LF

5%

1/16W

21

R8525

NO STUFF

10%
50V

0.0022uF

CERM

402

2

1

C8520

MF-LF

1/16W

5%

402

100K

2

1

R8526

2N7002DW-X-F

SOT-363

4

5

3

Q8523

2N7002DW-X-F

SOT-363

1

2

6

Q8523

NO STUFF

2N7002

SOT23-LF

2

1

3

Q8554

MF-LF

1/16W

66.5K

402

1%

2

1

R8587

MF-LF

1/16W

402

1%

10K

2

1

R8588

2.2uF

603

CERM1

6.3V

20%

2

1

C8581

6.3V
X5R

10uF

20%
603

2

1

C8580

805

22uF

X5R

20%

6.3V

2

1

C8589

SOI

MAX1673

CRITICAL

4

5

1

8

7

6

2

3

U8580

SI3446DV

TSOP-LF

4

3 6

5

2

1

Q8575

1/16W

5%

402

MF-LF

0

NO STUFF

2

1

R8520

0.22UF

402

X5R

6.3V

20%

2

1

C8509

402

MF-LF

1/16W

0

5%

2

1

R8509

051-6941

SYNC_MASTER=(MASTER)

104

12

85

GPU (M56) Core Supplies

SYNC_DATE=(MASTER)

=PPVCORE_S0_GPU_REG

GND_GPUVCORE_SGND

GPUBBP_ADJ

GPUBB_EN_L

=PPVCORE_S0_GPU_BBP

GPUBB_EN_L

=PPVOUT_S0_GPUBBP_LDO

GPUBB_EN

GPU_GENERICD

=PP5V_S0_GPUBBCTL

GPU_VCORE_HIGH

GPUBB_EN

=PP3V3_S0_GPUBBP

GPUBBP_ADJ_LOW

GPUVCORE_COMP_R

GPUVCORE_FSET

GPUVCORE_COMP

GPUVCORE_FCCM

=GPUVCORE_EN

=GPUVCORE_PGOOD

=PP3V3R5V_S0_GPUISENS

GPUVCORE_IOUT

MIN_NECK_WIDTH=0.25 mm

GPUVCORE_LG

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_UG

MIN_NECK_WIDTH=0.25 mm

GPUVCORE_ISEN

=PP3V3_S0_GPU

GPU_VCORE_HIGH

GPU_VCORE_LOW

GPU_VCORE_HIGH_RC

=PP3V3_S0_GPUBBN

=PNVOUT_S0_GPUBBN_REG

GPUBBN_CAPN

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

GPUBBN_CAPP

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

GPUBBN_FB

GPUBB_EN

PP5V_S0_GPUVCORE_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GPUVCORE_BOOT

GPUVCORE_BOOT_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

GPUISENS_RC

GPUISENS_NEG

GPUISENS_POS

GPUVCORE_FB_RC

GPUVCORE_FB_LOW

GPUISENS_NTC

=PP5V_S0_GPUVCORE
=PPVIN_S0_GPUVCORE

GPUVCORE_PHASE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

GPUVCORE_FB

72 69

63

5

66

63

66

63

66

72

63

66

66

63

5

5

62

62

63

63

66

69

63

63

66

63

63

MEMORY & CORE POWER / GROUND

(1.0V/1.2V)

(1.0V/1.2V)

(7 OF 7)

VDDR1

VSS

VSS

(1.8V/2.0V)

VSS

VDDC

BBP BBN

VDDCI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100mA (Preliminary)

100mA (Preliminary)

2.0A @ 500MHz 1.8V GDDR3

14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

- =PP1V5_GPU_VDD15

Power aliases required by this page:

Page Notes

Signal aliases required by this page:

BOM options provided by this page:

- =PP1VR1V3_GPU_VCORE

(NONE)

(NONE)

OMIT

BGA

M56P

P17

P15

P7

P6

P5

P1

N8

N7

N3

M32

A31

M28

M24

M9

M8

M7

M6

M3

L29

L7

L6

A25

L1

K30

K27

K17

K16

K12

K10

J30

J28

J24

A22

J21

J16

J12

J9

J6

J3

H32

H28

H21

H20

A19

H16

H7

H5

H1

G25

G22

G21

G20

G19

G16

A16

G13

F30

F27

F24

F22

F21

F19

F18

F16

F15

A13

F13

F10

F6

F3

E32

E30

E28

E25

E19

E16

A11

E13

E12

E9

E8

E5

D30

D11

C27

C24

C21

A8

C20

C18

C15

C10

AM13

AM2

AL13

AL1

AK16

AJ10

AH16

AH11

AH10

C9

AG23

AG16

AG11

AF16

AF14

AE17

AE16

AE15

AE14

AE8

C6

AD17

AD16

AD15

AD14

AD13

AD10

AD9

AD8

AD7

AD6

C5

AC10

AC9

AA6

AA4

Y7

Y6

Y5

Y1

W18

W16

C4

V19

V17

V6

V3

U18

U14

U10

U9

U8

U7

B32

U6

U5

U1

T19

T15

T10

R16

R14

R6

R3

B1

A2

K23

C32

C1

A30

A24

A21

AA1

Y10

Y9

Y8

A18

V1

R9

R1

P10

P9

P8

N10

N9

M10

M1

A15

L32

L24

L23

K24

K21

K20

K19

K13

K11

J32

A12

J20

J19

J18

J13

J11

J10

J1

H19

H13

F32

A9

A3

W17

W10

U19

T23

T14

P16

K14

T18

T17

T16

R19

R18

R17

R15

AD11

AC12

AC11

P19

W19

W15

W14

V18

V16

V15

V14

U17

U16

U15

P18

P14

AC14

V10

M23

K18

AC17

Y23

R10

K15

U8400

0.1uF

402

X5R

16V

10%

2

1

C8697

10%

402

1uF

CERM

6.3V

2

1

C8696

10%

402

1uF

CERM

6.3V

2

1

C8691

0.1uF

402

X5R

16V

10%

2

1

C8692

CERM

6.3V

1uF

402

10%

2

1

C8610

6.3V
CERM

1uF

402

10%

2

1

C8609

6.3V
CERM

1uF

402

10%

2

1

C8608

6.3V
CERM

1uF

402

10%

2

1

C8607

6.3V
CERM

1uF

402

10%

2

1

C8606

6.3V
CERM

1uF

402

10%

2

1

C8605

402

6.3V
CERM

1uF

10%

2

1

C8604

10%

402

1uF

CERM

6.3V

2

1

C8616

10%

402

1uF

CERM

6.3V

2

1

C8615

10%

402

1uF

CERM

6.3V

2

1

C8614

10%

402

1uF

CERM

6.3V

2

1

C8613

10%

402

1uF

CERM

6.3V

2

1

C8612

MF-LF

1/10W

603

5%

0

2

1

R8630

6.3V
CERM

1uF

402

10%

2

1

C8634

6.3V
CERM

1uF

402

10%

2

1

C8633

6.3V
CERM

1uF

402

10%

2

1

C8632

6.3V
CERM

1uF

402

10%

2

1

C8631

6.3V
CERM

1uF

402

10%

2

1

C8660

10%

402

1uF

CERM

6.3V

2

1

C8666

6.3V
CERM

1uF

402

10%

2

1

C8659

6.3V
CERM

1uF

402

10%

2

1

C8658

6.3V
CERM

1uF

402

10%

2

1

C8657

10%

402

1uF

CERM

6.3V

2

1

C8665

10%

402

1uF

CERM

6.3V

2

1

C8664

10%

402

1uF

CERM

6.3V

2

1

C8663

6.3V
CERM

1uF

402

10%

2

1

C8656

10%

402

1uF

CERM

6.3V

2

1

C8662

6.3V
CERM

1uF

402

10%

2

1

C8655

10%

402

1uF

CERM

6.3V

2

1

C8661

6.3V
CERM

1uF

402

10%

2

1

C8672

10%

402

1uF

CERM

6.3V

2

1

C8678

6.3V
CERM

1uF

402

10%

2

1

C8671

6.3V
CERM

1uF

402

10%

2

1

C8670

6.3V
CERM

1uF

402

10%

2

1

C8669

10%

402

1uF

CERM

6.3V

2

1

C8677

10%

402

1uF

CERM

6.3V

2

1

C8676

10%

402

1uF

CERM

6.3V

2

1

C8675

6.3V
CERM

1uF

402

10%

2

1

C8668

10%

402

1uF

CERM

6.3V

2

1

C8674

CERM

6.3V

1uF

402

10%

2

1

C8667

10%

402

1uF

CERM

6.3V

2

1

C8673

6.3V
X5R

22uF

805

20%

2

1

C8653

20%

6.3V
X5R
805

22uF

2

1

C8652

X5R

6.3V

22uF

805

20%

2

1

C8651

22uF

805

X5R

6.3V

20%

2

1

C8650

10%

402

1uF

CERM

6.3V

2

1

C8683

10%

402

1uF

CERM

6.3V

2

1

C8682

10%

402

1uF

CERM

6.3V

2

1

C8681

10%

402

1uF

CERM

6.3V

2

1

C8680

6.3V
CERM

1uF

402

10%

2

1

C8679

22uF

805

X5R

6.3V

20%

2

1

C8601

6.3V
CERM

1uF

402

10%

2

1

C8611

20%

6.3V
X5R
805

22uF

2

1

C8690

20%

6.3V
X5R
805

22uF

2

1

C8695

20%

6.3V
X5R
805

22uF

2

1

C8630

20%

6.3V
X5R
805

22uF

2

1

C8600

ATI M56 Core Power

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

12

051-6941

104

86

=PNBB_S0_GPU

=PP1V8R2V0_S0_FB_GPU

=PPVCORE_S0_GPU

=PPBB_S0_GPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PPVCORE_S0_GPU_VDDCI

VOLTAGE=1.2V

72

68

63

63

63

51

63

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI
BI

BI

BI
BI

BI
BI

BI
BI

BI

BI
BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN
IN
IN

IN

IN

IN
IN

BI
BI
BI
BI
BI
BI
BI
BI BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DQA_58
DQA_59

WEA1*

DQA_61
DQA_62

MVREFD_0
MVREFS_0

VDDRH0

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15

DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*

QSA_1

QSA_2

QSA_0

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*

CLKA0
CLKA0*

CSA0_0*

CKEA0

RASA0*

CASA0*

WEA0*

ODTA0

CLKA1*

CSA1_0*

CKEA1

RASA1*

CASA1*

ODTA1

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43

DQA_45

DQA_44

DQA_46
DQA_47
DQA_48

DQA_50
DQA_51

DQA_49

DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57

DQA_60

DQA_63

VSSRH0

CLKA1

CSA0_1*

CSA1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE A

(3 OF 7)

2.0V)

(1.8V/

DQB_62

VDDRH1

MVREFS_1

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11
MAB_12

MAB_15

MAB_14

MAB_13

DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*

QSB_0

QSB_1

QSB_2

QSB_4

QSB_3

QSB_5

QSB_6

QSB_7

QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*

CLKB0*

CLKB0

CSB0_0*

CKEB0

RASB0*

WEB0*

CASB0*

ODTB0

CLKB1
CLKB1*

CKEB1

RASB1*

WEB1*

CASB1*

ODTB1

DRAM_RST

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12

DQB_15

DQB_14

DQB_13

DQB_16
DQB_17
DQB_18

DQB_20

DQB_19

DQB_22

DQB_21

DQB_23

DQB_25

DQB_24

DQB_27

DQB_26

DQB_28

DQB_30

DQB_29

DQB_33

DQB_31
DQB_32

DQB_35

DQB_34

DQB_37

DQB_36

DQB_38

DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46

DQB_48

DQB_47

DQB_52
DQB_53

DQB_56

DQB_55

DQB_54

DQB_58

DQB_57

DQB_60

DQB_59

DQB_61

DQB_63

MVREFD_1

VSSRH1

TEST_MCLK
TEST_YCLK
MEMTEST

DQB_39

CSB1_0*

DQB_51

DQB_50

DQB_49

CSB0_1*

CSB1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE B

(4 OF 7)

(1.8V/

2.0V)

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

IN
IN
IN
IN
IN
IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

NC

NCNC

NC

(NONE)

(NONE)

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

- =PP1V8R2V0_S0_FB_GPU

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

69

70

70

70

70

70

70

70

70

70

70

70

71

71

71

71

71

71

71

71

71

71

71

71

71

69

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

1%
1/16W
MF-LF
402

40.2

2

1

R8722

1%
1/16W
MF-LF

402

40.2

2

1

R8720

0.1uF

402

X5R

16V

10%

2

1

C8723

100

402

MF-LF

1/16W

1%

2

1

R8723

1/16W

100

402

MF-LF

1%

2

1

R8721

16V

0.1uF

402

X5R

10%

2

1

C8721

71

71

71

71

71

71

71

71

70

70

70

70

70

70

70

70 71

71

71

71

71

71

71

71

10%
16V
X5R
402

0.1uF

2

1

C8713

1%
1/16W
MF-LF
402

40.2

2

1

R8712

100

402

MF-LF

1%
1/16W

2

1

R8713

402

X5R

16V

10%

0.1uF

2

1

C8711

1%
1/16W
MF-LF

402

40.2

2

1

R8710

100

402

MF-LF

1/16W

1%

2

1

R8711

402

243

1%
1/16W
MF-LF

2

1

R8732

MF-LF

1/16W

5%

4.7K

402

2

1

R8731

4.7K

402

5%
1/16W
MF-LF

2

1

R8730

71

71

71

71

71 70

5%
1/16W
MF-LF
402

4.7K

2

1

R8733

70

70

70

70

70

70

70

70

70

70

70

70

70

70

M56P

BGA

OMIT

B21

B31

A28

A27

B24

B28

J15

H15

D15

D16

C16

B16

D21

D20

G24

F23

K26

K25

K28

K29

K31

J31

D24

F29

C30

C31

B26

C26

F25

D27

E26

E24

D25

D28

C25

B25

E29

E27

B27

D29

F28

D26

J17

D14

B15

E21

G23

J26

J29

H31

M29

M27

F31

J14

H14

G14

G15

G30

G17

G18

H17

H18

D13

F14

E14

E15

F17

E17

G31

E18

D17

B13

C13

B14

C14

B17

C17

B18

B19

H30

D18

D19

F20

E20

E22

D23

D22

E23

J22

J23

L30

H22

H23

H24

H25

G26

F26

H26

H27

G28

J25

L31

L25

M25

L26

M26

G27

G29

H29

J27

L27

L28

M30

M31

C23

B23

C28

B29

C19

B20

E31

D31

C22

B30

B22

C29

U8400

M56P

BGA

OMIT

M2

B2

E1

F1

AA2

AA5

J2

E2

V9

V8

V4

U4

U3

U2

M4

N4

J7

K6

G10

H10

E10

D10

B10

B9

J4

D6

C3

B3

AA7

G2

G3

H6

F4

G5

J5

H4

E4

H3

H2

D5

F5

F2

D4

E6

G4

AA3

T9

W4

V2

M5

K7

G9

D9

B8

D12

F12

B6

W9

W8

W7

V7

C7

T7

R7

T8

R8

Y4

W6

W5

V5

T6

T5

B7

R5

T4

Y2

Y3

W2

W3

T2

T3

R2

P2

C8

R4

P4

N6

N5

L5

K4

L4

K5

L9

K9

C11

L8

K8

J8

H8

G7

G6

G8

F8

E7

H9

B11

H11

H12

G11

G12

F7

D7

D8

F9

F11

E11

C12

B12

K3

K2

E3

D2

P3

N2

B5

B4

L3

C2

L2

D3

U8400

6.3V
402

10%

CERM

1uF

2

1

C8716

10%

402

CERM

6.3V

1uF

2

1

C8715

10%

402

1uF

CERM

6.3V
2

1

C8726

6.3V
CERM

1uF

402

10%

2

1

C8725

FERR-220-OHM

0402

21

L8725

FERR-220-OHM

0402

21

L8715

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

SM

21

XW8725

SM

21

XW8715

SYNC_MASTER=(MASTER)

ATI M56 Frame Buffer I/F

SYNC_DATE=(MASTER)

12

051-6941

104

87

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8R2V0_S0_GPU_VDDRH0

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V

GND_GPU_VSSRH0

GPU_MVREFS0

FB_A_DQ<57>

FB_A_DQM_L<5>

FB_A_DQ<60>

FB_A_WDQS<7>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<4>

FB_A_WDQS<2>
FB_A_WDQS<3>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_RDQS<6>
FB_A_RDQS<7>

FB_A_RDQS<5>

FB_A_RDQS<4>

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_DQM_L<6>
FB_A_DQM_L<7>

FB_A_BA<1>

FB_A_MA<10>

FB_A_MA<8>
FB_A_MA<9>

FB_A_CLK_P<1>

FB_A_DQ<63>

FB_A_DQ<56>

FB_A_DQ<55>

FB_A_DQ<54>

FB_A_DQ<53>

FB_A_DQ<52>

FB_A_DQ<49>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<48>

FB_A_DQ<47>

FB_A_DQ<46>

FB_A_DQ<44>
FB_A_DQ<45>

FB_A_DQ<43>

FB_A_DQ<42>

FB_A_DQ<41>

FB_A_DQ<40>

FB_A_DQ<39>

FB_A_DQ<38>

FB_A_DQ<37>

FB_A_DQ<36>

FB_A_DQ<35>

FB_A_DQ<34>

FB_A_DQ<33>

FB_A_DQ<32>

FB_A_DQ<31>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<28>

FB_A_DQ<27>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_DQ<24>

FB_A_DQ<23>

FB_A_DQ<22>

FB_A_DQ<21>

FB_A_DQ<20>

FB_A_DQ<19>

FB_A_DQ<18>

FB_A_DQ<17>

FB_A_DQ<16>

FB_A_DQ<15>

FB_A_DQ<14>

FB_A_DQ<13>

FB_A_DQ<12>

FB_A_DQ<11>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<8>

FB_A_DQ<7>

FB_A_DQ<6>

FB_A_DQ<5>

FB_A_DQ<4>

FB_A_DQ<3>

FB_A_DQ<2>

FB_A_DQ<1>

TP_FB_A_ODT<1>

FB_A_CAS_L<1>

FB_A_RAS_L<1>

FB_A_CKE<1>

FB_A_CS_L<1>

FB_A_CLK_N<1>

TP_FB_A_ODT<0>

FB_A_WE_L<0>

FB_A_CAS_L<0>

FB_A_RAS_L<0>

FB_A_CKE<0>

FB_A_CS_L<0>

FB_A_CLK_P<0>

FB_A_DQM_L<4>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<1>

FB_A_DQM_L<0>

TP_FB_A_MA12

FB_A_MA<11>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<5>

FB_A_MA<2>

FB_A_MA<1>

FB_A_MA<0>

GPU_MVREFD0

FB_A_DQ<62>

FB_A_DQ<61>

FB_A_WE_L<1>

FB_A_DQ<59>

FB_A_DQ<58>

FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>

FB_B_CS_L<1>

FB_B_DQ<39>

GPU_MEMTEST

GPU_TEST_YCLK

GPU_TEST_MCLK

GPU_MVREFD1

FB_B_DQ<63>

FB_B_DQ<61>

FB_B_DQ<59>
FB_B_DQ<60>

FB_B_DQ<57>
FB_B_DQ<58>

FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>

FB_B_DQ<53>

FB_B_DQ<52>

FB_B_DQ<47>
FB_B_DQ<48>

FB_B_DQ<46>

FB_B_DQ<45>

FB_B_DQ<44>

FB_B_DQ<43>

FB_B_DQ<42>

FB_B_DQ<41>

FB_B_DQ<40>

FB_B_DQ<38>

FB_B_DQ<36>
FB_B_DQ<37>

FB_B_DQ<34>
FB_B_DQ<35>

FB_B_DQ<32>

FB_B_DQ<31>

FB_B_DQ<33>

FB_B_DQ<29>
FB_B_DQ<30>

FB_B_DQ<28>

FB_B_DQ<26>
FB_B_DQ<27>

FB_B_DQ<24>
FB_B_DQ<25>

FB_B_DQ<23>

FB_B_DQ<21>
FB_B_DQ<22>

FB_B_DQ<19>
FB_B_DQ<20>

FB_B_DQ<18>

FB_B_DQ<17>

FB_B_DQ<16>

FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>

FB_B_DQ<12>

FB_B_DQ<11>

FB_B_DQ<10>

FB_B_DQ<9>

FB_B_DQ<8>

FB_B_DQ<7>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<4>

FB_B_DQ<3>

FB_B_DQ<2>

FB_B_DQ<1>

FB_B_DQ<0>

FB_DRAM_RST

TP_FB_B_ODT<1>

FB_B_CAS_L<1>
FB_B_WE_L<1>

FB_B_RAS_L<1>

FB_B_CKE<1>

FB_B_CLK_N<1>

FB_B_CLK_P<1>

TP_FB_B_ODT<0>

FB_B_CAS_L<0>
FB_B_WE_L<0>

FB_B_RAS_L<0>

FB_B_CKE<0>

FB_B_CS_L<0>

FB_B_CLK_P<0>
FB_B_CLK_N<0>

FB_B_WDQS<7>

FB_B_WDQS<6>

FB_B_WDQS<5>

FB_B_WDQS<4>

FB_B_WDQS<3>

FB_B_WDQS<2>

FB_B_WDQS<1>

FB_B_WDQS<0>

FB_B_RDQS<7>

FB_B_RDQS<6>

FB_B_RDQS<5>

FB_B_RDQS<3>
FB_B_RDQS<4>

FB_B_RDQS<2>

FB_B_RDQS<1>

FB_B_RDQS<0>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_DQM_L<4>

FB_B_DQM_L<3>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_BA<2>
FB_B_BA<0>
FB_B_BA<1>

TP_FB_B_MA12

FB_B_MA<9>

FB_B_MA<8>

FB_B_MA<7>

FB_B_MA<6>

FB_B_MA<5>

FB_B_MA<4>

FB_B_MA<3>

FB_B_MA<2>

FB_B_MA<1>

FB_B_MA<0>

GPU_MVREFS1

FB_B_DQ<62>

FB_A_DQ<0>

FB_A_MA<3>
FB_A_MA<4>

FB_B_MA<10>
FB_B_MA<11>

FB_A_BA<0>

FB_A_CLK_N<0>

=PP1V8R2V0_S0_FB_GPU

=PP1V8R2V0_S0_FB_GPU

=PP1V8R2V0_S0_FB_GPU

GND_GPU_VSSRH1

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

PP1V8R2V0_S0_GPU_VDDRH1

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A_BA<2>

=PP1V8R2V0_S0_FB_GPU

68

68

68

68

67

67

67

67

63

63

63

63

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Required for debug access

Required for debug access

Required for debug access

Required for debug access

0000 = 128MB
0010 = 256MB

0110 = Reserved

0100 = 64MB

ROMCFGID[3..0]

Required for debug access

Also required: GPIO10 - GPIO13

Renamed signals

Unused signals

TESTIN[0] TX_PWRS_ENb

TESTIN[6] Reserved

TESTIN[5] Reserved

TESTIN[3] Reserved

VDD_VCL TESTIN[2] Reserved

TESTOUT[11] ROMIDCFG[2]

TESTIN[4] DEBUG_ACCESS

TESTIN[9] PWRCNTL

IPD

Serial ROM TestBus Misc Straps

TESTIN[1] TX_DEEMPH_EN

IPD

TESTIN[8]

IPD
IPD

IPD

IPD

TESTOUT[10] ROMIDCFG[1]

ROMSCK TESTOUT[8]

ROMSI ROMIDCFG[3]

ROMSO TESTWR Reserved

ENA_BL TESTIN[7]

IPD

TESTOUT[9] ROMIDCFG[0]

SS_IN
Thm Mon Int

402

MF-LF

10K

5%

1/16W

2

1

R8800

GPU_DEEPMH_EN

10K

5%
1/16W
MF-LF
402

2

1

R8801

MF-LF

5%

1/16W

10K

402

NO STUFF

2

1

R8802

5%
1/16W
MF-LF
402

10K

NO STUFF

2

1

R8803

5%

10K

1/16W

402

MF-LF

NO STUFF

2

1

R8806

402

1/16W

5%

10K

MF-LF

NO STUFF

2

1

R8804

1/16W
MF-LF

10K

402

5%

NO STUFF

2

1

R8808

10K

402

MF-LF

1/16W

5%

2

1

R8805

5%

GPU_MEM_256M

1/16W
MF-LF

402

10K

2

1

R8812

1/16W
MF-LF

402

5%

10K

NO STUFF

2

1

R8809

NO STUFF

5%
1/16W

10K

402

MF-LF

2

1

R8811

402

MF-LF

10K

1/16W

5%

GPU_MEM_64M

2

1

R8813

1/16W

402

MF-LF

4.7K

5%

2

1

R9391

MF-LF

402

1/16W

4.7K

5%

2

1

R9390

MF-LF

402

1/16W

10K

5%

GPU_MEM_256M

2

1

R8824

1/16W
MF-LF

10K

402

5%

GPU_MEM_HYNIX

2

1

R8827

GPU Straps

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

88

GPU_GPIO_16
GPU_GPIO_17

GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20

GPU_GPIO_14

GPU_GPIO_7

GPU_GPIO_10

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_22

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_32

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_33

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_34

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_29

NO_TEST=TRUE

NC_GPU_GPIO_30

MAKE_BASE=TRUE

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_31

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_26

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_23

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_19

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_20

MAKE_BASE=TRUE

NC_GPU_GPIO_18

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_17

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_14

NO_TEST=TRUE

GPU_GPIO_15

GPU_GPIO_21

GPU_GPIO_23

GPU_GPIO_22

GPU_GPIO_26

GPU_GPIO_25

GPU_GPIO_28

GPU_GPIO_31

GPU_GPIO_30

GPU_GPIO_29

GPU_GPIO_34

GPU_GPIO_33

GPU_GPIO_32

MAKE_BASE=TRUE

GPU_CLK27MSS_IN

TP_GPU_GPIO_10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_BLON

GPU_GPIO_0
GPU_GPIO_1

NC_GPU_GPIO_21

MAKE_BASE=TRUE
NO_TEST=TRUE

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_GPU_GPIO_25

GPU_GPIO_24

GPU_GPIO_27

MAKE_BASE=TRUE

GPU_VCORE_LOW

GPU_DDC_B_CLK
GPU_DDC_B_DATA

=PP3V3_S0_GPU

ATI_DVPDATA<15..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_DVPDATA<15..0>

ATI_DVPCNTL<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_DVPCNTL<2..0>

LVDS_L_DATA_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAN<3>

ATI_DVPCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ATI_DVPCLK

LVDS_L_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAP<3>

LVDS_U_DATA_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_U_DATAN<3>

LVDS_U_DATA_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_U_DATAP<3>

GPU_TV_COMP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_TV_COMP

GPU_TV_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_TV_Y

GPU_TV_C

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_TV_C

GPU_VGA_VSYNC

MAKE_BASE=TRUE

TP_GPU_VGA_VSYNC

GPU_VGA_HSYNC

MAKE_BASE=TRUE

TP_GPU_VGA_HSYNC

GPU_VGA_B

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_VGA_B

GPU_VGA_R

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_VGA_R

GPU_VGA_G

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_VGA_G

GPU_GENERICC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GENERICC

GPU_GENERICB

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GENERICB

GPU_GENERICA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GENERICA

TP_FB_B_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_MA12

TP_FB_A_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_MA12

TP_ATI_ROMCS_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ATI_ROMCS_L

GPU_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_XTALOUT

GPU_XTALIN

MAKE_BASE=TRUE

GPU_CLK27M

ATI_DVPDATA<23..16>

MAKE_BASE=TRUE

TP_ATI_DVPDATA<23..16>

GPU_GPIO_5

GPU_GPIO_4

GPU_GPIO_12

GPU_GPIO_8

GPU_GPIO_6

GPU_GPIO_11

GPU_GPIO_3

GPU_GPIO_9

GPU_GPIO_2

GPU_GPIO_13

MAKE_BASE=TRUE

GPU_MEM_256M

MAKE_BASE=TRUE

GPU_MEMID

=PP3V3_S0_GPU_GPIOS

72 66

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

34

74

72

72

72

72

66

73

73

63

72

72

73

72

73

73

73

73

73

73

73

73

73

73

73

72

72

72

68

68

72

72

72 34

72

72

72

72

72

72

72

72

72

72

72

63

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

IN

IN

BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

NOTE: U8900 DQ0-7 MUST connect to GPU

within byte-lane, but software must know

U8900.J12

U8900.J1

Connect to designated pin, then GND

NC
NCNC

NC

U8900.J1

U8900.J12

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

(NONE)
BOM options provided by this page:

GDDR3 vendor/device identification scheme.

how these bits are mapped for GPU to support

DQA0-7 or DQA8-15. Bits can be swapped

Connect to designated pin, then GND

1/16W

1%

402

MF-LF

2.37K

2

1

R8930

402

1/16W

1%

MF-LF

5.49K

2

1

R8931

16V

10%

402

X5R

0.1uF

2

1

C8903

0.1uF

16V

10%

402

X5R

2

1

C8902

16V

10%

402

X5R

0.1uF

2

1

C8904

16V

10%

402

X5R

0.1uF

2

1

C8901

16V

10%
402

X5R

0.1uF

2

1

C8922

X5R

16V

10%
402

0.1uF

2

1

C8923

16V

10%
402

X5R

0.1uF

2

1

C8924

16V

10%
402

X5R

0.1uF

2

1

C8925

0.1uF

16V

10%
402

X5R

2

1

C8926

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U8900

OMIT

CRITICAL

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8900

1/16W

5%

402

MF-LF

0

2

1

R8949

1/16W

0

MF-LF
402

5%

2

1

R8941

1/16W

1%

402

MF-LF

243

2

1

R8948

1/16W

1%

402

MF-LF

60.4

2

1

R8945

60.4

MF-LF

402

1%

1/16W

2

1

R8946

0.1uF

X5R
402

10%
16V

2

1

C8933

2.37K

MF-LF

402

1%

1/16W

2

1

R8932

1/16W

1%

402

MF-LF

5.49K

2

1

R8933

10%

0.1uF

X5R
402

16V

2

1

C8921

0402

FERR-220-OHM

21

L8910

FERR-220-OHM

0402

21

L8915

16V

10%

402

X5R

0.1uF

2

1

C8915

10%
16V

402

X5R

0.1uF

2

1

C8910

1%

121

MF-LF

402

1/16W

2

1

R8940

1%

121

MF-LF
402

1/16W

2

1

R8947

1/16W

402

MF-LF

121

1%

2

1

R8944

MF-LF

1%

121

402

1/16W

2

1

R8943

1/16W

402

MF-LF

121

1%

2

1

R8942

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

70 68

70 68

70 68

71 70 68

70 68

68

68

68

68

68

68

68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

68

68

68

68

68

68

68

68

71 70 63

71 70 63

70 68

70 68

70 68

68

68

68

68

68

68

68

68

71

70 68

68

68

68

68

68

68

68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

70 68

1/16W

5%

402

MF-LF

0

2

1

R8991

1/16W

402

MF-LF

121

1%

2

1

R8990

1%

121

MF-LF

402

1/16W

2

1

R8992

10%

0.1uF

X5R
402

16V

2

1

C8971

0.1uF

X5R
402

10%
16V

2

1

C8972

243

MF-LF

402

1%

1/16W

2

1

R8998

0

MF-LF
402

5%
1/16W

2

1

R8999

CRITICAL

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U8950

1/16W
402

MF-LF

121

1%

2

1

R8993

60.4

MF-LF
402

1%
1/16W

2

1

R8995

1%

121

MF-LF

402

1/16W

2

1

R8994

1/16W
402

MF-LF

121

1%

2

1

R8997

1/16W

1%

402

MF-LF

60.4

2

1

R8996

5.49K

MF-LF

402

1%

1/16W

2

1

R8981

2.37K

MF-LF

402

1%

1/16W

2

1

R8980

5.49K

MF-LF

402

1%

1/16W

2

1

R8983

1/16W

1%

402

MF-LF

2.37K

2

1

R8982

0.1uF

X5R
402

10%
16V

2

1

C8973

0.1uF

X5R
402

10%
16V

2

1

C8981

0.1uF

X5R
402

10%
16V

2

1

C8974

0.1uF

X5R
402

10%
16V

2

1

C8975

16V

10%

402

X5R

0.1uF

2

1

C8983

CRITICAL

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U8950

0.1uF

X5R
402

10%
16V

2

1

C8976

71 70 63

0402

FERR-220-OHM

21

L8965

0402

FERR-220-OHM

21

L8960

71 70 63

X5R

0.1uF

402

10%
16V

2

1

C8951

402

0.1uF

X5R

10%
16V

2

1

C8952

0.1uF

X5R
402

10%
16V

2

1

C8960

0.1uF

X5R
402

10%
16V

2

1

C8953

0.1uF

X5R
402

10%
16V

2

1

C8965

0.1uF

X5R
402

10%
16V

2

1

C8954

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

22uF

20%

805

X5R

6.3V
2

1

C8900

X5R

22uF

805

6.3V

20%

2

1

C8920

20%

6.3V
X5R
805

22uF

2

1

C8950

805

20%

6.3V
X5R

22uF

2

1

C8970

16V

10%

402

X5R

0.1uF

2

1

C8931

GDDR3 Frame Buffer A

89

104

12

051-6941

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PP1V8_S0_FB_VDDQ

=PP1V8_S0_FB_VDD

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A0_VDDA1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A0_VREF0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A1_VREF0

FB_A_CKE<1>

FB_A_MA<10>

FB_A_MA<8>

FB_A_MA<11>

FB_A_MA<5>

FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<7>

FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>

FB_A_CLK_P<1>

FB_A_MA<1>

FB_A_MA<0>

FB_A_MA<2>

FB_A_MA<4>

FB_A_MA<3>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<9>

FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_WE_L<1>
FB_A_CAS_L<1>

FB_A1_ZQ
FB_A1_MF

FB_DRAM_RST

FB_A1_SEN

FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<62>
FB_A_DQ<56>

FB_A_DQ<57>

FB_A_DQ<61>

FB_A_DQ<59>

FB_A_DQ<54>
FB_A_DQ<53>
FB_A_DQ<60>

FB_A_DQ<55>

FB_A_DQ<52>

FB_A_DQ<51>

FB_A_DQ<50>

FB_A_DQ<49>

FB_A_DQ<48>

FB_A_DQ<45>

FB_A_DQ<47>

FB_A_DQ<44>

FB_A_DQ<39>

FB_A_DQ<35>

FB_A_DQ<32>

FB_A_MA<10>

FB_A_MA<8>

FB_A_DQM_L<0>

FB_A_DQM_L<2>
FB_A_DQM_L<3>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<3>

FB_A_WDQS<0>

FB_A_MA<1>

FB_A_MA<0>

FB_A_MA<3>

FB_A_MA<9>

FB_A_CLK_N<0>
FB_A_CS_L<0>
FB_A_WE_L<0>

FB_A0_ZQ
FB_A0_MF

FB_A_DQ<31>

FB_A_DQ<28>

FB_A_DQ<29>
FB_A_DQ<30>

FB_A_DQ<27>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_DQ<20>
FB_A_DQ<22>
FB_A_DQ<24>

FB_A_DQ<21>

FB_A_DQ<23>

FB_A_DQ<17>

FB_A_DQ<18>

FB_A_DQ<16>

FB_A_DQ<19>

FB_A_DQ<13>

FB_A_DQ<12>

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<11>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<7>
FB_A_DQ<8>

FB_A_DQ<4>

FB_A_DQ<6>

FB_A_DQ<5>

FB_A_DQ<3>

FB_A_DQ<2>

FB_A_DQ<0>
FB_A_DQ<1>

FB_A_MA<7>

FB_A_MA<2>

FB_A_MA<6>

FB_A_MA<11>

FB_A_WDQS<2>

FB_A_WDQS<1>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A0_VREF1

=PP1V8_S0_FB_VDDQ

FB_A_RAS_L<1>

FB_A_BA<2>FB_A_BA<2>

=PP1V8_S0_FB_VDD

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A1_VDDA0

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A1_VDDA1

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_A0_VDDA0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A1_VREF1

FB_A_DQM_L<1>

FB_A_CLK_P<0>

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A0_SEN

FB_A_RDQS<0>

FB_DRAM_RST

FB_A_RAS_L<0>

FB_A_CAS_L<0>

FB_A_CKE<0>

FB_A_MA<4>
FB_A_MA<5>

FB_A_DQ<34>
FB_A_DQ<33>

FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>

FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<46>

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

IN

IN

BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power aliases required by this page:

Page Notes

BOM options provided by this page:

Signal aliases required by this page:
(NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

U9000.J12

U9000.J1

NC
NC NC

NC

U9000.J1

U9000.J12

Connect to designated pin, then GNDConnect to designated pin, then GND

2.37K

MF-LF

402

1%

1/16W

2

1

R9030

5.49K

MF-LF

402

1%

1/16W

2

1

R9031

402

0.1uF

X5R

10%
16V

2

1

C9003

0.1uF

X5R
402

10%
16V

2

1

C9002

0.1uF

X5R
402

10%
16V

2

1

C9004

0.1uF

X5R

10%
16V

402

2

1

C9001

0.1uF

X5R
402

10%
16V

2

1

C9022

0.1uF

X5R
402

10%
16V

2

1

C9023

0.1uF

X5R
402

10%
16V

2

1

C9024

0.1uF

X5R
402

10%
16V

2

1

C9025

16V
402

0.1uF

X5R

10%

2

1

C9026

OMIT

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U9000

FBGA

OMIT

CRITICAL

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U9000

0

MF-LF
402

5%
1/16W

2

1

R9049

1/16W

5%

402

MF-LF

0

2

1

R9041

243

MF-LF

402

1%

1/16W

2

1

R9048

60.4

MF-LF
402

1%
1/16W

2

1

R9045

1/16W

1%

402

MF-LF

60.4

2

1

R9046

16V

10%

402

X5R

0.1uF

2

1

C9033

2.37K

1/16W

1%

402

MF-LF

2

1

R9032

5.49K

MF-LF

402

1%

1/16W

2

1

R9033

402

0.1uF

X5R

10%
16V

2

1

C9021

0402

FERR-220-OHM

21

L9010

0402

FERR-220-OHM

21

L9015

0.1uF

X5R
402

10%
16V

2

1

C9015

0.1uF

X5R
402

10%
16V

2

1

C9010

1/16W

402

MF-LF

121

1%

2

1

R9040

1/16W
402

MF-LF

121

1%

2

1

R9047

1%

121

MF-LF

402

1/16W

2

1

R9044

1/16W
402

MF-LF

121

1%

2

1

R9043

1%

121

MF-LF

402

1/16W

2

1

R9042

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

71 68

71 68

71 68

71 70 68

71 68

68

68

68

68

68

68

68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

68

68

68

68

68

68

68

68

71 70 63

71 70 63

71 68

71 68

71 68

68

68

68

68

68

68

68

68

71 70 68

68

68

68

68

68

68

68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

71 68

MF-LF
402

5%
1/16W

0

2

1

R9091

1%

121

MF-LF

402

1/16W

2

1

R9090

1/16W

402

1%

121

MF-LF

2

1

R9092

0.1uF

16V

10%
402

X5R

2

1

C9071

0.1uF

16V

10%
402

X5R

2

1

C9072

1%

243

MF-LF

402

1/16W

2

1

R9098

5%

0

MF-LF
402

1/16W

2

1

R9099

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11

D11

D2

V4

J3

J2

V9

P3

P10

D10

D3

H10

A9

B10

B11

G3

F2

F3

E2

T3

T2

C3

R3

R2

M3

N2

L3

M2

T10

T11

R10

R11

C2

M10

N11

L10

M11

G10

F11

F10

E11

C10

C11

B3

B2

N3

N10

E10

E3

F4

H9

J10

J11

F9

H3

G4

G9

M4

K2

L4

K3

H2

K4

M9

K10

L9

K11

H11

K9

U9050

121

1/16W
402

MF-LF

1%

2

1

R9093

60.4

1/16W

1%

402

MF-LF

2

1

R9095

402

1%
1/16W
MF-LF

121

2

1

R9094

121

MF-LF

1/16W

1%

402

2

1

R9097

60.4

MF-LF

402

1%

1/16W

2

1

R9096

1/16W

1%

5.49K

MF-LF

402

2

1

R9081

1/16W

1%

2.37K

MF-LF

402

2

1

R9080

1%

1/16W

402

5.49K

MF-LF

2

1

R9083

2.37K

1%

1/16W

402

MF-LF

2

1

R9082

0.1uF

16V
X5R
402

10%

2

1

C9073

16V

10%

402

X5R

0.1uF

2

1

C9081

0.1uF

X5R
402

10%
16V

2

1

C9074

0.1uF

16V

10%
402

X5R

2

1

C9075

0.1uF

X5R

16V

10%

402

2

1

C9083

16MX32-GDDR3-500MHZ

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

G11

G2

D12

D9

D4

D1

B12

B9

T12

T9

T4

T1

P12

P9

P4

P1

L11

L2

B4

B1

J12

J1

V10

V3

L12

L1

G12

G1

A10

A3

H12

H1

E12

E9

E4

E1

C12

C9

C4

V12

V1

C1

R12

R9

R4

R1

N12

N9

N4

N1

J9

J4

A12

A1

K12

K1

V11

V2

M12

M1

F12

F1

A11

A2

U9050

0.1uF

16V

10%
402

X5R

2

1

C9076

71 70 63

FERR-220-OHM

0402

21

L9065

FERR-220-OHM

0402

21

L9060

71 70 63

16V

10%

402

X5R

0.1uF

2

1

C9051

16V

10%

402

X5R

0.1uF

2

1

C9052

0.1uF

X5R
402

10%
16V

2

1

C9060

0.1uF

X5R
402

10%
16V

2

1

C9053

0.1uF

X5R
402

10%
16V

2

1

C9065

16V

10%

402

X5R

0.1uF

2

1

C9054

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

20%

6.3V
X5R
805

22uF

2

1

C9000

20%

6.3V
X5R
805

22uF

2

1

C9020

20%

6.3V
X5R
805

22uF

2

1

C9050

22uF

20%

6.3V
X5R
805

2

1

C9070

X5R

0.1uF

402

10%
16V

2

1

C9031

051-6941

SYNC_MASTER=(MASTER)

GDDR3 Frame Buffer B

SYNC_DATE=(MASTER)

12

104

90

FB_B_MA<4>

FB_B_CS_L<1>

FB_B_MA<9>

FB_B_DQ<2>

FB_B_DQ<7>

FB_B_DQ<24>

FB_B_DQ<13>

FB_B_DQ<14>

FB_B_DQ<12>

FB_B_DQ<15>

FB_B_DQM_L<3>

FB_B_WDQS<1>

FB_B_RDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<2>

FB_DRAM_RST

FB_B0_ZQ

FB_B0_SEN

FB_B_DQ<23>

FB_B_CLK_N<1>

FB_B_CAS_L<1>

FB_B_WE_L<1>

FB_B_RAS_L<1>

FB_B1_ZQ

FB_B_DQ<61>

FB_B_DQ<46>

FB_B_CLK_P<1>

FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>

FB_B_CKE<1>

FB_B_DQ<58>

FB_B_DQ<59>

=PP1V8_S0_FB_VDDQ

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_B0_VDDA0

=PP1V8_S0_FB_VDD

FB_B_MA<5>

FB_B_MA<7>

FB_B_BA<0>
FB_B_BA<1>

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_B1_VDDA1

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_B1_VDDA0

=PP1V8_S0_FB_VDD

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0_FB_B0_VDDA1

FB_B_CKE<0>

FB_B_DQ<9>
FB_B_DQ<11>

FB_B_DQ<8>

FB_B_DQ<18>

FB_B_DQ<10>

FB_B_DQ<17>
FB_B_DQ<19>
FB_B_DQ<16>
FB_B_DQ<20>
FB_B_DQ<22>

FB_B_DQ<21>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<28>
FB_B_DQ<31>
FB_B_DQ<27>

FB_B_DQ<1>

FB_B_DQ<25>

FB_B_DQ<26>

FB_B_DQ<6>
FB_B_DQ<0>
FB_B_DQ<5>
FB_B_DQ<3>

FB_B_DQ<4>

FB_B_RDQS<1>

FB_B0_MF

FB_B_CAS_L<0>

FB_B_WE_L<0>

FB_B_CS_L<0>

FB_B_CLK_N<0>

FB_B_MA<9>

FB_B_MA<6>
FB_B_MA<7>

FB_B_MA<0>
FB_B_MA<1>

FB_B_WDQS<3>

FB_B_WDQS<2>

FB_B_WDQS<0>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_MA<5>

FB_B_MA<11>

FB_B_MA<8>

FB_B_MA<10>

FB_B_DQ<53>

FB_B_DQ<54>

FB_B_DQ<52>
FB_B_DQ<55>

FB_B_DQ<48>
FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<44>

FB_B_DQ<51>

FB_B_DQ<47>
FB_B_DQ<45>

FB_B_DQ<43>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<37>
FB_B_DQ<32>
FB_B_DQ<39>
FB_B_DQ<34>
FB_B_DQ<36>
FB_B_DQ<35>

FB_B_DQ<63>

FB_B_DQ<33>

FB_B_DQ<62>
FB_B_DQ<60>
FB_B_DQ<56>

FB_B_DQ<57>

FB_B_RDQS<7>

FB_B_RDQS<4>

FB_B_RDQS<6>

FB_B1_SEN

FB_DRAM_RST

FB_B1_MF

FB_B_MA<6>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>
FB_B_BA<0>

FB_B_BA<1>

FB_B_DQM_L<7>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_MA<11>

FB_B_MA<8>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B1_VREF1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B1_VREF0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF0

FB_B_RAS_L<0>

FB_B_BA<2> FB_B_BA<2>

FB_B_RDQS<5>

FB_B_MA<10>

FB_B_DQ<38>

=PP1V8_S0_FB_VDDQ

FB_B_MA<4>

FB_B_MA<3>

FB_B_MA<2>

FB_B_CLK_P<0>

GPIO_0
GPIO_1

TESTEN

GPIO_2

GPIO_27

PLLTEST

XTALOUT

XTALIN

MPVSS

MPVDD

PVSS

PVDD

GPIO_16
GPIO_17

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_10

GPIO_9

GPIO_8

GPIO_7_BLON

GPIO_6

GPIO_5

GPIO_4

GPIO_3

VREFG

GPIO_33

GPIO_31
GPIO_32

GPIO_25
GPIO_26

GPIO_24

GPIO_21

GPIO_20

GPIO_19

DMINUS

DPLUS

ROMCS*

GPIO_34

GPIO_29
GPIO_30

NC_DVOVMODE_0
NC_DVOVMODE_1

DVPCLK

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DVPDATA_2

DVPDATA_1

DVPDATA_0

DVPDATA_4

DVPDATA_3

DVPDATA_5

DVPDATA_7

DVPDATA_6

DVPDATA_9

DVPDATA_8

DVPDATA_10
DVPDATA_11

DVPDATA_13

DVPDATA_12

DVPDATA_15

DVPDATA_14

DVPDATA_16

DVPDATA_18

DVPDATA_17

DVPDATA_19

DVPDATA_21

DVPDATA_20

DVPDATA_23

DVPDATA_22

GENERICA
GENERICB
GENERICC
GENERICD

DIGON

VARY_BL

NC0

GPIO_18

VDDPLL

GPIO_28

GPIO_22
GPIO_23

GENERAL PURPOSE I/O

(1.2V)

(2.5V)

ROM

TEST

PLL & XTAL

VIP HOST / EXTERNAL TMDS

PANEL
CONTROL

VDDR3

(3.3V)

(2.5V)

VDD25

VDDR5

(1.8V/3.3V)

(1.8V/3.3V)

VDDR4

DIODE

THERMAL

(2.5V)

(6 OF 7)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

20mA

70mA total for VDD25

Power aliases required by this page:

- =I2C_GPU_TMDS_SCL - I2C clock line for

WHY ARE THESE SEPARATE?

Page Notes

(PP1V0R1V2_S0_GPU_MPVDD)

Add ferrite bead

NC

NC

NC

NC

Signal aliases required by this page:

(GND_GPU_PVSS)

(GND_GPU_MPVSS)

(PP2V5_S0_GPU_PVDD_F)

- =I2C_GPU_TMDS_SDA - I2C data line for

- =PP3V3_GPU_GPIOS

- =PP1V8_GPU_LVDS_PLL

external TMDS transmitters

(NONE)

- =PP2V5_PVDD

external TMDS transmitters

20mA

Typically <50mA

Typically <50mA

Typically <50mA

BOM options provided by this page:

100mA

10%
16V
X5R

0.1uF

402

2

1

C9112

6.3V
CERM

1uF

402

10%

2

1

C9111

402

1uF

6.3V
CERM

10%

2

1

C9116

6.3V
CERM

1uF

10%

402

2

1

C9117

10%
X5R

402

0.1uF

16V

2

1

C9137

6.3V
CERM
402

10%

1uF

2

1

C9136

FERR-220-OHM

0402

21

L9135

6.3V
CERM

1uF

402

10%

2

1

C9141

FERR-220-OHM

0402

21

L9140

X5R

16V

0.1uF

10%

402

2

1

C9142

5%
1/16W
MF-LF
402

1K

2

1

R9195

SM

21

XW9140

1%

499

1/16W
MF-LF
402

2

1

R9191

1%

499

402

MF-LF

1/16W

2

1

R9190

SM

21

XW9135

22uF

805

X5R

6.3V

20%

2

1

C9100

20%

6.3V
X5R
805

22uF

2

1

C9110

22uF

805

X5R

6.3V

20%

2

1

C9115

20%

6.3V
X5R
805

22uF

2

1

C9120

22uF

805

X5R

6.3V

20%

2

1

C9125

10%

402

1uF

6.3V
CERM

2

1

C9132

22uF

805

X5R

6.3V

20%

2

1

C9130

805

X5R

6.3V

20%

22uF

2

1

C9135

22uF

805

X5R

6.3V

20%

2

1

C9140

10%
16V
X5R
402

0.1uF

2

1

C9191

OMIT

BGA

M56P

AM26

AL26

AC8

AE5

AE4

AE3

AE2

AM5

AL5

AK5

AJ5

AD20

AD19

AD18

AC20

AC19

AB10

AB9

AA9

AC15

AC18

AC16

AC13

AA10

L10

K22

AD12

AG22

AC7

AH14

AJ14

AG14

AL4

AK4

AB6

A5

A6

AC5

AC6

AB2

AC3

AC2

AC1

AG8

AH7

AG9

AH8

AJ8

AD3

AH9

AG10

AF10

AH6

AF8

AF7

AE9

AE10

AG7

AF9

AD1

AF13

AE13

AB7

AA8

AB8

AD5

AB5

AB4

AB3

AC4

AD2

AD4

AD23

AE23

AF23

AK22

AL2

AK3

AK1

AK2

AJ1

AJ2

AH3

AG6

AE7

AF6

AH5

AH2

AG5

AJ4

AH4

AJ3

AG4

AF5

AF4

AE6

AM3

AL3

AG3

AG2

AF3

AF1

AF2

AG1

AG12
AH12

AE11

U8400

0.1uF

402

X5R

16V

10%

2

1

C9127

10%

402

1uF

CERM

6.3V

2

1

C9126

10%
16V
X5R

0.1uF

402

2

1

C9122

6.3V
CERM

1uF

10%

402

2

1

C9121

0402

FERR-220-OHM

21

L9120

FERR-220-OHM

0402

21

L9125

0402

200-OHM-EMI

21

L9130

10%

402

CERM

6.3V

1uF

2

1

C9131

10%

402

1uF

CERM

6.3V

2

1

C9101

6.3V

1uF

10%

402

CERM

2

1

C9102

6.3V
CERM

1uF

402

10%

2

1

C9103

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

ATI M56 GPIO/DVO/Misc

91

104

12

051-6941

PPVCORE_S0_GPU_MPVDD

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

GND_GPU_MPVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_PVDD_F

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

GND_GPU_PVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

PP1V2_S0_GPU_VDDPLL

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

=PP3V3_S0_GPU_VDDR3

=PP1V2_S0_GPU_VDDPLL

=PP2V5_S0_GPU_PVDD

=PPVCORE_S0_GPU

=PP1V8R3V3_S0_GPU_VDDR5

=PP1V8R3V3_S0_GPU_VDDR4

=PP2V5_S0_GPU_VDD25

=PP2V5_S0_GPU_VDDC_CT

GPU_GPIO_30
GPU_GPIO_31

GPU_GPIO_8

ATI_DVPDATA<0>

ATI_DVPDATA<19>

ATI_DVPDATA<2>

ATI_TDIODE_P

GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2

GPU_GPIO_27

GPU_XTALOUT

GPU_XTALIN

GPU_GPIO_16
GPU_GPIO_17

GPU_GPIO_15

GPU_GPIO_14

GPU_GPIO_13

GPU_GPIO_12

GPU_GPIO_11

GPU_GPIO_10

GPU_GPIO_9

GPU_GPIO_7

GPU_GPIO_6

GPU_GPIO_5

GPU_GPIO_3

GPU_GPIO_33

GPU_GPIO_32

GPU_GPIO_25
GPU_GPIO_26

GPU_GPIO_21

GPU_GPIO_20

GPU_GPIO_19

ATI_TDIODE_N

TP_ATI_ROMCS_L

GPU_GPIO_34

GPU_GPIO_29

ATI_DVPCLK

ATI_DVPCNTL<0>
ATI_DVPCNTL<1>
ATI_DVPCNTL<2>

ATI_DVPDATA<1>

ATI_DVPDATA<4>

ATI_DVPDATA<3>

ATI_DVPDATA<5>

ATI_DVPDATA<7>

ATI_DVPDATA<6>

ATI_DVPDATA<9>

ATI_DVPDATA<8>

ATI_DVPDATA<10>
ATI_DVPDATA<11>

ATI_DVPDATA<13>

ATI_DVPDATA<12>

ATI_DVPDATA<15>

ATI_DVPDATA<14>

ATI_DVPDATA<16>

ATI_DVPDATA<18>

ATI_DVPDATA<17>

ATI_DVPDATA<21>

ATI_DVPDATA<20>

ATI_DVPDATA<23>

ATI_DVPDATA<22>

GPU_GENERICA
GPU_GENERICB
GPU_GENERICC
GPU_GENERICD

GPU_DIGON
GPU_VARY_BL

GPU_GPIO_18

GPU_GPIO_28

GPU_GPIO_22
GPU_GPIO_23

ATI_TESTEN

PP1V8R3V3_S0_GPU_VDDR5_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_S0_GPU

ATI_VREFG

GPU_GPIO_24

GPU_GPIO_4

PP1V8R3V3_S0_GPU_VDDR4_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

67

69

63

66

63

63

63

51

63

63

63

63

69

69

69

69

69

69

50

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

50

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

66

74

74

69

69

69

69

63

69 69

DDC3DATA

DDC3CLK

DDC2DATA

DDC2CLK

DDC1DATA

DDC1CLK

TXOUT_L3N

TXOUT_L3P

TXOUT_L2N

TXOUT_L2P

TXOUT_L1N

TXOUT_L1P

TXOUT_L0N

TXOUT_L0P

TXCLK_LP
TXCLK_LN

TXOUT_U3N

TXOUT_U2N
TXOUT_U3P

TXOUT_U2P

TXOUT_U1N

TXOUT_U1P

TXOUT_U0N

TXOUT_U0P

TXCLK_UN

TXCLK_UP

COMP

C

Y

V2SYNC

H2SYNC

B2

G2

R2

VSYNC

HSYNC

B

G

R

TX2M

TX2P

TX1M

TX0M
TX1P

TX0P

TXCM

HPD1

LPVSS

LPVDD

R2SET

VDD2DI
VSS2DI

A2VSSQ

NC_A2VDDQ

VSS1DI

RSET

AVSSQ

VDD1DI

TXCP

TPVSS

TPVDD

TX3P
TX3M
TX4P
TX4M
TX5P
TX5M

A2VSS

A2VDD

(2.5V)

AVSS

(2.5V)

AVDD

TXVSSR

IDENTIFICATION

(5 OF 7)

LVDDR

LVSSR

DAC (CRT)

DAC2 (TV/CRT2)

LVDS

MONITOR

TXVDDR

(2.5V)

(2.5V)

(2.5V)

(2.5V)

(2.5V)

(2.5V)

INTEGRATED TMDS

IN

OUT
OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI
BI

BI
BI

BI
BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

20mA peak

20mA peak

20mA peak

130mA peak

- =PP1V8R2V5_S0_GPU_LVDDR

- =PP2V5_S0_GPU

(NONE)

(NONE)
BOM options provided by this page:

NC

150mA peak

65mA peak

200mA peak

Comp B Pb

C R Pr

Y G Y

Composite/S-Video VGA Component

20mA peak

Signal aliases required by this page:

Power aliases required by this page:

Sum of peak currents on this page: 605mA

Page Notes

BGA

M56P

OMIT

AJ15

AJ22

AJ17

AL23

AJ16

AM23

AG15

AM7

AL7

AK8

AK7

AJ7

AM6

AL6

AK6

AJ6

AH21
AG21

AG20
AH20

AK20
AJ20

AG18
AH18

AJ18
AK18

AM21
AL21

AM20
AL20

AL19
AK19

AM9
AL9

AJ21
AK21

AM18
AL18

AJ12
AK12

AJ11
AK11

AJ9
AK9

AM12
AL12

AM11
AL11

AL10
AK10

AL8

AM8

AL22

AK14

AK15

AK24

AL14

AK17

AJ19

AH19

AH17

AG19

AG17

AF22

AF21

AF18

AF17

AF20

AF19

AE22

AE21

AE20

AD22

AD21

AC22

AC21

AE18

AE19

AJ23

AF11

AF15

AM15

AM24

AE12

AF12

AH13

AG13

AH22

AH23

AH15

AJ13

AL15

AL24

AK23

AK25

AJ24

AM25

AL25

AK13

AM17

AL17

AM16

AL16

U8400

1/16W

1%

402

MF-LF

499

2

1

R9350

0.1uF

X5R
402

10%
16V

2

1

C9346

0.1uF

X5R
402

10%
16V

2

1

C9342

6.3V
402

CERM

1uF

10%

2

1

C9341

0402

FERR-220-OHM

21

L9300

1uF

CERM

10%

6.3V
402

2

1

C9301

1uF

CERM
402

10%

6.3V

2

1

C9306

FERR-220-OHM

0402

21

L9305

10%

402

X5R

0.1uF

16V

2

1

C9307

FERR-220-OHM

0402

21

L9330

6.3V

10%

402

CERM

1uF

2

1

C9331

SM

21

XW9345

SM

21

XW9330

X5R
402

10%

0.1uF

16V

2

1

C9322

1uF

402

10%
CERM

6.3V

2

1

C9321

FERR-220-OHM

0402

21

L9320

SM

21

XW9320

10%
402

X5R

0.1uF

16V

2

1

C9312

6.3V

10%
CERM

1uF

402

2

1

C9311

FERR-220-OHM

0402

21

L9310

SM

21

XW9310

SM

21

XW9305

SM

21

XW9300

SM

21

XW9314

SM

21

XW9324

75

16V

10%
X5R

0.1uF

402

2

1

C9317

402

CERM

6.3V

10%

1uF

2

1

C9316

16V

10%
402

X5R

0.1uF

2

1

C9327

6.3V
402

CERM

10%

1uF

2

1

C9326

FERR-220-OHM

0402

21

L9325

0402

FERR-220-OHM

21

L9315

0402

FERR-220-OHM

21

L9345

69

69

69

77 74

77 74

77 74

69

69

77 74

77 74

77 74

77 74

77 74

77 74

77 74

77 74

77 74

77 74

77 74

77 74

77 74

69

69

69

69

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

79 75 74

75

75

69

69

74

74

0.1uF

X5R
402

10%
16V

2

1

C9347

20%

6.3V
X5R
805

22uF

2

1

C9340

22uF

805

X5R

6.3V

20%

2

1

C9345

6.3V

10%

402

CERM

1uF

2

1

C9332

1uF

CERM

10%

402

6.3V

2

1

C9302

6.3V
X5R
805

22uF

20%

2

1

C9300

22uF

805

X5R

6.3V

20%

2

1

C9305

20%

6.3V
X5R
805

22uF

2

1

C9310

22uF

805

X5R

6.3V

20%

2

1

C9315

20%
X5R

22uF

805

6.3V

2

1

C9320

X5R

6.3V

20%

22uF

805

2

1

C9325

20%

6.3V
805

22uF

X5R

2

1

C9330

75

75

75 74

75 74

75 74

69

69

69

715

MF-LF
402

1%
1/16W

2

1

R9351

93

104

12

051-6941

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

ATI M56 Video Interfaces

=PP2V5_S0_GPU

VOLTAGE=0V

GND_GPU_TPVSS

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=2.5V

PP2V5_S0_GPU_TXVDDR

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

GND_GPU_TXVSSR

VOLTAGE=0V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

GPU_TV_C

VOLTAGE=0V

GND_GPU_LPVSS

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

GPU_TV_COMP

GPU_TV_Y

GPU_VGA_R
GPU_VGA_G
GPU_VGA_B

GPU_R2
GPU_G2
GPU_B2

GPU_V2SYNC

VOLTAGE=0V

GND_GPU_AVSSN

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_TPVDD

ATI_R2SET

ATI_RSET

GPU_HPD

LVDS_U_DATA_N<3>

LVDS_U_DATA_P<3>

LVDS_U_DATA_N<1>

LVDS_U_DATA_P<1>

LVDS_L_CLK_P

LVDS_L_DATA_P<0>

LVDS_L_DATA_P<1>

LVDS_L_DATA_N<0>

GPU_VGA_VSYNC

GPU_VGA_HSYNC

LVDS_U_CLK_P
LVDS_U_CLK_N

LVDS_U_DATA_P<0>
LVDS_U_DATA_N<0>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

TMDS_DATA_N<5>

TMDS_DATA_N<4>

TMDS_DATA_N<3>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<3>
LVDS_L_DATA_N<3>

GPU_DDC_A_CLK

GPU_DDC_B_DATA

GPU_DDC_B_CLK

GPU_DDC_A_DATA

ATI_RSET
ATI_R2SET

LVDS_U_DATA_N<2>

LVDS_U_DATA_P<2>

LVDS_L_CLK_N

GPU_DDC_C_CLK
GPU_DDC_C_DATA

VOLTAGE=2.5V

PP2V5_S0_GPU_AVDD

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

GND_GPU_AVSSQ

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

PP2V5_S0_GPU_A2VDD

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_VDD1DI

VOLTAGE=0V

GND_GPU_A2VSSN

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

GND_GPU_LVSSR

VOLTAGE=0V

MIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.25 mm

GPU_H2SYNC

VOLTAGE=0V

GND_GPU_A2VSSQ

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_VDD2DI

PP2V5_S0_GPU_LVDDR

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

PP2V5_S0_GPU_LPVDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

TMDS_CLK_P

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

63

73

73

73

73

G

D

S

N-CHN

S

D

G

P-CHN

G

D

S

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

no-panel case (development)

LCD (LVDS) INTERFACE

INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL

518S0289

518S0293

NC

Panel has 2K pull-ups

100K pull-ups are for

NET_TYPE

NC

NC

INVERTER INTERFACE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

100K

MF-LF

402

5%

1/16W

2

1

R9450

0.001uF

CERM

402

20%
50V

2

1

C9454

50V

20%

402

CERM

0.001uF

2

1

C9452

0.001uF

50V

20%

402

CERM

2

1

C9450

10UF

X5R
603

20%

6.3V
2

1

C9451

SM

FERR-1K-OHM-EMI

21

L9450

SM-1

400-OHM-EMI

21

L9454

10V

20%
402

CERM

0.1uF

INVERTER_BUF

2

1

C9453

SM-1

400-OHM-EMI

21

L9452

0.001uF

CERM

20%
50V

402

2

1

C9420

1/16W

5%

402

MF-LF

100K

2

1

R9410

402

0.001uF

CERM

20%
50V

2

1

C9410

1/16W

5%

402

MF-LF

100K

2

1

R9411

0.001uF

20%

CERM

402

50V

2 1

C9421

MSC-RB30-5-FA

F-RT-SM

CRITICAL

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

34

33

J9400

FERR-250-OHM

SM

2

1

L9455

0.001uF

402

20%
50V
CERM

2

1

C9455

0.001uF

CERM

20%
50V

402

2

1

C9401

SM

FERR-250-OHM

L9400

50V

CERM

0.0022uF

10%

402

21

C9400

100K

MF-LF

402

1/16W

5%

R9401

MF-LF

402

5%

1/16W

100K

2

1

R9400

SI3443DV

TSOP-LF

4
3 6

5
2
1

Q9400

2N7002

SOT23-LF

2

1

3

Q9401

5%
1/16W
MF-LF

402

10K

2

1

R9489

100K

402

MF-LF

1/16W

5%

2

1

R9494

INVERTER_UNBUF

5%

1/16W

402

0

MF-LF

21

R9496

MC74VHC1G08

SC70

INVERTER_BUF

5

4

1

2

3

U9453

SM-2MT-LF

CRITICAL

4

3

2

1

6

5

J9450

SC70-6

FDG6332C_NL

1

2

6

Q9450

SC70-6

FDG6332C_NL

4

5

3

Q9450

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

94

104

12

051-6941

Internal Display Connectors

LVDS_U_CLK_N

LVDS LVDS

VGAVGA

GPU_G2

GPU_VARY_BL

=PP3V3_S0_INVERTER

INVERTER_PWM_F

=GND_CHASSIS_INVERTER

=PPBUS_S0_INVERTER

=PP3V3_S0_LCD

LCD_PWREN_L

GPU_DIGON

LCD_PWREN_L_RC

LVDS_L_DATA_N<2..0>

LVDS LVDS

TMDS_DATA_N<2..0>

TMDSTMDS

TMDS_DATA_P<2..0>

TMDSTMDS

TMDS_DATA_N<5..3>

TMDSTMDS

TMDS_DATA_P<5..3>

TMDSTMDS

TMDS_CLK_N

TMDSTMDS

TMDS_CLK_P

TMDSTMDS

LVDSLVDS

LVDS_L_DATA_P<2..0>

LVDS_L_CLK_N

LVDSLVDS

LVDS_L_CLK_P

LVDS LVDS

LVDSLVDS

LVDS_U_DATA_N<2..0>

LVDSLVDS

LVDS_U_DATA_P<2..0>

LVDS

LVDS_U_CLK_P

LVDS

VGAVGA

GPU_B2

VGAVGA

GPU_R2

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_LCD_SW

=GND_CHASSIS_LCD2

GPU_DDC_C_CLK
GPU_DDC_C_DATA

=GND_CHASSIS_LCD1

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_LCD_CONN

VOLTAGE=3.3V

=GND_CHASSIS_LCD4

LVDS_L_DATA_P<0>

LVDS_L_DATA_N<0>

LVDS_U_DATA_N<0>

LVDS_L_CLK_N
LVDS_L_CLK_P

LVDS_L_DATA_P<2>

LVDS_L_DATA_N<2>

LVDS_L_DATA_P<1>

LVDS_L_DATA_N<1>

LVDS_U_DATA_P<0>

LVDS_U_DATA_N<1>
LVDS_U_DATA_P<1>

LVDS_U_DATA_N<2>
LVDS_U_DATA_P<2>

LVDS_U_CLK_N
LVDS_U_CLK_P

=GND_CHASSIS_LCD3

=PP3V3_S0_DDC_LCD

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PPBUS_S0_INVERTER

PP5V_INVERTER_SW

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

INVERTER_PWM

FP_PWR_EN_L

GPU_BLON

PP5V_INVERTER_SW_F

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

=PP5V_S0_INVERTER

GND_INVERTER

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

77

77

79

79

79

79

79

79

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

77

74

75

74

75

75

75

75

75

75

74

74

74

74

74

74

75

75

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

73

73

72

63

6

63

63

72

73

73

73

73

73

73

73

73

73

73

73

73

73

73

73

6

73

73

6

6

73

73

73

73

73

73

73

73

73

73

73

73

73

73

73

73

6

63

69

63

G

SD

G

SD

G

SD

LCFILTER

LCFILTER

LCFILTER

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TMDS Filtering

Place series R’s and common-mode filtering close to GPU, common mode chokes near connector.

(DAC2 Comp)

(DAC2 Y)

(DAC2 C)

PLACE CLOSE TO CONNECTOR

ANALOG FILTERING

PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR

VGA SYNC BUFFERS

DVI INTERFACE

DVI DDC CURRENT LIMIT

3V LEVEL SHIFTERS

(55mA requirement per DVI spec)

PHYSICAL

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

Isolation required for DVI power switch

(PP5V_S0_DDC)

PLACE NEAR C5A & C5B

PLACE NEAR 3, 11 & 19

514-0278

1/16W

5%
MF-LF

10K

402

2

1

R9721

1/16W

5%

402

MF-LF

10K

2

1

R9720

SOT-363

2N7002DW-X-F

1

2

6

Q9711

SOT-363

2N7002DW-X-F

4

5

3

Q9711

1/16W

5%

402

MF-LF

100K

2

1

R9722

50V

5%

402

CERM

100pF

2

1

C9713

4.7K

MF-LF
402

5%
1/16W

2

1

R9712

1/16W

5%

402

MF-LF

4.7K

2

1

R9710

100pF

CERM
402

5%
50V

2

1

C9711

0.01uF

CERM

603

20%
50V

2

1

C9710

400-OHM-EMI

SM-1

21

L9710

SOT-363

2N7002DW-X-F

4

5

3

Q9714

CRITICAL

0.5AMP-13.2V

SM-LF

21

F9710

B0530WXF

SOD-123

21

D9710

402

100pF

CERM

5%
50V

2

1

C9714

MF-LF

402

5%

1/16W

100

21

R9711

MF-LF

402

5%

1/16W

100

21

R9713

MF-LF

402

5%

1/16W

100

21

R9714

0

MF-LF

402

5%

1/16W

2 1

R9730

0

MF-LF

5%

1/16W

402

2 1

R9731

3.3pF

CERM
402

0.25%
50V

2

1

C9741

1/16W

1%

402

MF-LF

75

2

1

R9742

1/16W

1%

402

MF-LF

75

2

1

R9740

1/16W

1%

402

MF-LF

75

2

1

R9741

3.3pF

CERM
402

0.25%
50V

2

1

C9742

3.3pF

CERM
402

0.25%
50V

2

1

C9740

CRITICAL

SM-220MHZ-LF

43

21

FL9740

SM-220MHZ-LF

CRITICAL

43

21

FL9741

CRITICAL

SM-220MHZ-LF

43

21

FL9742

CRITICAL

90-OHM-300mA

2012H

4

32

1

L9702

CRITICAL

90-OHM-300mA

2012H

4

32

1

L9701

33

5%
1/16W
MF-LF

402

21

R9750

1/16W

5%

402

MF-LF

33

21

R9751

90-OHM-300mA

2012H

CRITICAL

4

32

1

L9703

90-OHM-300mA

2012H

CRITICAL

4

32

1

L9704

CRITICAL

90-OHM-300mA

2012H

4

32

1

L9705

90-OHM-300mA

2012H

CRITICAL

4

32

1

L9700

QH11121-RIG02-4F

F-RT-TH-DVI

CRITICAL

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

34

33

32

31

C5B C5A

C4

C3

C2

C1

J9700

5%
1/16W
MF-LF

402

20K

2

1

R9715

1%

1/16W

402

MF-LF

182

2

1

R9786

5%
1/16W
MF-LF

0

402

21

R9785

5%
1/16W
MF-LF

0

402

21

R9784

402

MF-LF

1/16W

1%

182

2

1

R9782

0

402

MF-LF

1/16W

5%

21

R9780

5%
1/16W
MF-LF

402

0

21

R9781

0

402

MF-LF

1/16W

5%

21

R9777

5%
1/16W
MF-LF

402

0

21

R9776

1%
1/16W
MF-LF

402

182

2

1

R9778

402

MF-LF

1/16W

1%

90.9

2

1

R9775

1%
1/16W
MF-LF
402

90.9

2

1

R9774

402

0

MF-LF

1/16W

5%

21

R9773

5%

402

0

MF-LF

1/16W

21

R9772

10%
50V

CERM

402

0.001uF

21

C9774

1%
1/16W
MF-LF

402

182

2

1

R9770

5%

MF-LF

402

0

1/16W

21

R9769

5%

402

0

MF-LF

1/16W

21

R9768

MF-LF

1/16W

1%

402

182

2

1

R9766

5%
1/16W
MF-LF

0

402

21

R9765

402

0

MF-LF

1/16W

5%

21

R9764

5%
1/16W
MF-LF

402

0

21

R9761

0

402

MF-LF

1/16W

5%

21

R9760

CRITICAL

SM

370-OHM

4

32

1

L9706

402

0.1uF

10V

20%

CERM

2

1

C9751

0.1uF

402

CERM

10V

20%

2

1

C9750

SC70

MC74VHC1G08

5

4

1

2

3

U9750

SC70

MC74VHC1G08

5

4

1

2

3

U9751

402

1/16W
MF-LF

182

1%

2

1

R9762

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

External Display Connector

051-6941

12

104

97

=GND_CHASSIS_DVI1

=GND_CHASSIS_DVI5

=GND_CHASSIS_DVI3

TMDS_DATA_F_P<0>

TMDS_DATA_F_N<2>
TMDS_DATA_F_N<1>

TMDS_DATA_F_P<1>

DVI_DDC_CLK_R

DVI_DDC_DATA_R

VGA_VSYNC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=5V

PP5V_S0_DDC

TMDS_DATA_F_P<3>

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<3>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<2>

VGA_G

VGA_R

=GND_CHASSIS_DVI4

DVI_HPD_R

TMDS TMDS

TMDS_DATA_R_N<5..0>

TMDS_CLK_R_P

TMDS TMDS

=PP5V_S0_DVI_DDC

PP5V_S0_DDC_PULLUPS

VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI2

PP5V_S0_DDC_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

DVI_HPD

DVI_DDC_CLK

DVI_DDC_DATA

TMDS_CLK_F_P

TMDS_CLK_F_N

VGA_B

VGA_HSYNC

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

=PP3V3_S0_DDC_DVI

TMDS_DATA_F_P<0>

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<1>

TMDS_DATA_F_N<1>

TMDS_DATA_F_P<2>

TMDS_DATA_F_N<2>

TMDS_CLK_F_P

TMDS_CLK_F_N

TMDS_CLK_CMF

TMDS_CLK_R_N

TMDS_CLK_R_P

TMDS_DATA_F_P<3>

TMDS_DATA_F_N<3>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<4>

=PP3V3_S0_VGASYNC

=PP3V3_S0_VGASYNC

GPU_H2SYNC

GPU_V2SYNC

VGA_HSYNC_R

VGA_HSYNC

VGA_VSYNC_R

VGA_VSYNC

TMDSTMDS

TMDS_DATA_R_P<5..0>

TMDS TMDS

TMDS_CLK_R_N

TMDS_DATA_F_N<5..0>

TMDSCONNTMDSCONN

TMDS_DATA_F_P<5..0>

TMDSCONN TMDSCONN

TMDS_CLK_F_P

TMDSCONNTMDSCONN

TMDS_CLK_F_N

TMDSCONNTMDSCONN

VGA_B

VGA_G

VGA_R

GPU_B2

GPU_G2

GPU_R2

GPU_DDC_A_CLK

GPU_DDC_A_DATA

GPU_HPD

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<5>

TMDS_DATA_N<0>

TMDS_DATA_P<0>

TMDS_DATA_N<1>

TMDS_DATA_P<1>

TMDS_DATA_N<2>

TMDS_DATA_P<2>

TMDS_DATA_R_P<0>

TMDS_DATA_R_N<1>

TMDS_DATA_R_P<1>

TMDS_DATA_R_N<2>

TMDS_DATA_R_P<2>

TMDS_DATA_N<3>

TMDS_DATA_P<3>

TMDS_DATA_N<4>

TMDS_DATA_P<4>

TMDS_DATA_N<5>

TMDS_DATA_P<5>

TMDS_DATA_R_N<3>

TMDS_DATA_R_P<3>

TMDS_DATA_R_N<4>

TMDS_DATA_R_P<4>

TMDS_DATA_R_N<5>

TMDS_DATA_R_P<5>

TMDS_CLK_N

TMDS_CLK_P

TMDS_DATA_R_N<0>

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

75

75

79

79

79

79

74

74

74

79

79

74

74

74

74

74

74

74

74

74

74

74

74

74

74

6

75

75

75

75

75

75

75

75

75

75

75

75

75

6

75

75

63

6

75

75

75

75

75

75

63

75

75

75

75

75

75

75

75

75

75

75

75

75

75

63

63

73

73

75

75

75

75

75

75

75

75

75

75

75

73

73

73

73

73

73

75

75

73

73

73

73

73

73

75

75

75

75

75

73

73

73

73

73

73

75

75

75

75

75

75

73

73

75

BI
BI

IN

OUT

SYM_VER-1

IN

IN

OUT

OUT

SYM_VER-1

BI
BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0395

Left ALS Connector

516S0412

NC

NC

Bluetooth (M13P) & SATA HDD Flex Connector

NOTE: _UF_ nets cross DDR2 signals and pick
up significant noise. Common-mode chokes
are to remove this noise from SATA signals.

6

6

47

6 5

F-RT-SM

CRITICAL

FH19-4S-0.5SH-48

4

3

2

1

6

5

J6430

53

5

2012H

90-OHM-300mA

PLACEMENT_NOTE=Place FL4960 close to J4960
CRITICAL

4

32

1

FL4960

21

21

PLACEMENT_NOTE=Place C4960 close to southbridge

402

25V

CERM

10%

0.0047uF

21

C4960

PLACEMENT_NOTE=Place C4961 next to C4960

10%

402

0.0047uF

CERM

25V

21

C4961

21

21

90-OHM-300mA

2012H

CRITICAL

PLACEMENT_NOTE=Place FL4965 close to southbridge

4

32

1

FL4965

10%

0.0047uF

CERM

25V
402

PLACEMENT_NOTE=Place C4965 close to J4960

12

C4965

0.0047uF

402

10%

CERM

25V

PLACEMENT_NOTE=Place C4966 next to C4965

12

C4966

6

6

48

QT500206-L020

M-ST-SM

CRITICAL

9

87

65

43

20

2

19

1817

1615

1413

1211

10

1

J4960

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

98

104

12

051-6941

M1 Specific Connectors

SATA_C_D2R_UF_N

=PP5V_S3_IR

=PP3V3_S3_BT

=PP5V_S0_HDD

SATA_C_D2R_N

SATA_C_D2R_P

SATA_C_D2R_UF_P

SATA_C_D2R_C_P
SATA_C_D2R_C_N

LTALS_OUT

ALS_GAIN

SYS_LED_ANODE

=USB_IR_P

=USB_IR_N

=USB_BT_P

=USB_BT_N

SATA_C_R2D_P

SATA_C_R2D_N

SATA_C_R2D_UF_N

SATA_C_R2D_C_P

SATA_C_R2D_UF_P

SATA_C_R2D_C_N

=PP3V3_S3_LTALS

63

63

63

63

5

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: These parts are to counter an invalid state caused by the

LVDS Interface Pull-downs

on LVDS signals when they should be 0V.

the pump-up in the panel, though some voltage will still be seen

and long-term reliability issues. Pull-down resistors reduce

requirements. Resulting pump-up in LCD panel can cause startup

when they should be tri-stated to meet panel power sequence

M56 part. Bias voltage is present on LVDS interface pins even

10K

1/16W

5%

LVDS_PD

SM-LF

81

RP9900

5%

1/16W

10K

LVDS_PD

SM-LF

81

RP9902

5%

1/16W

10K

LVDS_PD

SM-LF

63

RP9902

10K

1/16W

5%

LVDS_PD

SM-LF

54

RP9902

5%

1/16W

10K

LVDS_PD

SM-LF

72

RP9903

1/16W

5%

10K

LVDS_PD

SM-LF

81

RP9903

5%

1/16W

10K

LVDS_PD

SM-LF

63

RP9903

10K

1/16W

5%

LVDS_PD

SM-LF

54

RP9903

5%

1/16W

10K

LVDS_PD

SM-LF

72

RP9900

10K

1/16W

5%

LVDS_PD

SM-LF

54

RP9900

5%

1/16W

10K

LVDS_PD

SM-LF

63

RP9900

5%

1/16W

10K

LVDS_PD

SM-LF

72

RP9901

10K

1/16W

5%

LVDS_PD

SM-LF

81

RP9901

5%

1/16W

10K

LVDS_PD

SM-LF

63

RP9901

10K

1/16W

5%

LVDS_PD

SM-LF

54

RP9901

10K

1/16W

5%

LVDS_PD

SM-LF

72

RP9902

051-6941 12

104

99

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

LVDS Interface Pull-downs

LVDS_L_DATA_N<0>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_L_CLK_N

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<1>

LVDS_U_DATA_N<2>

LVDS_U_CLK_N

LVDS_L_DATA_P<0>

LVDS_L_DATA_P<1>

LVDS_L_DATA_P<2>

LVDS_L_CLK_P

LVDS_U_DATA_P<0>

LVDS_U_DATA_P<1>

LVDS_U_DATA_P<2>

LVDS_U_CLK_P

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

73

73

73

73

73

73

73

73

73

73

73

73

73

73

73

73

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DMS Release #08000-11000 (EVT releases)

(11.9.0)

2005/12/02 - 4256256 - Added BOMOPTION to R8801 to allow per-project control.
2005/12/02 - 4363848 - Removed M56 GPU die rev B13 support from BOM.

2005/12/01 - 4347845 - RPAK pinswaps to LVDS pull-downs for PCB layout.

2005/12/01 - 4362566 - Restructured BOM for thick/thin PCB versions.

2005/12/01 - 4227340 - Changed supply for 1.8V S3 current sense amp.

2005/10/09 - 4235898 - Part moves & refdes changes to support sync with M9.

2005/10/10 - 4247941 - Net property updates found via back-annotation.

2005/10/10 - 4229560 - Removed Physical Security circuitry.

2005/10/10 - 4248911 - Sync with M38 & M42.

2005/08/31 - 4227328 - Added ESD protection diode on right USB port.

2005/08/31 - 4237025 - Added R8824 and R8827 for GPU memory configuration straps.

2005/08/31 - 4227315 - Changed BSA bus pull-ups from 2K to 10K.

DMS Checkin #11002

2005/11/22 - 4352020 - Changed 2.5V S3 supply inductor & compensation values.
2005/11/28 - 4347845 - Added pull-down resistors on LVDS interface.
2005/11/30 - 4227340 - Removed CPU VCore current sense input RC.

2005/10/10 - 4232826 - Swapped Vtt RPAK functions to optimize layout.

DMS Checkin #07007

2005/08/31 - 4227328 - Changed EMI caps from 50V to 16V to fid in ESD protection.

2005/09/03 - 4232534 - Added notes for power supplies and connectors.

DMS Checkin #04007

2005/09/06 - 4240486 - Removed NO_TEST property from GPU HSYNC and VSYNC.

2005/09/06 - 4232534 - Fixed label BOM tables to call out proper EEE #’s.

2005/09/08 - 4248911 - Sync with M38 & M42.

DMS Release #03000 (RFA #394758)

2005/08/12 - 4231030 - Changed pinout of J4960, added placement notes.

2005/08/27 - 4235213 - Changed R8305, R8310, R8315 to slow down FET RCs.

2005/08/27 - 4227325 - Removed S0 option for camera, now S3-only.

2005/10/08 - 4214493 - Simplified FireWire port power circuit for BOM consolidation.

2005/10/10 - 4214493 - Cost reductions to GPU power supply circuitry.

2005/10/11 - 4261313 - Updated SATA connector pinout to match latest flex.

2005/10/12 - 4214494 - Implemented circuit to power down ethernet in S3 on battery.

2005/10/17 - 4304248 - Updated GPU VCore / BBP voltages for B13/B24 support.

2005/11/16 - 4346006 - Updated J5500 pinout to match updated LIO board pinout.

2005/11/19 - 4229560 - Changed FW chip back to REQ/GNT3.

(11.7.0)

2005/11/21 - 4351196 - Added 1K pull-down on IDE_RESET_L.

(11.5.0)

2005/11/21 - 4343202 - Changed RC value and net name for USB OC.

2005/08/31 - 4240157 - Corrected pinout at SATA/BT conn (J4960) to match flex.
2005/08/31 - 4240150 - Swapped PCIE Mini Card R2D/D2R connections at J5500.

(11.4.0)

2005/10/14 - 4247941 - Restored NO_TEST properties, added EXPOSED_VIA properties.

2005/11/15 - 4310267 - Synced 5 pages from mlb_evt branch back to trunk.

2005/11/16 - 4235898 - Aliased connection to ALS_GAIN to support M9 request.

2005/11/16 - 4345921 - FUNC_TEST updates per test team request.

2005/11/16 - 4343202 - Changed USB overcurrent switch to TPS2051B, added OC* RC.

2005/11/16 - 4235898 - Sync with M38 & M42.

2005/11/18 - 4235898 - Changed R4210 package size per M9 request.

2005/11/19 - 4346184 - Fixed location of SATA R2D common-mode choke.

2005/11/19 - 4350840 - Simplified TMDS filtering to allow movement of filter.

2005/11/19 - 4292165 - Refreshed schematic symbol for U3750 (library update).

2005/08/29 - 4217524 - Changed R6430 from 4.5K to 3.5K.

2005/08/29 - 4232826 - Changed MEM_ODT* from RPAKs to discrete Rs.

2005/08/29 - 4235179 - Changed J8200 to proper 6-pin part.

2005/10/09 - 4272237 - Changed 2.5V S0 FET RC to 100K to slow down turn-on.

2005/08/29 - 4227335 - Changed U5900 to resolve ROHS issue.

2005/08/28 - 4232715 - Added FireWire ISense resistor, changed INA193 to INA194.

2005/08/27 - 4235208 - Changed value of R7707 to fix 2.5V S3 supply.

2005/08/27 - 4227369 - Removed SMC options for display/backlight, now GPU-only.

2005/08/30 - 4217535 - Removed BOM tables and OMITs for new 4-pin WTB connector.

2005/09/19 - 4235898 - Moved signal alias to improve schematic reuse.

DMS Checkin #04005

DMS Checkin #04006

DMS Checkin #04003

DMS Checkin #04001

DMS Checkin #04004

DMS Checkin #04002

2005/08/29 - 4227336 - Changed Y5920 to 197S0169.

2005/08/29 - 4237119 - Changed LIO 5V S3 to 5V S5.

2005/08/29 - 4227322 - Sync page 44 with M42 to fix FW power net S-states.

2005/08/29 - 4227312 - Resolved sync issues with M38 (SB page 23).

2005/09/16 - 4229560 - Changed FW PCI REQ/GNT pair for Physical Security.

2005/09/16 - 4256660 - Updated FUNC_TEST property for merged PBUS.

2005/09/08 - 4229560 - First implementation of Physical Security Guidelines.

2005/09/20 - 4214847 - Updated L1970 (old part no longer exists in library).

2005/09/21 - 4234952 - Replaced FDG6324L parts with FDG6332C for cost & supply.

2005/09/26 - 4274915 - Thermal sensor BOM updates from Proto 2 MLB branch.

Date - Radar # - Description

2005/09/26 - 4274915 - U6301 part number updated to M1 development BootROM.

2005/09/19 - 4247941 - GND line/neck/voltage properties updated per PCB request.

2005/09/21 - 4227306 - Changed CPU VCore caps to proper production part number.

2005/09/06 - 4246683 - Removed NO STUFF option from R8805 per ATI request.

2005/08/31 - 4232563 - Corrected net properties on R2/G2/B2 nets.

2005/08/27 - 4225433 - Changed PBUS voltage sense circuit.

2005/08/27 - 4230219 - Changed Y3301 to non-obsoleted part.

2005/08/28 - 4217524 - Added LEFT ALS connector (J6430).

DMS Release #05000-07000 (Proto 2 releases)

2005/08/28 - 4217535 - Added Left ALS FFC connector.

2005/08/28 - 4235203 - Changed BOM settings to stuff R2251.

2005/08/11 - 4214109 - Changed J4931 to proper 518S0342 part.

2005/10/11 - 4227308 - Deleted unnecessary MCH TVDAC filtering.

2005/10/07 - 4248911 - Sync with M38 & M42.

DMS Checkin #07004

DMS Checkin #07001

DMS Checkin #07002

2005/10/12 - 4298899 - Changed stuffing option to disable PLT_RST gating.

2005/10/12 - 4223808 - Power supply changes per vendor feedback.

DMS Checkin #07008

2005/08/28 - 4217535 - OMITs and tables to change 4-pin WTB connector parts.

2005/08/28 - 4225369 - OMITs and tables for staged LeMenu BOM approach.

2005/08/29 - 4227309 - Resolved sync issues with M38 (SB page 21).

2005/10/07 - 4286888 - BOM restructuring per EVT build plan.

DMS Checkin #07005

2005/10/12 - 4247941 - Added properties to resolve a PCB constraint issue.

2005/10/12 - 4298943 - Replaced last remaining non-RoHS compliant connector.

DMS Checkin #07009

2005/09/26 - 4239505 - Updated J4200 (old part no longer exists in library).

DMS Checkin #07003

2005/10/08 - 4286729 - Changed value of TPM Xtal caps.

2005/10/10 - 4295280 - Changed sleep LED connection per new SMC ERS.

2005/10/12 - 4248911 - Sync with M38 & M42.

2005/10/13 - 4247941 - Swapped pins at trackpad ESD protection diode.

2005/10/21 - 4235898 - Synced 2 pages from m9/mlb.

2005/08/28 - 4225369 - Changed ISL6269 PVCC aliases, added RC for 3.3V S5.
2005/08/28 - 4225433 - Changed PBUS Voltage Sense circuit.

2005/08/28 - 4235217 - Added RC on Q3820 gate to slow down ODD FET turn-on.

2005/08/28 - 4227323 - Repinned Top-Case Flex connector.

2005/08/29 - 4225369 - Changed 3.3V S5 sequence to follow 5V S5 PGOOD.

2005/08/29 - 4227310 - Resolved sync issues with M38 (SB page 22).

2005/08/29 - 4227332 - Resolved sync issues with M38 (SMC page 58).

2005/08/30 - 4225433 - Fixed voltage divider values in PBUS VSense circuit.

2005/09/02 - 4244019 - Moved GPU-related power alias from PP3V3_S0 to PP3V3_S0_GPU.

2005/09/08 - 4214493 - Combined RTC coin cell diodes into dual-diode package.

2005/09/03 - 4232534 - Fixed documentation of battery address on I2C page.

2005/09/08 - 4247941 - Net property & name changes to support PCB/ICT requests.

2005/10/13 - 4247941 - Removed NO_TEST properties from CPU FSB strobe signals.

2005/10/13 - 4247941 - Unswapped pins at trackpad ESD protection diode.

2005/08/31 - 4240486 - Power line width & neck reductions at PCB request.

2005/08/31 - 4240300 - Changed C6455 to a smaller part for cost & MCO.

2005/09/02 - 4241087 - Fixed pinout of USB D+/D- at camera connector to match FHB.

2005/11/16 - 4235898 - Changed Yukon power rail neck widths per M9 request.

2005/10/08 - 4290735 - Swapped trackpad & PCIe Mini Card USB connections.

2005/10/08 - 4293072 - Various BOM / connection changes at IMVP6 (CPU VCore).

2005/10/10 - 4214847 - Changed 0-ohm resistor to solder jumper.

2005/10/12 - 4227320 - Updated SB pin name for GPIO 5 (ODD_PWR_EN_L).

2005/10/13 - 4247941 - Spacing/Physical rule updates to match latest board database.

2005/10/21 - 4310267 - Synced 3 pages from mlb_evt branch back to trunk.

2005/11/15 - 4298899 - Removed unused platform reset gate.

2005/11/16 - 4345498 - Updated Ethernet & FireWire crystal part numbers.

2005/08/31 - 4227306 - Swapped primary & alt part numbers for CPU VCore caps.

2005/08/31 - 4223808 - Various power supply R/C updates, plus some R/C adds.

2005/08/31 - 4214109 - Reversed pinout of J4931 to match updated PCB footprint.

2005/08/31 - 4240257 - Swapped some top & bottom EMC connections at DVI connector.

2005/09/02 - 4243269 - Inverted GPU VCore control, adjusted supply R values.

2005/09/03 - 4244539 - Added GPUVCORE_PGOOD to 1.2V, 1.8V, & 2.5V S0 sequence.

2005/11/16 - 4346184 - Inserted common-mode chokes on SATA R2D/D2R pairs.

(11.2.0)

(11.1.0)

2005/11/19 - 4347717 - Changed SMS self-test pull-up to pull-down.

2005/11/16 - 4227333 - Fixed single-pin nets caused by SMC net name updates.

2005/11/18 - 4235898 - Changed C9710 GND connection per M9 request.

2005/11/16 - 4298899 - Fixed ethernet reset net name on page 26.

DMS Checkin #11001

2005/11/19 - 4350849 - Added option to connect SB_GPIO30 to ENET_LOM_DIS_L.
2005/11/19 - 4340256 - Changed topcase flex trackpad power from 3.3V to 5V.

2005/09/30 - 4261313 - Added placeholder connector for IR FFC connector.

2005/09/30 - 4248911 - Sync with M38 & M42.

2005/10/07 - 4292633 - Changed IMVP6 10K NTC from 10% to 5% part.

2005/11/03 - 4310267 - Synced 6 pages from mlb_evt branch back to trunk.

2005/11/15 - 4322537 - Updated thru-hole SO-DIMM connector part number.

(11.3.0)

2005/11/16 - 4227333 - Updated SMC net names per ERS v1.2.1.

2005/10/20 - 4310267 - Synced 4 pages from mlb_evt branch back to trunk.

2005/10/09 - 4214494 - Changed GPU VCore supply enable to use 1.2V/2.5V S3 PGOODs.

2005/10/06 - 4227330 - Added ESD protection on top-case USB port.

Date - Radar # - Description

2005/10/12 - 4298905 - Changed ethernet VMAIN_AVLBL connection.

2005/10/12 - 4214493 - Consolidated 0.22uF caps in design.

2005/10/12 - 4244539 - Retasked FET to control 3.3V S0 FET from GPU VCore PGOOD.

2005/10/12 - 4297684 - Split FW323 VSSA from VSS to reduce noise.

2005/10/11 - 4229560 - Changed SB GNT3#/GNT4# back to test points.

DMS Checkin #07006

2005/08/28 - 4235179 - Changed PBUS net names to merge PBUS A & PBUS B.

2005/08/28 - 4235179 - OMIT and table to change 8-pin DC-In connector to 6-pin.

2005/08/28 - 4227322 - Changed FW323 PCI_VIOS pin from 3.3V S0 to 3.3V S3.

2005/08/28 - 4221973 - Added pull-up for SB GPIO22 (REQ4#).

2005/08/28 - 4232563 - Changed analog video from Y/C/Comp to G2/R2/B2.

2005/08/27 - 4235401 - Moved a few pins at LIO BTB connector.

Changes from Proto Branch (DMS Release #04000):

2005/09/03 - 4227315 - Changed SMBus pull-ups to 4.7K.

2005/09/03 - 4244484 - Changed P1V5S0_RUNSS circuit to work properly in G3Hot.

2005/09/02 - 4240486 - Adjusted line/neck widths, changed J4931 to 518S0371.

2005/10/17 - 4292633 - Changed remaining 10K NTCs to new 5% part.

2005/10/26 - 4310267 - Synced 4 pages from mlb_evt branch back to trunk.

(11.6.0)

2005/09/29 - 4232826 - Swapped Vtt RPAK functions to free up unnecessary part.

2005/11/30 - 4331670 - Added CRITICAL flags to some more parts.

2005/11/22 - 4350840 - Swapped TMDS termination components for placement.

2005/09/28 - 4221965 - Added 2.2uF caps on SO-DIMM VREF pins.

2005/11/30 - 4351181 - Changed ITP connector BOM option.

2005/11/30 - 4343864 - Added EMI/ESD parts at camera connector.

2005/11/30 - 4358831 - Added pull-downs on two SB-to-SMC signals.

2005/11/30 - 4351196 - Changed IDE_RESET_L pull-down from 1K to 15K.

(11.8.0)

Date - Radar # - Description

2005/09/28 - 4278828 - Adjusted P5VS5_PGOOD R’s, added cap on PM_RSMRST_L.

2005/09/30 - 4282162 - Changed GPU BBN supply to MAX1673.

2005/09/30 - 4282349 - Added CRITICAL flags to parts identified in scrub.
2005/09/30 - 4274915 - C1001 stuffing change from Proto 2 MLB branch.

2005/10/04 - 4256409 - Changed fan CTL series R’s to 2N7002 level-shifter.
2005/10/04 - 4261313 - Deleted placeholder connector, grew HDD connector for IR.

DMS Checkin #11003

2005/12/01 - 4362404 - Changed TMDS diff term from 100-ohm to 180-ohm.
2005/12/01 - 4352020 - Changed 2.5V supply inductor to RoHS-compliant part.

2005/10/04 - 4281394 - BOM option change to stuff right USB ESD protection part.

DMS Release #12000

(11.10.0)

2005/12/02 - 4363870 - Removed M1a support from BOM.
2005/12/02 - 4217524 - Updated part number for J6430.

SYNC_DATE=N/A

SYNC_MASTER=N/A

12

100 104

12

051-6941

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

I70

I71

I72

I73

SYNC_DATE=(MASTER)

M1 Net Properties

051-6941

12

104104

SYNC_MASTER=(MASTER)

TMDS_DATA_F_N<2..0>

TMDSCONNTMDSCONN

TMDS_DATA_F_N<5..3>

TMDSCONNTMDSCONN

TMDS_DATA_F_P<2..0>

TMDSCONNTMDSCONN

TMDS_DATA_F_P<5..3>

TMDSCONNTMDSCONN

TMDS_DATA_N<2..0>

TMDSTMDS

TMDS_DATA_N<5..3>

TMDSTMDS

TMDS_DATA_P<2..0>

TMDSTMDS

TMDS_DATA_P<5..3>

TMDSTMDS

TMDS_CLK_F_P

TMDSCONNTMDSCONN

TMDS_CLK_F_N

TMDSCONNTMDSCONN

FSB_LOCK_L

FSB_COMMON

FSB_55S

MEM_DQS MEM_85D

FB_CLK FB_75D

SATA

SATA_100D

ENET

ENET_100D

CPU_COMP<1>

CPU_COMP

CPU_55S

SMB

SMB_55S

FSB_BPRI_L

FSB_COMMON

FSB_55S

CPU_XDP_CLK_N

CPU_ITP

CLK_FSB_100D

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S

CPU_INTR

CPU_55S

FSB_ADSTB_L<3..0>

FSB_ADSTB

FSB_55S

FSB_D_L<63..0>

FSB_DATA

FSB_55S

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

USB2 USB2_90D

FW

FW_110D

CLK_FSB

CLK_FSB_100D

FSB_TRDY_L

FSB_COMMON

FSB_55S

FSB_CPURST_L

FSB_COMMON

FSB_55S

FSB_DBSY_L

FSB_COMMON

FSB_55S

FSB_DSTBP_L<3..0>

FSB_DSTB

FSB_55S

FSB_DINV_L<3..0>

FSB_DATA

FSB_55S

FSB_DSTBN_L<3..0>

FSB_DSTB

FSB_55S

CPU_COMP<2>

CPU_COMP

CPU_27P4S

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_GTLREF

CPU_GTLREF

CPU_55S

PM_DPRSLPVR

CPU_2TO1

CPU_55S

CPU_IGNNE_L

CPU_55S

CPU_DPSLP_L

CPU_55S

CPU_A20M_L

CPU_55S

CPU_NMI

CPU_55S

CPU_PWRGD

CPU_55S

IMVP_DPRSLPVR

CPU_2TO1

CPU_55S

FSB_FERR_L

CPU_55S

FSB_A_L<31..3>

FSB_ADDR

FSB_55S

CPU_VCCSENSE_N

THERM

CPU_VCCSENSE

CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_27P4S

CPU_XDP_CLK_P

CPU_ITP

CLK_FSB_100D

XDP_BPM_L<5..0>

CPU_ITPCPU_55S

FSB_BREQ0_L

FSB_COMMON

FSB_55S

FSB_ADS_L

FSB_COMMON

FSB_55S

MEM_CMD MEM_55S

MEM_CLK MEM_70D
MEM_CTRL

MEM_45S

MEM_DATA

MEM_55S

CPU_SMI_L

CPU_55S

CPU_INIT_L

CPU_55S

FB_ADCTRL

FB_55S

FB_ADCTRL

FB_35S_TO_55S

FB_DATA

FB_40S

DMI

DMI_100D

FSB_IERR_L

CPU_55S

CPU_THERMTRIP_L

CPU_2TO1

CPU_55S

FSB_HIT_L

FSB_COMMON

FSB_55S

IDE

IDE_55S

CLK_PCIE

CLK_PCIE_100D

CLK_MED

CLK_MED_55S

SB_ACZ_RST_L

AUDIO

AUDIO_55S

ACZ_RST_L

AUDIO

AUDIO_55S

ACZ_SDATAOUT

AUDIO

AUDIO_55S

SB_ACZ_SDATAOUT

AUDIO

AUDIO_55S

ACZ_SDATAIN<0>

AUDIO

AUDIO_55S

ACZ_SYNC

AUDIO

AUDIO_55S

TMDS_CLK_N

TMDSTMDS

SB_ACZ_SYNC

AUDIO

AUDIO_55S

FSB_DEFER_L

FSB_COMMON

FSB_55S

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_BNR_L

FSB_COMMON

FSB_55S

TMDS_CLK_P

TMDSTMDS

PCIE

PCIE_100D

TMDS

TMDS_100D

LVDS

LVDS_100D

VGA

VGA_75S

CPU_STPCLK_L

CPU_55S

FSB_REQ_L<4..0>

FSB_ADDR

FSB_55S

FSB_DPWR_L

FSB_COMMON

FSB_55S

SPI

SPI_55S

CLK_SLOW CLK_SLOW_55S

ACZ_BITCLK

AUDIO

AUDIO_55S

SB_ACZ_BITCLK

AUDIO

AUDIO_55S

CPU_VCCSENSE_P

THERM

CPU_VCCSENSE

CPU_27P4S

CPU_VID<6..0>

CPU_2TO1

CPU_55S

CPU_VID<6..0>

CPU_2TO1

CPU_55S

ITPRESET_L

CPU_ITPCPU_55S

75

75

75

75

12

12

12

12

12

12

12

12

12

57

12

12

12

12

45

45

45

45

75

12

12

75

12

45

79

79

74

74

74

74

7

12

34

21

7

7

7

12

12

11

7

7

7

7

23

21

21

21

21

21

7

57

34

11

7

7

21

21

7

21

21

21

21

74

12

7

7

74

21

7

12

21

57

9

9

75

75

75

75

73

73

73

73

75

75

5

7

7

11

57

7

5

5

5

7

7

7

5

5

5

5

7

7

7

14

7

7

7

7

7

57

5

8

57

7

11

7

5

5

7

7

7

5

21

5

5

21

5

5

73

21

7

5

5

73

7

5

7

5

21

8

8

8

11