Apple A1150 Schematic Rev12

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

DVT Build - 12/02/2005

Schematic / PCB #’s

Mullet

M1 MLB

12/03/05

412764ENGINEERING RELEASED

12

?

051-6941

12

1

104

SCHEM,MULLET,M1

Table of Contents

N/A

N/A

1

1

Date

(.csa)

SyncContentsPage

42

FireWire Ports

(MASTER)

(MASTER)

46

TITLE=MULLET

ABBREV=DRAWING

LAST_MODIFIED=Fri Dec 2 23:03:42 2005

Page

(.csa)

SyncContents

Date

1

SCH

051-6941

SCHEM,MULLET,M1

CRITICAL

1

PCBF,MULLET,M1

PCB

820-1881 CRITICAL

PCB_THICK

1

PCB

CRITICAL PCB_THIN920-0342

PCBF,MULLET_THIN,M1

43

Internal USB Connections

(MASTER)

(MASTER)

49

44

External USB Connector

(MASTER)

(MASTER)

52

45

Left I/O Board Connector

(MASTER)

(MASTER)

55

46

PCI-E Connections

(MASTER)

(MASTER)

57

47

SMC

10/07/2005

M38

58

48

SMC Support

(MASTER)

(MASTER)

59

49

LPC+ Debug Connector

07/20/2005

M42

60

50

Thermal Sensors

(MASTER)

(MASTER)

61

51

Current & Voltage Sensing

(MASTER)

(MASTER)

62

52

SPI BOOTROM

11/16/2005

M42

63

53

ALS Support

(MASTER)

(MASTER)

64

54

Fan Connectors

(MASTER)

(MASTER)

65

55

Sudden Motion Sensor (SMS)

(MASTER)

(MASTER)

66

56

TPM

11/16/2005

M38

67

57

IMVP6 CPU VCore Regulator

(MASTER)

(MASTER)

75

58

5V / 1.5V Power Supply

(MASTER)

(MASTER)

76

59

2.5V & 1.2V Regulators

(MASTER)

(MASTER)

77

60

1.8V Supply

(MASTER)

(MASTER)

78

61

3.3V / 1.05V Power Supplies

(MASTER)

(MASTER)

79

62

3.3V G3Hot Supply & Power Control

(MASTER)

(MASTER)

80

63

Power Aliases

(MASTER)

(MASTER)

81

64

PBus-In & Battery Connectors

(MASTER)

(MASTER)

82

65

ATI M56 PCI-E

(MASTER)

(MASTER)

84

66

GPU (M56) Core Supplies

(MASTER)

(MASTER)

85

67

ATI M56 Core Power

(MASTER)

(MASTER)

86

68

ATI M56 Frame Buffer I/F

(MASTER)

(MASTER)

87

69

GPU Straps

(MASTER)

(MASTER)

88

70

GDDR3 Frame Buffer A

(MASTER)

(MASTER)

89

71

GDDR3 Frame Buffer B

(MASTER)

(MASTER)

90

72

ATI M56 GPIO/DVO/Misc

(MASTER)

(MASTER)

91

73

ATI M56 Video Interfaces

(MASTER)

(MASTER)

93

74

Internal Display Connectors

(MASTER)

(MASTER)

94

75

External Display Connector

(MASTER)

(MASTER)

97

76

M1 Specific Connectors

(MASTER)

(MASTER)

98

77

LVDS Interface Pull-downs

(MASTER)

(MASTER)

99

78

Revision History

N/A

N/A

100

79

M1 Net Properties

(MASTER)

(MASTER)

104

System Block Diagram

N/A

N/A

2

2

Power Block Diagram

N/A

N/A

3

3

BOM Configuration

N/A

N/A

4

4

Functional / ICT Test

N/A

N/A

5

5

Signal Aliases

N/A

N/A

6

6

CPU 1 OF 2-FSB

M42

11/16/2005

7

7

CPU 2 OF 2-PWR/GND

M42

11/16/2005

8

8

CPU Decoupling & VID

(MASTER)

(MASTER)

9

9

CPU MISC1-TEMP SENSOR

M42

10/07/2005

10

10

CPU ITP700FLEX DEBUG

M42

10/12/2005

11

11

NB CPU Interface

(MASTER)

(MASTER)

12

12

NB PEG / Video Interfaces

(MASTER)

(MASTER)

13

13

NB Misc Interfaces

(MASTER)

(MASTER)

14

14

NB DDR2 Interfaces

(MASTER)

(MASTER)

15

15

NB Power 1

(MASTER)

(MASTER)

16

16

NB Power 2

(MASTER)

(MASTER)

17

17

NB Grounds

(MASTER)

(MASTER)

18

18

NB (GM) Decoupling

(MASTER)

(MASTER)

19

19

NB Config Straps

(MASTER)

(MASTER)

20

20

SB: 1 OF 4

M38

11/16/2005

21

21

SB: 2 of 4

(M38)

09/08/2005

22

22

SB: 3 OF 4

M38

11/16/2005

23

23

SB: 4 OF 4

M38

11/16/2005

24

24

SB Decoupling

M42

11/16/2005

25

25

SB Misc

(MASTER)

(MASTER)

26

26

M1 SMBus Connections

(MASTER)

(MASTER)

27

27

DDR2 SO-DIMM Connector A

(MASTER)

(MASTER)

28

28

DDR2 SO-DIMM Connector B

(MASTER)

(MASTER)

29

29

Memory Active Termination

(MASTER)

(MASTER)

30

30

Memory Vtt Supply

(MASTER)

(MASTER)

31

31

DDR2 VRef

(MASTER)

(MASTER)

32

32

CLOCKS

M42

10/12/2005

33

33

Clock Termination

(MASTER)

(MASTER)

34

34

Mobile Clocking

(MASTER)

(MASTER)

35

37

PATA Connector

(MASTER)

(MASTER)

36

38

ETHERNET CONTROLLER

M42

10/12/2005

37

41

Ethernet Connector

(MASTER)

(MASTER)

38

42

Yukon Power Control

(MASTER)

(MASTER)

39

43

FIREWIRE CONTROLLER

(M42)

08/29/2005

40

44

FireWire Port Power

(MASTER)

(MASTER)

41

45

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SYNC_DATE=N/A

12

System Block Diagram

SYNC_MASTER=N/A

051-6941

2

104

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

5V/1.5V

PM_SLP_S3_L

U8500

PP3V3_S0

NC

3.3V

1.5V

PP3V3_S5

PGOOD

(ISL6269)

S5

3.3V

ENABLE

U7900

?V

PPVCORE_S0_CPU

1.05V

PP1V05_S0

PGOOD

1.05V

U7950

1.2V - 1.0V

PPVCORE_S0_GPU

S0

(ISL6269)

PGOOD

GPU VCore

ENABLE

3.3V

NC

(LTC3412)

S3

PGOOD

1.2V

ENABLE

U7750

1.2V

PP1V2_S3

2.5V

PP2V5_S0

2.5V

PP2V5_S3

NC

(LTC3411)

2.5V
S3

PGOOD

ENABLE

U7700

3.3V

PP3V3_S3

PP5V_S0

5.0V

PP5V_S3

PP1V5_S0

5.0V

PP5V_S5

SMC_PM_G2_ENABLE

NC

(LTC3728)

S5/S0

PGOOD

ENABLES

U7600

5V

1.5V

PM_SLP_S3_L

SMC_PM_G2_ENABLE

PGOOD

VR_PWRGOOD_DELAY

"IMVP6"

S0

(ISL6262)

CPU VCore

U7500

ENABLES

IMVP_PWRGD_IN

IMVP_VR_ON

RSMRST_PWRGD

(ISL6269)

S0

IMVP_PWRGD_IN/ALL_SYS_PWRGD

PM_SLP_S3_L

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S3_LS5V_L

Q8305

Q8310

Q8315

Q8320

ENABLE

ENABLE

J5500

Connector

Inverter

PP1V8_S3

1.8V

NC

1.8V

U7800

S3

ENABLE

(ISL6269)

PGOOD

PM_SLP_S3_L

U3100

0.9V (Vtt)
S0

(BD3533FVM)

PP0V9_S0

0.9V

FWPWR_EN

Q4565

12.6V - 9V

PPBUS_S5_FWPORT

Q8300

Q8330

PP1V2_S0

1.2V

PM_SLP_S3_LS5V_L

PM_SLP_S3_LS5V_L

Q8325

PP1V8_S0

1.8V

5.0V

U8000

3.425V

PP3V42_G3H

(LT3470)

G3Hot

3.425

ENABLE

12.6V - 9V

PPBUS_G3H_B

18.5V - 9V

PPDCIN_G3H

J5500

J8200

LIO Flex

Connector

LIO Power

12.6V - 9V

PPBUS_G3H_A

Connector

PM_SLP_S4_L

SYNC_DATE=N/A

SYNC_MASTER=N/A

3

104

12

051-6941

Power Block Diagram

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

"Better" BOMs

Phantom BOM #’s

"LeMenu Stage #3" Parts

The above stages and build settings are per 8/25 strategy statement.

LeMenu Stage Mappings

"Best" BOMs

Phantom BOMs

BOMOPTION Groups

"LeMenu Stage #1" Parts

The number of parts managed as Le Menu decreases as a project progresses.

"LeMenu Stage #2" Parts

M1,BTR,HY128

M1,BST,SAM256

M1,BST,HY256

M1,BST,HY128

M1,BST,SAM128

M1,BTR,SAM128

Bar Code Label / EEE #’s

Module Parts

VRAM_256_SAMSUNG

333S0350 CRITICAL

U8900,U8950,U9000,U9050

4

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

4

CRITICAL333S0358

VRAM_128_HYNIX

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

4

CRITICAL333S0351

VRAM_256_HYNIX

VRAM_128_SAMSUNG

CRITICAL333S0354

4

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

CRITICAL

1

826-4393

EEE_UNK

[EEE:UNK]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEE:UR8]

EEE_UR8

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL
CRITICAL

[EEE:UR9]

EEE_UR9

1

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

CRITICAL

1

826-4393

[EEE:UNJ]

EEE_UNJ

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

EEE_TYY

CRITICAL

[EEE:TYY]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEE:UNH]

EEE_UNH

BOM3

256SAM,B13,MULLET,M1

075-0138

1

075-0138 CRITICAL

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-6941

BOM Configuration

12

104

4

LEMENU_STAGE1

CRITICAL

IC,SMC,HS8/2116

338S0274

1

U5800

U4102

CRITICAL

LEMENU_STAGE1

341S1797

1

IC,EEPROM,SERIAL IIC,8KBIT,SO8

LEMENU_STAGE2,LEMENU_STAGE3

LEMENU_PROTOEVTDVT

PROJ_PVTRAMP

BOOTROM_FINAL,LEMENU_STAGE1,LEMENU_STAGE2

075-0154

128HY,MULLET,M1

GPU_MEM_HYNIX,VRAM_128_HYNIX

075-0138

256SAM,MULLET,M1

GPU_MEM_256M,VRAM_256_SAMSUNG

075-0155

256HY,MULLET,M1

GPU_MEM_256M,GPU_MEM_HYNIX,VRAM_256_HYNIX

ENETPWR_S3AC,GPU_BB_CTL,GPUTHM_A_GPU,HSTHMSNS_HAS,INVERTER_BUF

M1_COMMON1

KBDLED_HAS,LVDS_PD,MEMVREF_S3,MEMVTT_EN_PU,PCB_THICK

M1_COMMON2

RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU,USB_G_OC_PU

M1_COMMON3

U6301

CRITICAL

1

341S1813

IC,EFI,BOOTROM FINAL,M1

BOOTROM_FINAL

1

CRITICAL

IC,EFI,BOOTROM DEVELOPMENT,M1

341S1812

U6301

BOOTROM_DEVEL

LEMENU_PVTRAMP

LEMENU_STAGE3

PROJ_PROTOEVTDVT

BOOTROM_DEVEL,LEMENU_STAGE1

LEMENU_LOCALPROTO

BOOTROM_DEVEL,LEMENU_STAGE1,LEMENU_STAGE2,LEMENU_STAGE3

LEMENU_STAGE3

CRITICAL

1

343S0385

IC,SB,652BGA

U2100

CRITICAL

1

U0700

337S3268

IC,M1 BST,479 BGA

CPU_BST

CRITICAL

LEMENU_STAGE3

1

338S0269

IC,945GM,SOUTHBRIDGE

U1200

CRITICAL

1

U0700

337S3267

IC,M1 BTR,479 BGA

CPU_BTR

341S1789

U6700

1

CRITICAL

IC, TPM, 28-PIN TSSOP

LEMENU_STAGE2

IC,CY28445-5,CLOCK GEN,68PIN QFN

U3301

359S0101

1

CRITICAL

LEMENU_STAGE1

U7530

353S1235

1

IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE

LEMENU_STAGE1

CRITICAL

338S0309 CRITICAL

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

1

U8400

LEMENU_STAGE1

BOM2 075-0171075-0171

1

CRITICAL

LE MENU,MULLET BST,M1

BOM3 075-0155075-0155

1

CRITICAL

256HY,MULLET,M1

BOM3 075-0154

1

075-0154 CRITICAL

128HY,MULLET,M1

BOM3 CRITICAL 075-0156075-0156

1

128SAM,MULLET,M1

BOM2 CRITICAL 075-0140

1

075-0140

LE MENU,MULLET BTR,M1

BOM1

PROJ PTS,MULLET,M1

075-0139075-0139

1

CRITICAL

M1_DEBUG

DEVELOPMENT,ITP,LPCPLUS

M1_COMMON

M1_COMMON1,M1_COMMON2,M1_COMMON3

075-0156

128SAM,MULLET,M1 VRAM_128_SAMSUNG

CPU_BST,LEMENU_PROTOEVTDVT

075-0171

LE_MENU,MULLET_BST,M1

CPU_BTR,LEMENU_PROTOEVTDVT

075-0140

LE_MENU,MULLET_BTR,M1

075-0139

COMMON,M1_COMMON,M1_DEBUG,PROJ_PROTOEVTDVTPROJ_PTS,MULLET,M1

PCBA,MULLET_BST,HY256,M1

075-0139,075-0171,075-0155,EEE_UNJ

630-7402

PCBA,MULLET_BST,SAM256,M1

075-0139,075-0171,075-0138,EEE_TYY

630-7254

PCBA,MULLET_BST,HY128,M1

075-0139,075-0171,075-0154,EEE_UR9

630-7430

PCBA,MULLET_BST,SAM128,M1

075-0139,075-0171,075-0156,EEE_UR8

630-7429

PCBA,MULLET_BTR,SAM128,M1

075-0139,075-0140,075-0156,EEE_UNK

630-7403

PCBA,MULLET_BTR,HY128,M1

075-0139,075-0140,075-0154,EEE_UNH

630-7401

LEMENU_STAGE1

U4101

CRITICAL338S0270

1

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

CRITICAL

LEMENU_STAGE1

U4400

1

IC,FW32306,1394A LINK,BGA,129P

338S0268

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FUNC_TEST

Left I/O Power Connector

Left ALS Connector

Battery Digital Connector

Functional Test Points

2 TPs per

Current Sense Calibration

Other Func Test Points

FUNC_TEST

FUNC_TEST

Thermal Diode Connectors

FUNC_TEST

Camera Connector

Left I/O Data Connector

Fan Connectors

LPC+ Debug Connector

FUNC_TEST

FUNC_TEST

FUNC_TEST FUNC_TEST

EXPOSED_VIA

Misc EXPOSED_VIA Nets

EXPOSED_VIA

EXPOSED_VIA property indicates that the net
should have a via with 10-mil soldermask
opening for use as engineering probe point.

FUNC_TEST

FUNC_TEST property removed
since these test points
are not on the proper side
for Functional Test points.

FUNC_TEST

NO_TEST

NO_TEST

EXPOSED_VIA

Power Supply NO_TESTs

CPU FSB NO_TESTs

8 TPs, 2 with each of above TP pairs

called out separately in these notes.

NOTE: 10 additional GND test points are

Request for at least 10 GND test points

051-6941

12

104

5

SYNC_MASTER=N/A

SYNC_DATE=N/A

Functional / ICT Test

TRUE

GND\g

TRUE

GND\g

TRUE

GND\g

TRUE

GND\g

TRUE

P1V8S3_COMP

TRUE

P1V05S0_FSET

TRUE

GPUVCORE_FSET

TRUE

FSB_A_L<31..3>
FSB_ADS_L

TRUE

TRUE

FSB_BNR_L

TRUETRUE

FSB_DINV_L<3..0>
FSB_DRDY_L

TRUE

TRUE

GPUBBP_ADJ

TRUE

GPUVCORE_COMP

TRUE

FSB_DSTBN_L<3..0>

TRUE

TRUE

FSB_HIT_L

TRUE

P3V42G3H_FB

TRUE

FSB_DBSY_L

TRUE

P1V5S0_RUNSS

TRUE

P1V2S3_RUNSS

TRUE

P1V2S3_RT

TRUE

P3V3S5_COMP

TRUE

P3V3S5_FSET

TRUE

P2V5S3_SHDNRT

TRUE

P5VS5_RUNSS

TRUE

IMVP6_COMP

TRUE

IMVP6_RBIAS

TRUE

P2V5S3_MODE

TRUE

P1V8S3_FSET

TRUE

P1V05S0_COMP

=PP3V3_S5_LPCPLUS

TRUE

TRUE

ACZ_SDATAOUT

SMC_BATT_CHG_EN

TRUE

SMC_BC_ACOK

TRUE

TRUE

=PP1V5_S0_LIO
=PPDCIN_G3H_LIO

TRUE
TRUE

=PP5V_S5_LIO

PP5V_S0_AUDIO

TRUE

PCIE_CLK100M_EXCARD_N

TRUE

TRUE

=PCIE_EXCARD_D2R_N

=SMBUS_BATT_SCL

TRUE

SMC_BS_ALRT_L

TRUE

=SMBUS_BATT_SDA

TRUE

SMC_ADAPTER_EN

TRUE

TRUE

=PCIE_EXCARD_D2R_P

TRUE

=PCIE_EXCARD_R2D_P

=USB2_EXCARD_N

TRUE

=USB2_EXCARD_P

TRUE

=USB2_LT_N

TRUE

=USB2_LT_P

TRUE

ACZ_SYNC

TRUE

SMC_EXCARD_PWR_EN

TRUE
TRUE

LIO_PLT_RESET_L

SMC_EXCARD_CP

TRUE

EXCARD_CLKREQ_L

TRUE

MINI_CLKREQ_L

TRUE

SMC_BATT_TRICKLE_EN_L

TRUE

LIO_P3V3S3_EN

TRUE

TRUE

LIO_DCIN_ISENSE

LIO_BATT_ISENSE

TRUE

SMC_SYS_ISET

TRUE

TRUE

SMC_TDO
SMC_MD1

TRUE

SMC_TRST_L

TRUE

PP5V_S0_AUDIO_PWR

TRUE

=PP3V42_G3H_LIO

TRUE

TRUE

GND_AUDIO_PWR

TRUE

GND_AUDIO

SMC_RX_L

TRUE

SMC_RST_L

TRUE

SMC_TX_L

TRUE

LPC_AD<1>

TRUE

TRUE

ACZ_SDATAIN<0>

=PP5V_S0_LPCPLUS

TRUE

DEBUG_RST_L

TRUE

BOOT_LPC_SPI_L

TRUE

PM_CLKRUN_L

TRUE

LPC_FRAME_L

TRUE

LPC_AD<0>

TRUE

SMC_TMS

TRUE

TRUE

ACZ_BITCLK

PCIE_CLK100M_EXCARD_P

TRUE

TRUE

FSB_ADSTB_L<1..0>

TRUE

TRUE

FSB_D_L<63..0>

TRUE

FSB_BREQ0_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_LOCK_L

TRUE

FSB_HITM_L

TRUETRUE

FSB_DSTBP_L<3..0>

TRUE

DMI_N2S_N<1..0>

TRUE

DMI_N2S_P<1..0>

TRUE

SB_CLK100M_SATA_N

TRUE

SB_CLK100M_SATA_P

FAN_RT_TACH

FAN_LT_PWM
FAN_LT_TACH

FAN_RT_PWM

=PP5V_S0_FAN_LT

TRUE

LPC_AD<3>

PCI_CLK_PORT80_LPC

TRUE

LPC_AD<2>

TRUE

INT_SERIRQ

TRUE

SMC_TDI

TRUE

=PCIE_EXCARD_R2D_N

TRUE

SV_SET_UP

TRUE

SMC_NMI

TRUE

SMC_TCK

TRUE

PM_SUS_STAT_L

TRUE

FWH_INIT_L

TRUE

=SMBUS_ATS_SDA

TRUE

TRUE

=PP3V3_S3_LTALS

TRUE

ALS_GAIN
LTALS_OUT

TRUE

TRUE

RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

=USB2_CAMERA_P

TRUE

=SMBUS_ATS_SCL

TRUE

PM_SYSRST_L

TRUE

SMC_ONOFF_L

TRUE

=PP1V05_S0_REG

TRUE

TRUE

HSTHMSNS_DX_P

=PP5V_S0_ISENSECAL

TRUE

PP1V8_S3_REG

TRUE

PP1V5_S0_REG

TRUE

PPVCORE_S0_GPU

TRUE

PPVCORE_S0_CPU

TRUE

GND_BATT

TRUE

TRUE

LTUSB_OC_L

TRUE

ACZ_RST_L

TRUE

EXCARD_OC_L

SMC_BATT_ISET

TRUE

LIO_P3V3S0_EN_L

TRUE

SYS_ONEWIRE

TRUE

=USB2_CAMERA_N

TRUE

=PP5V_S3_CAMERA

TRUE

=PCIE_MINI_R2D_N

TRUE
TRUE

=PCIE_MINI_R2D_P

TRUE

=PCIE_MINI_D2R_P

TRUE

=PCIE_MINI_D2R_N

TRUE

PCIE_CLK100M_MINI_P

TRUE

=SMBUS_LIO_SMC_SCL

TRUE

PCIE_CLK100M_MINI_N

TRUE

=SMBUS_LIO_SMC_SDA

TRUE

=SMBUS_LIO_SB_SCL

TRUE

=SMBUS_LIO_SB_SDA

TRUE

PCIE_WAKE_L

=PPBUS_G3H_LIO_CONN

TRUE

HSTHMSNS_DX_N

TRUE

ISENSE_CAL_EN

TRUE

56

56

48

56

49

56

56

56

56

56

49

51

79

79

79

79

79

79

79

79

79

48

48

64

47

79

48

48

49

49

49

49

49

79 49

47

49

49

49

79

79

79

79

79

79

79

79

49

49

49

49

49

48

49

76

47

48

63

79

48

48

45

12

12

12

12

12

12

12

12

62

59

62

63

45

47

47

63

63

63

45

46

64

48

64

45

46

46

45

45

45

45

45

47

45

47

45

45

47

62

51

51

47

48

49

49

63

48

48

48

47

45

63

49

47

40

47

47

48

45

45

12

12

12

12

12

12

12

22

22

34

34

63

47

49

47

47

48

46

49

49

48

47

48

43

76

47

76

43

43

26

47

61

45

45

45

47

62

47

43

63 46

46

46

46

45

45

45

45

45

45

37

64

60

61

66

7

7

7

7

7

66

66

7

7

62

7

58

39

59

61

61

59

58

57

57

59

60

61

49

21

45

45

45

45

45

45

34

45

27

47

27

41

45

45

6

6

6

6

21

45

26

45

34

34

45

45

45

45

45

47

47

47

45

45

45

45

47

47

47

21

21

49

26

22

23

21

21

47

21

34

7

7

7

7

7

7

7

14

14

21

21

54

54

54

54

54

21

34

21

23

47

45

23

47

47

23

21

27

63

6

53

50

50

6

27

23

43

51

50

63

63

63

63

64

6

21

6

45

45

45

6

43 45

45

45

45

34

27

34

27

27

27

23

63

50

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"ENET_LOM_DISABLE" are mutually-exclusive.

NOTE: BOM options "USB_G_OC_PU" and

Ethernet Power Management Support

NOTE: NB_CFG<13..12> require test access

Trace deleted to make room for other diffpairs over RAM connector.

USB Port "H" = Reserved (PCI-E Mini Card)

USB Port "E" = ExpressCard

USB Port "B" = Trackpad (Geyser)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "G" = Bluetooth (M13P)

USB Port "C" = Left USB 2.0 Port

USB Port "F" = IR Receiver

USB Port "D" = Camera

Chassis connection to be made at the mounting hole east of the LVDS connector

Chassis connection to be made at the mounting hole northwest of the DVI connector

Chassis connection to be made at the mounting hole southwest of the USB connector

HOLE-VIA-P5RP25

1

ZT0600

HOLE-VIA-P5RP25

1

ZT0601

HOLE-VIA-P5RP25

1

ZT0602

SHLD-SM-LF

OG-503040

3

2

1

SH0600

22

5%
1/16W
MF-LF

402

ENET_LOM_DISABLE

0

21

R0600

37

SYNC_DATE=N/A

SYNC_MASTER=N/A

6

104

12

051-6941

Signal Aliases

=GND_CHASSIS_DVI5

=GND_CHASSIS_DVI3

GND_CHASSIS_DVI_BOT

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI1

=GND_CHASSIS_DVI2
=GND_CHASSIS_DVI4

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V

MAKE_BASE=TRUE

GND_CHASSIS_DVI_TOP

MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_ENET
=GND_CHASSIS_FW_EMI
=GND_CHASSIS_FW_PORT1
=GND_CHASSIS_RTUSB

MAKE_BASE=TRUE

LTUSB_OC_L

=USB_IR_P

USB_F_P

=USB2_LT_N

USB_E_P

=USB2_EXCARD_P
=USB2_EXCARD_N

MAKE_BASE=TRUE

USB_BT_N

USB_BT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_EXCARD_P

=USB2_CAMERA_N

USB2_CAMERA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_CAMERA_P

USB_G_P
USB_G_N

USB_E_N

MAKE_BASE=TRUE

EXCARD_OC_L

USB_E_OC_L

USB_D_OC_L

USB_D_N

=USB2_LT_P

=USB_TRACKPAD_N

MAKE_BASE=TRUE

USB_TRACKPAD_N

MAKE_BASE=TRUE

USB_TRACKPAD_P

=RTUSB_OC_L

RTUSB_OC_L

MAKE_BASE=TRUE

USB_C_N
USB_C_OC_L

USB_C_P

MAKE_BASE=TRUE

UNUSED_USB_B_OC_L

USB_B_OC_L

USB_B_N

USB_B_P

USB_A_OC_L

USB_A_N

USB_A_P

=USB2_RT_N

=USB2_RT_P

USB2_RT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_RT_N

=GND_CHASSIS_LCD1

=GND_CHASSIS_INVERTER

=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD3

GND_CHASSIS_LVDS

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

NC_CPU_A32_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A33_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A34_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A35_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A37_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A38_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A39_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_HFPLL

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE0

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE2

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_SPARE1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE4

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_CPU_A32_L

TP_CPU_A33_L

TP_CPU_A34_L

TP_CPU_A35_L

TP_CPU_A37_L

TP_CPU_A36_L

TP_CPU_A38_L

TP_CPU_A39_L

TP_CPU_APM1_L

TP_CPU_EXTBREF

TP_CPU_SPARE0

TP_CPU_SPARE2

TP_CPU_SPARE1

TP_CPU_SPARE4

MAKE_BASE=TRUE

UNUSED_USB_D_OC_L

USB_F_N

=USB_BT_N

=USB_IR_N

USB_IR_P

MAKE_BASE=TRUE

USB_IR_N

MAKE_BASE=TRUE

USB_D_P

=USB_TRACKPAD_P

USB2_LT_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_LT_N

NC_CPU_EXTBREF

MAKE_BASE=TRUE
NO_TEST=TRUE

TP_CPU_HFPLL

NC_CPU_APM0_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_APM1_L

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_CPU_A36_L

MAKE_BASE=TRUE
NO_TEST=TRUE

GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_LCD2

=USB2_CAMERA_P

USB2_EXCARD_N

MAKE_BASE=TRUE

USB_H_P
USB_H_N

TP_USB2_HP

MAKE_BASE=TRUE

TP_USB2_HN

MAKE_BASE=TRUE

TP_CPU_APM0_L

=USB_BT_P

MEM_A_A<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_A<15..14>

MEM_B_A<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_A<15..14>

NB_CFG<4..3>

MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<6>

NB_CFG<8>

MAKE_BASE=TRUE

TP_NB_CFG<8>

NB_CFG<11..10>

MAKE_BASE=TRUE

TP_NB_CFG<11..10>

NB_CFG<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<15..14>

NB_CFG<17>

MAKE_BASE=TRUE

TP_NB_CFG<17>

NB_CFG<13..12>

MAKE_BASE=TRUE

TP_NB_CFG<13..12>

SUS_CLK_SB

MAKE_BASE=TRUE

TP_SB_SUS_CLK

TP_SB_XOR_T5

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_T5

TP_SB_XOR_V3

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_V3

TP_SB_XOR_U5

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_U5

TP_SB_XOR_W3

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_W3

TP_SB_XOR_V4

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_SB_XOR_V4

SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

=RTALS_GAIN

MAKE_BASE=TRUE

ALS_GAIN

ENET_CTRL12

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_ENET_CTRL12

ENET_CTRL25

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_ENET_CTRL25

ENET_LOM_DIS_L

SB_GPIO30

48

76

45

45

45

45

43

45

45

43

47

75

75

75

75

75

38

42

42

44

5

76 22

5

22

5

5

5

22

22

22

5

22

22

22

5

43

44

22

22

22

22

22

22

22

22

22

44

44

74

74

74

74

7

7

7

7

7

7

7

7

7

7

7

7

7

7

22

76

76

22

43

7

74

5

22

22

7

76

28

29

14

14

14

14

14

14

14

23

21

21

21

21

21

47

53

5

37

37

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN
IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

A7*

RSVD14
RSVD15

BCLK1

BCLK0

RSVD20

RSVD17
RSVD18
RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1*
BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6
RSVD7
RSVD8

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

RSVD9
RSVD10

SMI*

LINT0
LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30*
A31*

A27*
A28*
A29*

A26*

A25*

A24*

A22*
A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14*
A15*
A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1 ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2
COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52*
D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45*
D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0
BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26*
D27*
D28*

D24*
D25*

D23*

D21*
D22*

D20*

D19*

D18*

D16*
D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF
NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

0.1" AWAY

ROUTE TO TP VIA AND

SPARE[7-0],HFPLL:

STUB)

PM_THRMTRIP#
SHOULD CONNECT TO

CPU_PROCHOT_L TO SMC

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".

ICH7-M AND GMCH

LAYOUT NOTE: 0.5" MAX LENGTH

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

PLACE GND VIA W/IN 1000 MILS

TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WITHOUT T-ING (NO

AND CPU VR TO INFORM
CPU IS HOT

1%

54.9

MF-LF
402

1/16W

2

1

R0702

68

1/16W

5%
402

MF-LF

2

1

R0704

1K

MF-LF
402

1%
1/16W

2

1

R0705

2.0K

MF-LF
402

1%
1/16W

2

1

R0706

1%

402

54.9

21

R0719

27.4

21

R0718

1%

402

54.9

21

R0717

27.4

402

21

R0716

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79

12

5

79 12

5

79 12

5

57 21

79 21

79 12

12

57

79 21

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79

12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

34

34

34

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

5

79 12

79 12

79 12

5

79 12

5

79 12

5

79 12

5

79

12

5

79

12

5

79 11

79 11

79 11

79 11

79 11

79 11

11

26 11

10

48 21 14

79 21

79 12 11

79 12

79 12

79 12

79 12

11

7

11

7

11

7

11

10

34

34

79 21

79 21

79 21

79 21

79 21

79 21

21

NOSTUFF

402

0

21

R0730

1/16W

5%
402

MF-LF

1K

NOSTUFF

2

1

R0707

51

1/16W

5%
402

MF-LF

2

1

R0712

402

MF-LF

1/16W

1%

54.9

2

1

R0703

1%

402

54.9

21

R0720

54.9

402

1%

21

R0721

1%

402

54.9

21

R0722

OMIT

CPU

YONAH

BGA

AB6

G2

AB5

C7

A25

A24

AB3

AA6

AC5

D5

A3

B2

V3

T2

N5

M4

AA3

AB2

C24

AA4

C23

D22

AF1

C1

D3

F6

D2

T22

B25

C3

AA1

G3

F4

F3

B1

L5

J3

K2

H2

K3

D21

AC1

AC2

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V4

L2

H1

J1

N2

M1

K5

M3

L4

Y1

W2

J4

Y4

W5

W3

T3

T5

R4

U2

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L1

P2

P5

N3

U0700

OMIT

BGA

YONAH

CPU

D25

C26

D7

D6

AE6

A2

AD26

AE24

Y25

N25

G22

AD23

W24

M24

H23

D24

B5

E5

AC20

V23

M26

J26

G24

K24

E23

AF26

AF22

AF25

AE25

E25

AD21

AE21

AD24

AF23

AE22

AD20

AC25

AB21

AA21

AB22

G25

AC23

AC22

AA24

AC26

Y22

Y26

AA26

Y23

W22

AB25

F23

U22

U25

U23

W25

V26

V24

AB24

AA23

N24

T25

H22

L26

R24

T24

P23

P22

P25

M23

L23

L22

L25

E26

R23

P26

K25

N22

H25

K22

F26

H26

J23

J24

F24

E22

V1

U1

U26

R26

C21

B23

B22

U0700

CPU 1 OF 2-FSB

SYNC_MASTER=M42

7

12

051-6941

104

SYNC_DATE=11/16/2005

FSB_RS_L<0>
FSB_RS_L<1>

XDP_BPM_L<5>

FSB_HITM_L

FSB_HIT_L

FSB_RS_L<2>
FSB_TRDY_L

=PP1V05_S0_CPU

XDP_BPM_L<1>

FSB_DBSY_L

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

XDP_TMS

XDP_TDI

XDP_TCK

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>

FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_ADSTB_L<0>

FSB_REQ_L<2>

FSB_REQ_L<0>
FSB_REQ_L<1>

FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>

FSB_A_L<23>

FSB_A_L<22>
FSB_A_L<24>

FSB_A_L<25>
FSB_A_L<26>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<31>

FSB_A_L<30>
FSB_ADSTB_L<1>

CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L

CPU_STPCLK_L
CPU_NMI

CPU_INTR
CPU_SMI_L

TP_CPU_APM1_L

TP_CPU_APM0_L

TP_CPU_A36_L

TP_CPU_A35_L

TP_CPU_A34_L

TP_CPU_A33_L

TP_CPU_A32_L

TP_CPU_A39_L

TP_CPU_A38_L

TP_CPU_A37_L

TP_CPU_HFPLL

FSB_DEFER_L
FSB_DRDY_L

FSB_BREQ0_L
FSB_IERR_L

CPU_INIT_L
FSB_LOCK_L
FSB_CPURST_L

XDP_BPM_L<0>
XDP_BPM_L<2>

XDP_BPM_L<3>
XDP_BPM_L<4>

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L

CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N

PM_THRMTRIP_L

TP_CPU_EXTBREF
TP_CPU_SPARE0

TP_CPU_SPARE3

TP_CPU_SPARE6

TP_CPU_SPARE5

TP_CPU_SPARE4

TP_CPU_SPARE7

FSB_CLK_CPU_P
FSB_CLK_CPU_N

TP_CPU_SPARE2

TP_CPU_SPARE1

FSB_A_L<7>

CPU_GTLREF

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>

FSB_D_L<17>

FSB_D_L<16>
FSB_D_L<18>

FSB_D_L<19>
FSB_D_L<20>

FSB_D_L<22>

FSB_D_L<21>
FSB_D_L<23>
FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>

FSB_DSTBP_L<1>
FSB_DINV_L<1>

CPU_TEST1
CPU_TEST2

CPU_BSEL<1>

CPU_BSEL<0>

FSB_DSTBN_L<1>

CPU_BSEL<2>

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>

FSB_D_L<46>

FSB_D_L<45>

FSB_DSTBP_L<2>

FSB_D_L<47>
FSB_DSTBN_L<2>

FSB_DINV_L<2>
FSB_D_L<48>

FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>

FSB_D_L<53>

FSB_D_L<52>
FSB_D_L<54>

FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_DINV_L<3>

FSB_DSTBN_L<3>
FSB_DSTBP_L<3>

CPU_COMP<0>
CPU_COMP<1>

CPU_COMP<3>

CPU_COMP<2>

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD
FSB_SLPCPU_L
CPU_PSI_L

FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L

63

63

63

63

11

11

11

11

9

9

9

9

8

8

8

8

11

11

11

7

7

7

7

7

7

7

6

6

6

6

6

6

6

6

6

6

6

79

6

6

6

6

6

79 79

79

79

79

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VSS_82
VSS_83
VSS_84
VSS_85

VSS_87

VSS_86

VSS_88
VSS_89
VSS_90

VSS_92

VSS_91

VSS_93
VSS_94
VSS_95

VSS_97

VSS_96

VSS_100

VSS_98
VSS_99

VSS_102

VSS_101

VSS_105

VSS_103
VSS_104

VSS_106
VSS_107

VSS_110

VSS_109

VSS_108

VSS_111
VSS_112

VSS_115

VSS_114

VSS_113

VSS_116
VSS_117
VSS_118

VSS_120

VSS_119

VSS_123

VSS_121
VSS_122

VSS_124
VSS_125

VSS_128

VSS_126
VSS_127

VSS_129
VSS_130

VSS_133

VSS_131
VSS_132

VSS_134
VSS_135

VSS_138

VSS_136
VSS_137

VSS_139
VSS_140
VSS_141

VSS_143

VSS_142

VSS_146

VSS_144
VSS_145

VSS_147
VSS_148

VSS_151

VSS_150

VSS_149

VSS_152
VSS_153

VSS_156

VSS_155

VSS_154

VSS_157
VSS_158
VSS_159

VSS_161

VSS_160

VSS_162

VSS_1
VSS_2
VSS_3

VSS_5

VSS_4

VSS_6
VSS_7
VSS_8

VSS_10

VSS_9

VSS_11
VSS_12

VSS_15

VSS_13
VSS_14

VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

VSS_23

VSS_22

VSS_21

VSS_24
VSS_25

VSS_28

VSS_27

VSS_26

VSS_29
VSS_30

VSS_33

VSS_32

VSS_31

VSS_34
VSS_35

VSS_38

VSS_37

VSS_36

VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

VSS_46

VSS_44
VSS_45

VSS_47
VSS_48

VSS_51

VSS_49
VSS_50

VSS_52
VSS_53

VSS_56

VSS_54
VSS_55

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

VSS_63

VSS_62

VSS_64
VSS_65
VSS_66

VSS_69

VSS_68

VSS_67

VSS_70
VSS_71

VSS_74

VSS_73

VSS_72

VSS_75
VSS_76

VSS_79

VSS_78

VSS_77

VSS_80
VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59
VCC_60

VCC_58

VCC_57

VCC_56

VCC_54
VCC_55

VCC_53

VCC_51
VCC_52

VCC_49
VCC_50

VCC_48

VCC_47

VCC_46

VCC_44
VCC_45

VCC_43

VCC_41
VCC_42

VCC_40

VCC_39

VCC_38

VCC_36
VCC_37

VCC_33

VCC_35

VCC_34

VCC_31
VCC_32

VCC_29
VCC_30

VCC_28

VCC_26
VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18
VCC_19

VCC_17

VCC_16

VCC_15

VCC_13
VCC_14

VCC_12

VCC_10
VCC_11

VCC_8
VCC_9

VCC_7

VCC_6

VCC_5

VCC_3
VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82
VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90
VCC_91
VCC_92

VCC_94

VCC_93

VCC_95
VCC_96
VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12
VCCP_13
VCCP_14

VCCP_16

VCCP_15

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTH

VCCSENSE AND VSSSENSE LINES

LAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE

VID FOR CPU POWER SUPPLY
IF NO USE, NEED PULL-UP OR
PULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

79

9

79

9

79

9

79

9

79

9

79

9

1/16W

1%
402

MF-LF

100

2

1

R0803

79

9

79 57

79 57

100

MF-LF
402

1%
1/16W

2

1

R0802

OMIT

BGA

YONAH

CPU

V22

V5

V2

U24

U21

U6

U3

T26

T23

T4B6

T1

R25

R22

R5

R2

P24

P21

P6

P3

N26

A26

N23

N4

N1

M25

M22

M5

M2

L24

L21

L6

A23

L3

K26

K23

K4

K1

J25

J22

J5

J2

H24

A19

H21

H6

H3

G26

G23

G1

G4

F25

F22

F2

A16

F19

F16

F13

F11

F8

F5

E24

E21

E19

E16

A14

E14

E11

E8

E6

E3

D26

D23

D19

D16

D13

A11

D11

D8

D4

D1

C25

C22

C2

C19

C16

C14

A8

C11

C8

C5

AF24

AF21

AF19

B24

AF16

AF13

AF11

AF8

AF6

AF3

AE26

AE23

AE19

AE16

B21

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

AD13

B19

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

AC11

B16

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

AB8

B13

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

AA5

B11

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

V25

B8

A4

U0700

OMIT

BGA

YONAH

CPU

AE7

AE2

AF2

AE3

AF4

AE5

AF5

AD6

AF7

N21

M21

K21

J21

M6

K6

J6

G21

W21

V21

T6

T21

R6

R21

N6

V6

B26

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

AE17

A20

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

AD12

A18

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

AC7

A17

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

AB9

A15

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

F20

A13

F18

F17

F15

F14

F12

F10

F9

F7

E20

E18

A12

E17

E15

E13

E12

E10

E9

E7

D18

D17

D15

A10

D14

D12

D10

D9

C18

C17

C15

C13

C12

C10

A9

C9

B20

B18

B17

B15

B14

B12

B10

B9

AF20

B7

A7

U0700

CPU 2 OF 2-PWR/GND

SYNC_MASTER=M42

051-6941

12

8

104

SYNC_DATE=11/16/2005

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU
CPU_VID<0>

CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

63

63

63

51

11

51

9

9

9

8

7

8

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

VCCA (CPU AVdd) Decoupling

1x 470uF, 6x 0.1uF 0402

between CPU and NB

1x 10uF, 1x 0.01uF

4x 470uF. 20x 22uF 0805

CPU VCORE VID Connections

Resistors to allow for override of CPU VID
Will probably be removed before production

VCCP (CPU I/O) Decoupling

CPU VCORE HF AND BULK DECOUPLING

NOTE: This cap is shared

6.3V

20%
X5R

805

22uF

2

1

C0906

6.3V

20%
X5R

22uF

805

2

1

C0904

6.3V

20%
X5R

22uF

805

2

1

C0916

6.3V

20%
X5R

22uF

805

2

1

C0914

6.3V

20%
X5R

22uF

805

2

1

C0908

6.3V

20%
X5R

22uF

805

2

1

C0903

6.3V

20%
X5R

22uF

805

2

1

C0907

6.3V

20%
X5R

22uF

805

2

1

C0902

6.3V

20%
X5R

805

22uF

2

1

C0901

6.3V

20%
X5R

805

22uF

2

1

C0913

6.3V

20%
X5R

22uF

805

2

1

C0912

6.3V

20%
X5R

22uF

805

2

1

C0911

6.3V

20%
X5R

22uF

805

2

1

C0919

6.3V

20%
X5R

22uF

805

2

1

C0900

6.3V

20%
X5R

22uF

805

2

1

C0910

0.1UF

CERM
402

20%
10V

2

1

C0936

20%

2.5V
TANT

D2T

470uF-7MOHM

CRITICAL

32

1

C0935

6.3V

20%
X5R

22uF

805

2

1

C0905

6.3V

20%
X5R

22uF

805

2

1

C0909

20%
X5R

22uF

6.3V
805

2

1

C0915

6.3V

20%
X5R

22uF

805

2

1

C0917

0.1UF

CERM
402

20%
10V

2

1

C0937

0.1UF

CERM
402

20%
10V

2

1

C0938

0.1UF

CERM
402

20%
10V

2

1

C0939

0.1UF

CERM
402

20%
10V

2

1

C0940

0.1UF

CERM
402

20%
10V

2

1

C0941

22uF

X5R

20%

6.3V
805

2

1

C0918

20%

D2T

2.5V
TANT

470uF-7MOHM

CRITICAL

3 2

1

C0950

20%

2.5V
D2T

TANT

470uF-7MOHM

CRITICAL

3 2

1

C0952

470uF-7MOHM

20%

2.5V
TANT
D2T

CRITICAL

3 2

1

C0953

470uF-7MOHM

20%

2.5V
TANT
D2T

CRITICAL

3 2

1

C0954

16V

0.01UF

CERM
402

20%

2

1

C0981

X5R

10uF

20%

6.3V
603

2

1

C0980

0

5%
1/16W
MF-LF

402

21

R0996

0

5%
1/16W
MF-LF

402

21

R0995

402

MF-LF

1/16W

5%

0

21

R0993

402

1/16W

5%

0

MF-LF

21

R0994

402

MF-LF

1/16W

5%

0

21

R0991

402

MF-LF

1/16W

5%

0

21

R0992

402

MF-LF

1/16W

5%

0

21

R0990

CPU Decoupling & VID

051-6941

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

12

9

104

IMVP6_VID<6>

CPU_VID<1>

CPU_VID<3>

IMVP6_VID<3>

CPU_VID<5>

IMVP6_VID<5>

CPU_VID<0>

IMVP6_VID<0>

CPU_VID<2>

IMVP6_VID<2>

CPU_VID<4>

IMVP6_VID<4>

CPU_VID<6>

IMVP6_VID<1>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

63 11

63

79

79

79

79

79

79

79

8

63

51

57

8

8

57

8

57

8

57

8

57

8

57

8

57

7

8

8

D+
D-

ALERT*/

THM*

SCLK

SDATA

VDD

GND

THM2*

BI
BI

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACEHOLDER ADT7461A

LAYOUT NOTE:

(TO CPU INTERNAL THERMAL DIODE)

CPU_THERMD_N

LAYOUT NOTE:

CPU ZONE THERMAL SENSOR

ROUTE CPU_THERMD_P AND

10 MIL TRACE

LAYER.

10 MIL SPACING

FOR CPU_THERMD_P AND CPU_THERMD_N ON SAME

ADD GND GUARD TRACE

PLACE U1001 NEAR THE U1200

CRITICAL

MSOP

ADT7461

1

4

7

8

5

3

2

6

U1001

MF-LF

499

1/16W

402

1%

21

R1001

CERM

50V

0.001uF

10%

402

2

1

C1001

27

27

X5R

0.1UF

16V

10%

402

2

1

C1002

7

7

499

1%

MF-LF

402

1/16W

21

R1002

1/16W

5%

402

10K

MF-LF

2

1

R1005

10K

1/16W
402

MF-LF

5%

2

1

R1006

051-6941

12

10

104

SYNC_MASTER=M42

SYNC_DATE=10/07/2005

CPU MISC1-TEMP SENSOR

THRM_CPU_DX_P
THRM_CPU_DX_N

CPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_THRM_SNR

THRM_ALERT_L
THRM_ALERT

SMB_THRM_CLK
SMB_THRM_DATA

50

50

63

OUT
OUT
OUT

OUT

OUT

IN

IN
IN

BI

BI

BI

BI

BI

BI

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)

(AND WITH RESET BUTTON)

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

NC

NC

NC

(DBA#)
(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

MF-LF

22.6

1%

1/16W

402

ITP

21

R1100

ITP

402

1%

22.6

1/16W
MF-LF

21

R1102

54.9

1/16W

1%
402

MF-LF

ITP

2

1

R1103

402

X5R

16V

10%

0.1UF

2

1

C1100

1/16W

240

402

MF-LF

5%

2

1

R1104

F-RT-SM

52435-2872

CRITICAL

ITPCONN

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J1101

1/16W
402

54.9

1%
MF-LF

2

1

R1101

680

402

5%
1/16W
MF-LF

2

1

R1106

7

7

7

11

7

11

7

7

79 34

79

7

79

7

79

7

79

7

79

7

79

7

79 12

7

CPU ITP700FLEX DEBUG

SYNC_DATE=10/12/2005

051-6941

12

11 104

SYNC_MASTER=M42

=PP1V05_S0_CPU

FSB_CPURST_L

XDP_BPM_L<0>

XDP_TCK

XDP_TDI

XDP_TDO

=PP3V3_S5_SB_PM

=PP1V05_S0_CPU

XDP_TMS

CPU_XDP_CLK_N

XDP_TRST_L

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

CPU_XDP_CLK_P

ITP_TDO

XDP_DBRESET_L

ITPRESET_L

63

63

11

11

9

63

9

8

26

8

7

23

7

79

BI

BI
BI

OUT

OUT

OUT

BI

BI

BI

BI
BI

BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

BI
BI
BI
BI

BI
BI

OUT

BI

OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI

IN

BI

IN

BI

BI

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM*
HLOCK*

HHIT*

HDSTBP2*
HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1*
HDSTBN2*

HDSTBN0*

HDINV2*
HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP
HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10*
HD11*
HD12*
HD13*
HD14*

HD5*

HD7*
HD8*
HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21*
HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10*
HA11*
HA12*

HADSTB1*

HREQ0*
HREQ1*
HREQ2*
HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI

BI
BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

79

7 5

79

7 5

79

7 5

79 11

7

79

7

79

7

79

7 5

79

7 5

79

7 5

79

7

79

7 5

79

7 5

402

X5R

16V

10%

0.1uF

2

1

C1211

200

1%
1/16W
MF-LF
402

2

1

R1211

100

1%
1/16W
MF-LF
402

2

1

R1210

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7

79

7 5

7

79

7

79

7

79

7

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

34

79

7 5

34

54.9

1%
1/16W
MF-LF

402

2

1

R1220

402

MF-LF

1/16W

1%

24.9

2

1

R1221

221

1%
1/16W
MF-LF
402

2

1

R1225

1%
1/16W
MF-LF
402

100

2

1

R1226

0.1uF

402

X5R

16V

10%

2

1

C1226

402

X5R

16V

10%

0.1uF

2

1

C1236

221

1%
1/16W
MF-LF
402

2

1

R1235

54.9

1%
1/16W
MF-LF

402

2

1

R1230

79

7 5

1%
1/16W
MF-LF
402

100

2

1

R1236

402

MF-LF

1/16W

1%

24.9

2

1

R1231

79

7 5

BGA

NB

945GM

OMIT

W1

U1

Y1

E4

E2

E1

E7

E3

D6

E6

B4

A8

F8

B8

G8

D8

B3

D4

D3

K13

AC5

AA5

T6

K3

AC4

Y5

T7

K4

H8

J9

AB10

U3

W8

J7

C3

A7

K1

K9

G2

AC8

AD4

AD10

AB5

G1

AC6

AD7

AC1

AD9

AD1

AC2

AB3

AC11

AB11

AC9

K2

AB4

AA1

Y8

AA10

AA6

AA2

AA7

AA4

W2

AB8

H3

Y10

W5

Y7

Y3

W3

W4

AA9

AB7

T5

W6

J6

T9

U5

W7

T4

T8

T1

W9

T11

U11

U9

H1

U7

T3

W11

T10

G4

K11

J3

H4

J8

K7

J1

F1

B7

AG1

AG2

C7

F6

C6

J13

C13

B9

E8

F9

G12

F11

G11

E11

C9

D14

C14

H9

A14

C12

B14

B12

F12

G13

E13

A13

A12

C11

A11

D12

F14

J15

H13

J14

D9

G14

J12

H11

U1200

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

79

7 5

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB CPU Interface

12

12

104

051-6941

FSB_D_L<17>

FSB_DSTBN_L<2>
FSB_DSTBN_L<3>

FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>

FSB_DINV_L<0>

FSB_DSTBN_L<0>

FSB_DINV_L<1>
FSB_DINV_L<2>

NB_FSB_VREF

FSB_D_L<1>
FSB_D_L<2>

FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<3>

FSB_D_L<0>

FSB_D_L<16>

FSB_TRDY_L

FSB_SLPCPU_L

FSB_RS_L<1>

FSB_RS_L<0>

FSB_HITM_L
FSB_LOCK_L

FSB_HIT_L

FSB_DSTBP_L<0>

FSB_DSTBN_L<1>

FSB_DINV_L<3>

FSB_DRDY_L

FSB_DPWR_L

FSB_DEFER_L

FSB_DBSY_L

FSB_CPURST_L

FSB_BREQ0_L

FSB_BPRI_L

FSB_BNR_L

FSB_CLK_NB_N

FSB_CLK_NB_P

NB_FSB_YSWING

NB_FSB_YRCOMP
NB_FSB_YSCOMP

NB_FSB_XSWING

NB_FSB_XSCOMP

FSB_A_L<13>

FSB_ADS_L
FSB_ADSTB_L<0>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<15>

FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<31>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<21>
FSB_A_L<22>

FSB_A_L<17>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>

FSB_ADSTB_L<1>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>

FSB_D_L<30>

FSB_REQ_L<4>

FSB_RS_L<2>

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

NB_FSB_XRCOMP

63

63

63

34

34

34

19

19

19

12

12

12

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF
TV_IRTNA

TV_DACB_OUT
TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK
L_DDC_DATA

EXP_A_COMPI
EXP_A_COMPO

EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8

EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11
EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9
EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15

L_CLKCTLB

L_BKLTEN
L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

IN

OUT

IN

OUT
OUT
OUT
OUT

IN
IN

OUT
OUT
OUT

OUT

IN

OUT

OUT

BI

IN

IN
IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

IN

BI
BI

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

OUT
OUT
OUT

OUT

OUT

OUT

BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#
SDVO_INT#

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:
Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implemented
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

BGA

NB

945GM

OMIT

B19

B18

B16

J20

A19

C18

A16

F29

F28

D30

D29

G30

F30

E27
E26

A37

A36

B35

B34

C37

B37

A33
A32

C32

C33

F32

C35

B38

G25

G26

H29

H30

J30

D32

G23

R40

P36

N40

M36

L40

J36

H40

G36

AB40

AA36

Y40

W36

V40

T36

F40

D36

T40

R36

P40

N36

M40

L36

J40

H36

AC40

AB36

AA40

Y36

W40

V36

G40

F36

R38

P34

N38

M34

L38

J34

H38

G34

AB38

AA34

Y38

W34

V38

T34

F38

D34

T38

R34

P38

N34

M38

L34

J38

H34

AC38

AB34

AA38

Y34

W38

V34

G38

F34

D38

D40

H23

B21

A21

J22

B22

C22

C25

C26

D23

E23

U1200

65

65

402

MF-LF

1/16W

1%

24.9

2

1

R1310

19

65

19

19

19

19

19

19

19

19

19

19

65

19

19

19

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

19

19

19

19

65

19

19

19

19

19

19

19

19

65

19

19

19

19

19

19

19

19

19

19

65

19

19

19

19

19

19

19

19

051-6941

12

104

13

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NB PEG / Video Interfaces

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<15>

CRT_BLUE_L

CRT_BLUE

CRT_GREEN_L

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFL

LVDS_VREFH

TP_LVDS_VBG

LVDS_IBG

LVDS_DDC_CLK
LVDS_DDC_DATA

PEG_COMP

PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<11>
PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>
PEG_R2D_C_P<0>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

LVDS_BKLTEN
LVDS_CLKCTLA

LVDS_BKLTCTL

=PP1V5_S0_NB_PCIE

LVDS_CLKCTLB

CRT_VSYNC_R

CRT_HSYNC_R

63 19

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2
RSVD3

RSVD6

RSVD4
RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10
RSVD11
RSVD12
RSVD13

CFG1

CFG0

CFG2
CFG3
CFG4

CFG6

CFG5

CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14

CFG17

CFG16

CFG15

CFG18
CFG19
CFG20

PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*

SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*

NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

NC0
NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0
SM_CK1
SM_CK2

SM_CK0*

SM_CK3

SM_CK1*
SM_CK2*
SM_CK3*

SM_CKE0
SM_CKE1

SM_CKE3

SM_CS1*
SM_CS2*
SM_CS3*

SMOCDCOMP0
SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0
SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

IN

IN

IN

IN

OUT

OUT

IN
IN

IN

BI
BI
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN

IN
IN
IN
IN
IN
IN

IN
IN
IN
IN

IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC
NC

IPD

IPD

(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)

(H_EDRDY#)

(D_PLLMON1)

(H_PROCHOT#)

(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)

(H_PLLMON1)

(H_PLLMON1#)

(H_PCREQ#)

(VSS_MCHDETECT)

(D_PLLMON1#)

NC
NC
NC

NC

NC

NC

NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

NC
NC
NC
NC
NC

IPU

IPD

IPU

IPU

IPU
IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

NC

NC

IPU

IPU

NC

NC

NC

BGA

NB

945GM

OMIT

AK41

AK1

AV9
AT9

AF10

AL20

AU21

AY20

BA12

BA13

AW21

AY21

AW12

AW13

AY29

BA29

AT20

AU20

AY40

AW40

AY7

AW7

AT1

AR1

AW35

AY35

H27

H28

K30

J19

H7

AF11

AG11

F7

F3

R32

D27

D28

A34

A35

A41

J29

T32

AH34

AH33

G6

H26

F25

G28

B41

BA1

BA2

BA3

BA39

BA40

BA41

C1

A3

A39

A4

A40

AW1

AW41

AY1

AY41

B2

C41

D1

K28

AF33
AG33

AG41

AF37

AE41

AC37

AH41

AG37

AF41

AE37

AG39

AF35

AE39

AC35

AH39

AG35

AF39

AE35

C40
D41

A27
A26

H32

G16

D16

D19

E18

F15

E15

F18

J26

J18

K27

J25

H15

G18

H16

C15

K15

G15

D15

E16

K18

K16

U1200

6

6

20

402

MF-LF

1/16W

5%

100

21

R1430

26

10K

402

5%
MF-LF

1/16W

2

1

R1441

10K

402

5%
1/16W
MF-LF

2

1

R1440

32

0.1uF

402

CERM

10V

20%

2

1

C1416

0.1uF

402

CERM

10V

20%

2

1

C1415

23

48 21

7

48 47

79 57 23

57 26

19

19

22

33

28

29

29

28

28

29

29

28

30 28

30 28

30 29

30 28

30 29

30 28

30 29

30 29

30 28

30 28

30 29

30 29

1/16W

1%

402

MF-LF

80.6

2

1

R1410

1/16W

1%

402

MF-LF

80.6

2

1

R1411

32

34

34

19

19

19

19

22

22

22

22

22

22

22

22

22

5

22

22

22

5

22

5

22

5

22

22

1/16W

5%

402

MF-LF

10K

2

1

R1420

34

34

34

20

20

6

20

6

6

6

6

6

6

20

6

20

6

20

NB Misc Interfaces

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

14

TP_NB_XOR_FSB2_H7

TP_NB_XOR_LVDS_D27

TP_NB_XOR_LVDS_D28

TP_NB_XOR_LVDS_A34

MEM_VREF_NB_1

MEM_VREF_NB_0

MEM_RCOMP

MEM_RCOMP_L

=PP1V8_S3_MEM_NB

MEM_CKE<2>

MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>

MEM_ODT<1>
MEM_ODT<2>

NB_CFG<12>

MEM_CS_L<0>

NB_BSEL<1>

NB_BSEL<0>

NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>

NB_CFG<6>

NB_CFG<5>

NB_CFG<7>

NB_CFG<9>
NB_CFG<10>

NB_CFG<14>

NB_CFG<17>

NB_CFG<16>

NB_CFG<15>

NB_CFG<19>
NB_CFG<20>

PM_BMBUSY_L

PM_THRMTRIP_L
VR_PWRGOOD_DELAY

SDVO_CTRLCLK
SDVO_CTRLDATA
NB_SB_SYNC_L

MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>

MEM_CLK_N<0>

MEM_CLK_P<3>

MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>

MEM_CKE<0>
MEM_CKE<1>

MEM_CKE<3>

MEM_ODT<0>

MEM_ODT<3>

NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

NB_RST_IN_L

NB_CFG<8>

NB_CFG<11>

NB_CFG<13>

NB_CFG<18>

=PP3V3_S0_NB

PM_DPRSLPVR

TP_NB_TESTIN_L

TP_NB_XOR_LVDS_A35

NB_TV_DCONSEL0
NB_TV_DCONSEL1

=PP3V3_S0_NB

NB_CLK_DREFSSCLKIN_P

NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFCLKIN_P

NB_CLK_DREFCLKIN_N

CLK_NB_OE_L

NB_RST_IN_L_R

PM_EXTTS_L

63

63

63

20

20

19

19

19

19

19

19

16

14

19

14

SA_DQ1

SA_DQ0

SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0
SA_DM1
SA_DM2
SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6
SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA1

SA_MA0

SA_MA2
SA_MA3

SA_MA5

SA_MA4

SA_MA6
SA_MA7

SA_MA9

SA_MA8

SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

BI

BI
BI
BI
BI
BI

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

BI
BI
BI

BI

BI
BI
BI
BI

BI BI

BI
BI
BI
BI
BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

SB_DQ1

SB_DQ0

SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0
SB_DM1
SB_DM2
SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6
SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*

SB_MA1

SB_MA0

SB_MA2
SB_MA3

SB_MA5

SB_MA4

SB_MA6
SB_MA7

SB_MA9

SB_MA8

SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

BI
BI
BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

BI

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI
BI

OUT

BI

BI

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

BI

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC

NC

NC

BGA

945GM

NB

OMIT

AY14

AK24

AK23

AW14

AT16

AW17

AU17

AV17

AU16

BA17

BA16

AW16

AV12

AV20

AT17

AU13

AU14

AY16

AH5

AG5

AN3

AP3

AL8

AN8

AM12

AN12

AM21

AM22

AN27

AN28

AU33

AT33

AK32

AK33

AP33

AN35

AH31

AF8

AF4

AH6

AG9

AJ32

AF6

AG4

AF9

AG7

AL2

AN1

AT3

AV2

AN2

AP1

AK35

AW2

AY2

AL5

AT5

AN9

AP9

AK7

AK8

AN7

AK9

AJ36

AL12

AL14

AT12

AT13

AP12

AP13

AR14

AR12

AT21

AP20

AM33

AP24

AL23

AN20

AP21

AL22

AP23

AP26

AM24

AL28

AK28

AM31

AN24

AM26

AL27

AK26

AN33

AM34

AM36

AN38

AP31

AR31

AJ34

AJ35

AH4

AR3

AL9

AM14

AN22

AL26

AM35

AJ33

AY13

BA20

AV14

AU12

U1200

28

28

28

28

28

28

28

28

28

28

28

28

28

28

29

29

29

29

29

29

29

29

28 29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

BGA

945GM

NB

OMIT

AR27

AK18

AK16

AU23

AW27

AV27

AV28

AU27

AT28

AT27

AR28

AY24

AR23

AY27

BA27

AV24

AW24

AY23

AP5

AN5

AT7

AR7

AT10

AR10

AP16

AR16

AP29

AR29

AT35

AU35

AU39

AT39

AM40

AM39

AV41

AT40

AP41

AJ3

AJ5

AK5

AT4

AN41

AK3

AK4

AR5

AV4

AY5

AW5

AY9

AY10

AW4

BA4

AK38

AW10

BA10

AJ8

AK10

AH11

AK13

AN10

AJ9

AH10

AJ11

AJ38

AL15

AP15

AM16

AN17

AN14

AP14

AL19

AM19

AW29

AV29

AR41

AW31

AU31

AU29

AT31

BA33

AY33

AP34

AP35

AU36

BA36

AP39

AP36

AR36

AV36

BA38

AY38

AW38

AR40

AP38

AV38

AU38

AJ37

AK39

AN4

BA5

AH8

AL17

BA31

AT36

AR38

AK36

AR24

AY28

AV23

AT24

U1200

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

30 29

30 29

30 29

28

30 29

30 29

30 29

30 29

30 29

30 29

30 29

30 29

30 29

30 29

28

30 29

30 29

30 29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

29

29

29

28

29

29

29

29

29

29

29

30 29

30 29

30 29

28

30 29

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

30 28

30 28

30 28

28

30 28

28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

30 28

28

28

28

28

28

28

28

28

28

28

28

28

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB DDR2 Interfaces

051-6941

12

104

15

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_BS<2>
MEM_B_CAS_L

MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<3>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<6>
MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>

MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_BS<2>
MEM_A_CAS_L

MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<2>
MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47
VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37
VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34
VCCAUX_NCTF35

VCCAUX_NCTF32
VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27
VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24
VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42
VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19
VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14
VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7
VSS_NCTF8

VSS_NCTF5
VSS_NCTF6

VSS_NCTF4

VSS_NCTF2
VSS_NCTF3

VSS_NCTF0
VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61
VCC_NCTF62
VCC_NCTF63

VCC_NCTF60

VCC_NCTF57
VCC_NCTF58
VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53
VCC_NCTF54

VCC_NCTF52

VCC_NCTF50
VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46
VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38
VCC_NCTF39

VCC_NCTF36
VCC_NCTF37

VCC_NCTF34
VCC_NCTF35

VCC_NCTF33

VCC_NCTF31
VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18
VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13
VCC_NCTF14

VCC_NCTF11
VCC_NCTF12

VCC_NCTF10

VCC_NCTF8
VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0
VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NCTF balls are Not Critical To Function

These connections can break without

impacting part performance.

Layout Note:
Place near pin BA23

Place near pin BA15

Layout Note:

Layout Note:
Place in cavity

1.05V or 1.5V

1.05V, External Graphics: 1500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, Internal Graphics: 3500mA Max

667MTs 1700mA 3200mA

533MTs 1500mA 2800mA

400MTs 1300mA 2400mA

Speed 1 Channel 2 Channel

1.8V Max Current

BGA

NB

945GM

OMIT

AT6

AV6

AW6

AY6

BA6

AP8

AR8

AT8

AV8

AW8

AT34

AY8

BA8

AK11

AG12

AH12

AJ12

AK12

AH13

AJ13

AJ14

AU34

AJ15

AR15

AT15

AU15

AV15

AW15

AY15

BA15

AH16

AJ16

AV34

AH17

AJ17

AJ18

AJ19

AK19

AP19

AR19

AT19

AU19

AV19

AW34

AW19

AY19

BA19

AK20

AK21

AJ22

AK22

AP22

AR22

AT22

AY34

AU22

AV22

AW22

AY22

BA22

AJ23

BA23

AH24

AJ24

AH25

BA34

AJ25

AH26

AJ26

AR26

AT26

AU26

AV26

AW26

AY26

BA26

AU40

AH27

AJ27

AH28

AJ28

AH29

AJ29

AK29

AL29

AM29

AM30

AM41

AN30

AP30

AR30

AT30

AU30

AV30

AW30

AY30

BA30

AJ1

AV1

AJ6

AK6

AL6

AN6

AP6

AR6

AR34

AT41

AU41

N19

Y19

AA19

AB19

L20

M20

N20

P20

W20

Y20

V32

AB20

AC20

L21

M21

N21

W21

AA21

AC21

L22

M22

W32

N22

P22

W22

Y22

AB22

AC22

L23

M23

N23

P23

Y32

Y23

AA23

AB23

M24

N24

P24

L25

M25

N25

L26

AA32

N26

P26

L27

M27

N27

P27

L28

M28

N28

P28

J33

R28

T28

U28

V28

Y28

AA28

AB28

L29

M29

P29

L33

R29

U29

V29

W29

Y29

AA29

L30

M30

N30

P30

N33

R30

T30

U30

V30

W30

Y30

AA30

M31

N31

P31

P33

R31

T31

V31

W31

AA31

J32

L32

M32

L16

N32

M16

N16

M17

N17

P17

L18

M18

N18

L19

M19

P32

W33

AA33

U1200

402

6.3V
CERM-X5R

0.47uF

20%

2

1

C1610

603

20%
X5R

6.3V

10uF

2

1

C1621

10uF

6.3V
X5R

20%

603

2

1

C1620

945GM

NB

BGA

OMIT

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

U17

Y17

AC17

AE26

AE27

AF23

AG23

AF24

AG24

R15

T15

U15

V15

W15

Y15

AA15

AB15

AF25

AC15

AD15

AE15

AF15

AG15

R16

T16

U16

V16

W16

AG25

Y16

AA16

AB16

AC16

AD16

AE16

AF16

AG16

R17

T17

AF26

V17

W17

AA17

AB17

AD17

AE17

AF17

AG17

R18

AF18

AG26

AG18

R19

AF19

AG19

AF20

AG20

AF21

AG21

AF22

AG22

AF27

AG27

R27

T27

T18

U18

V18

U27

W18

Y18

AA18

AB18

AC18

AD18

T19

U19

V19

AD19

V27

R20

T20

U20

V20

AD20

R21

T21

U21

V21

AD21

W27

R22

T22

U22

V22

AD22

R23

T23

U23

V23

AD23

Y27

R24

T24

U24

V24

W24

Y24

AA24

AB24

AC24

AD24

AA27

R25

T25

U25

V25

W25

Y25

AA25

AB25

AC25

AD25

AB27

R26

T26

U26

V26

W26

Y26

AA26

AB26

AC26

AD26

AC27

AD27

U1200

402

6.3V
CERM-X5R

0.47uF

20%

2

1

C1611

402

6.3V

CERM-X5R

0.47uF

20%

2

1

C1612

402

6.3V
CERM-X5R

20%

0.47uF

2

1

C1613

402

6.3V

CERM-X5R

20%

0.47uF

2

1

C1614

402

6.3V
CERM-X5R

20%

0.47uF

2

1

C1615

NB Power 1

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

16

=PP1V8_S3_MEM_NB

NB_VCCSM_LF1

NB_VCCSM_LF2

NB_VCCSM_LF5

NB_VCCSM_LF4

=PPVCORE_S0_NB

=PPVCORE_S0_NB

=PP1V5_S0_NB_VCCAUX

63

63

63

63

19

19

19

19

14

16

16

17

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25

VTT27

VTT26

VTT28
VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35
VTT36
VTT37

VTT39

VTT38

VTT40
VTT41
VTT42
VTT43
VTT44
VTT45

VTT48

VTT46
VTT47

VTT49
VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58
VTT59
VTT60
VTT61
VTT62

VTT64

VTT63

VTT65
VTT66
VTT67

VTT69

VTT68

VTT70
VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG
VSSA_TVBG

VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0
VCCD_LVDS1

VCCD_TVDAC

VCC_HV1
VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14
VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23
VCCAUX24

VCCAUX22

VCCAUX25
VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30
VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34
VCCAUX35
VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39
VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1900mA Max

40mA Max

See VCCSYNC

150mA Max

120mA Max

45mA Max

45mA Max

50mA Max

50mA Max

10mA Max

24mA Max

20mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

60mA Max

2mA Max

800mA Max

1500mA Max VCC3G/3GPLL

OMIT

BGA

NB

945GM

L14

M14

M1

N1

P1

R1

AB1

D2

M2

N14

P2

R2

M3

N3

P3

R3

M4

N4

P4

M5

P14

N5

P5

R5

A6

M6

P6

R6

M7

N7

P7

R14

M8

N8

P8

R8

M9

N9

P9

M10

N10

P10

T14

R10

M11

N11

P11

R11

L12

M12

N12

P12

R12

V14

T12

U12

V12

W12

Y12

AA12

AB12

L13

M13

N13

W14

R13

T13

U13

V13

W13

Y13

AA13

AB13

AC13

AD13

AB14

AC14

G20

B39

G21

H41

H22

D21

H19

C28

B28

A28

AH2

AH1

AF30

AG30

AH30

AJ30

AK30

AD12

AL30

AE12

AF12

AE13

AF13

Y14

AE14

AF14

AG14

AH14

P15

AC31

AH15

P16

P19

AH19

AH20

AJ20

AH21

AJ21

AH22

AE28

AE31

AF28

AG28

AC29

AD29

AE29

AF29

AG29

AC30

AD30

AE30

AF31

AK31

F20

E20

D20

C20

F19

E19

H20

AF2

A38

AF1

C39

B26

E21

F21

AC33

G41

A30

B30

C30

B25

B23

A23

L41

N41

R41

V41

Y41

AB41

AJ41

U1200

402

CERM-X5R

6.3V

0.47uF

20%

2

1

C1711

20%

0.22uF

6.3V
402

X5R

2

1

C1712

402

6.3V

CERM-X5R

20%

0.47uF

2

1

C1713

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Power 2

051-6941

12

104

17

PP2V5_S0_NB_VCCA_CRTDAC

=PP1V5_S0_NB_VCCAUX

PP1V5_S0_NB_VCCD_QTVDAC

=PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCA_MPLL

=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_DPLLB

GND_NB_VSSA_CRTDAC

GND_NB_VSSA_3GBG

=PP2V5_S0_NB_VCCA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB_VCC3G

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

NB_VTTLF_CAP1

NB_VTTLF_CAP2

NB_VTTLF_CAP3

=PP1V05_S0_NB_VTT

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_LVDS

63 19

63

63

63

63

19

16

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

VSS_1

VSS_0

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7

VSS_9

VSS_8

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17

VSS_19

VSS_18

VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26

VSS_28

VSS_27

VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47

VSS_49

VSS_48

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71

VSS_73

VSS_72

VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79

VSS_82

VSS_80
VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92
VSS_93
VSS_94

VSS_96

VSS_95

VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125

VSS_127

VSS_126

VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135

VSS_137

VSS_136

VSS_138
VSS_139
VSS_140
VSS_141

VSS_143

VSS_142

VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156

VSS_158

VSS_157

VSS_159
VSS_160
VSS_161
VSS_162

VSS_164

VSS_163

VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170

VSS_172

VSS_171

VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269
VSS_270

VSS_268

VSS_266
VSS_267

VSS_265

VSS_264

VSS_263

VSS_261
VSS_262

VSS_260

VSS_259

VSS_258

VSS_256
VSS_257

VSS_255

VSS_254

VSS_253

VSS_251
VSS_252

VSS_250

VSS_248
VSS_249

VSS_247

VSS_246

VSS_245

VSS_243
VSS_244

VSS_242

VSS_241

VSS_240

VSS_238
VSS_239

VSS_237

VSS_236

VSS_235

VSS_233
VSS_234

VSS_232

VSS_231

VSS_230

VSS_228
VSS_229

VSS_227

VSS_225
VSS_226

VSS_224

VSS_223

VSS_222

VSS_220
VSS_221

VSS_219

VSS_218

VSS_217

VSS_215
VSS_216

VSS_214

VSS_213

VSS_212

VSS_210
VSS_211

VSS_209

VSS_207
VSS_208

VSS_205
VSS_206

VSS_204

VSS_202
VSS_203

VSS_201

VSS_200

VSS_199

VSS_197
VSS_198

VSS_196

VSS_195

VSS_194

VSS_192
VSS_193

VSS_191

VSS_190

VSS_189

VSS_187
VSS_188

VSS_186

VSS_184
VSS_185

VSS_183

VSS_182

VSS_180
VSS_181

VSS_273
VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282
VSS_283
VSS_284

VSS_286

VSS_285

VSS_287
VSS_288
VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301
VSS_302

VSS_300

VSS_304

VSS_303

VSS_305
VSS_306
VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312
VSS_313
VSS_314
VSS_315

VSS_317

VSS_316

VSS_318
VSS_319
VSS_320

VSS_322

VSS_321

VSS_323
VSS_324
VSS_325

VSS_327

VSS_326

VSS_328
VSS_329
VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338
VSS_339
VSS_340

VSS_342
VSS_343

VSS_341

VSS_345

VSS_344

VSS_346
VSS_347
VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB

945GM

BGA

OMIT

AF34

AG34

AK34

AN34

D35

F35

G35

H35

J35

L35

AP40

M35

N35

P35

R35

T35

V35

W35

Y35

AA35

AB35

AV40

AH35

AR35

AV35

BA35

B36

C36

AC36

AE36

AF36

AG36

F41

AH36

AN36

AW36

AY36

D37

F37

G37

H37

J37

L37

J41

M37

N37

P37

R37

T37

V37

W37

Y37

AA37

AB37

M41

AH37

AK37

C38

AE38

AF38

AG38

AH38

AM38

AT38

D39

P41

F39

G39

H39

J39

L39

M39

N39

P39

R39

T39

T41

V39

W39

Y39

AA39

AB39

AC39

AJ39

AN39

AR39

AV39

W41

AW39

AY39

AW23

AL24

AU24

BA24

A25

D25

E25

H25

K25

P25

B40

AK25

D26

F26

K26

M26

AN26

B27

C27

F27

G27

AE40

J27

AK27

AM27

AP27

E28

J28

W28

AC28

AD28

AM28

AF40

AP28

AU28

AW28

BA28

A29

B29

C29

E29

G29

K29

AG40

N29

T29

AB29

AN29

AT29

E30

AB30

Y31

AB31

AG31

AH40

AJ31

AN31

AV31

AY31

B32

G32

AB32

AC32

AE32

AF32

AJ40

AG32

AH32

B33

D33

F33

G33

H33

M33

R33

T33

AK40

V33

Y33

AB33

AE33

AR33

AV33

AW33

C34

AC34

AE34

AN40

AA41

AC41

U1200

NB

945GM

BGA

OMIT

AL1

C2

F2

H2

J2

N2

T2

U2

Y2

AB2

AD2

AJ2

AK2

AP2

AR2

AT2

G3

AA3

AC3

AD3

AF3

AG3

AH3

AL3

AV3

AW3

AY3

C4

F4

J4

R4

U4

Y4

AJ4

AL4

AP4

AR4

AY4

AD5

AF5

AV5

B6

H6

K6

N6

U6

Y6

AB6

AD6

AG6

D7

G7

R7

AC7

AF7

AH7

AJ7

AL7

AP7

AV7

BA7

C8

K8

U8

AA8

AD8

AG8

A9

E9

G9

R9

Y9

AB9

AH9

AR9

AW9

BA9

U10

W10

AC10

AG10

AJ10

AL10

AP10

AV10

B11

D11

J11

Y11

AA11

AD11

E12

H12

K12

AC12

AY12

B13

D13

F13

P13

AG13

AL13

AM13

AN13

AR13

AV13

E14

H14

K14

U14

AA14

AD14

AK14

AT14

BA14

A15

B15

L15

M15

N15

AK15

AM15

AN15

C16

F16

J16

AL16

AN16

AV16

AK17

AM17

AP17

AR17

AY17

A18

D18

H18

P18

AH18

C19

G19

K19

W19

AC19

AN19

A20

B20

K20

AA20

AM20

AR20

AW20

C21

H21

J21

K21

P21

Y21

AB21

AL21

AN21

AR21

AV21

BA21

A22

D22

E22

F22

G22

K22

AA22

C23

F23

J23

K23

W23

AC23

AH23

AM23

AN23

AT23

U1200

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Grounds

051-6941

12

104

18

IN

IN

IN

IN

IN

IN
IN
IN

IN

IN
IN
IN

IN

IN

IN

IN

IN
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

GMCH CORE PWR 1.05V BYPASS

1500mA Max

1500mA Max
10mA Max?

?mA Max

?mA Max

60mA Max

70mA Max

3200mA Max

24mA Max

100mA Max

?mA Max

800mA Max

3674mA Max

?mA Max
40mA Max

40mA Max?

1500mA Max

2mA Max

1900mA Max

150mA Max

2310mA Max?

Power Interface

These are the power signals that leave the NB "block"

132mA Max

3200mA Max

Rail Totals:

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH LVDS DATA/CLK TX 2.5V PWR)

(MCH LVDS DIGITAL 1.5V PWR)

(MCH LVDS ANALOG 2.5V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

(MCH DISPLAY A PLL 1.5V PWR)

(MCH DISPLAY B PLL 1.5V PWR)

1500mA Max

be close to MCH
on opposite side.

GMCH VCCA_3GPLL FILTER

(PCI-E/DMI ANALOG 1.5V PWR)

10uF caps should

Layout Note: Route to caps, then GND

(3GIO PLL 1.5V PWR)

GMCH VCC3G FILTER

Layout Note:

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Place L and C
close to MCH

Layout Note:

1500mA Max

GMCH VCCA_HPLL FILTER

45mA Max

(HOST PLL 1.5V PWR)

(MCH MEMORY PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

45mA Max

100mA Max

GMCH VCCAUX FILTER
(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

MCH VCCA_3GBG BYPASS

2mA Max

MCH VCC_HV BYPASS
(MCH HV BUFFER 3.3V PWR)

40mA Max

Place on the edge

Layout Note:

(SHARE C0940 470UF)

MCH VTT BYPASS
(MCH FSB 1.05V PWR)

Layout Note:
Place in cavity

800mA Max

0.22uF

X5R

6.3V

20%

402

2

1

C1907

X5R
603

20%

6.3V

10uF

2

1

C1972

220UF

20%

2.5V
POLY
SMB2

2

1

C1970

6.3V

20%
402

X5R

0.22uF

2

1

C1967

6.3V
603

2.2uF

20%
CERM1

2

1

C1966

6.3V

20%
603

CERM

4.7uF

2

1

C1965

63 34 12

63 19 17

63 13

63 19

63 17

63 19 17 16

63 19

19 17

63 19 17

63 19

63 19 17

470uF-7MOHM

20%

2.5V
TANT
D2T

CRITICAL

3 2

1

C1900

63 19

63 19

91nH

1210

21

L1970

0.1uF

402

20%
10V

CERM

2

1

C1916

6.3V

20%

402

X5R

0.22uF

2

1

C1906

10V

20%
402

CERM

0.1uF

2

1

C1915

6.3V

20%
603

X5R

10uF

2

1

C1914

6.3V
402

20%
X5R

0.22uF

2

1

C1905

20%
10V

402

CERM

0.1uF

2

1

C1935

FERR-120-OHM-0.2A

0603

21

L1934

0.1uF

CERM

20%
10V

402

2

1

C1937

402

6.3V

1uF

CERM

10%

2

1

C1904

FERR-120-OHM-0.2A

0603

21

L1936

22uF

X5R
805

20%

6.3V
2

1

C1934

22uF

X5R
805

20%

6.3V

2

1

C1936

6.3V
X5R

20%

603

10uF

2

1

C1903

6.3V

20%

603

X5R

10uF

2

1

C1902

10V

20%
402

CERM

0.1uF

2

1

C1918

10V

20%
402

CERM

0.1uF

2

1

C1976

1.0UH-220MA-0.12-OHM

0805

21

L1975

6.3V

20%
603

X5R

10uF

2

1

C1975

MF-LF

402

0.51

1/16W

1%

21

R1975

10uF

X5R
603

20%

6.3V

2

1

C1971

NB (GM) Decoupling

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

051-6941

12

104

19

=PP1V05_S0_NB_VTT

=PP3V3_S0_NB_VCC_HV

=PP2V5_S0_NB_VCCA_3GBG

=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_PLL

PP1V5_S0_NB_VCCA_MPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_VCCA_HPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_NB_3GPLL_F

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

VOLTAGE=1.5V

PP1V5_S0_NB_VCC3G

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

GND_NB_VSSA_3GBG

PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_3G

NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N

TP_NB_VCCA_DPLLB

MAKE_BASE=TRUE

PP1V5_S0_NB_VCCA_DPLLB

MAKE_BASE=TRUE

TP_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_DPLLA

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVBG

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACA

PP1V5_S0_NB_VCCD_QTVDAC

PP1V5_S0_NB_VCCD_TVDAC

=PP2V5_S0_NB_VCCSYNC

PP2V5_S0_NB_VCCA_CRTDAC
GND_NB_VSSA_CRTDAC

NO_TEST=TRUE

NC_GND_NB_VSSA_LVDS

MAKE_BASE=TRUE

GND_NB_VSSA_LVDS

=PP2V5_S0_NB_VCCA_LVDS

=PP1V5_S0_NB_VCCD_LVDS

=PP2V5_S0_NB_VCC_TXLVDS

=PP1V5_S0_NB_TVDAC

=PPVCORE_S0_NB

=PPVCORE_S0_NB

=PP1V5_S0_NB

=PP1V05_S0_NB_VTT

=PP1V5_S0_NB_3G

=PP1V5_S0_NB_PCIE

=PP1V05_S0_FSB_NB

=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV

=PP2V5_S0_NB_VCCA_3GBG

=PP1V8_S3_MEM_NB

=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_PLL

=PP1V5_S0_NB_3GPLL

=PP1V05_S0_NB_CRT

=PPVCORE_S0_NB

MAKE_BASE=TRUE

TP_CRT_DDC_CLK

CRT_DDC_DATA

MAKE_BASE=TRUE

TP_CRT_DDC_DATA

CRT_DDC_CLK

CRT_IREF

CRT_BLUE_L

CRT_GREEN_L

CRT_RED_L

CRT_BLUE

CRT_GREEN

CRT_RED

=PP1V05_S0_NB_CRT

TV_DACB_OUT
TV_DACC_OUT

TV_DACA_OUT

TV_IRTNA

TV_IREF

TV_IRTNC

TV_IRTNB

LVDS_BKLTEN

MAKE_BASE=TRUE

TP_LVDS_BKLTEN

LVDS_BKLTCTL

MAKE_BASE=TRUE

TP_LVDS_BKLTCTL

LVDS_CLKCTLA

MAKE_BASE=TRUE

TP_LVDS_CLKCTLA

LVDS_CLKCTLB

MAKE_BASE=TRUE

TP_LVDS_CLKCTLB

LVDS_DDC_CLK

MAKE_BASE=TRUE

TP_LVDS_DDC_CLK

LVDS_IBG

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IBG

LVDS_DDC_DATA

MAKE_BASE=TRUE

TP_LVDS_DDC_DATA

LVDS_VREFL

MAKE_BASE=TRUE

TP_LVDS_VREFL

LVDS_VDDEN

MAKE_BASE=TRUE

TP_LVDS_VDDEN

LVDS_VREFH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_VREFH

LVDS_A_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_CLKP

LVDS_A_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_CLKN

LVDS_A_DATA_P<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<2..0>

LVDS_A_DATA_N<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<2..0>

LVDS_B_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_CLKN

LVDS_B_DATA_P<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_DATAP<2..0>

LVDS_B_CLK_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_CLKP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A35

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D27

TP_NB_XOR_LVDS_D28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_D28

TP_NB_XOR_LVDS_A35

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_NB_XOR_LVDS_A34

SDVO_CTRLDATA

MAKE_BASE=TRUE

TP_SDVO_CTRLDATA

SDVO_CTRLCLK

MAKE_BASE=TRUE

TP_SDVO_CTRLCLK

TP_NB_XOR_LVDS_A34

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<2..0>

=PP1V5_S0_NB_TVDAC

CRT_VSYNC_R

CRT_HSYNC_R

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

LVDS_B_DATA_N<2..0>

TP_NB_XOR_LVDS_D27

63

63 63

63 19

63

63

19 19

19 17

63

63

63

19

19

63

19

19

63

63

17 17

17 16

19

17

17

17

17

17 19

19

14

14

14

14

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

19

16

16

13

13

13

13

13

13

13

13

13

19

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

14

14

14

14

14

19

13

13

13

14

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Internal pull-ups

Internal pull-up

RESERVED

RESERVED

NB_CFG<11>

NB_CFG<10>

High = Mobile CPU

NB_CFG<7>

RESERVED

Internal pull-up

DMI x2 Select

PROBABLY NOT NEEDED

PROBABLY NOT NEEDED

Lane Reversal

NB_CFG<4>

NB_CFG<3>

RESERVED

NB_CFG<13:12>

NB_CFG<14>

NB_CFG<5>

NB_CFG<15>

NB_CFG<16>

NB_CFG<6>

NB_CFG<17>

NB_CFG<18>

NB_CFG<8>

NB_CFG<9>

NB_CFG<19>

NB_CFG<20>

Low = DMIx2

High = DMIx4

Low = RESERVED

High = Normal

PCIE Graphics

RESERVED

CPU Strap

RESERVED

Low = Reversed

Internal pull-up

11 = Normal Operation

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

00 = Partial Clock Gating Disable

RESERVED

Internal pull-up

RESERVED

High = Enabled
Low = Disabled

RESERVED

FSB Dynamic
ODT

or PCIe x1

Low = Only SDVO

High = Both active

945 External Design Spec says reserved

Internal pull-down

Internal pull-down

Internal pull-down

Low = 1.05V

High = 1.5V

Low = Normal

High = Reversed
DMI Lane
Reversal

VCC Select

Interop. Mode

PCIe Backward

402

5%

2.2K

1/16W
MF-LF

NBCFG_DMI_X2

2

1

R2075

2.2K

5%
1/16W
MF-LF
402

NBCFG_DYN_ODT_DISABLE

2

1

R2085

402

1/16W

5%

2.2K

NBCFG_VCC_1V5

MF-LF

2

1

R2058

402

MF-LF

1/16W

5%

2.2K

NBCFG_DMI_REVERSE

2

1

R2059

NBCFG_SDVO_AND_PCIE

402

MF-LF

1/16W

5%

2.2K

2

1

R2060

402

MF-LF

1/16W

5%

2.2K

NO STUFF

2

1

R2077

402

MF-LF

1/16W

5%

2.2K

NBCFG_PEG_REVERSE

2

1

R2079

20

104

12

051-6941

NB Config Straps

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

=PP3V3_S0_NB

=PP3V3_S0_NB

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<19>

NB_CFG<20>

NB_CFG<16>

NB_CFG<5>

NB_CFG<7>

NB_CFG<9>

63

63

63

20

20

20

19

19

19

14

14

14

14

14

14

14

14

14

14

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN
IN

BI
BI
BI
BI

IN

BI

DDACK*

SATARBIASN
SATARBIASP

SATA_CLKN
SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN
SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0
LAN_TXD1

LAN_RXD1
LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0
LAD1

EE_DOUT
EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY
DDREQ

DD0
DD1

DD3

DD2

DD5

DD4

DD6
DD7
DD8

DD11

DD9

DD10

DD12
DD13
DD14
DD15

DA0
DA1
DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT
OUT

OUT
IN

OUT

IN
IN

IN
IN

OUT
OUT

OUT
OUT

IN
IN

OUT
OUT
OUT

IN
IN
IN

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(WEAK INT PU)

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

INTEL HIGH DEFINITION AUDIO

ACZ_SDOUT

ACZ_SYNC

ACZ_BIT_CLK
ACZ_RST#

ACZ_SDIN[0-2]

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

AC ’07

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

NONE

INTERNAL 20K PD

INTERNAL 20K PD ONLY ENABLED IN S3COLD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

NOTE: DD<7> HAS INTERNAL 11.5K PD

(HSTROBE)
(STOP)

20K PD
20K PD
20K PD

(DSTROBE)

< 2 IN OF R2107 W/O STUB

LAYOUT NOTE: R2108 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB

BOM CONSOLIDATION

NOTE: RISING-EDGE TRIGGERED AT CPU

NOTE: KEYBOARD CONTROLLER RESET CPU

POR IS SMC WILL PUT LAN INT’F

NOTE:

INTO RESET STATE TO SAVE PWR.

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTEL CONFIRMS OK TO LEAVE PINS AS NC

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

NOTE: PULLED UP PER INTEL

NOTE: R2110=56 IN CV.
CHANGED TO 54.9 FOR
BOM CONSOLIDATION

NOTE: R2108=56 IN CV.

(WEAK INT PD)

(INT PU)

(INT PU)

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

36

48 14

7

79

7

79

7

79

7

79

7

49 48

5

79

7

79

7

7

79

7

57

7

56 49 47

5

79

7

26

26

26

26

36

36

56 49 47

5

56 49 47

5

56 49 47

5

NOSTUFF

1/16W

MF-LF

0

5%

402

21

R2100

47

NOSTUFF

402

2.2K

5%
1/16W
MF-LF

21

R2101

MF-LF

5%

39

402

1/16W

21

R2195

39

21

R2198

39

21

R2197

39

21

R2196

402

10K

5%
1/16W
MF-LF

2

1

R2199

BGA

SB

ICH7-M

OMIT

AH25

AF24

AF26

AH22

AF23

AG10

AH10

AF18

AE1

AF1

AH6

AG6

AE7

AF7

AH2

AG2

AE3

AF3

AB2

AB1

AA3

AG23
AH24

AB3

AA5

AC3

V7

V6

U7

T5

V4

U5

U3

V3

Y6

AC4

AB5

AA6

AG16

W4

Y5

AF25

AG21
AF22

AG22

AH16

AG24

AG26

Y1
Y2
W3

W1

AH15

AF15

AE15

AF16

AF12

AE12

AC12

AD12

AC13

AD14

AF13

AG13

AC15

AH14

AH13

AF14

AC14

AB13

AE14

AB15

AD16

AE16

AF17

AE17

AH17

AG27

R6

T4

T1

T3

T2

R5

U1

AH28

AE22

U2100

402

10K

5%
1/16W
MF-LF

2

1

R2194

332K

402

1%

1/16W

MF-LF

2

1

R2105

24.9

MF-LF
1/16W

1%

402

21

R2107

402

MF-LF
1/16W

1%

54.9

2

1

R2108

MF-LF
1/16W

402

54.9

1%

21

R2110

79 45

5

79 45

5

79 45

5

79 45

5

79 45

5

36

36

76

76

36

36

76

76

34

5

34

5

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

12

21

104

051-6941

SYNC_MASTER=M38

SYNC_DATE=11/16/2005

SB: 1 OF 4

TP_SB_XOR_V7

TP_SB_XOR_V6

TP_SB_XOR_U7

TP_SB_XOR_Y2

TP_SB_XOR_Y1

TP_SB_XOR_W1

SB_INTVRMEN

=PP1V05_S0_SB_CPU_IO

CPU_FERR_L

SB_A20GATE

CPU_RCIN_L

SATA_C_D2R_P

IDE_PDDACK_L

SATA_RBIAS_N
SATA_RBIAS_P

SB_CLK100M_SATA_N
SB_CLK100M_SATA_P

SATA_C_R2D_C_P

SATA_C_R2D_C_N

SATA_C_D2R_N

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_A_D2R_P

SATA_A_D2R_N

TP_SB_SATALED_L

SB_ACZ_SDATAOUT

TP_SB_ACZ_SDIN1
TP_SB_ACZ_SDIN2

ACZ_SDATAIN<0>

SB_ACZ_SYNC

SB_ACZ_BITCLK

SB_SM_INTRUDER_L

SB_RTC_X1

CPU_THERMTRIP_R

CPU_STPCLK_L

CPU_NMI

CPU_SMI_L

CPU_INTR

CPU_INIT_L

FWH_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L

CPU_DPSLP_L

CPU_A20M_L

TP_CPU_CPUSLP_L

SB_ACZ_RST_L

IDE_PDIOR_L

IDE_IRQ14

IDE_PDIOW_L

IDE_PDIORDY
IDE_PDDREQ

IDE_PDD<0>
IDE_PDD<1>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<7>
IDE_PDD<8>

IDE_PDD<11>

IDE_PDD<9>
IDE_PDD<10>

IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>

IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

ACZ_SYNC

SMC_RCIN_L

=PP1V05_S0_SB_CPU_IO

PM_THRMTRIP_L

ACZ_SDATAOUT

IDE_PDD<6>

=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_GPIO

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

TP_SB_DRQ0_L
TP_SB_GPIO23

LPC_FRAME_L

SB_RTC_X2
SB_RTC_RST_L

ACZ_BITCLK

ACZ_RST_L

PP3V3_S5_SB_RTC

TP_SB_XOR_U3
TP_SB_XOR_U5

TP_SB_XOR_V4
TP_SB_XOR_T5

TP_SB_XOR_W3
TP_SB_XOR_V3

IDE_PDD<2>
IDE_PDD<3>

63

63

25

25 63

63

26

24

24 23

23

25

21

79

79

79

79

21 21

21

24

6

6

6

6

IN

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI
BI

BI
BI

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI2TXN
DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P

USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBP4N

OC0*
OC1*
OC2*
OC3*
OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK
SPI_CS*

SPI_MOSI
SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN
DMI1RXP

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0*
C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE2*
C/BE3*

GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*

PIRQA*
PIRQB*
PIRQC*
PIRQD*

RSVD0
RSVD1
RSVD2
RSVD3

MISC

INT I/F

PCI

(2 OF 6)

BI

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

IN

BI

BI

BI

BI

OUT

BI

BI

BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

AND PWROK=H

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

BOM NOTE FOR PD ON PCI_GNT3_L:

IR

BT

CF/SD

CAMERA

AIRPORT (MINI-PCIE)

EXTERNAL 2

EXTERNAL 1

EXTERNAL 0

NOTE:

STUFF - A16 SWAP OVERRIDE

(STRAPPED TO TOP-BLOCK SWAP MODE
IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)

SB BOOT BIOS SELECT

GNT4#GNT5#

TO RSVD[1-9]

NOTE: CHANGE SYMBOL

R2210STRAP
11
10
01

STUFF

UNSTUFF

UNSTUFFUNSTUFF

STUFF

UNSTUFF

SPI

PCI

LPC (DEFAULT)

NOTE:

LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

(INT PD)

(INT PD)

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

NOTE: FWH_WP_L NOT USED

R2211

ENABLED ONLY WHEN PCIRST#=0

SB: 2 OF 4

(AKA TP3, INTERNAL 20K PU)

(INT 20K PU)

GNT[0-3]# HAVE INT 20K PU

NO STUFF - DEFAULT

34

40

40 26

40

40

40

40

40

40 26

26

26

26

49 47

5

37

37

46

46

46

46

1/16W

402

24.9

MF-LF

1%

21

R2203

46

46

46

46

46

46

37

37

46

46

46

46

46

46

46

46

46

46

52 47

52 47

52 47

52 47

22

6

6

6

6

6

6

6

6

6

6

6

6

6

34

14

34

14

14

14

14

14

5

14

5

14

5

14

5

14

14

14

14

14

14

14

10K

1/16W
MF-LF

5%
402

USB_G_OC_PU

2

1

R2222

402

22.6

1%
1/16W
MF-LF

21

R2204

1/16W

5%

10K

MF-LF
402

2

1

R2223

10K

5%
1/16W
MF-LF
402

2

1

R2225

402

MF-LF

1/16W

10K

5%

2

1

R2226

40

10K

5%
1/16W
MF-LF
402

2

1

R2299

OMIT

BGA

SB

ICH7-M

D2
D1

N3

N4

M2

M1

L5

L4

K2

K1

J3

J4

H2

H1

G3

G4

F2

F1

P5
P2

P6

R2

P1

R27

N27

L27

J27

G27

E27

R28

N28

L28

J28

G28

E28

T24

P25

M25

K25

H25

F25

T25

P26

M26

K26

H26

F26

B3

A2

C3

E5

D4

D5

C4

D3

C25
D25

AE27

AE28

AC27

AC28

AD24

AD25

AA27

AA28

AB25

AB26

W27

W28

Y25

Y26

U27

U28

V25

V26

U2100

SB

BGA

ICH7-M

OMIT

F14

F15

B10

F21

AH8

AG8

AE9

AD9

AH4

AG4

AD5

AE5

A13

E13

C17

C16

D7

B19

C26

E11

B5

C5

B4

A3

C9

B18

A9

E10

AH20

A7

G7

F8

F7

G8

D8

C8

A14

F13

D17

D16

E7

F16

A12

C15

D12

C12

B15

C14

A15

A17

E17

A18

E16

D6

E6

F18

B6

C7

A6

A8

B9

D9

E9

F10

F11

A10

A16

A11

D11

C11

E12

G13

G15

C13

B12

D14

E14

C18

E18

U2100

47

MF-LF

1/16W

5%

10K

402

2

1

R2200

402

MF-LF

1/16W

5%

10K

USB_C_OC_PU

2

1

R2250

10K

5%
1/16W
MF-LF
402

USB_E_OC_PU

2

1

R2251

USB_D_OC_PU

MF-LF

1/16W

5%

10K

402

2

1

R2255

MF-LF
402

1/16W

5%

10K

2

1

R2298

40

MF-LF

402

5%

10K

1/16W

2

1

R2205

402

10K

MF-LF

5%

1/16W

NOSTUFF

2

1

R2206

MF-LF
1/16W

10K

402

5%

2

1

R2207

VOLTAGE=0V

1/16W
MF-LF

5%

1K

402

2

1

R2211

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40 26

26

26

26

40 26

14

36

26

26

26

26

40 26

40 26

40 26

26

40 26

40 26

051-6941

104

22

12

PCI_PME_FW_L

=PP3V3_S0_SB

SPI_SI

SPI_CE_L

SB_GPIO30

PCI_REQ2_L

BOOT_LPC_SPI_L

PCI_C_BE_L<2>

SPI_SCLK

PCI_STOP_L

PCI_REQ3_L

PCI_REQ1_L

PCI_REQ0_L

PCI_AD<1>

PCI_AD<6>

USB_E_OC_L

SB_GPIO29

TP_SB_XOR_AE9
TP_SB_XOR_AG8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AH8

TP_SB_XOR_AE5

TP_SB_XOR_AD9

TP_SB_XOR_AH4

TP_SB_XOR_AG4

TP_SB_XOR_AD5

INT_PIRQD_L

USB_H_P

SPI_SO

SPI_ARB

USB_C_OC_L
USB_D_OC_L

USB_B_OC_L

USB_A_OC_L

USB_C_OC_L

=PP3V3_S5_SB_IO

PP1V5_S0_SB_VCC1_5_B

SB_GPIO31

PCIE_F_R2D_C_P

PCIE_F_R2D_C_N

PCIE_F_D2R_P

PCIE_F_D2R_N

PCIE_E_R2D_C_P

PCIE_E_R2D_C_N

PCIE_E_D2R_P

PCIE_E_D2R_N

PCIE_D_R2D_C_P

PCIE_D_R2D_C_N

PCIE_D_D2R_P

PCIE_D_D2R_N

PCIE_C_R2D_C_P

PCIE_C_R2D_C_N

PCIE_C_D2R_P

PCIE_C_D2R_N

PCIE_B_R2D_C_P

PCIE_B_R2D_C_N

PCIE_B_D2R_P

PCIE_B_D2R_N

PCIE_A_R2D_C_P

PCIE_A_R2D_C_N

PCIE_A_D2R_P

PCIE_A_D2R_N

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_N<1>
DMI_S2N_P<1>

DMI_N2S_N<2>
DMI_N2S_P<2>

SB_CLK100M_DMI_N

SB_GPIO29
SB_GPIO30

USB_E_N

USB_H_N

USB_G_P

USB_G_N

USB_F_P

USB_F_N

USB_E_P

USB_D_P

USB_D_N

USB_C_P

USB_C_N

USB_B_P

USB_B_N

USB_A_P

USB_A_N

DMI_N2S_P<3>
DMI_S2N_N<3>
DMI_S2N_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

USB_RBIAS_PN

SB_CLK100M_DMI_P

DMI_IRCOMP_R

INT_PIRQC_L

INT_PIRQB_L

INT_PIRQA_L

PCI_C_BE_L<3>

PCI_AD<31>

PCI_AD<30>

PCI_AD<29>

PCI_AD<28>

PCI_AD<27>

PCI_AD<26>

PCI_AD<25>

PCI_AD<24>

PCI_AD<23>

PCI_AD<22>

PCI_AD<21>

PCI_AD<20>

PCI_AD<19>

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_AD<0>

PCI_SERR_L

PCI_LOCK_L

PCI_PAR

PCI_CLK_SB

PCI_IRDY_L

PCI_FRAME_L

PCI_TRDY_L

PLT_RST_L

TP_PCI_PME_L

PCI_RST_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_C_BE_L<1>

PCI_C_BE_L<0>

SB_GPIO2
SB_GPIO3
SB_GPIO4
ODD_PWR_EN_L

TP_SB_RSVD9

NB_SB_SYNC_L

SB_GPIO31

USB_A_OC_L

USB_E_OC_L

USB_B_OC_L

USB_D_OC_L

=PP3V3_S5_SB_USB

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_GNT2_L

PCI_GNT3_L

TP_PCI_GNT4_L

63

22

22

22

22

22

22

22

25

22

22

22

22

25

6

6

22

6

6

6

6

6

63

24

22

22

6

22

6

6

6

63

IN

IN

IN

IN

OUT

OUT
OUT
OUT

OUT

IN

IN

BI
BI

OUT
OUT

OUT
IN

IN

BI

IN

IN

BI

IN

IN
IN

IN

OUT

BI

BI

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3*
SLP_S4*
SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25
GPIO35
GPIO38
GPIO39

SMBCLK
SMBDATA
LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR
SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ
THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

HI = PRESENT
LO = NOT PRESENT

SV_SET_UP IS LINDACARD DETECT

NOTE:

NOTE:
SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F
IN RESET STATE TO SAVE PWR

DEF=GPI

DEF=GPI

DEF=GPI

OD

(INT 20K PU)

NOTE FOR GPIO25:

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

LAYOUT NOTE:

(INT WEAK PD)

NOTE: RESERVED FOR FUTURE

NOT USED

NOTE FOR R2323 (DEF=NOSTUFF)
SB WILL DISABLE TCO TIMER

STRAPPING @ PWROK RISING:
SYSTEM REBOOT FEATURE

RESERVED FOR MOBILE
AZALIA DOCKING INT’F

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

47

47

47

79 57 14

62 47 41

62 47 39

48 47

6

34

34

27

27

33

33

56 49 48 47

5

47 26

5

14

56 49 47 40

5

45 37

5

47

56 49 47

5

26

47

47

26

23

100

21

R2302

100

21

R2303

100

21

R2305

36

36

48 47

23

47

NOSTUFF

402
5%

MF-LF

1/16W

10K

2

1

R2306

10K

402
5%

MF-LF

1/16W

2

1

R2307

402

1/16W
MF-LF

5%

10K

2

1

R2308

5%

MF-LF

1/16W

0

402

NOSTUFF

2

1

R2309

402
5%

MF-LF

1/16W

10K

2

1

R2310

1/16W
MF-LF

5%

NOSTUFF

402

10K

2

1

R2311

10K

1/16W
MF-LF

5%

402

2

1

R2313

402

NOSTUFF

0

1/16W
MF-LF

5%

2

1

R2314

33

402

10K

1/16W
MF-LF

5%

2

1

R2316

402

10K

1/16W
MF-LF

5%

2

1

R2317

10K

402

1/16W
MF-LF

5%

2

1

R2318

10K

1/16W
MF-LF

5%

402

2

1

R2319

402
5%

MF-LF

1/16W

10K

2

1

R2320

1/16W

5%

10K

SM-LF

5678

4321

RP2300

5%

402

MF-LF

1/16W

100K

21

R2399

1/16W
MF-LF

5%

402

1K

2

1

R2398

5%

MF-LF

1/16W

8.2K

402

2

1

R2397

MF-LF
5%

1/16W

10K

402

2

1

R2396

8.2K

1/16W
MF-LF

402
5%

2

1

R2395

OMIT

BGA

SB

ICH7-M

F20

AD22

C21

AF20

A22

C20

A27

A19

A25

B25

B22

C22

F22

D23

B24

AH21

Y4

A28

AA4

C23

A26

C19

E20

E21

AC18

AC21

AE20

AD20

AE19

AH19

AD21

U2

AC19

AG18

E23

B21

A21

D20

R3

AF19

AF21

AH18

AC20

AC22

E22

R4

E19

F19

B23

A20

AB18

B2

AC1

U2100

402

10K

5%
1/16W
MF-LF

2

1

R2390

402

1/16W
MF-LF

5%

10K

2

1

R2388

MF-LF

402
5%

1K

1/16W

NO_REBOOT_MODE

2

1

R2323

NOSTUFF

10K

1/16W
MF-LF
402
5%

2

1

R2326

NOSTUFF

5%

MF-LF

1/16W
402

10K

2

1

R2327

5%
402

8.2K

1/16W
MF-LF

2

1

R2343

47

SB: 3 OF 4

SYNC_DATE=11/16/2005

SYNC_MASTER=M38

051-6941

104

23

12

SMC_RUNTIME_SCI_L
SMC_EXTSMI_L

PM_THRM_L

SB_GPIO26

SMB_ALERT_L

PM_CLKRUN_L

PCIE_WAKE_L
INT_SERIRQ

=PP3V3_S5_SB

SMB_DATA

SB_SPKR

PM_BMBUSY_L

PM_STPCPU_L

FWH_MFG_MODE

TP_AZ_DOCK_RST_L

PM_STPPCI_L

PATA_PWR_EN_L

=PP3V3_S5_SB

SATA_C_PWR_EN_L

=PP3V3_S0_SB_GPIO

CRB_SV_DET

SMC_WAKE_SCI_L

SMS_INT_L

PATA_PWR_EN_L

SMC_SB_NMI

=PP3V3_S0_SB_GPIO

BIOS_REC

FWH_MFG_MODE

=PP3V3_S5_SB

CRB_SV_DET

TP_SB_GPIO38

TP_SB_GPIO6

IDE_RESET_L

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB

VR_PWRGD_CK410

TP_AZ_DOCK_EN_L

BIOS_REC

PM_SUS_STAT_L
PM_SYSRST_L

PM_RI_L

SMLINK<0>
SMLINK<1>

SMB_LINK_ALERT_L

SATA_C_PWR_EN_L

SB_CLK100M_SATA_OE_L

TP_SB_GPIO25_DO_NOT_USE

SV_SET_UP

PM_LAN_ENABLE

PM_PWRBTN_L

PM_DPRSLPVR

PM_BATLOW_L

PM_SB_PWROK

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

SUS_CLK_SB

SB_CLK14P3M_TIMER

SB_GPIO37

SB_CLK48M_USBCTLR

SB_GPIO21
SB_GPIO19

SATA_C_DET_L

SMB_CLK

PM_RSMRST_L

SV_SET_UP

63

63

63

63

63

63

63

63

49

49

25

25

23

23

25

25

26

25

23

23

23

23

23

23

23

21

23

21

23

23

23

23

23

11

23

23

5

5

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB CORE

VCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCCSUS3_3

VCC1_5_A

VCC1_5_A

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CODEC IC’S CONSIDERED SO FAR ARE 3.3V

DEPENDING ON VIO OF AZALIA INTERFACE

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V

NOTE:

VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE

CHANGE SYMBOL TO 1.05

CHANGE SYMBOL TO 1.05

S0 OR S3 IF NOT

S3 IF INTERNAL LAN IS USED

NOTE FOR VCCLAN_3_3:

0 0

OMIT

BGA

ICH7-M

SB

AE21

AE18

AE13

AE11

AE8

AE4

AE2

AD23

AD19

AD15

AD11

AD8

AD7

AD4

AD3

AD1

AC11

AC9

AC5

AC2

AB28

AB27

AB24

AB21

AB19

AB16

AB14

AB11

AB6

AB4

AA26

AA25

AA24

AA1

Y28

Y27

Y24

Y3

W26

W25

W24

W6

V28

V27

V24

V15

V13

V2

U26

U25

U24

U17

U16

U15

U14

U13

U12

U4

T17

T16

T15

T14

T13

T12

T6

R18

R17

R16

R15

R14

R13

R12

R11

R1

P28

P27

P24

P17

P16

P15

P14

P13

P12

P4

P3

N26

N25

N24

AH27

AH23

AH12

AH7

N18

AH3

AH1

AG25

AG20

AG17

AG14

AG11

AG7

AG3

AG1

N17

AF28

AF27

AF11

AF8

AF4

AF2

AE25

AE24

N16

N15

N14

N13

N12

N11

N6

N5

N2

N1

M28

M27

M24

M17

M16

M15

M14

M13

M12

M5

M4

M3

L26

L25

L24

L15

L13

K28

K27

K24

J26

J25

J24

J5

J2

J1

H28

H27

H24

H5

H4

H3

G26

G25

G24

G21

G18

G14

G9

G6

G5

G2

G1

F28

F27

F12

F5

F4

F3

E15

E8

E4

E2

E1

D24

D21

D18

D13

D10

C27

C6

C2

B28

B26

B20

B17

B14

B11

B8

B1

A23

A4

U2100

OMIT

BGA

SB

ICH7-M

C1

K6

K5

K4

K3

G19

D22

D19

C24

E3

N7

M7

M6

L7

L6

L3

L2

L1

A24

P7

R7

G20

C28

K7

AD2

W5

W7

W2

V1

V5

Y7

AA2

AG28

AG15

AG12

AD18

AD13

AC16

AB20

AB12

G16

AA7

G12

G11

F9

D15

C10

B7

B16

B13

A5

AG19

AH11

B27

U6

AD27

AD26

AC26

AC25

Y23

Y22

W23

AC24

W22

V23

V22

U23

U22

T28

T27

T26

T23

T22

AC23

R26

R25

R24

R23

R22

P23

P22

N23

N22

M23

AB23

M22

L23

L22

K23

K22

J23

J22

H23

H22

G23

AB22

G22

F24

F23

E26

E25

E24

D28

D27

D26

AD28

AA23

AA22

AB10

AH5

AG5

AF6

AF5

AE6

AD6

J7

J6

H7

H6

A1

AC8

AB8

G17

F17

T7

AC7

AC17

AB17

AH9

AG9

AF9

AF10

AE10

AD10

AC10

AB9

AC6

AB7

P11

M18

M11

L18

L17

L16

L14

V18

L12

V17

V16

V14

V12

V11

U18

U11

T18

T11

P18

L11

AH26

AE26

AE23

F6

AD17

G10

U2100

SB: 4 OF 4

SYNC_DATE=11/16/2005

SYNC_MASTER=M38

12

24

104

051-6941

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S5_SB_VCCSUS3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ARX

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3

=PP1V05_S0_SB_CPU_IO

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_VCCLAN3_3

=PPVCORE_S0_SB

PP5V_S5_SB_V5REF_SUS

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

63

26

63

63

63

63

63

63

63

25

25

63

63

25

63

25

63

63

25

25

63

63

25

25

25

25

24

21

25

25

24

25

24

25

25

25

24

21

25

25

25

25

22