Analog Devices AD7225UE, AD7225TQ, AD7225TE, AD7225LR, AD7225LP Datasheet

LC2MOS Quad 8-Bit DAC

a

FEATURES
Four 8-Bit DACs with Output Amplifiers
Separate Reference Input for Each DAC
mP Compatible with Double-Buffered Inputs
Simultaneous Update of All Four Outputs
Operates with Single or Dual Supplies
Extended Temperature Range Operation
No User Trims Required
Skinny 24-Pin DIP, SOIC and 28-Terminal Surface

Mount Packages

GENERAL DESCRIPTION

The AD7225 contains four 8-bit voltage output digital-to­analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. Each D/A converter has a
separate reference input terminal. No external trims are re­quired to achieve full specified performance for the part.

The double-buffered interface logic consists of two 8-bit regis­ters per channel–an input register and a DAC register. Control
inputs A0 and A1 determine which input register is loaded when
WR goes low. Only the data held in the DAC registers deter­mines the analog outputs of the converters. The double­buffering allows simultaneous update of all four outputs under
control of
level compatible and the control logic is speed compatible with
most 8-bit microprocessors.

Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. The part is also
specified for single supply operation using a reference of +10 V.
Each output buffer amplifier is capable of developing +10 V
across a 2 kΩ load.

The AD7225 is fabricated on an all ion-implanted high-speed
Linear Compatible CMOS (LC
specifically developed to integrate high speed digital logic cir­cuits and precision analog circuitry on the same chip.

LDAC. All logic inputs are TTL and CMOS (5 V)

2

MOS) process which has been

with Separate Reference Inputs

AD7225

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. DACs and Amplifiers on CMOS Chip
The single-chip design of four 8-bit DACs and amplifiers al­lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert­ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one end of the package and all
digital inputs at the other.

2. Single or Dual Supply Operation
The voltage-mode configuration of the AD7225 allows single
supply operation. The part can also be operated with dual
supplies giving enhanced performance for some parameters.

3. Versatile Interface Logic
The AD7225 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. The double-buffered in­terface allows simultaneous update of the four outputs.

4. Separate Reference Input for Each DAC
The AD7225 offers great flexibility in dealing with input sig­nals with a separate reference input provided for each DAC
and each reference having variable input voltage capability.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7225–SPECIFICA TIONS

DUAL SUPPLY

(VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; V
All specifications T

MIN

to T

unless otherwise noted.)

MAX

= +2 V to (VDD – 4 V)1 unless otherwise noted.

REF

K, B L, C

Parameter Versions2Versions2T Version U Version Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8 8 8 8 Bits
Total Unadjusted Error ±2 ±1 ±2 ±1 LSB max V
Relative Accuracy ± 1 ± 1/2 ± 1 ±1/2 LSB max

= +15 V ± 5%, V

DD

REF

Differential Nonlinearity ± 1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error ±1 ±1/2 ±1 ±1/2 LSB max
Full-Scale Temp. Coeff. ±5 ±5 ±5 ±5 ppm/°C typ VDD = 14 V to 16.5 V, V
Zero Code Error @ 25°C ±25 ±15 ±25 ±15 mV max

T

to T

MIN

Zero Code Error Temp Coeff. ±30 ±30 ±30 ±30 µV/°C typ

MAX

±30 ±20 ±30 ±20 mV max

REFERENCE INPUT

Voltage Range 2 to (VDD – 4) 2 to (VDD – 4) 2 to (VDD – 4) 2 to (VDD – 4) V min to V max
Input Resistance 11 11 11 11 kΩ min
Input Capacitance
Channel-to-Channel Isolation360 60 60 60 dB min V
AC Feedthrough

3

3

100 100 100 100 pF max Occurs when each DAC is loaded with all 1s.

= 10 V p-p Sine Wave @ 10 kHz

–70 –70 –70 –70 dB max V

REF

= 10 V p-p Sine Wave @ 10 kHz

REF

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current ±1 ±1 ±1 ±1 µA max VIN = 0 V or V
Input Capacitance

INH

INL

3

2.4 2.4 2.4 2.4 V min

0.8 0.8 0.8 0.8 V max
8 8 8 8 pF max

DD

Input Coding Binary Binary Binary Binary

DYNAMIC PERFORMANCE

Voltage Output Slew Rate32.5 2.5 2.5 2.5 V/µs min
Voltage Output Settling Time

Positive Full-Scale Change 5 5 5 5 µs max V

Negative Full-Scale Change 5 5 5 5 µs max V
Digital Feedthrough
Digital Crosstalk

3

3

Minimum Load Resistance 2 2 2 2 kΩ min V

3

= +10 V; Settling Time to ±1/2 LSB

REF

= +10 V; Settling Time to ±1/2 LSB

50 50 50 50 nV secs typ Code transition all 0s to all 1s.

REF

50 50 50 50 nV secs typ Code transition all 0s to all 1s.

= +10 V

OUT

POWER SUPPLIES

VDD Range 11.4/16.5 11.4/16.5 11.4/16.5 11.4/16.5 V min to V max For Specified Performance
I

DD

I

SS

SWITCHING CHARACTERISTICS

t

1

@ 25°C 95 9 5 95 95 ns min Write Pulse Width

T

to T

MIN

MIN

MIN

MIN

MIN

MIN

to T

to T

to T

to T

to T

MAX

MAX

MAX

MAX

MAX

MAX

t

2

@ 25°C 0 0 0 0 ns min Address to Write Setup Time

T
t

3

@ 25°C 0 0 0 0 ns min Address to Write Hold Time

T
t

4

@ 25°C 70 7 0 70 70 ns min Data Valid to Write Setup Time

T
t

5

@ 25°C 10 1 0 10 10 ns min Data Valid to Write Hold Time

T
t

6

@ 25°C 95 9 5 95 95 ns min Load DAC Pulse Width

T

NOTES

1

Maximum possible reference voltage.

2

Temperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C

3

Sample Tested at 25°C to ensure compliance.

4

Switching characteristics apply for single and dual supply operation.

Specifications subject to change without notice.

10 10 12 12 mA max Outputs Unloaded; VIN = V
9 9 10 10 mA max Outputs Unloaded; VIN = V

3, 4

120 120 150 150 ns min

0 0 0 0 ns min

0 0 0 0 ns min

90 90 90 90 ns min

10 10 10 10 ns min

120 120 150 150 ns min

= +10 V

= +10 V

REF

or V

INL

or V

INL

INH
INH

–2–

REV. B

AD7225

(VDD = +15 V 6 5%; VSS = AGND = DGND = O V; V

SINGLE SUPPLY

Parameter Versions2Versions

All specifications T

K, B L, C

MIN

to T

MAX

unless otherwise noted.)

2

T Version U Version Units Conditions/Comments

= +10 V1 unless otherwise noted.

REF

STATIC PERFORMANCE

Resolution 8888Bits
Total Unadjusted Error
Differential Nonlinearity

3

3

±2 ±1 ±2 ±1 LSB max
± 1 ±1 ±1 ±1 LSB max Guaranteed Monotonic

REFERENCE INPUT

Input Resistance 11 11 11 11 kΩ min
Input Capacitance
Channel-to-Channel Isolation
AC Feedthrough

4

3, 4, 5

100 100 100 100 pF max Occurs when each DAC is loaded with all 1s.

3, 4

60 60 60 60 dB min V
–70 –70 –70 –70 dB max V

= 10 V p-p Sine Wave @ 10 kHz

REF

= 10 V p-p Sine Wave @ 10 kHz

REF

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current ±1 ±1 ±1 ±1 µA max VIN = 0 V or V
Input Capacitance

INH

INL

4

2.4 2.4 2.4 2.4 V min

0.8 0.8 0.8 0.8 V max
8888pF max

DD

Input Coding Binary Binary Binary Binary

DYNAMIC PERFORMANCE

Voltage Output Slew Rate
Voltage Output Settling Time

4

2222V/µs min

4

Positive Full-Scale Change 5555µs max Settling Time to ±1/2 LSB

Negative Full-Scale Change 7777µs max Settling Time to ±1/2 LSB
Digital Feedthrough
Digital Crosstalk
Minimum Load Resistance 2222kΩ min V

3, 4

3, 4

50 50 50 50 nV secs typ Code transition all 0s to all 1s.
50 50 50 50 nV secs typ Code transition all 0s to all 1s.

= +10 V

OUT

POWER SUPPLIES

VDD Range 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 V min to V max For Specified Performance
I

DD

SWITCHING CHARACTERISTICS

t

1

@ 25°C 95 95 95 95 ns min Write Pulse Width

T

to T

MIN

MIN

MIN

MIN

MIN

MIN

to T

to T

to T

to T

to T

MAX

MAX

MAX

MAX

MAX

MAX

t

2

@ 25°C 0000ns minAddress to Write Setup Time

T
t

3

@ 25°C 0000ns minAddress to Write Hold Time

T
t

4

@ 25°C 70 70 70 70 ns min Data Valid to Write Setup Time

T
t

5

@ 25°C 10 10 10 10 ns min Data Valid to Write Hold Time

T
t

6

@ 25°C 95 95 95 95 ns min Load DAC Pulse Width

T

NOTES

1

Maximum possible reference voltage.

2

Temperature ranges are as follows:

K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C

10 10 12 12 mA max Outputs Unloaded; VIN = V

4

120 120 150 150 ns min

0000ns min

0000ns min

90 90 90 90 ns min

10 10 10 10 ns min

120 120 150 150 ns min

3

Sample Tested at 25°C to ensure compliance.

4

Switching characteristics apply for single and dual supply operation.

Specifications subject to change without notice.

ORDERING GUIDE

INL

or V

INH

Total
Temperature Unadjusted Package
Range Error Option

Model

1

AD7225KN –40°C to +85°C ±2 LSB N-24
AD7225LN –40°C to +85° C ±1 LSB N-24
AD7225KP –40°C to +85°C ±2 LSB P-28A
AD7225LP –40°C to +85°C ±1 LSB P-28A
AD7225KR –40°C to +85° C ±2 LSB R-24
AD7225LR –40°C to +85° C ±1 LSB R-24
AD7225BQ –40°C to +85°C ±2 LSB Q-24
AD7225CQ –40°C to +85°C ±1 LSB Q-24

REV. B

Total
Temperature Unadjusted Package
Range Error Option

Model

1

2

AD7225TQ –55°C to +125°C ±2 LSB Q-24
AD7225UQ –55°C to +125°C ±1 LSB Q-24
AD7225TE –55°C to +125°C ±2 LSB E-28A
AD7225UE –55°C to +125 °C ±1 LSB E-28A

NOTES

1

To order MIL-STD-883 processed parts, add /883B to part number. Contact your
local sales office for military data sheet.

2

E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

–3–

2

AD7225

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V

DD

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +24 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

DD

Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V

V

to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

REF

V

to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

OUT

DD

Power Dissipation (Any Package) to +75°C . . . . . . . . 500 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C

Operating Temperature

Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C

Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C

Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Outputs may be shorted to any voltage in the range VSS to VDD provided that the

power dissipation of the package is not exceeded. Typical short circuit current for
a short to AGND or VSS is 50 mA.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7225 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP and SOIC LCCC PLCC

TERMINOLOGY
TOTAL UNADJUSTED ERROR

Total Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy, and zero code error.
Maximum output voltage is V
(ideal) is V

/256. The LSB size will vary over the V

REF

– 1 LSB (ideal), where 1 LSB

REF

REF

Hence the zero code error will, relative to the LSB size, increase
as V

decreases. Accordingly, the total unadjusted error,

REF

which includes the zero code error, will also vary in terms of
LSBs over the V

range. As a result, total unadjusted error is

REF

specified for a fixed reference voltage of +10 V.

RELATIVE ACCURACY

Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al­lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.

range.

DIGITAL FEEDTHROUGH

Digital Feedthrough is the glitch impulse transferred to the out­put of the DAC due to a change in its digital input code. It is
specified in nV secs and is measured at V

REF

= 0 V.

DIGITAL CROSSTALK

Digital Crosstalk is the glitch impulse transferred to the output
of one converter (not addressed) due to a change in the digital
input code to another addressed converter. It is specified in
nV secs and is measured at V

REF

= 0 V.

AC FEEDTHROUGH

AC Feedthrough is the proportion of reference input signal
which appears at the output of a converter when that DAC is
loaded with all 0s.

CHANNEL-TO-CHANNEL ISOLATION

Channel-to-channel isolation is the proportion of input signal
from the reference of one DAC (loaded with all 1s) which ap­pears at the output of one of the other three DACs (loaded with
all 0s) The figure given is the worst case for the three other out­puts and is expressed as a ratio in dBs.

FULL-SCALE ERROR

Full-Scale Error is defined as:

Measured Value – Zero Code Error – Ideal Value

–4–

REV. B