Analog Devices AD6624 b Datasheet

Four-Channel, 80 MSPS Digital

a

FEATURES
80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI)
Dual High Speed Data Input Ports
Four Independent Digital Receivers in Single Package
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Programmable Attenuator Control for Clip Prevention

and External Gain Ranging via Level Indicator

Flexible Control for Multicarrier and Phased Array

3.3 V I/O, 2.5 V CMOS Core
User-Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan

APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136,

EDGE, PHS, IS95
Micro and Pico Cell Systems
Wireless Local Loop
Smart Antenna Systems
Software Radios
In-Building Wireless Telephony

PRODUCT DESCRIPTION

The AD6624 is a four-channel (quad) digital receive signal
processor (RSP) with four cascaded signal-processing elements:
a frequency translator, two fixed-coefficient decimating filters,
and a programmable-coefficient decimating filter.

Receive Signal Processor (RSP)

AD6624

The AD6624 is part of Analog Devices’ SoftCell® multicarrier
transceiver chipset designed for compatibility with Analog
Devices’ family of high sample rate IF sampling ADCs (AD6640/
AD6644 12- and 14-bit). The SoftCell receiver comprises a
digital receiver capable of digitizing an entire spectrum of
carriers and digitally selecting the carrier of interest for tuning
and channel selection. This architecture eliminates redundant
radios in wireless base station applications.

High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.

The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 30 dB or more. In addition, the programmable RAM
coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost­effective filter.

The AD6624 is compatible with standard ADC converters such
as the AD664x, AD9042, AD943x, and the AD922x families of
data converters. The AD6624 is also compatible with the AD6600
Diversity ADC, providing a cost and size reduction path.

FUNCTIONAL BLOCK DIAGRAM

16 BITS 18 BITS 20 BITS 24 BITS

INA[13:0]

EXPA[2:0]

IENA

LIA-A

LIA-B

SYNCA
SYNCB
SYNCC
SYNCD

INB[13:0]

EXPB[2:0]

IENB

LIB-A
LIB-B

CH A NCO

CH B NCO

INPUT MATRIX

CH C NCO

CH D NCO

EXTERNAL SYNC

RESAMPLER

RESAMPLER

RESAMPLER

RESAMPLER

CIRCUITRY

rCIC2

rCIC2

rCIC2

rCIC2

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

CIC5

CIC5

CIC5

CIC5

JTAG

INTERFACE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

RAM

COEFFICIENT

FILTER

RAM

COEFFICIENT

FILTER

RAM

COEFFICIENT

FILTER

RAM

COEFFICIENT

FILTER

BUILT-IN

SELF-TEST

SERIAL AND MICROPORT

SDIN[3:0]

SDO[3:0]

DR[3:0]

SDFS[3:0]

SDFE[3:0]

SCLK[3:0]

MODE

DS(RD)
CS

RW (WR)
DTACK(RDY)

A[2:0]

D[7:0]

AD6624

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS/CHARACTERISTICS . . . . . . . . . . . . . 3

GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . 4

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 11

ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

EXAMPLE FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 14

INPUT DATA PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Gain Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input Data Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Scaling with Fixed-Point ADCs . . . . . . . . . . . . . . . . . . . . 16

Scaling with Floating-Point or Gain-Ranging ADCs . . . . 16

NUMERICALLY CONTROLLED OSCILLATOR . . . . . 17

Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

NCO Frequency Hold-Off Register . . . . . . . . . . . . . . . . . 17

Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clear Phase Accumulator on HOP . . . . . . . . . . . . . . . . . . 17

Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Mode 00: Blank On IEN Low . . . . . . . . . . . . . . . . . . . . . 17

Mode 01: Clock On IEN High . . . . . . . . . . . . . . . . . . . . 18

Mode 10: Clock on IEN Transition to High . . . . . . . . . . 18

Mode 11: Clock on IEN Transition to Low . . . . . . . . . . . 18

WB Input Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Sync Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SECOND ORDER rCIC FILTER . . . . . . . . . . . . . . . . . . . 18

rCIC2 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Example Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Decimation and Interpolation Registers . . . . . . . . . . . . . . 19

rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FIFTH ORDER CASCADED INTEGRATOR COMB

FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CIC5 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 20

RCF Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . 21

RCF Decimation Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 21

RCF Filter Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

RCF Output Scale Factor and Control Register . . . . . . . . 21

USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) 22

RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CHANNEL BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . 22

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SERIAL OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . 24

Serial Output Data Format . . . . . . . . . . . . . . . . . . . . . . . 24

Serial Data Frame (Serial Bus Master) . . . . . . . . . . . . . . . 24

Serial Data Frame (Serial Cascade) . . . . . . . . . . . . . . . . . 25

Configuring the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Port Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Port to DSP Interconnection . . . . . . . . . . . . . . . . . 25

Serial Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Ports Cascaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Output Frame Timing (Master and Slave) . . . . . . . 26

Serial Port Timing Specifications . . . . . . . . . . . . . . . . . . . 26

SBM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SDFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SDFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Serial Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SDFS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mapping RCF Data to the BIST Registers . . . . . . . . . . . . 29

0x00–0x7F: Coefficient Memory (CMEM) . . . . . . . . . . . 29

0x80: Channel Sleep Register . . . . . . . . . . . . . . . . . . . . . 30

0x81: Soft_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . 30

0x82: Pin_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . 30

0x83: Start Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . 30

0x84: NCO Frequency Hold-Off Counter . . . . . . . . . . . . 30

0x85: NCO Frequency Register 0 . . . . . . . . . . . . . . . . . . 30

0x86: NCO Frequency Register 1 . . . . . . . . . . . . . . . . . . 30

0x87: NCO Phase Offset Register . . . . . . . . . . . . . . . . . . 30

0x88: NCO Control Register . . . . . . . . . . . . . . . . . . . . . . 30

0x90: rCIC2 Decimation – 1 (M
0x91: rCIC2 Interpolation – 1 (L

–1) . . . . . . . . . . . . . 31

rCIC2

–1) . . . . . . . . . . . . 31

rCIC2

0x92: rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

0x93: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

0x94: CIC5 Decimation – 1 (M

–1) . . . . . . . . . . . . . . 31

CIC5

0x95: CIC5 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

0x96: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

0xA0: RCF Decimation – 1 (M
0xA1: RCF Decimation Phase (P
0xA2: RCF Number of Taps Minus One (N
0xA3: RCF Coefficient Offset (CO

–1) . . . . . . . . . . . . . . . 31

RCF

) . . . . . . . . . . . . . . . 31

RCF

) . . . . . . . . . . . . . . 31

RCF

-1) . . . . . 31

RCF

0xA4: RCF Control Register . . . . . . . . . . . . . . . . . . . . . . 31

0xA5: BIST Register for I . . . . . . . . . . . . . . . . . . . . . . . . 32

0xA6: BIST Register for Q . . . . . . . . . . . . . . . . . . . . . . . 32

0xA7: BIST Control Register . . . . . . . . . . . . . . . . . . . . . 32

0xA8: RAM BIST Control Register . . . . . . . . . . . . . . . . 32

0xA9: Serial Port Control Register . . . . . . . . . . . . . . . . . 32

MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 33

External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Access Control Register (ACR) . . . . . . . . . . . . . . . . . . . . 33

External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Channel Address Register (CAR) . . . . . . . . . . . . . . . . . . . 34

SOFT_SYNC Control Register . . . . . . . . . . . . . . . . . . . . 34

PIN_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . . 34

SLEEP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 34

Data Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Write Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Read Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Read/Write Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . 35

Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . 35

Input Port Control Registers . . . . . . . . . . . . . . . . . . . . . . 35

SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 36

JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 36

INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . 37

Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . 37

Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 38

–2–

REV. B

AD6624

SPECIFICATIONS

(VDD = 2.5 V ⴞ 5%, VDDIO = 3.3 V ⴞ 10%. All specifications TA = T

MIN

to T

, unless otherwise noted.)

MAX

RECOMMENDED OPERATING CONDITIONS

Test AD6624AS

Parameter Level Min Typ Max Unit

VDD IV 2.375 2.5 2.675 V
VDDIO IV 3.0 3.3 3.6 V
T

AMBIENT

IV –40 +25 +70 °C

ELECTRICAL CHARACTERISTICS

Test AD6624AS

Parameter (Conditions) Temp Level Min Typ Max Unit

LOGIC INPUTS

Logic Compatibility Full 3.3 V CMOS
Logic “1” Voltage Full IV 2.0 5.0 V
Logic “0” Voltage Full IV –0.3 +0.8 V
Logic “1” Current Full IV 1 10 µA
Logic “0” Current Full IV 1 10 µA
Input Capacitance 25°CV 4 pF

LOGIC OUTPUTS

Logic Compatibility Full 3.3 V CMOS/TTL
Logic “1” Voltage (I
Logic “0” Voltage (IOL = 0.25 mA) Full IV 0.2 0.4 V

IDD SUPPLY CURRENT

CLK = 80 MHz, (VDD = 2.75 V, VDDIO = 3.6 V) Full IV

I

VDD

I

VDDIO

CLK = GSM Example (65 MSPS, VDD = 2.5 V,

VDDIO = 3.3 V, Dec = 2/10/6 120 Taps 4 Channels) 25°CV
I

VDD

I

VDDIO

POWER DISSIPATION

CLK = 80 MHz TD-SCDMA Full IV 1.1 W
CLK = 65 MHz
Sleep Mode Full IV 287 µW

(5 V TOLERANT)

= 0.25 mA) Full IV 2.4 VDD – 0.2 V

OH

400 mA
60 mA

250 mA
24 mA

GSM/EDGE Example V 700 mW

Specifications subject to change without notice.

REV. B

–3–

AD6624–SPECIFICATIONS

GENERAL TIMING CHARACTERISTICS

1, 2

Test AD6624AS

Parameter (Conditions) Temp Level Min Typ Max Unit

CLK Timing Requirements:
t

CLK

t

CLKL

t

CLKH

CLK Period Full I 12.5 ns
CLK Width Low Full IV 4.5 0.5 × t
CLK Width High Full IV 4.5 0.5 × t

CLK

CLK

ns
ns

RESET Timing Requirement:
t

RESL

RESET Width Low Full I 30.0 ns

Input Wideband Data Timing Requirements:
t

SI

t

HI

Input to ↑CLK Setup Time Full IV 0.8 ns
Input to ↑CLK Hold Time Full IV 2.0 ns

Level Indicator Output Switching Characteristic:
t

DLI

↑CLK to LI (A–A, B; B–A, B) Output Delay Time Full IV 3.8 12.6 ns

SYNC Timing Requirements:
t

SS

t

HS

Serial Port Timing Requirements (SBM = 1):
Switching Characteristics:

t

DSCLK1

t

DSCLKH

t

DSCLKL

t

DSCLKLL

t

DSDFS

t

DSDFE

t

DSDO

t

DSDR

t

DDR

SYNC (A, B, C, D) to ↑CLK Setup Time Full IV 1.0 ns
SYNC (A, B, C, D) to ↑CLK Hold Time Full IV 2.0 ns

3

↑CLK to ↑SCLK Delay (Divide by 1) Full IV 3.9 13.4 ns
↑CLK to ↑SCLK Delay (For Any Other Divisor) Full IV 4.4 14.0 ns
↑CLK to ↓SCLK Delay (Divide by 2 or Even #) Full IV 3.25 6.7 ns
↓CLK to ↓SCLK Delay (Divide by 3 or Odd #) Full IV 3.8 6.9 ns
↑SCLK to SDFS Delay Full IV 0.2 5.3 ns
↑SCLK to SDFE Delay Full IV –0.4 +4.7 ns
↑SCLK to SDO Delay Full IV –1.0 +4.0 ns
↑SCLK to DR Delay Full IV –0.3 +4.6 ns
↑CLK to DR Delay Full IV 5.4 17.6 ns

Input Characteristics:
t

SSI

t

HSI

Serial Port Timing Requirements (SBM = 0):
Switching Characteristics:

t

SCLK

t

SCLKL

t

SCLKH

t

DSDFE

t

DSDO

t

DSDR

SDI to ↓SCLK Setup Time Full IV 2.4 ns
SDI to ↓SCLK Hold Time Full IV 3.0 ns

3

SCLK Period Full IV 16 ns
SCLK Low Time (When SDIV = 1, Divide by 1) Full IV 5.0 ns
SCLK High Time (When SDIV = 1, Divide by 1) Full IV 5.0 ns

↑SCLK to SDFE Delay Full IV 3.8 15.4 ns
↑SCLK to SDO Delay Full IV 3.7 15.2 ns
↑SCLK to DR Delay Full IV 3.9 15.9 ns

Input Characteristics:
t

SSF

t

HSF

t

SSI

t

HSI

NOTES

1

All timing specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.

2

C

LOAD

3

The timing parameters for SCLK, SDFS, SDFE, SDO, SDI, and DR apply to all four channels (0, 1, 2, and 3). The slave serial port’s (SCLK) operating frequency is

limited to 62.5 MHz.

Specifications subject to change without notice.

SDFS to ↑SCLK Setup Time Full IV 1.9 ns
SDFS to ↑SCLK Hold Time Full IV 0.7 ns
SDI to ↓SCLK Setup Time Full IV 2.4 ns
SDI to ↓SCLK Hold Time Full IV 2.0 ns

= 40 pF on all outputs unless otherwise specified.

–4–

REV. B

AD6624

MICROPROCESSOR PORT TIMING CHARACTERISTICS

1, 2

Test AD6624AS

Parameter (Conditions) Temp Level Min Typ Max Unit

MICROPROCESSOR PORT, MODE INM (MODE = 0)

MODE INM Write Timing:
t

SC

t

HC

t

HWR

t

SAM

t

HAM

t

DRDY

t

ACC

Control3 to ↑CLK Setup Time Full IV 5.5 ns
Control3 to ↑CLK Hold Time Full IV 1.0 ns
WR(RW) to RDY(DTACK) Hold Time Full IV 8.0 ns
Address/Data to WR(RW) Setup Time Full IV –0.5 ns
Address/Data to RDY(DTACK) Hold Time Full IV 7.0 ns

WR(RW) to RDY(DTACK) Delay Full IV 4.0 ns
WR(RW) to RDY(DTACK) High Delay Full IV 4 × t

CLK

5 × t

CLK

9 × t

CLK

ns

MODE INM Read Timing:
t

SC

t

HC

t

SAM

t

HAM

t

DRDY

t

ACC

Control3 to ↑CLK Setup Time Full IV 4.0 ns
Control3 to ↑CLK Hold Time Full IV 2.0 ns
Address to RD(DS) Setup Time Full IV 0.0 ns
Address to Data Hold Time Full IV 7.0 ns

RD(DS) to RDY(DTACK) Delay Full IV 4.0 ns
RD(DS) to RDY(DTACK) High Delay Full IV 8 × t

CLK

10 × t

CLK

13 × t

CLK

ns

MICROPROCESSOR PORT, MODE MNM (MODE = 1)

MODE MNM Write Timing:
t

SC

t

HC

t

HDS

t

HRW

t

SAM

t

HAM

t

ACC

Control3 to ↑CLK Setup Time Full IV 5.5 ns
Control3 to ↑CLK Hold Time Full IV 1.0 ns
DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns
RW(WR) to DTACK(RDY) Hold Time Full IV 8.0 ns
Address/Data to RW(WR) Setup Time Full IV –0.5 ns
Address/Data to RW(WR) Hold Time Full IV 7.0 ns
RW(WR) to DTACK(RDY) Low Delay Full IV 4 × t

CLK

5 × t

CLK

9 × t

CLK

ns

MODE MNM Read Timing:
t

SC

t

HC

t

SAM

t

HAM

t

ZD

t

ACC

NOTES

1

All timing specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.

2

C

= 40 pF on all outputs unless otherwise specified.

LOAD

3

Specification pertains to control signals: RW, (WR), DS, (RD), CS.

Specifications subject to change without notice.

Control3 to ↑CLK Setup Time Full IV 4.0 ns
Control3 to ↑CLK Hold Time Full IV 2.0 ns
Address to DS(RD) Setup Time Full IV 8.0 ns
Address to Data Hold Time Full IV 0.0 ns
Data Three-State Delay Full IV 7.0 ns
DS(RD) to DTACK(RDY) Low Delay Full IV 8 × t

CLK

10 × t

CLK

13 × t

CLK

ns

REV. B

–5–

AD6624

R

TIMING DIAGRAMS

t

CLK

t

CLKL

CLK

t

CLKH

t

LIA-A
LIA-B
LIB-A
LIB-B

Figure 1. Level Indicator Output Switching Characteristics

DLI

CLK

t

DSCLKH

t

SCLKH

SCLK

t

SCLKL

Figure 4. SCLK Switching Characteristics (Divide by 1)

ESET

t

SSF

Figure 2.

CLK

IN[13:0]

EXP[2:0]

RESET

Timing Requirements

tSIt

HI

DATA

Figure 3. Input Data Timing Requirements

SCLK

t

DSDFS

SDFS

SDI

SDFE

t

SSI

t

DATAn

HSI

CLK

t

DSCLKH

SCLK

t

SCLKL

Figure 5. SCLK Switching Characteristic (Divide by 2 or
EVEN Integer)

CLK

t

DSCLKH

SCLK

t

DSCLKLL

Figure 6. SCLK Switching Characteristic (Divide by 3 or
ODD Integer)

t

DSDFE

Figure 7. Serial Port Switching Characteristics

–6–

REV. B

AD6624

CLK

IN[13:0]

EXP[2:0]

IEN

t

SI

t

HI

t

DSDO

SCLK

SDO

SDFE

I

15

I

14

Q

Figure 8. SDO, SDFE Switching Characteristics

CLK

t

DDR

DR

Figure 9. CLK, DR Switching Characteristics

SCLK

t

DSDR

DR

Figure 10. SCLK, DR Switching Characteristics

t

DSDFE

1

Q

0

SCLK

SDFS

t

SSF

t

HSF

Figure 11. SDFS Timing Requirements (SBM = 0)

Figure 12. Input Timing for A and B Channels

CLK

SYNCA
SYNCB
SYNCC
SYNCD

t

SS

t

HS

Figure 13. SYNC Timing Inputs

REV. B

–7–

AD6624

CLK

RD (DS)

WR (RW)

A[2:0]

D[7:0]

DTACK

(RDY)

t

SC

t

SAM

t

ZD

VA LID DATA

VA LID ADDRESS

t

ACC

t

HC

CS

t

ZD

t

HAM

t

DD

t

DDTACK

t

HDS

NOTES

1.

t

ACC

ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

MEASURED FROM FE OF DS TO THE FE OF DTACK.

2.

t

ACC

REQUIRES A MAXIMUM 13 CLK PERIODS.

TIMING DIAGRAMS—INM MICROPORT MODE TIMING DIAGRAMS—MNM MICROPORT MODE

CLK

RD (DS)

t

WR (RW)

CS

A[2:0]

D[7:0]

RDY

(DTACK)

NOTES

t

ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

1.

ACC

MEASURED FROM FE OF WR TO THE RE OF RDY.

t

REQUIRES A MAXIMUM 9 CLK PERIODS.

2.

ACC

SC

VAL I D DATA

t

DRDY

t

ACC

t

t

HAM

HAM

t

SAM

VA LID ADDRESS

t

SAM

t

t

HC

HWR

Figure 14. INM Microport Write Timing Requirements

CLK

t

HC

RD (DS)

t

SC

CLK

t

t

SC

t

VAL I D DATA

t

ACC

t

t

HDS

HAM

HAM

DS (RD)

RW (WR)

CS

t

SAM

A[2:0]

D[7:0]

DTACK

(RDY)

NOTES

t

1.

ACC

MEASURED FROM FE OF DS TO THE FE OF DTACK.

t

2.

ACC

VA LID ADDRESS

t

SAM

ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS

REQUIRES A MAXIMUM 9 CLK PERIODS.

HC

t

HRW

t

DDTACK

Figure 16. MNM Microport Write Timing Requirements

WR (RW)

CS

t

SAM

VA LID ADDRESS

t

ZD

t

DRDY

t

ACC

ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS

REQUIRES A MAXIMUM OF 13 CLK PERIODS AND APPLIES TO

t

DD

A[2:0]

D[7:0]

RDY

(DTACK)

NOTES

t

1.

ACC

TIME IS MEASURED FROM FE OF WR TO THE RE OF RDY.

t

2.

ACC

A[2:0] = 7, 6, 5, 3, 2, 1

Figure 15. INM Microport Read Timing Requirements

t

HAM

VA LID DATA

t

ZD

Figure 17. MNM Microport Read Timing Requirements

–8–

REV. B

AD6624

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V

Input Voltage . . . . . . . . . . . . –0.3 V to +5.3 V (5 V Tolerant)

Output Voltage Swing . . . . . . . . . . –0.3 V to VDDIO + 0.3 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . 125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . 280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Thermal Characteristics

128-Lead Plastic Quad Flatpack:

= 41°C/W, No Airflow

θ

JA

= 39°C/W, 200

θ

JA

θ

= 37°C/W, 400

JA

LFPM Airflow
LFPM Airflow

Thermal measurements made in the horizontal position on
a 4-layer board.

ORDERING GUIDE

Model Temperature Range Package Description Option

AD6624AS –40°C to +70°C (Ambient) 128-Lead MQFP (Plastic Quad Flatpack) S-128-1
AD6624S/PCB Evaluation Board with AD6624 and Software

EXPLANATION OF TEST LEVELS

I. 100% Production Tested.
II. 100% Production Tested at 25°C, and Sample Tested at

Specified Temperatures.

III. Sample Tested Only.

IV. Parameter Guaranteed by Design and Analysis.

V. Parameter is Typical Value Only.
VI. 100% Production Tested at 25°C, and Sample Tested at

Temperature Extremes.

Package

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6624 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–9–

AD6624

IENB

LIB-B

LIB-A

EXPA0

EXPA1

EXPA2

INA13

INA12

INA11

INA10

VDDIO

VSSIO

IENA

LIA-B

LIA-A

VSS

INB5

INB4

INB3

INB2

INB1

VDD

INB0

VSS

CLK

VDD

INA9

INA8

INA7

INA6

INA5

INA4

INA3

INA2

VDD

INA1

INA0

VSS

PIN CONFIGURATION

VSSIO

INB6

INB7

INB8

INB9

VDDIO

INB10

INB11

INB12

INB13

VDD

EXPB2

EXPB1

EXPB0

DR3

VSS

SDFE3

SDIN3

SDO3

SDFS3

VDDIO

SCLK3

DR2

SDFE2

SDIN2

VSSIO

121

122

123

125

126

128

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

VSSIO

127

41

40

SYNCD

SYNCC

124

43

42

SYNCB

SYNCA

44

VDD

46

45

D7

RESET

120

47

D6

119

48

D5

116

118

117

AD6624

TOP VIEW

(Not to Scale)

505152

49

D3D2D1

D4

VSS

115

114

53

113

54

VDD

112

55

D0

111

110

565758

DS(RD)

DTACK/RDY

109

RW(WR)

108

107

60

59

MODE

VDDIO

106

61

A2

105

62

A1

104

63

A0

103

102

101

100

98

94

85

83

66

64

VSSIO

99

97

96

95

93

92

91

90

89

88

87

86

84

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

65

VSS

SDO2

SDFS2

SCLK2

DR1

SDFE1

VDD

SDIN1

SDO1

SDFS1

SCLK1

VSSIO

DR0

SDFE0

SDIN0

SDO0

VDDIO

SDFS0

SCLK0

SDIV0

SDIV1

VDD

SDIV2

SDIV3

SBM0

CHIP_ID0

VSS

CHIP_ID1

CHIP_ID2

CHIP_ID3

TDI

VDDIO

TDO

TMS

TCLK

TRST
CS

VSS

–10–

REV. B

AD6624

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Function

1, 12, 38, 50, 65, 76, 102, 113 VSS G Ground
2–6 INB[5:1]
7, 17, 32, 44, 54, 81, 96, 118 VDD P 2.5 V Supply
8INB0
9 IENB
10 LIB-B O Level Indicator—Input B, Interleaved—Data B
11 LIB-A O Level Indicator—Input B, Interleaved—Data A
13 CLK I Input Clock
14–16 EXPA[0:2]
18–21 INA[13:10]
22, 59, 71, 86, 108, 123 VDDIO P 3.3 V Supply
23–26 INA[9:6]
27, 39, 64, 91, 103, 128 VSSIO G Ground
28–31 INA[5:2]
33–34 INA[1:0]
35 IENA
36 LIA-B O Level Indicator—Input A, Interleaved—Data B
37 LIA-A O Level Indicator—Input A, Interleaved—Data A
40 SYNCD
41 SYNCC
42 SYNCB
43 SYNCA
45 RESET IActive Low Reset Pin
46–49 D[7:4] I/O/T Bidirectional Microport Data
51–53 D[3:1] I/O/T Bidirectional Microport Data
55 D0 I/O/T Bidirectional Microport Data—LSB
56 DS(RD)IActive Low Data Strobe (Active Low Read)
57 DTACK(RDY)
58 RW(WR)IRead Write (Active Low Write)
60 MODE I Intel or Motorola Mode Select
61–63 A[2:0] I Microport Address Bus
66 CS
67 TRST
68 TCLK
69 TMS
70 TDO O/T Test Data Output
72 TDI
73–75 CHIP_ID[3:1]
77 CHIP_ID0
78 SBM0
79–80 SDIV[3:2]
82–83 SDIV[1:0]
84 SCLK0
85 SDFS0
87 SDO0
88 SDIN0
89 SDFE0 O Serial Data Frame End—Channel 0
90 DR0 O Output Data Ready Indicator—Channel 0

1

1

2

1

1

1

1

1

2

1

1

1

1

1

2

1

2

2

1

1

1

1

1

1

1

1

1

IB Input Data (Mantissa)

IB Input Data (Mantissa)—LSB
I Input Enable—Input B

IA Input Data (Exponent)
IA Input Data (Mantissa)

IA Input Data (Mantissa)

IA Input Data (Mantissa)
IA Input Data (Mantissa)
I Input Enable—Input A

IAll Sync Pins Go to All Four Output Channels
IAll Sync Pins Go to All Four Output Channels
IAll Sync Pins Go to All Four Output Channels
IAll Sync Pins Go to All Four Output Channels

2

O/T Active Low Data Acknowledge (Microport Status Bit)

IChip Select
ITest Reset Pin
ITest Clock Input
ITest Mode Select Input

ITest Data Input
IChip ID Selector
IChip ID Selector—LSB
I Serial Bus Master—Channel 0 Only
I Serial Clock Divisor—Channel 0
I Serial Clock Divisor—Channel 0
I/O Bidirectional Serial Clock—Channel 0
I/O Bidirectional Serial Data Frame Sync—Channel 0
O/T Serial Data Output—Channel 0
I Serial Data Input—Channel 0

REV. B

–11–

AD6624

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Type Function

92 SCLK1
93 SDFS1
94 SDO1
95 SDIN1
97 SDFE1 O Serial Data Frame End—Channel 1
98 DR1 O Output Data Ready Indicator—Channel 1
99 SCLK2
100 SDFS2
101 SDO2
104 SDIN2
105 SDFE2 O Serial Data Frame End—Channel 2
106 DR2 O Output Data Ready Indicator—Channel 3
107 SCLK3
109 SDFS3
110 SDO3
111 SDIN3
112 SDFE3 O Serial Data Frame End—Channel 3
114 DR3 O Output Data Ready Indicator—Channel 3
115–117 EXPB[0:2]
119–122 INB[13:10]
124–127 INB[9:6]

NOTES

1

Pins with a pull-down resistor of nominal 70 kΩ.

2

Pins with a pull-up resistor of nominal 70 kΩ.

Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-State.

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

I/O Bidirectional Serial Clock—Channel 1
I/O Bidirectional Serial Data Frame Sync—Channel 1
O/T Serial Data Output—Channel 1
I Serial Data Input—Channel 1

I/O Bidirectional Serial Clock—Channel 2
I/O Bidirectional Serial Data Frame Sync—Channel 2
O/T Serial Data Output—Channel 2
I Serial Data Input—Channel 2

I/O Bidirectional Serial Clock—Channel 3
I/O Bidirectional Serial Data Frame Sync—Channel 3
O/T Serial Data Output—Channel 3
I Serial Data Input—Channel 3

IB Input Data (Exponent)
IB Input Data (Mantissa)
IB Input Data (Mantissa)

–12–

REV. B