Analog Devices AD6600ST-PCB, AD6600AST Datasheet

Dual Channel, Gain-Ranging

a

FEATURES
Dual IF Inputs, 70 MHz–250 MHz

Diversity or Two Independent IF Signals
Separate Attenuation Paths

Oversample RF Channels

20 MSPS on a Single Carrier
10 MSPS/Channel in Diversity Mode

Total Signal Range 90+ dB

30 dB from Automatic Gain-Ranging (AGC)
60 dB from A/D Converter
Range >100 dB After Processing Gain

Digital Outputs

11-Bit ADC Word
3-Bit RSSI Word
2 Clock, A/B Indicator

Single 5 V Power Supply

Output DVCC 3.3 V or 5 V

775 mW Power Dissipation

APPLICATIONS
Communications Receivers
PCS/Cellular Base Stations

GSM, CDMA, TDMA

Wireless Local Loop, Fixed Access

PRODUCT DESCRIPTION

The AD6600 mixed-signal receiver chip directly samples signals
at analog input frequencies up to 250 MHz. The device includes

ADC with RSSI

AD6600

two input channels, each with 1 GHz input amplifiers and
30 dB of automatic gain-ranging circuitry. Both channels are
sampled with a 450 MHz track-and-hold followed by an 11-bit,
20 MSPS analog-to-digital converter. Digital RSSI outputs, an
A/B channel indicator, a 2× Clock output, references, and con­trol circuitry are all on-chip. Digital output signals are two’s
complement, CMOS-compatible and interface directly to

3.3 V or 5 V digital processing chips.

The primary use for the dual analog input structure is sampling
both antennas in a two-antenna diversity receiver. However,
Channels A and B may also be used to sample two independent
IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS
per channel. In single-channel mode, the full clock rate of
20 MSPS may be applied to a single carrier.

The AD6600 may be used as a stand-alone sampling chip, or it
may be combined with the AD6620 Digital Receive Signal Pro­cessor. The AD6620 provides 10 dB–25 dB of additional pro­cessing gain before passing data to a fixed- or floating-point DSP.

Driving the AD6600 is simplified by using the AD6630 differen­tial IF amplifier. The AD6630 is easily matched to inexpensive
SAW filters from 70 MHz to 250 MHz.

Designed specifically for cellular/PCS receivers, the AD6600
supports GSM, IS-136, CDMA and Wireless LANs, as well as
proprietary air interfaces used in WLL/fixed-access systems.

Units are available in plastic, surface-mount packages (44-lead
LQFP) and specified over the industrial temperature range
(–40°C to +85°C).

FUNCTIONAL BLOCK DIAGRAM

0dB, –12dB, –24dB

AIN

AIN

DETECT

BIN

BIN

ATTEN

SET

PEAK

RSSI

ATTEN

0dB, –12dB, –24dB

GAIN

3

GAIN

RSSI

+12, +18dB

ANALOG MUX

SELECT GAIN

GAIN

AD6600

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

NOISE FILTER

FLT FLT

630

ENCODE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

RESONANT

ENCODE

PORT

A/D

CONVERTER

TIMING

TWO'S

COMPLEMENT

11

3

RSSI

DVCCENCENCGNDAVCCB_SELA_SEL

AB_OUT

D10–D0

RSSI [2:0]

CLK2

AD6600–SPECIFICATIONS

DC SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; T

= –40C, T

MIN

= +85C unless otherwise noted.)

MAX

Test AD6600AST

Parameter Temp Level Min Typ Max Unit

ANALOG INPUTS (AIN, AIN/BIN, BIN)

Differential Analog Input Voltage Range
Differential Analog Input Resistance

1

2

Full V 2.0 V p-p
Full IV 160 200 240 Ω

Differential Analog Input Capacitance 25°C V 1.5 pF

PEAK DETECTOR (Internal), RSSI

Resolution 3 Bits
RSSI Gain Step Full V 6 dB
RSSI Hysteresis

3

Full V 6 dB

RESONANT PORT (FLT, FLT)

Differential Port Resistance Full V 630 Ω
Differential Port Capacitance Full V 1.75 pF

A/D CONVERTER

Resolution Full IV 11 Bits

ENCODE INPUTS (ENC, ENC)

Differential Input Voltage (AC-Coupled)

4

Full IV 0.4 V p-p

Differential Input Resistance 25°CV 11 kΩ
Differential Input Capacitance 25°C V 2.5 pF

A/B MODE INPUTS (A_SEL, B_SEL)

5

Input High Voltage Range Full IV 4.75 5.25 V
Input Low Voltage Range Full IV 0.0 0.5 V

POWER SUPPLY

Supply Voltages

AVCC Full II 4.75 5.0 5.25 V
DVCC Full IV 3.0 3.3 5.25 V

Supply Current

I

(AVCC = 5.0 V) Full II 145 182 mA

AVCC

I

(DVCC = 3.3 V) Full II 15 20 mA

DVCC

POWER CONSUMPTION

NOTES

1

Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.

2

Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.

3

Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.

4

Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.

5

A_SEL and B_SEL should be tied directly to ground or AVCC.

6

Maximum power consumption is computed as maximum current at nominal supplies.

Specifications subject to change without notice.

6

Full II 775 976 mW

DIGITAL SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; T

= –40C, T

MIN

= +85C unless otherwise noted.)

MAX

Test AD6600AST

Parameter Temp Level Min Typ Max Unit

LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)

1

Logic Compatibility CMOS
Logic “1” Voltage (DVCC = 3.3 V) Full II 2.8 DVCC – 0.2 V
Logic “0” Voltage (DVCC = 3.3 V) Full II 0.2 0.5 V
Logic “1” Voltage (DVCC = 5.0 V) Full IV 4.0 DVCC – 0.35 V
Logic “0” Voltage (DVCC = 5.0 V) Full IV 0.35 0.5 V
Output Coding (D10–D0) Two’s Complement

CLK2× OUTPUT

1, 2

Logic “1” Voltage (DVCC = 3.3 V) Full II 2.8 DVCC – 0.2 V
Logic “0” Voltage (DVCC = 3.3 V) Full II 0.2 0.5 V
Logic “1” Voltage (DVCC = 5.0 V) Full IV 4.0 DVCC – 0.3 V
Logic “0” Voltage (DVCC = 5.0 V) Full IV 0.35 0.5 V

NOTES

1

Digital output load is one LCX gate.

2

CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz.

Specifications subject to change without notice.

–2–

REV. 0

AD6600

TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS; T

Parameter Name Temp Level Min Typ Max Unit

A/D CONVERTER

Conversion Rate f
Maximum Conversion Rate Full II 20 MSPS
Minimum Conversion Rate Full IV 6 MSPS
Aperture Uncertainty t

ENCODE INPUTS (ENC, ENC)

Period t
Pulsewidth High
Pulsewidth Low

3

4

2× CLOCK OUTPUT (CLK2×)

Output Frequency 2× f
Output Period

CLK2× Pulsewidth Low
Output Risetime
Output Falltime

6

6

7

7

OUTPUT RISE/FALL TIMES

2

t
t

5

t
t
t

8

Output Risetime (D10:D0, RSSI2:0) Full V 8 ns
Output Falltime (D10:D0, RSSI2:0) Full V 8.4 ns
Output Risetime (AB_OUT) Full V 6 ns
Output Falltime (AB_OUT) Full V 6.2 ns

NOTES

1

See AD6600 Timing Diagrams.

2

All switching specifications tested by driving ENC and ENC differentially.

3

Several timing specifications are a function of Encode high time, t
should be kept as close to 50% as possible.

4

Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.

5

The 2× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2 × are
referenced to 2.0 V crossing.

6

This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.

7

Output rise time is measured from 20% point to 80% point of total CLK2× voltage swing; output fall time is measured from 80% point to 20% point of total CLK2×
voltage swing.

8

Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage
swing. All outputs specified with 10 pF load.

Specifications subject to change without notice.

MIN

ENC

j

ENC

ENCH

ENCL

CLK2×_1
CLK2×_2
CLK2×L

= –40C, T

= +85C unless otherwise noted.)

MAX

Test AD6600AST

25°C V 0.3 ps rms

Full II 50 ns
Full IV 20 ns
Full IV 20 ns

Full V t
Full V t
Full V t
Full V 3 ns
Full V 2.6 ns

; these specifications are shown in the data tables and timing diagrams. Encode duty cycle

ENCH

1

1/(t

) MSPS

ENC

ENC

ENCL

ENCH

/2 ns

ENCH

MSPS
ns
ns

REV. 0 –3–

AD6600–SPECIFICATIONS

TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; T

Parameter Name Temp Level Min Typ Max Unit

ENCODE/CLK2×

Encode Rising to CLK2× Falling
Encode Rising to CLK2× Rising

3

4

t

CF

t

CR

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 25.7 27.2 28.7 ns
@ Encode = 20 MSPS, 50% Duty Cycle Full IV 19.0 20.5 22.0 ns

CLK2×/DATA (D10:0, RSSI2:0)

CLK2× to DATA Rising Low Delay
CLK2× to DATA Hold Time
CLK2× to DATA Falling Low

CLK2× to DATA Setup Time

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 16.5 23.0 ns
@ Encode = 20 MSPS, 50% Duty Cycle

CLK2×/AB_OUT

5

CLK2× to AB_OUT Rising Low Delay
CLK2× to AB_OUT Hold Time
CLK2× to AB_OUT Falling Low Delay

CLK2× to AB_OUT Setup Time

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 12.5 19.5 ns
@ Encode = 20 MSPS, 50% Duty Cycle

ENCODE/DATA (D10:0, RSSI2:0)

ENCODE to DATA Rising Low Delay
ENCODE to DATA Hold Time

5

3

3

3, 6

4

3

3

3, 6

4

4

4

t

2×_DRL

t

H_D2×

t

2×_DFL

t

S_D2×

6

t

2×_ARL

t

H_A2×

t

2×_AFL

t

S_A2×

6

t

EN_DRL

t

H_DEN

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 28.7 33.7 ns

@ Encode = 20 MSPS, 50% Duty Cycle Full IV 22.0 27.0 ns
ENCODE to DATA Falling Low Delay
ENCODE to DATA Delay (Setup)

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 26.2 34.2 ns

@ Encode = 20 MSPS, 50% Duty Cycle

4

4

t

EN_DFL

t

S_DEN

6

ENCODE/AB_OUT

ENCODE to AB_OUT Rising Low Delay4t
ENCODE to AB_OUT Delay (Hold)

4

EN_ARL

t

H_AEN

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 32.7 38.2 ns

@ Encode = 20 MSPS, 50% Duty Cycle Full IV 26.0 31.5 ns
ENCODE to AB_OUT Falling Low Delay
ENCODE to AB_OUT Delay (Setup)

@ Encode = 13 MSPS, 50% Duty Cycle Full IV 22.2 30.7 ns

@ Encode = 20 MSPS, 50% Duty Cycle

NOTES

1

See AD6600 Timing Diagrams.

2

All switching specifications tested by driving ENC and ENC differentially.

3

This specification IS NOT a function of Encode period and duty cycle.

4

This specification IS a function of Encode period and duty cycle.

5

CLK2× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.

6

For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40°C to +85°C.

Specifications subject to change without notice.

4

t

4

EN_AFL

t

S_AEN

6

= –40C, T

MIN

Test AD6600AST

Full IV 6.5 8.0 9.5 ns
Full IV tCF + (t

Full IV 3.0 6.5 ns
Full IV 3.0 6.5 ns
25°C IV 10.0 15.0 20.0 ns
Full IV 11.0 15.5 22.0 ns
Full IV t

25°C IV 5.0 10.0 ns
Full IV 3.0 9.5 ns

Full IV 7.0 11.0 ns
Full IV 7.0 11.0 ns
25°C IV 12.0 18.0 23.0 ns
Full IV 10.7 19.0 26.0 ns
Full IV t

25°C IV 2.0 7.0 ns
Full IV –1.0 6.0 ns

Full IV tCR + t
Full IV t

Full IV tCR + t
Full IV t

25°C IV 8.0 14.5 ns
Full IV 6.0 14.0 ns

Full IV tCR + t
Full IV t

Full IV tCR + t
Full IV t

25°C IV 5.0 11.5 ns
Full IV 2.0 10.5 ns

1, 2

= +85C unless otherwise noted.)

MAX

ENCH

– t

ENCH

– t

ENCH

EN_DRL

– t

ENC

EN_ARL

– t

ENC

2×_DFL

2×_AFL

2×_DRL

2×_DFL

EN_DFL

2×_ARL

2×_AFL

EN_AFL

)/2 ns

ns

ns

ns
ns

ns
ns

ns
ns

ns
ns

–4–

REV. 0

AD6600

(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; T

AC SPECIFICATIONS

otherwise noted.)

Test AD6600AST

Parameter Temp Level Min Typ Max Unit

ANALOG INPUTS

Analog Input 3 dB Bandwidth

1

2

Full V 450 MHz

Differential Analog Input Voltage Range

70 MHz Full V 2.45 V p-p
150 MHz Full V 2.57 V p-p
200 MHz Full V 2.62 V p-p
250 MHz Full V 2.86 V p-p

Differential Analog Input Impedance

3

70 MHz 25°C V 197–j24 Ω
150 MHz 25°C V 188–j48 Ω
200 MHz 25°C V 175–j57 Ω
250 MHz 25°C V 161–j67 Ω
300 MHz 25°C V 151–j73 Ω
350 MHz 25°C V 140–j80 Ω
400 MHz 25°C V 141–j75 Ω
450 MHz 25°C V 173–j107 Ω

Full-Scale Input Power

70 MHz Full V 5.8 dBm
150 MHz Full V 6.3 dBm
200 MHz Full V 6.7 dBm
250 MHz Full V 7.7 dBm

Full-Scale Gain Tolerance

70 MHz–250 MHz Full V ± 0.5 dB
200 MHz

5

4

25°C I –1.0 ±0.1 +1.0 dB

Gain Error

AIN = 200 MHz

@ –76 dBFS 25°C I –1.5 +1.5 dB

Gain Matching (Input A:B)

70 MHz–250 MHz Full V ± 0.1 dB
200 MHz Full II –0.5 ±0.05 +0.5 dB

Range-to-Range Gain Tolerance

70 MHz–250 MHz Full V ± 0.1 dB

Range-to-Range Phase Tolerance

70 MHz Full V 0.2 Degree
250 MHz Full V 0.5 Degree

Channel Isolation

70 MHz–250 MHz Full IV 45 50 dB

7

Noise

6

Minimum Attenuation Level Full V 34 µV rms
Maximum Attenuation Level Full V 869 µV rms

Attenuator 3OIP
Signal-to-Noise Ratio (SNR)

8

9, 10, 11

Full V +33 dBm

AIN = 70 MHz

@ –1 dBFS 25°CIV5559 dB
@ –6 dBFS 25°C V 54.5 dB
@ –10 dBFS 25°CIV4549 dB
@ –12 dBFS to –42 dBFS 25°C IV 41 48 ±6dB
@ –54 dBFS 25°CIV3134 dB

AIN = 150 MHz

@ –1 dBFS 25°CIV5558 dB
@ –6 dBFS 25°CV 54 dB
@ –10 dBFS 25°CIV4549 dB
@ –12 dBFS to –42 dBFS 25°C IV 41 48 ±6dB
@ –54 dBFS 25°CIV3134 dB

= –40C, T

MIN

= +85C unless

MAX

REV. 0 –5–

AD6600–SPECIFICATIONS

AC SPECIFICATIONS (continued)

Test AD6600AST

Parameter Temp Level Min Typ Max Unit

ANALOG INPUTS (Continued)

Signal-to-Noise Ratio (Continued)

AIN = 200 MHz

@ –1 dBFS 25°C I 55 57.5 dB
@ –6 dBFS 25°C V 53.5 dB
@ –10 dBFS 25°C I 45 49 dB
@ –12 dBFS to –42 dBFS 25°C I 40.5 48 ± 6dB
@ –54 dBFS 25°C I 31 34 dB

AIN = 250 MHz

@ –1 dBFS 25°CIV5256 dB
@ –6 dBFS 25°C V 53.5 dB
@ –10 dBFS 25°CIV4349 dB
@ –12 dBFS to –42 dBFS 25°C IV 40 48 ±6dB
@ –54 dBFS 25°CIV3034 dB

SECOND HARMONIC

AIN = 70 MHz

@ –1 dBFS Full V 69 dBc

@ –6 dBFS Full V 68 dBc

@ –12 dBFS to –42 dBFS Full V 68 ±6 dBc
AIN = 150 MHz

@ –1 dBFS Full V 60 dBc

@ –6 dBFS Full V 59 dBc

@ –12 dBFS to –42 dBFS Full V 67 ±6 dBc
AIN = 200 MHz

@ –1 dBFS 25°C I 50 60 dBc

@ –6 dBFS Full V 56 dBc

@ –10 dBFS 25°C I 48 55 dBc

@ –12 dBFS to –42 dBFS Full V 65 ±6 dBc

@ –54 dBFS Full V 50 dBc
AIN = 250 MHz

@ –1 dBFS Full V 54 dBc

@ –6 dBFS Full V 62 dBc

@ –12 dBFS to –42 dBFS Full V 65 ±6 dBc

THIRD HARMONIC

AIN = 70 MHz

@ –1 dBFS Full V 77 dBc

@ –6 dBFS Full V 76 dBc

@ –12 dBFS to –42 dBFS Full V 67 ±6 dBc
AIN = 150 MHz

@ –1 dBFS Full V 65 dBc

@ –6 dBFS Full V 70 dBc

@ –12 dBFS to –42 dBFS Full V 66 ±6 dBc
AIN = 200 MHz

@ –1 dBFS 25°C I 50 55 dBc

@ –6 dBFS Full V 58 dBc

@ –10 dBFS 25°C I 55 66 dBc

@ –12 dBFS to –42 dBFS Full V 65 ±6 dBc

@ –54 dBFS Full V 62 dBc
AIN = 250 MHz

@ –1 dBFS Full V 50 dBc

@ –6 dBFS Full V 56 dBc

@ –12 dBFS to –42 dBFS Full V 65 ±6 dBc
AIN = 70 MHz–250 MHz

@ –75 dBFS Full IV 28 35 dBc

9, 10, 11

9, 10, 11

–6–

REV. 0

AD6600

AC SPECIFICATIONS (continued)

Test AD6600AST

Parameter Temp Level Min Typ Max Unit

WORST OTHER SPUR (4th or Higher)

AIN = 70 MHz

@ –1 dBFS Full V 74.5 dBc
@ –6 dBFS Full V 71 dBc
@ –12 dBFS to –42 dBFS Full V 68 ±6 dBc

AIN = 150 MHz

@ –1 dBFS Full V 67 dBc
@ –6 dBFS Full V 65 dBc
@ –12 dBFS to –42 dBFS Full V 67 ±6 dBc

AIN = 200 MHz

@ –1 dBFS 25°C I 60 67 dBc
@ –6 dBFS Full V 66 dBc
@ –10 dBFS 25°C I 55 66 dBc
@ –12 dBFS to –42 dBFS Full V 65 ±6 dBc

AIN = 250 MHz

@ –1 dBFS Full V 66.5 dBc
@ –6 dBFS Full V 65 dBc
@ –12 dBFS to –42 dBFS Full V 65 ±6 dBc

NOTES

1

AIN, AIN/BIN, BIN: The AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70 MHz–250 MHz specified operating range.

Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results.

2

Analog Input 3 dB Bandwidth is determined by internal track-and-hold. The front-end attenuators have a bandwidth of 1 GHz.

3

Measured real and imaginary values using Network Analyzer.

4

Full-scale gain tolerance is the typical variation in gain at a given IF input frequency. The nominal value for full-scale input power is a function of frequency as

shown in previous specification.

5

Full-scale gain tolerance measured at 200 MHz analog input referenced to 6.7 dBm nominal full-scale input power. For the gain measurement test, the input signal

level is set to –6 dBFS. Tuning port bandwidth is set to 50 MHz.

6

Main channel set to full-scale input power. Diversity channel swept from –20 dBFS to –90 dBFS.

7

Measurement includes thermal and quantization noise at 70 MHz analog input. Tuning port bandwidth is set to 50 MHz.

8

Test tones at 160.05 MHz and 170.05 MHz.

9

Measurements at –1 dFBS, –6 dBFS, and –10 dBFS are in highest attenuation mode, RSSI = 101.

10

Each gain-range is checked at ~3 dB from RSSI trip point (not in hysteresis); nominally –16 dBFS (RSSI = 100), –22 dBFS (RSSI = 011), –28 dBFS (RSSI = 010),

–35 dBFS (RSSI = 001).

11

Measurement at –54 dBFS is in the lowest attenuation mode, RSSI = 000.

Specifications subject to change without notice.

REV. 0 –7–

AD6600

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

Parameter Min Max Unit

ELECTRICAL

AVCC Voltage 0 7 V
DVCC Voltage 0 7 V
Analog Input Voltage
Analog Input Current
Digital Input Voltage
Output Current
Resonant Port Voltage

ENVIRONMENTAL

2

2

3

4

5

6

0 AVCC V

25 mA

0 AVCC V

4mA

0 AVCC V

Operating Temperature Range

(Ambient) –40 +85 °C
Maximum Junction Temperature 150 °C
Lead Temperature (Soldering, 10 sec) 300 °C
Storage Temperature Range (Ambient) –65 +150 °C

NOTES

1

Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

2

Pins AIN, AIN, BIN, BIN.

3

Pins ENC, ENC, A_SEL, B_SEL.

4

Pins D10:0, RSSI2:0, AB_OUT, CLK2×.

5

Pins FLT, FLT.

6

Typical thermal impedance (44-lead LQFP); θJC = 16°C/W, θJA = 55°C/W.

EXPLANATION OF TEST LEVELS
Test Level

I. 100% Production Tested.
II. 100% Production Tested at 25°C and guaranteed by design

and characterization at temperature extremes.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD6600AST –40°C to 44-Terminal LQFP ST-44

+85°C (Low-Profile Quad
(Ambient) Plastic Flatpack)

AD6600ST/PCB Evaluation Board

with AD6600AST

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6600 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom­mended to avoid performance degradation or loss of functionality.

–8–

REV. 0