ANALOG DEVICES AD660 Service Manual
Monolithic 16-Bit
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FEATURES
Complete 16-bit digital-to-analog function
On-chip output amplifier
On-chip buried Zener voltage reference
±1 LSB integral linearity
15-bit monotonic over temperature
Microprocessor compatible
Serial or byte input
Double-buffered latches
Fast (40 ns) write pulse
Asynchronous clear (to 0 V) function
Serial output pin facilitates daisy-chaining
Unipolar or bipolar output
Low glitch: 15 nV-s
Low THD + N: 0.009%
GENERAL DESCRIPTION
The AD660 DACPORT® is a complete 16-bit monolithic digitalto-analog converter with an on-board voltage reference, doublebuffered latches, and an output amplifier. It is manufactured on
the Analog Devices, Inc., BiMOS II process. This process allows
the fabrication of low power CMOS logic functions on the same
chip as high precision bipolar linear circuitry.
The AD660 architecture ensures 15-bit monotonicity over time
and temperature. Integral and differential nonlinearity is maintained at ±0.003% maximum. The on-chip output amplifier
provides a voltage output settling time of 10 μs to within ½ LSB for
a full-scale step.
The AD660 has an extremely flexible digital interface. Data can
be loaded into the AD660 in serial mode or as two 8-bit bytes.
This is made possible by two digital input pins that have dual
functions. The serial mode input format is pin selectable to be
MSB or LSB first. The serial output pin allows the user to daisychain several AD660 devices by shifting the data through the
input latch into the next DAC, thus minimizing the number of
control lines required to SIN,
format is also flexible in that the high byte or low byte data can
be loaded first. The double buffered latch structure eliminates
data skew errors and provides for simultaneous updating of DACs
in a multiDAC system.
The AD660 is available in five grades. AN and BN versions are
specified from −40°C to +85°C and are packaged in a 24-lead
300 mil plastic DIP. AR and BR versions are also specified from
−40°C to +85°C and are packaged in a 24-lead SOIC. The SQ
version is packaged in a 24-lead 300 mil CERDIP package and
CS
and LDAC. The byte mode input
Serial/Byte DACPORT
AD660
FUNCTIONAL BLOCK DIAGRAM
LOGIC
10kΩ
10V REF
24
REF OUT
DB0/
DB8/
DB1/DB9/
SIN
DATADIR
CS
121415
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
1 2 3 4
–V
EE
11
+V
Figure 1.
DB15
CC
DB7/
5
AD660
10kΩ
10.05kΩ
+V
LL
DGND
13
22
21
20
S
OUT
SPAN/
BIPOL AR
OFFSET
V
OUT
AGND
LBE/
CLEAR SELECT
16
HBE
SER
CLR
LDAC
REF IN
17
18
19
23
CONTRO L
is also available compliant to MIL-STD-883. Refer to the
AD660SQ/883B military data sheet for specifications and test
conditions.
PRODUCT HIGHLIGHTS
1. The AD660 is a complete 16-bit DAC, with a voltage
reference, double-buffered latches, and an output amplifier
on a single chip.
2. The internal buried Zener reference is laser trimmed to
10.000 V with a ±0.1% maximum error and a temperature
drift performance of ±15 ppm/°C. The reference is available
for external applications.
3. The output range of the AD660 is pin programmable and
can be set to provide a unipolar output range of 0 V to 10 V
or a bipolar output range of −10 V to +10 V. No external
components are required.
4. The AD660 is both dc and ac specified. DC specifications
include ±1 LSB INL and ±1 LSB DNL errors. AC specifications include 0.009% THD + N and 83 dB SNR.
5. The double-buffered latches on the AD660 eliminate data
skew errors and allow simultaneous updating of DACs in
multiDAC applications.
6. The clear function can asynchronously set the output
to 0 V regardless of whether the DAC is in unipolar or
bipolar mode.
7. The output amplifier settles within 10 μs to ±½ LSB for a
full-scale step and within 2.5 μs for a 1 LSB step over temperature. The output glitch is typically 15 nV-s when a full-scale
step is loaded.
01813-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.
AD660
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TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Performance Characteristics ................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Terminology ...................................................................................... 9
Theory of Operation ...................................................................... 10
Analog Circuit Connections ..................................................... 10
Unipolar Configuration ............................................................. 10
Bipolar Configuration ................................................................ 11
Internal/External Reference Use .............................................. 11
Output Settling and Glitch ........................................................ 13
Digital Circuit Details ................................................................ 14
Microprocessor Interface ............................................................... 15
AD660 to MC68HC11 (SPI Bus) Interface ............................. 15
AD660 to MICROWIRE Interface ........................................... 15
AD660 to ADSP-210x Family Interface .................................. 15
AD660 to Z80 Interface ............................................................. 16
Noise ............................................................................................ 16
Board Layout ................................................................................... 17
Supply Decoupling ..................................................................... 17
Grounding ................................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/08—Rev. A to Rev. B
Updated Format .................................................................. Universal
Updated Pin Name MSB/
Updated Pin Name
Throughout ....................................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Endnote 3 in Table 1 .................................................... 4
Changes to Figure 2 .......................................................................... 5
Changes to Figure 3 and Figure 5 ................................................... 6
LSB
to DATADIR Throughout ........... 1
UNI
/BIP CLEAR to CLEAR SELECT
Changes to Table 4 ............................................................................. 7
Added Pin Configuration and Function Descriptions Section ... 8
Changes to Internal/External Reference Use Section ................ 11
Changes to Figure 12 ...................................................................... 12
Changes to Figure 13, Figure 14, Figure 15, and Figure 16....... 13
Changes to Figure 17 and Figure 18............................................. 15
Changes to Figure 19 ...................................................................... 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
Rev. B | Page 2 of 20
AD660
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SPECIFICATIONS
TA = 25°C, +VCC = 15 V, −VEE = −15 V, +VLL = 5 V unless otherwise noted.
Table 1.
AD660AN/AR/SQ AD660BN/BR
Parameter
RESOLUTION 16 16 Bits
DIGITAL INPUTS (T
VIH (Logic 1) 2.0 5.5 2.0 5.5 V
VIL (Logic 0) 0 0.8 0 0.8 V
IIH (VIH = 5.5 V) −10 +10 −10 +10 μA
IIL (VIL = 0 V) −10 +10 −10 +10 μA
TRANSFER FUNCTION CHARACTERISTICS1
Integral Nonlinearity
Bipolar Operation −2 +2 −1 +1 LSB
T
to T
MIN
Unipolar Operation −2 +2 −1 +1.5 LSB
T
to T
MIN
Differential Nonlinearity −2 +2 −1 +1 LSB
T
to T
MIN
MAX
Monotonicity Over Temperature 14 15 Bits
Gain Error
Gain Drift (T
DAC Gain Error4 −0.05 +0.05 −0.05 +0.05 % of FSR
DAC Gain Drift4 10 10 ppm/°C
Unipolar Offset −2.5 +2.5 −2.5 +2.5 mV
Unipolar Offset Drift (T
Bipolar Zero Error −7.5 +7.5 −7.5 +7.5 mV
Bipolar Zero Error Drift (T
REFERENCE INPUT
Input Resistance 7 10 13 7 10 13 kΩ
Bipolar Offset Input Resistance 7 10 13 7 10 13 kΩ
REFERENCE OUTPUT
Voltage 9.99 10.00 10.01 9.99 10.00 10.01 V
Drift 25 15 ppm/°C
External Current5 2 4 2 4 mA
Capacitive Load 1000 1000 pF
Short-Circuit Current 25 25 mA
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Current 5 5 mA
Capacitive Load 1000 1000 pF
Short-Circuit Current 25 25 mA
2, 3
Unipolar Configuration 0 +10 0 +10 V
Bipolar Configuration −10 +10 −10 +10 V
to T
MIN
−4 +4 −2 +2 LSB
MAX
−4 +4 −2 +2 LSB
MAX
−4 +4 −2 +2 LSB
to T
MIN
)
MAX
−0.1 +0.1 −0.1 +0.1 % of FSR
) 25 15 ppm/°C
MAX
to T
MIN
) 3 3 ppm/°C
MAX
to T
MIN
) 5 5 ppm/°C
MAX
Unit Min Typ Max Min Typ Max
Rev. B | Page 3 of 20
AD660
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AD660AN/AR/SQ AD660BN/BR
Parameter
POWER SUPPLIES
Voltage
6
+V
+13.5 +16.5 +13.5 +16.5 V
CC
6
−V
−13.5 −16.5 −13.5 −16.5 V
EE
+VLL +4.5 +5.5 +4.5 +5.5 V
Current (No Load)
ICC +12 +18 +12 +18 mA
IEE −12 −18 −12 −18 mA
ILL
@ VIH = 5 V, VIL = 0 V 0.3 2 0.3 2 mA
@ VIH = 2.4 V, VIL = 0.4 V 3 7.5 3 7.5 mA
Power Supply Sensitivity 1 2 1 2 ppm/%
Power Dissipation (Static, No Load) 365 625 365 625 mW
TEMPERATURE RANGE
Specified Performance (A, B) −40 +85 −40 +85 °C
Specified Performance (S) −55 +125 °C
1
For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for full-scale range
and is 10 V in a unipolar mode and 20 V in bipolar mode.
2
Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660
can be used with a precision external reference such as the AD587, AD586, or AD688.
3
Gain error is measured with fixed 50 Ω resistors as shown in the Theory of Operation section. Eliminating these resistors increases the gain error by 0.25% of FSR
(unipolar mode) or 0.50% of FSR (bipolar mode).
4
DAC gain error and drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference.
5
External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660.
6
Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference Use
section.
Unit Min Typ Max Min Typ Max
AC PERFORMANCE CHARACTERISTICS
With the exception of total harmonic distortion + noise (THD + N) and signal-to-noise (SNR) ratio, these characteristics are included for
design guidance only and are not subject to test. THD + N and SNR are 100% tested.
T
≤ TA ≤ T
MIN
Table 2.
Parameter Limit Unit Test Conditions/Comments
OUTPUT SETTLING TIME 13 μs max 20 V step, TA = 25°C
(Time to ±0.0008% FS 8 μs typ 20 V step, TA = 25°C
with 2 kΩ, 1000 pF Load) 10 μs typ 20 V step, T
6 μs typ 10 V step, TA = 25°C
8 μs typ 10 V step, T
2.5 μs typ 1 LSB step, T
TOTAL HARMONIC DISTORTION + NOISE
A, B, S Grade 0.009 % max 0 dB, 990.5 Hz, sample rate = 96 kHz, TA = 25°C
A, B, S Grade 0.056 % max −20 dB, 990.5 Hz, sample rate = 96 kHz, TA = 25°C
A, B, S Grade 5.6 % max −60 dB, 990.5 Hz, sample rate = 96 kHz, TA = 25°C
SIGNAL-TO-NOISE RATIO 83 dB min TA = 25°C
DIGITAL-TO-ANALOG GLITCH IMPULSE 15 nV-s typ DAC alternately loaded with 0x8000 and 0x7FFF
DIGITAL FEEDTHROUGH 2 nV-s typ
OUTPUT NOISE VOLTAGE
Density (1 kHz to 1 MHz) 120 nV/√Hz typ Measured at V
REFERENCE NOISE 125
, +VCC = 15 V, −VEE = −15 V, +VLL = 5 V except where noted.
MAX
nV/√Hz typ Measured at REF OUT
≤ TA ≤ T
MIN
≤ TA ≤ T
MIN
MIN
≤ TA ≤ T
MAX
MAX
MAX
DAC alternately loaded with 0x0000 and 0xFFFF, CS
, 20 V span, excludes reference
OUT
high
Rev. B | Page 4 of 20
AD660
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TIMING CHARACTERISTICS
+VCC = 15 V, −VEE = −15 V, +VLL = 5 V, V
Table 3.
Parameter Limit at TA = 25°C Limit at TA = −55°C to +125°C Unit
BYTE LOAD (see Figure 2)
tCS
tDS 40 50 ns min
tDH 0 10 ns min
t
40 50 ns min
BES
t
0 10 ns min
BEH
tLH 80 100 ns min
tLW 40 50 ns min
SERIAL LOAD (see Figure 3)
t
80 100 ns min
CLK
t
30 50 ns min
LOW
t
30 50 ns min
HIGH
tSS 0 10 ns min
tDS 40 50 ns min
tDH 0 10 ns min
tSH 0 10 ns min
tLH 80 100 ns min
tLW 40 50 ns min
ASYNCHRONOUS CLEAR TO BIPOLAR
OR UNIPOLAR ZERO (see Figure 4)
t
CLR
t
80 110 ns min
SET
t
0 10 ns min
HOLD
SERIAL OUT (see Figure 5)
t
50 100 ns min
PROP
tDS 50 80 ns min
= 2.4 V, V
HIGH
= 0.4 V.
LOW
40 50 ns min
80 110 ns min
DB0 TO DB7
t
HBE OR LBE
CS
LDAC
DS
t
BES
t
CS
Figure 2. AD660 Byte Load Timing
t
DH
t
BEH
t
LH
Rev. B | Page 5 of 20
t
LW
01813-002
AD660
C
(
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DB0 VALID 1
t
SER
DB1
(DATADIR)
LDAC
CS
SS
t
DS
t
DH
1 = MSB FIRST, 0 = LSB FIRST
t
LOW
t
HIGH
t
CLK
VAL I D 1 6
t
SH
t
LH
t
LW
01813-003
Figure 3. AD660 Serial Load Timing
t
CLR
t
t
SET
HOLD
01813-004
LBE
LR
1 = BIPOLAR 0, 0 = UNIPOLAR 0
Figure 4. Asynchronous Clear to Bipolar or Unipolar Zero
DB0
SER
DB1
DATADIR)
CS
S
OUT
VALID 16 VALID 17
t
DS
t
PROP
VAL I D S
OUT
1
01813-005
Figure 5. Serial Out Timing
Rev. B | Page 6 of 20
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