Analog Devices AD654 b Datasheet

Low Cost Monolithic

321

58 7 6

AD654

4

DRIVER OSC

F

OUT

LOGIC

COMMON

R

T

+V

IN

+V

S

C

T

C

T

–V

S

a

FEATURES
Low Cost
Single or Dual Supply, 5 V to 36 V, ⴞ5 V to ⴞ18 V
Full-Scale Frequency Up to 500 kHz
Minimum Number of External Components Needed
Versatile Input Amplifier

Positive or Negative Voltage Modes
Negative Current Mode

High Input Impedance, Low Drift
Low Power: 2.0 mA Quiescent Current
Low Offset: 1 mV

PRODUCT DESCRIPTION

The AD654 is a monolithic V/F converter consisting of an input
amplifier, a precision oscillator system, and a high current output
stage. A single RC network is all that is required to set up any
full scale (FS) frequency up to 500 kHz and any FS input voltage

up to ±30 V. Linearity error is only 0.03% for a 250 kHz FS,

and operation is guaranteed over an 80 dB dynamic range. The
overall temperature coefficient (excluding the effects of external
components) is typically
a single supply of 5 V to 36 V and consumes only 2.0 mA quies­cent current.

The low drift (4 µV/°C typ) input amplifier allows operation

directly from small signals such as thermocouples or strain gauges

while offering a high (250 MΩ) input resistance. Unlike most

V/F converters, the AD654 provides a square-wave output, and
can drive up to 12 TTL loads, optocouplers, long cables, or
similar loads.

PRODUCT HIGHLIGHTS

1. Packaged in both an 8-lead mini-DIP and an 8-lead SOIC
package, the AD654 is a complete V/F converter requiring
only an RC timing network to set the desired full-scale fre­quency and a selectable pull-up resistor for the open-collector
output stage. Any full scale input voltage range from 100 mV
to 10 volts (or greater, depending on +V
dated by proper selection of the timing resistor. The full­scale frequency is then set by the timing capacitor from the
simple relationship, f = V/10 RC.

±50 ppm/°C. The AD654 operates from

) can be accommo-

S

Voltage-to-Frequency Converter

AD654

FUNCTIONAL BLOCK DIAGRAM

2. A minimum number of low cost external components are
necessary. A single RC network is all that is required to set
up any full scale frequency up to 500 kHz and any full-scale

input voltage up to ±30 V.

3. Plastic packaging allows low cost implementation of the
standard VFC applications: A/D conversion, isolated signal
transmission, F/V conversion, phase-locked loops, and tuning
switched-capacitor filters.

4. Power supply requirements are minimal; only 2.0 mA of
quiescent current is drawn from the single positive supply
from 4.5 volts to 36 volts. In this mode, positive inputs can
vary from 0 volts (ground) to (+V
can easily be connected for below ground operation.

5. The versatile open-collector output stage can sink more than
10 mA with a saturation voltage less than 0.4 volts. The Logic
Common terminal can be connected to any level between
ground (or –V

) and 4 volts below +VS. This allows easy

S

direct interface to any logic family with either positive or
negative logic levels.

–4) volts. Negative inputs

S

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(TA = +25ⴗC and VS (total) = 5 V to 16.5 V, unless otherwise noted. All testing done

AD654–SPECIFICATIONS

@ VS = +5 V.)

AD654JN/JR

Model Min Typ Max Units

CURRENT-TO-FREQUENCY CONVERTER

Frequency Range 0 500 kHz
Nonlinearity

f

MAX

f

MAX

1

= 250 kHz 0.06 0.1 %
= 500 kHz 0.20 0.4 %

Full-Scale Calibration Error

C = 390 pF, I
vs. Supply (f

= +4.75 V to +5.25 V 0.20 0.40 %/V

V

S

= +5.25 V to +16.5 V 0.05 0.10 %/V

V

S

= 1.000 mA –10 +10 %

IN

≤ 250 kHz)

MAX

vs. Temp (0°C to +70°C) 50 ppm/°C

ANALOG INPUT AMPLIFIER

(Voltage-to-Current Converter)
Voltage Input Range

Single Supply 0 (+V
Dual Supply –V

S

– 4) V

S

(+VS – 4) V

Input Bias Current

(Either Input) 30 50 nA

Input Offset Current 5 nA

Input Resistance (Noninverting) 250 MΩ

Input Offset Voltage 0.5 1.0 mV

vs. Supply

= +4.75 V to +5.25 V 0.1 0.25 mV/V

V

S

= +5.25 V to +16.5 V 0.03 0.1 mV/V

V

S

vs. Temp (0°C to +70°C) 4 µV/°C

OUTPUT INTERFACE (Open Collector Output)

(Symmetrical Square Wave)
Output Sink Current in Logic “0”

V

= 0.4 V max, +25°C 10 20 mA

OUT

= 0.4 V max, 0°C to +70°C510 mA

V

OUT

2

Output Leakage Current in Logic “1” 10 100 nA

0°C to +70°C 50 500 nA

Logic Common Level Range –V
Rise/Fall Times (C

= 1 mA 0.2 µs

I

IN

I

= 1 µA1µs

IN

= 0.01 µF)

T

S

(+VS – 4) V

POWER SUPPLY

Voltage, Rated Performance 4.5 16.5 V
Voltage, Operating Range

Single Supply 4.5 36 V

Dual Supply ±5 ±18 V

Quiescent Current

(Total) = 5 V 1.5 2.5 mA

V

S

VS (Total) = 30 V 2.0 3.0 mA

TEMPERATURE RANGE

Operating Range –40 +85 °C

NOTES

1

At f

= 250 kHz; R

MAX

1

At f

= 500 kHz; R

MAX

2

The sink current is the amount of current that can flow into Pin 1 of the AD654 while maintaining a maximum voltage of 0.4 V between Pin 1 and Logic Common.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Specifications subject to change without notice.

= 1 kΩ, C

T

= 1 kΩ, C

T

= 390 pF, IIN = 0 mA–1 mA.

T

= 200 pF, IIN = 0 mA–1 mA.

T

–2–

REV. B

AD654

ABSOLUTE MAXIMUM RATING

Total Supply Voltage +VS to –VS . . . . . . . . . . . . . . . . . . . 36 V

Maximum Input Voltage

(Pins 3, 4) to –V

Maximum Output Current

Instantaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Sustained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Logic Common to –V

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Model Temperature Range Package Description Package Option

AD654JN –40°C to +85°C 8-Lead Plastic DIP N-8
AD654JR –40°C to +85°C 8-Lead SOIC SO-8

. . . . . . . . . . . . . . . . . . . . –300 mV to +V

S

. . . . . . . . . . . . . . . –500 mV to (+VS –4)

S

ORDERING GUIDE

S

REV. B

–3–

AD654

(

)

OSC/

DRIVER

AD654

OPTIONAL

R

COMP

CR1

–V

S

(0V TO –15V)

R1 R2

+V

S

(+5V TO –VS +30)

C

T

+V

LOGIC

R

PU

F

OUT

F

OUT

=

V

IN

(10V) (R1 + R2) C

T

V

IN

CLAMP
DIODE

CIRCUIT OPERATION

The AD654’s block diagram appears in Figure 1. A versatile
operational amplifier serves as the input stage; its purpose is to
convert and scale the input voltage signal to a drive current in the
NPN follower. Optimum performance is achieved when, at the
full-scale input voltage, a 1 mA drive current is delivered to the
current-to-frequency converter (an astable multivibrator). The
drive current provides both the bias levels and the charging current
to the externally connected timing capacitor. This “adaptive” bias
scheme allows the oscillator to provide low nonlinearity over
the entire current input range of 100 nA to 2 mA. The square
wave oscillator output goes to the output driver which provides
a floating base drive to the NPN power transistor. This floating

V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT

The AD654 can accommodate a wide range of negative input
voltages with proper selection of the scaling resistor, as indicated
in Figure 2. This connection, unlike the buffered positive con­nection, is not high impedance because the signal source must
supply the 1 mA FS drive current. However, large negative volt­ages beyond the supply can be handled easily by modifying the
scaling resistors appropriately. If the input is a true current source,
R1 and R2 are not used. Again, diode CR1 prevents latch-up by
insuring Logic Common does not drop more than 500 mV below

. The clamp diode (MBD101) protects the AD654 input

–V

S

from “below –V

” inputs.

S

drive allows the logic interface to be referenced to a level other

OPTIONAL

IN

R

S

COMP

R1

R2

.

+V

S

(+5V TO –VS +30)

C

OSC/

DRIVER

AD654

–V

S

0V TO –15V

T

CR1

+V

LOGIC

F

OUT

R

PU

F

OUT

V

=

IN

(10V) (R1 + R2) C

T

Figure 2. V-F Connections for Negative Input Voltages or
Current

than –V

V

Figure 1. Standard V-F Connection for Positive Input
Voltages

OFFSET CALIBRATION

In theory, two adjustments calibrate a V/F: scale and offset. In

V/F CONNECTION FOR POSITIVE INPUT VOLTAGES

In the connection scheme of Figure 1, the input amplifier presents

a very high (250 MΩ) impedance to the input voltage, which

is converted into the proper drive current by the scaling resistors
at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA
full-scale current with enough trim range to accommodate the
AD654’s 10% FS error and the components’ tolerances. Full­scale currents other than 1 mA can be chosen, but linearity will
be reduced; 2 mA is the maximum allowable drive. The AD654’s
positive input voltage range spans from –V

(ground in sink supply

S

operation) to four volts below the positive supply. Power sup­ply rejection degrades as the input exceeds (+V

– 3.5 V) the output frequency goes to zero.

(+V

S

– 3.75 V) and at

S

As indicated by the scaling relationship in Figure 1, a 0.01 µF

timing capacitor will give a 10 kHz full-scale frequency, and

0.001 µF will give 100 kHz with a 1 mA drive current. Good V/F

linearity requires the use of a capacitor with low dielectric
absorption (DA), while the most stable operation over tempera­ture calls for a component having a small tempco. Polystyrene,
polypropylene, or Teflon* capacitors are preferred for tempco and
dielectric absorption; other types will degrade linearity. The
capacitor should be wired very close to the AD654. In Figure 1,
Schottky diode CR1 (MBD101) prevents logic common from
dropping more than 500 mV below –V
required if –V

*Teflon is a trademark of E.I. Du Pont de Nemours & Co.

S

. This diode is not

S

is equal to logic common.

practice, most applications find the AD654’s 1 mV max voltage
offset sufficiently low to forgo offset calibration. However, the
input amplifier’s 30 nA (typ) bias currents will generate an offset
due to the difference in dc sound resistance between the input
terminals. This offset can be substantial for large values of R
R1 + R2 and will vary as the bias currents drift over temperature.
Therefore, to maintain the AD654’s low offset, the application may
require balancing the dc source resistances at the inputs (Pins
3 and 4).

For positive inputs, this is accomplished by adding a compensation
resistor nominally equal to R

in series with the input as shown

T

in Figure 3a. This limits the offset to the product of the 30 nA
bias current and the mismatch between the source resistance R
and R
offset current flowing through the source resistance R

. A second, smaller offset arises from the inputs’ 5 nA

COMP

or R

T

COMP

For negative input voltage and current connections, the compensa­tion resistor is added at Pin 4 as shown in Figure 3b in lieu of
grounding the pin directly. For both positive and negative inputs,
the use of R

may lead to noise coupling at Pin 4 and should

COMP

therefore be bypassed for lowest noise operation.

(OPTIONAL)

C

V

IN

R

COMP

R1 R2

AD654

Figure 3a. Bias Current Compensation—Positive Inputs

–4–

REV. B

=

T

T

.