ANALOG DEVICES AD5666 Service Manual
Quad, 16-Bit DAC with 5 ppm/°C
V
/
V
FEATURES
Low power quad 16-bit DAC
14-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware
function to programmable code
CLR
LDAC
with
SDO daisy-chaining option
Rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
override function
LDAC
On-Chip Reference in 14-Lead TSSOP
AD5666
FUNCTIONAL BLOCK DIAGRAM
SCLK
SYNC
SDO
V
DD
AD5666
LDAC
INTERFACE
LOGIC
DIN
LDAC
CLR
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
POWER-ON
RESET
POR
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
Figure 1.
REFIN
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
REFOUT
1.25V/2.5V
REF
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
LOGIC
GND
V
OUT
V
OUT
V
OUT
V
OUT
A
B
C
D
05298-001
The AD5666 is a low power, quad, 16-bit, buffered voltageoutput DAC. The part operates from a single 2.7 V to 5.5 V
supply and is guaranteed monotonic by design.
The AD5666 has an on-chip reference with an internal gain of 2.
The AD5666-1 has a 1.25 V 5 ppm/°C reference, giving a full-scale
output of 2.5 V; the AD5666-2 has a 2.5 V 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-board reference is off at
power-up, allowing the use of an external reference. The internal
reference is turned on by writing to the DAC.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR pin low) or to midscale
(POR pin high) and remains powered up at this level until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 400 nA at 5 V
and provides software-selectable output loads while in power-down
mode for any or all DAC channels.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The outputs of all DACs can be updated simultaneously using
the
function, with the added functionality of user-select-
LDAC
able DAC channels to simultaneously update. There is also an
asynchronous
that clears all DACs to a software-selectable
CLR
code—0 V, midscale, or full scale.
The AD5666 utilizes a versatile 3-wire serial interface that operates
at clock rates of up to 50 MHz and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
on-chip precision output amplifier enables rail-to-rail output
swing.
PRODUCT HIGHLIGHTS
1. Quad, 16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 14-lead TSSOP.
4. Selectable power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD5666
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String ............................................................................. 20
Applicat ions ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
D/A Section ................................................................................. 20
Internal Reference ...................................................................... 20
Output Amplifier ........................................................................ 21
Serial Interface ............................................................................ 21
Input Shift Register .................................................................... 22
Interrupt .......................................................................... 22
SYNC
Daisy-Chaining ........................................................................... 23
Internal Reference Register ....................................................... 23
Power-On Reset .......................................................................... 23
Power-Down Modes .................................................................. 23
Clear Code Register ................................................................... 25
Function .......................................................................... 25
LDAC
Power Supply Bypassing and Grounding ................................ 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
6/10—Rev. C to Rev. D
Changes to Figure 19 and Figure 20 Captions ............................ 14
10/09—Rev. B to Rev. C
Changes to Table 7 .......................................................................... 21
2/09—Rev. A to Rev. B
Changes to Reference Current Parameter, Table 1 ....................... 3
Changes to Reference Current Parameter, Table 2 ....................... 5
Updated Outline Dimensions ....................................................... 27
11/05—Rev. 0 to Rev. A
Change to General Description ...................................................... 1
Change to Specifications .................................................................. 3
10/05—Revision 0: Initial Version
Rev. D | Page 2 of 28
AD5666
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V
Table 1.
A Grade
1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments
2
STATIC PERFORMANCE
Resolution 16 16 Bits
Relative Accuracy ±32 ±16 LSB See Figure 6
Differential Nonlinearity ±1 ±1 LSB
Zero-Code Error 1 9 1 9 mV All 0s loaded to DAC register (see Figure 13)
Zero-Code Error Drift ±2 ±2 µV/°C
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 12)
Gain Error ±1 ±1 % FSR
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
Offset Error ±1 ±9 ±1 ±9 mV
DC Power Supply Rejection
–80 –80 dB V
Ratio
DC Crosstalk
10 10 µV
(External Reference)
5 5 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
DC Crosstalk
25 25 µV
(Internal Reference)
10 10 µV/mA Due to load current change
OUTPUT CHARACTERISTICS
3
Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V
Power-Up Time 4 4 µs Coming out of power-down mode VDD = 5 V
REFERENCE INPUTS
Reference Input Voltage VDD V
Reference Current 20 55 20 55 µA V
Reference Input Range 0 VDD 0 VDD V
Reference Input Impedance 14.6 14.6 kΩ Per DAC channel
REFERENCE OUTPUT
Output Voltage 2.495 2.505 2.495 2.505 V At ambient
Reference TC
Reference Output
3
±5 ±10 ±5 ±10 ppm/°C
7.5 7.5 kΩ
Impedance
LOGIC INPUTS
3
Input Current ±3 ±3 µA All digital inputs
Input Low Voltage, V
Input High Voltage, V
0.8 0.8 V VDD = 5 V
INL
2 2 V VDD = 5 V
INH
Pin Capacitance 3 3 pF
= VDD. All specifications T
REFIN
1
B Grade
V
DD
to T
MIN
MAX
Guaranteed monotonic by design
(see Figure 7)
± 10%
DD
Due to full-scale output change,
= 2 kΩ to GND or VDD
R
L
Due to full-scale output change,
= 2 kΩ to GND or VDD
R
L
= VDD = 5.5 V
REF
, unless otherwise noted.
Rev. D | Page 3 of 28
AD5666
A Grade
1
B Grade
1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL 0.4 0.4 V I
Output High Voltage, VOH
High Impedance Leakage
−
V
DD
1
VDD −
1
±0.25 ±0.25 A
I
= 2 mA
SINK
SOURCE
= 2 mA
Current
High Impedance Output
2 2 pF
Capacitance
POWER REQUIREMENTS
VDD 4.5 5.5 4.5 5.5 V
All digital inputs at 0 or V
DD
DAC active, excludes load current
IDD (Normal Mode)4 V
= VDD and VIL = GND
IH
VDD = 4.5 V to 5.5 V 0.7 0.9 0.7 0.9 mA Internal reference off
VDD = 4.5 V to 5.5 V 1.3 1.6 1.3 1.6 mA Internal reference on
IDD (All Power-Down Modes)5
VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND
1
Temperature range is −40°C to +105°C, typical at 25°C.
2
Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All four DACs powered down.
,
Rev. D | Page 4 of 28
AD5666
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V
Table 2.
A Grade
1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments
2
STATIC PERFORMANCE
Resolution 16 16 Bits
Relative Accuracy ±32 ±16 LSB See Figure 5
Differential Nonlinearity ±1 ±1 LSB
Zero-Code Error 1 9 1 9 mV All 0s loaded to DAC register (see Figure 13)
Zero-Code Error Drift ±2 ±2 µV/°C
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 12)
Gain Error ±1 ±1 % FSR
Gain Temperature
±2.5 ±2.5 ppm Of FSR/°C
Coefficient
Offset Error ±1 ±9 ±1 ±9 mV
DC Power Supply Rejection
–80 –80 dB V
Ratio
DC Crosstalk
10 10 µV
(External Reference)
5 5 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
DC Crosstalk
25 25 µV
(Internal Reference)
10 10 µV/mA Due to load current change
OUTPUT CHARACTERISTICS
3
Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 3 V coming out of power-down mode
Power-Up Time 4 4 s Coming out of power-down VDD = 3 V
REFERENCE INPUTS
Reference Input Voltage VDD VDD V
Reference Current 40 55 40 55 µA V
Reference Input Range 0 VDD 0 VDD
Reference Input Impedance 14.6 14.6 kΩ Per DAC channel
REFERENCE OUTPUT
Output Voltage 1.247 1.253 1.247 1.253 V At ambient
Reference TC
Reference Output
3
±5 ±15 ±5 ±15 ppm/°C
7.5 7.5 kΩ
Impedance
LOGIC INPUTS
3
Input Current ±3 ±3 µA
Input Low Voltage, V
Input High Voltage, V
0.8 0.8 V VDD = 3 V
INL
2 2 V VDD = 3 V
INH
Pin Capacitance 3 3 pF
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL 0.4 0.4 V I
Output High Voltage, VOH
High Impedance Leakage
V
0.5
±0.25 ±0.25 A
−
DD
V
0.5
−
DD
Current
High Impedance Leakage
2 2 pF
= VDD. All specifications T
REFIN
1
B Grade
Guaranteed monotonic by design (see Figure
6)
Due to full-scale output change,
R
Due to full-scale output change,
R
SINK
I
SOURCE
to T
MIN
± 10%
DD
= 2 kΩ to GND or VDD
L
= 2 kΩ to GND or VDD
L
= VDD = 3.6 V
REF
, unless otherwise noted.
MAX
= 2 mA
= 2 mA
Rev. D | Page 5 of 28
AD5666
A Grade
1
B Grade
1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments
Current
POWER REQUIREMENTS
VDD 2.7 3.6 2.7 3.6 V
All digital inputs at 0 or V
,
DD
DAC active, excludes load current
IDD (Normal Mode)
4
V
= VDD and VIL = GND
IH
VDD = 2.7 V to 3.6 V 0.65 0.85 0.65 0.85 mA Internal reference off
VDD = 2.7 V to 3.6 V 1.3 1.5 1.3 1.5 mA Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND
1
Temperature range is −40°C to +105°C, typical at 25°C.
2
Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All four DACs powered down.
Rev. D | Page 6 of 28
AD5666
AC CHARACTERISTICS
VDD =2.7V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V
Table 3.
Parameter
1, 2
Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time 6 10 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 29)
Reference Feedthrough −90 dB V
SDO Feedthrough 3 nV-s Daisy-chain mode; SDO load is 10 pF
Digital Feedthrough 0.1 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 2.5 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz
100 nV/√Hz DAC code = 0x8400, 10 kHz
Output Noise 15 V p-p 0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range is −40°C to + 105°C, typical at 25°C.
= VDD. All specifications T
REFIN
= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
REF
= 2 V ± 0.2 V p-p
REF
= 2 V ± 0.1 V p-p, frequency = 10 kHz
REF
MIN
3
to T
, unless otherwise noted.
MAX
Rev. D | Page 7 of 28
AD5666
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 5. V
Table 4.
Limit at T
Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments
1
t
1
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min
t5 4 ns min Data set-up time
t6 4 ns min Data hold time
t7 0 ns min
t8 15 ns min
t9 13 ns min
t10 0 ns min
t11 10 ns min
t12 15 ns min
t13 5 ns min
t14 0 ns min
t15 300 ns typ
2, 3
t
16
3
t
5 ns min
17
3
t
8 ns min
18
3
t
0 ns min
19
1
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode.
3
Daisy-chain mode only.
= 2.7 V to 5.5 V. All specifications T
DD
, T
MIN
MAX
20 ns min SCLK cycle time
22 ns max SCLK rising edge to SDO valid
MIN
to T
, unless otherwise noted.
MAX
SYNC
SCLK falling edge to SYNC
Minimum SYNC
SYNC
SCLK falling edge to SYNC
LDAC
SCLK falling edge to LDAC
CLR
SCLK falling edge to LDAC
CLR
SCLK falling edge to SYNC
SYNC
SYNC
to SCLK falling edge set-up time
rising edge
high time
rising edge to SCLK fall ignore
fall ignore
pulse width low
rising edge
pulse width low
falling edge
pulse activation time
rising edge
rising edge to SCLK rising edge
rising edge to LDAC falling edge
2mA I
OL
TO OUT P U T
PIN
50pF
C
L
2mA I
OH
VOH(MIN)
5298-002
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. D | Page 8 of 28
AD5666
t
10
SCLK
t
8
SYNC
DIN
1
LDAC
2
LDAC
CLR
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
DB31
t
4
t
6
t
5
t
1
t
t
3
2
DB0
t
9
t
7
t
11
t
14
t
12
t
13
5298-003
Figure 3. Serial Write Operation
t
1
SCLK
SYNC
DIN
t7t
t
4
t
8
3
t
9
32 64
t
2
DB0DB31
DB31
t
t
17
DB0
18
INPUT WO RD FOR DAC N
SDO
UNDEFINED
INPUT WO RD F OR DAC N + 1
t
16
DB31
INPUT WO RD FOR DAC N
DB0
t
19
t
11
LDAC
05298-004
Figure 4. Daisy-Chain Timing Diagram
Rev. D | Page 9 of 28
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