ANALOG DEVICES AD5625R, AD5645R, AD5665R Service Manual

Quad, 12-/14-/16-Bit nanoDACs with

A

V

/

V

2

5 ppm/°C On-Chip Reference, I

C Interface

AD5625R/AD5645R/AD5665R, AD5625/AD5665

FEATURES

Low power, smallest pin-compatible, quad nanoDACs AD5625R/AD5645R/AD5665R

12-/14-/16-bit nanoDACs On-chip, 2.5 V, 5 ppm/°C reference in TSSOP On-chip, 2.5 V, 10 ppm/°C reference in LFCSP On-chip, 1.25 V, 10 ppm/°C reference in LFCSP

AD5625/AD5665

12-/16-bit nanoDACs External reference only

3 mm × 3 mm 10-lead LFCSP and 14-lead TSSOP

2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale/midscale Per channel power-down Hardware

2

I

C-compatible serial interface supports standard (100 kHz),

LDAC

and

functions

CLR

fast (400 kHz), and high speed (3.4 MHz) modes

APPLICATIONS

Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

GENERAL DESCRIPTION

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 members of the nanoDAC® family are low power, quad, 12-/ 14-/16-bit, buffered voltage-out DACs with/without an on-chip reference. All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and have an I serial interface.

The AD5625R/AD5645R/AD5665R have an on-chip reference. The LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V, 10 ppm/°C reference, giving a full-scale output range of 2.5 V or 5 V; the TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The AD5625/AD5665 require an external reference voltage to set the output range of the DAC.

The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V (POR = GND) or midscale (POR = V

) and remains there until a valid write occurs. The

DD

on-chip precision output amplifier enables rail-to-rail output swing.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

2

C-compatible

FUNCTIONAL BLOCK DIAGRAMS

REFIN

STRING

V

REFOUT

1.25V/2.5V REF

DAC A

DAC B

DAC C

DAC D

REFIN

DAC A

DAC B

DAC C

DAC D

BUFFER

DD

AD5625R/AD5645R/AD5665R

DDR1

DDR2

SCL

SDA

NOTES

1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE: ADDR2, LDAC, CLR, POR.

INTERFACE

LDAC CLR POR

INPUT

REGISTER

INPUT

REGISTER

LOGIC

INPUT

REGISTER

INPUT

REGISTER

POWER-ON RE SET POWER-DOWN LOGIC

GND

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1. AD5625R/AD5645R/AD5665R

DD

AD5625/AD5665

ADDR1

ADDR2

SCL

SDA

NOTES

1. THE FOL LOWI NG PINS ARE AVAI LABLE ONL Y ON 14-LEAD PACKAG E:

ADDR2, LDAC, CLR, POR.

INTERFACE

LDAC CLR POR

INPUT

REGISTE R

INPUT

REGISTE R

LOGIC

INPUT

REGISTE R

INPUT

REGISTE R

POWER-O N RESET POWER-DOWN LOGIC

GND

DAC

REGISTE R

DAC

REGISTE R

DAC

REGISTE R

DAC

REGISTE R

Figure 2. AD5625/AD5665

The AD56x5R/AD56x5 use a 2-wire I2C-compatible serial interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes.

Table 1. Related Devices

Part No. Description

AD5025/AD5045/AD5065 Dual 12-/14-/16-bit DACs AD5624R/AD5644R/AD5664R,

AD5624/AD5664 AD5627R/AD5647R/AD5667R,

AD5627/AD5667 AD5666

Quad SPI 12-/14-/16-bit DACs, with/without internal reference

Dual I2C 12-/14-/16-bit DACs, with/without internal reference

Quad SPI 16-bit DAC with internal reference

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

06341-001

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

6341-002

AD5625R/AD5645R/AD5665R, AD5625/AD5665

REVISION HISTORY

12/09—Rev. A to Rev. B

Changes to Features Section, General Description Section,

and Table 1 ......................................................................................... 1

Changes to Table 2 ............................................................................ 3

Changes to Internal Reference Section ........................................ 22

Updated Outline Dimensions ....................................................... 32

Changes to Ordering Guide .......................................................... 33

6/09—Rev. 0 to Rev. A

Changes to Features and General Description Sections .............. 1

Changes to Table 2 ............................................................................ 3

Changes to Table 3 ............................................................................ 5

Changes to Digital-to-Analog Converter (DAC) Section, Added

Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22

Changes to Ordering Guide .......................................................... 33

3/07—Revision 0: Initial Version

Rev. B | Page 2 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

SPECIFICATIONS

SPECIFICATIONS—AD5665R/AD5645R/AD5625R

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 2.

A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

2

AD5665R

Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design

AD5645R

Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design

AD5625R

Resolution 12 12 Bits Relative Accuracy ±1 ±4 ±0.5 ±1 LSB

Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 2 10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.1 ±0.5 −0.1 ±0.5 % FSR All 1s loaded to DAC register Gain Error ±0.1 ±1.25 ±0.1 ±1 % FSR Zero-Code Error Drift ±2 ±2 µV/°C Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C DC Power Supply Rejection

−100 −100 dB DAC code = midscale; V

Ratio DC Crosstalk (External

15 15 µV

Reference) 10 10 µV/mA Due to load current change 8 8 µV Due to powering down (per channel) DC Crosstalk (Internal

25 25 µV

Reference) 20 20 µV/mA Due to load current change 10 10 µV Due to powering down (per channel)

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD 0 VDD V Internal reference disabled 0

2 × V

REF

Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 µs

REFERENCE INPUTS

Reference Current 210 260 210 260 µA V Reference Input Range 0.75 VDD 0.75 VDD V Reference Input Impedance 26 26 kΩ

REFERENCE OUTPUT (1.25 V)

Output Voltage 1.247 1.253 1.247 1.253 V At ambient Reference TC

3

±10 ±10 ppm/°C

Output Impedance 7.5 7.5 kΩ

= VDD; all specifications T

REFIN

2 × V

Rev. B | Page 3 of 36

to T

MIN

Due to full-scale output change, R

, unless otherwise noted.

MAX

= 2 kΩ to GND or V

L

= 2 kΩ to GND or V

L

Internal reference enabled

REF

Coming out of power-down mode; VDD = 5 V

= VDD = 5.5 V

REF

= 5 V ± 10%

DD

1

AD5625R/AD5645R/AD5665R, AD5625/AD5665

A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1

REFERENCE OUTPUT (2.5 V) VDD = 4.5 V to 5.5 V

Output Voltage 2.495 2.505 2.495 2.505 V At ambient Reference TC3 ±10 ±5 ±10 ppm/°C Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS (ADDRx, CLR,

, POR)3

LDAC IIN, Input Current ±1 ±1 μA V

, Input Low Voltage 0.15 × VDD 0.15 × VDD V

INL

V

, Input High Voltage 0.85 × VDD 0.85 × VDD V

INH

CIN, Pin Capacitance 2 2 pF V

, Input Hysteresis 0.1 × VDD 0.1 × VDD V

HYST

LOGIC INPUTS (SDA, SCL)3

IIN, Input Current ±1 ±1 μA V

, Input Low Voltage 0.3 × VDD 0.3 × VDD V

INL

V

, Input High Voltage 0.7 × VDD 0.7 × VDD V

INH

CIN, Pin Capacitance 2 2 pF V

, Input Hysteresis 0.1 × VDD 0.1 × VDD V High speed mode

HYST

0.05 × VDD 0.05 × VDD V Fast mode

LOGIC OUTPUTS (SDA)3

VOL, Output Low Voltage 0.4 0.4 V I

0.6 0.6 V I Floating-State Leakage

Current

Floating-State Output

Capacitance

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V IDD (Normal Mode)4 V

VDD = 4.5 V to 5.5 V 1.0 1.16 1.0 1.16 mA Internal reference off VDD = 2.7 V to 3.6 V 0.9 1.05 0.9 1.05 mA Internal reference off VDD = 4.5 V to 5.5 V 1.9 2.14 1.9 2.14 mA Internal reference on VDD = 2.7 V to 3.6 V 1.4 1.59 1.4 1.59 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD, VIL = GND (LFCSP) VDD = 3.6 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD, VIL = GND (TSSOP)

1

Temperature range of A and B grades is −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,024), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4064). Output

unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.

= 3 mA

SINK

= 6 mA

SINK

±1 ±1 μA

2 2 pF

= VDD, VIL = GND, full-scale loaded

IH

Rev. B | Page 4 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

SPECIFICATIONS—AD5665/AD5625

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 3.

B Grade Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

2

AD5665

Resolution 16 Bits

Relative Accuracy ±8 ±16 LSB

Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5625

Resolution 12 Bits

Relative Accuracy ±0.5 ±1 LSB

Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All 0s loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±0.5 % FSR All 1s loaded to DAC register Gain Error ±0.1 ±1 % FSR Zero-Code Error Drift ±2 µV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10% DC Crosstalk (External Reference) 15 µV

10 µV/mA Due to load current change 8 µV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 µV

20 µV/mA Due to load current change 10 µV Due to powering down (per channel)

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD V Capacitive Load Stability 2 nF RL = ∞ 10 nF RL = 2 kΩ DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA VDD = 5 V Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V

REFERENCE INPUTS

Reference Current 210 260 µA V Reference Input Range 0.75 VDD V Reference Input Impedance 26 kΩ

3

LOGIC INPUTS (ADDRx, CLR, LDAC, POR)

IIN, Input Current ±1 µA V

, Input Low Voltage 0.15 × VDD V

INL

V

, Input High Voltage 0.85 × VDD V

INH

CIN, Pin Capacitance 2 pF V

, Input Hysteresis 0.1 × VDD V

HYST

LOGIC INPUTS (SDA, SCL)

3

IIN, Input Current ±1 µA V

, Input Low Voltage 0.3 × VDD V

INL

V

, Input High Voltage 0.7 × VDD V

INH

CIN, Pin Capacitance 2 pF V

, Input Hysteresis 0.1 × VDD V High speed mode

HYST

0.05 × VDD V Fast mode

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

1

Due to full-scale output change,

= 2 kΩ to GND or V

R

L

DD

Due to full-scale output change, R

= 2 kΩ to GND or V

L

DD

= VDD = 5.5 V

REF

Rev. B | Page 5 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

B Grade Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUTS (SDA)

VOL, Output Low Voltage 0.4 V I

0.6 V I

3

= 3 mA

SINK

= 6 mA

SINK

Floating-State Leakage Current ±1 µA Floating-State Output Capacitance 2 pF

POWER REQUIREMENTS

VDD 2.7 5.5 V IDD (Normal Mode)

4

V

= VDD, VIL = GND, full-scale loaded

IH

VDD = 4.5 V to 5.5 V 1.0 1.16 mA VDD = 2.7 V to 3.6 V 0.9 1.05 mA

IDD (All Power-Down Modes)

5

VDD = 2.7 V to 5.5 V 0.48 1 µA VIH = VDD, VIL = GND (LFCSP) VDD = 3.6 V to 5.5 V 0.48 1 µA VIH = VDD, VIL = GND (TSSOP)

1

Temperature range of B grade is −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.

1

Rev. B | Page 6 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter

1, 2

Min Typ Max Unit Test Conditions/Comments

3

Output Voltage Settling Time

AD5625R/AD5625 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5645R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5665R/AD5665 4 7 µs ¼ to ¾ scale settling to ±2 LSB

Slew Rate 1.8 V/µs Digital-to-Analog Glitch Impulse 1 LSB change around major carry 15 nV-s LFCSP 5 nV-s TSSOP Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s External reference 4 nV-s Internal reference DAC-to-DAC Crosstalk 1 nV-s External reference 4 nV-s Internal reference Multiplying Bandwidth 340 kHz V Total Harmonic Distortion −80 dB V

= 2 V ± 0.1 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 µV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical @ 25°C.

Rev. B | Page 7 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

I2C TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V; all specifications T

MIN

to T

, f

= 3.4 MHz, unless otherwise noted.1

MAX

SCL

Table 5.

Parameter Test Conditions

3

f

SCL

Standard mode 100 kHz Serial clock frequency

2

Min Max Unit Description

Fast mode 400 kHz High speed mode, CB = 100 pF 3.4 MHz High speed mode, CB = 400 pF 1.7 MHz t1 Standard mode 4 s t

, SCL high time

HIGH

Fast mode 0.6 s High speed mode, CB = 100 pF 60 ns High speed mode, CB = 400 pF 120 ns t2 Standard mode 4.7 s t

, SCL low time

LOW

Fast mode 1.3 s High speed mode, CB = 100 pF 160 ns High speed mode, CB = 400 pF 320 ns t3 Standard mode 250 ns t

, data setup time

SU;DAT

Fast mode 100 ns High speed mode 10 ns t4 Standard mode 0 3.45 s t

, data hold time

HD;DAT

Fast mode 0 0.9 s High speed mode, CB = 100 pF 0 70 ns High speed mode, CB = 400 pF 0 150 ns t5 Standard mode 4.7 s t

, setup time for a repeated start condition

SU;STA

Fast mode 0.6 s High speed mode 160 ns t6 Standard mode 4 s t

, hold time (repeated) start condition

HD;STA

Fast mode 0.6 s High speed mode 160 ns t7 Standard mode 4.7 s

, bus-free time between a stop and a start

t

BUF

condition Fast mode 1.3 s t8 Standard mode 4 s t

, setup time for a stop condition

SU;STO

Fast mode 0.6 s High speed mode 160 ns t9 Standard mode 1000 ns t

, rise time of SDA signal

RDA

Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, CB = 400 pF 20 160 ns t10 Standard mode 300 ns t

, fall time of SDA signal

FDA

Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, CB = 400 pF 20 160 ns t11 Standard mode 1000 ns t

, rise time of SCL signal

RCL

Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns t

Standard mode 1000 ns

11A

, rise time of SCL signal after a repeated start

t

RCL1

condition and after an acknowledge bit Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, CB = 400 pF 20 160 ns

Rev. B | Page 8 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Parameter Test Conditions

t12 Standard mode 300 ns t

2

Min Max Unit Description

, fall time of SCL signal

FCL

Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns t13 Standard mode 10 ns

pulse width low

LDAC Fast mode 10 ns High speed mode 10 ns t14 Standard mode 300 ns

Falling edge of ninth SCL clock pulse of last byte

of a valid write to LDAC

falling edge Fast mode 300 ns High speed mode 30 ns t15 Standard mode 20 ns

pulse width low

CLR Fast mode 20 ns High speed mode 20 ns

4

t

SP

Fast mode 0 50 ns Pulse width of spike suppressed

High speed mode 0 10 ns

1

See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.

2

CB refers to the capacitance on the bus line.

3

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC

behavior of the part.

4

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.

t

SCL

SDA

t

7

PS S P

2

t

6

11

t

4

t

12

t

1

t

3

t

6

t

5

t

10

t

8

t

14

t

9

LDAC*

CLR

*ASYNCHRONOUS LDAC UPDAT E MODE.

t

15

Figure 3. 2-Wire Serial Interface Timing Diagram

t

13

06341-003

Rev. B | Page 9 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Operating Temperature Range, Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ maximum) 150°C

Power Dissipation (TJ max − TA)/θJA

θJA Thermal Impedance

LFCSP_WD (4-Layer Board) 61°C/W TSSOP 150.4°C/W

Reflow Soldering Peak Temperature,

RoHS Compliant

to GND −0.3 V to VDD + 0.3 V

260°C ± 5°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 10 of 36

AD5625R/AD5645R/AD5665R, AD5625/AD5665

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

LDAC

2

ADDR1

V

OUT

V

OUT

POR

REFIN/VREFOUT

V

DD

A

C

AD5625R/

3

AD5645R/

4

AD5665R

TOP VIEW

5

(Not to Scale)

6

7

Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version

1

LDAC

2

ADDR1

V

OUT

V

OUT

POR

V

REFIN

DD

A

C

AD5625/

3

AD5665

4

TOP VIEW

(Not to Scale)

5

6

7

Figure 5. Pin Configuration (14-Lead TSSOP)

14

13

12

11

10

9

8

14

SCL

13

SDA

12

GND

11

V

10

V

9

CLR

8

ADDR2

SCL

SDA

GND

V

OUT

V

OUT

CLR

ADDR2

B

D

OUT

1

V

A

OUT

2

V

B

OUT

3

B

D

06341-120

GND

4

V

C

OUT

5

V

D

OUT

EXPOSED PAD TIED TO GND.

Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version

V

A

OUT

V

B

OUT

GND

V

C

OUT

V

D

OUT

6341-121

EXPOSED PAD TIED TO GND.

Figure 7. Pin Configuration (10-Lead LFCSP)

Table 7. Pin Function Descriptions

Pin Number

14-Lead 10-Lead Mnemonic Description

1 N/A

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

2 N/A ADDR1

Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 9).

3 9 V

DD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be

decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. 4 1 V 5 4 V 6 N/A POR

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

Power-On Reset Pin. Tying the POR pin to GND powers up the part to 0 V. Tying the POR pin to V

powers up the part to midscale. 7 10 V

REFIN/VREFOUT

The AD56x5R have a common pin for reference input and reference output. When using the internal

reference, this is the reference output pin. When using an external reference, this is the reference

input pin. The default for this pin is as a reference input. (The internal reference and reference output

are only available on R suffix versions.) The AD56x5 has a reference input pin only. 8 N/A ADDR2 9 N/A

CLR

Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 9).

Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses

are ignored. When CLR

is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the falling edge of the ninth clock pulse of the last byte of the valid write. If CLR

is activated during a write sequence, the write is aborted. If CLR is

activated during high speed mode, the part exits high speed mode.

10 5 V 11 2 V 12 3 GND 13 8 SDA

D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

Ground Reference Point for All Circuitry on the Part. Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit

input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.

14 7 SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register.

N/A 6 ADDR

Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 8).

EPAD For the 10-lead LFCSP, the exposed pad must be tied to GND.

Rev. B | Page 11 of 36

AD5625R/ AD5645R/

AD5665R

TOP VIEW

(Not to Scale)

1

AD5625/

2

AD5665

3

TOP VIEW

(Not to Scale)

4

5

10

V

REFIN/VREFOUT

9

V

DD

8

SDA

7

SCL

6

ADDR

10

9

8

7

6

V

REFIN

V

DD

SDA

SCL

ADDR

06341-122

06341-123

DD

ANALOG DEVICES AD5625R, AD5645R, AD5665R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

SPECIFICATIONS—AD5665R/AD5645R/AD5625R

SPECIFICATIONS—AD5665/AD5625

AC CHARACTERISTICS

I2C TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS