ANALOG DEVICES AD5663 Service Manual

2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output,

V

FEATURES

Low power, dual 16-bit nanoDAC Relative accuracy: ±12 LSBs maximum Guaranteed monotonic by design 10-lead MSOP and 3 mm × 3 mm LFCSP_WD

2.7 V to 5.5 V power supply Per channel power-down Power-on reset to zero scale or midscale

Hardware

LDAC

Serial interface; up to 50 MHz

APPLICATIONS

Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

and

CLR

functions

Dual 16-Bit nanoDAC

FUNCTIONAL BLOCK DIAGRAM

DD

REF

LDAC

STRING

DAC

DAC A

STRING

DAC

DAC B

POWER-ON

RESET

GND

2.7 V to 5.5 V, dual 12-/14-/16-bit DACs with internal reference

CLR

INPUT

REGISTER

INPUT

REGISTER

AD5663

REGISTER

SCLK

SYNC

INTERFACE

LOGIC

DIN

LDAC

Figure 1.

Table 1. Related Devices

Part No. Description

AD5623R/AD5643R/AD5663R

AD5663

BUFFER

POWER-DOW N

LOGIC

®

V

A

OUT

V

B

OUT

05855-001

GENERAL DESCRIPTION

The AD5663, a member of the nanoDAC family, is a low power, dual, 16-bit buffered voltage-out DAC that operates from a single

2.7 V to 5.5 V supply and is guaranteed monotonic by design.

The AD5663 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V or midscale (AD5663-1) and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode.

The low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment. The power consumption is 1.25 mW at 5 V, going down to

2.4 µW in power-down mode.

The on-chip precision output amplifier of the AD5663 allows rail-to-rail output swing to be achieved.

The AD5663 uses a versatile, 3-wire serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards.

PRODUCT HIGHLIGHTS

1. Dual 16-bit DAC; relative accuracy of ±12 LSBs maximum.

2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm

LFCSP_WD packages.

3. Low power; typically consumes 0.6 mW at 3 V and

1.25 mW at 5 V.

4. 7 µs maximum settling time.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5663

REVISION HISTORY

4/06—Revision 0: Initial Version

Ordering Guide .......................................................................... 21

Rev. 0 | Page 2 of 24

AD5663

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 2.

A Grade

1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5663

Resolution 16 16 Bits Relative Accuracy ±8 ±16 ±6 ±12 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.15 ±1 −0.15 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 ±1.5 % of FSR Zero-Scale Error Drift

3

±2 ±2 µV/°C

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale, VDD ± 10% DC Crosstalk 10 10 µV

10 10 µV/mA Due to load current change 5 5 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS

Output Voltage Range 0 V

2

DD

Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 s

REFERENCE INPUTS

Reference Current 170 200 170 200 µA V Reference Input Range 0.75 V

DD

Reference Input Impedance 26 26 kΩ

LOGIC INPUTS

3

Input Current ±2 ±2 µA All digital inputs V

, Input Low Voltage 0.8 0.8 V VDD = 5 V, 3 V

INL

V

, Input High Voltage 2 2 V VDD = 5 V, 3 V

INH

Pin Capacitance 3 3 pF 19 19 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

4

2.7 5.5 2.7 5.5 V

VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 250 450 250 450 µA VDD = 2.7 V to 3.6 V 200 425 200 425 µA

IDD (All Power-Down

Modes)

5

VIH = VDD, VIL = GND

VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA

1

Temperature range: A grade and B grade are both equal to −40°C to +105°C.

2

Linearty calculated using a reduced code range: AD5663 (Code 512 to Code 65024). Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

Both DACs powered down.

= VDD; all specifications T

REF

B Grade

1

0 V

0.75 V

V

DD

V

DD

MIN

to T

, unless otherwise noted.

MAX

Due to full-scale output change R

L = 2 kΩ to GND or VDD

Coming out of power-down mode; V

= 5 V

DD

= VDD = 5.5 V, 3.6 V

REF

DIN, SCLK, and

SYNC

LDAC and CLR

Rev. 0 | Page 3 of 24

AD5663

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

2

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time 4 7 µs 1/4 to 3/4 scale settling to ±2 LSB Slew Rate 1.8 V/µs Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dBs V

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 1 nV-s Multiplying Bandwidth 340 kHz V Total Harmonic Distortion −80 dB V

= 2 V ± 0.1 V p-p

REF

= 2 V ± 0.1 V p-p; frequency = 10 kHz

REF

Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

μV p-p

0.1 Hz to 10 Hz

1

Rev. 0 | Page 4 of 24

AD5663

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. V

= 2.7 V to 5.5 V; all specifications T

DD

Table 4.

Limit at T

Parameter

2

t

1

VDD = 2.7 V to 5.5 V Unit Conditions/Comments

20 ns min SCLK cycle time

t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 13 ns min t5 5 ns min Data setup time t6 5 ns min Data hold time t7 0 ns min t8 15 ns min

t9 13 ns min t10 0 ns min t

11

t

12

10 ns min

15 ns min t13 5 ns min t14 0 ns min t

15

1

Guaranteed by design and characterization; not production tested.

2

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

300 ns max

MIN

to T

, T

, unless otherwise noted.1

MAX

SYNC to SCLK falling edge setup time

SCLK falling edge to Minimum

SYNC high time

SYNC rising edge

SYNC rising edge to SCLK fall ignore SCLK falling edge to

SYNC fall ignore LDAC pulse width low SCLK falling edge to

LDAC rising edge CLR pulse width low SCLK falling edge to

LDAC falling edge CLR pulse activation time

TIMING DIAGRAM

SCLK

SYNC

DIN

LDAC

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDAT E MODE.

2

SYNCHRONOUS LDAC UPDAT E MODE.

t

10

t

8

1

2

DB23

t

4

t

6

t

5

t

13

t

15

t

1

t

3

2

DB0

t

9

t

7

t

11

t

14

t

12

05855-002

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5663

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Operating Temperature Range

Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Power Dissipation (TJ max − TA)/θ LFCSP_WD Package (4-Layer Board)

θJA Thermal Impedance 61°C/W MSOP Package (4-Layer Board)

θJA Thermal Impedance 142°C/W

θJC Thermal Impedance 43.7°C/W Reflow Soldering Peak Temperature

Pb-Free 260(+0/−5)°C

JA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5663

PIN CONFIGURATION AND FUNCTION DESCRIPTION

V

OUT

V

OUT

GND

LDAC

CLR

1

A

2

B

3

4

5

AD5663

TOP VIEW

(Not to Scale)

10

V

REF

9

V

DD

8

DIN

7

SCLK

6

SYNC

5855-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground Reference Point for All Circuitry on the Part. 4

LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored.

CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part

When exits clear code mode on the 24th falling edge of the next write to the part. If

CLR is activated during a write

sequence, the write is aborted.

6

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,

it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device.

7 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz.

8 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

9 VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

10 V

Reference Voltage Input.

REF

Rev. 0 | Page 7 of 24

AD5663

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = V

8

T

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

= 25°C

A

REF

= 5V

CODE

Figure 4. INL

1.0 VDD = V T

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 10k 20k 30k 40k 50k 60k

= 25°C

A

REF

= 5V

CODE

Figure 5. DNL

8

6

= 5V

V

DD

4

T

= 25°C

A

2

0

–2

ERROR (L SB)

–4

–6

–8

–10

05855-004

0.75 1.25 1.75 2.25 4.253. 753.252.75 4.75 V

(V)

REF

Figure 7. INL and DNL Error vs. V

8

6

= 25°C

T

A

4

2

0

ERROR (L SB)

–2

–4

–6

–8

05855-005

2.7 3.2 3.7 4.74.2 5. 2 VDD (V)

Figure 8. INL and DNL Error vs. Supply

MAX INL

MAX DNL

MIN DNL

MIN INL

05855-007

REF

MAX INL

MAX DNL

MIN DNL

MIN INL

05855-008

8

6

V

= V

= 5V

DD

4

2

0

ERROR (LSB)

–2

–4

–6

–8

–40 –20 40200 1008060 120

REF

TEMPERATURE ( °C)

Figure 6. INL Error and DNL Error vs. Temperature

MAX INL

MAX DNL

MIN DNL

MIN INL

05855-006

Rev. 0 | Page 8 of 24

0

VDD = 5V

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

ERROR (% FSR)

–0.14

–0.16

–0.18

–0.20

–40 –20 40200 1008060

GAIN ERROR

FULL-SCAL E ERROR

TEMPERATURE (°C)

Figure 9. Gain Error and Full-Scale Error vs. Temperature

05855-009

ANALOG DEVICES AD5663 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

TYPICAL PERFORMANCE CHARACTERISTICS