Analog Devices AD5620 40 pra Datasheet

3 V/5 V, 12/14-Bit

10 ppm/°C Max On-Chip Reference in SOT-23

nano

DACTM D/A with

Preliminary Technical Data

FEATURES

AD5620: low power single 12-bit nanoDAC
AD5640: low power single 16-bit nanoDAC

12-bit accuracy guaranteed
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Tiny 8-lead SOT-23/MSOP package
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on reset to zero/midscale
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5620/40 parts are a member of the nanoDAC family of
devices. They are low power, single, 12-/14-bit buffered voltage­out DACs, guaranteed monotonic by design. The AD5620/40x-1
operate from a 3 V single supply featuring an internal reference
of 1.25 V and an internal gain of 2. The AD5620/40x-2/3 operate
from a 5 V single supply featuring an internal reference of 2.5 V
and an internal gain of 2. Each reference has a 10 ppm/°C max
temperature coefficient. The reference associated with each part
is available at the REFOUT pin.

The part incorporates a power-on reset circuit, which ensures
that the DAC output powers up to 0 V (AD5620/40x-1/2) or to
midscale (AD5620/40x-3) and remains there until a valid write
takes place. The part contains a power-down feature that reduces
the current consumption of the device to 200 nA at 5 V and
provides software selectable output loads while in power-down
mode.

The AD5620/40 uses a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™, and DSP interface
standards. Its on-chip precision output amplifier allows rail-to­rail output swing to be achieved.

Rev. PrA

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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

AD5620/AD5640

FUNCTIONAL BLOCK DIAGRAM

V

REFOUT

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SYNC SCLK DIN

1.25/2.5V
REF

REF(+)

DAC

POWER-DOWN

CONTROL LOGIC

The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.7 mW at 5 V, reducing to 1 µW in
power-down mode.

The AD5620/40 is designed with new technology and is the
next generation to the AD53xx family.

RELATED DEVICES

Part No. Description

AD5660 3 V/5 V 16-bit DAC in SOT-23, internal reference
AD5662 2.7 V to 5.5 V 16-bit DAC in SOT-23, external reference

PRODUCT HIGHLIGHTS

1. 16-bit DAC; 12-bit accuracy guaranteed.

2. On-chip 1.25 V/2.5 V, 10 ppm/°C max reference.

3. Available in 8-lead SOT-23 and 8-lead MSOP packages.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 50 nA at 3 V and 200 nA at 5 V.

6. 10 µS settling time.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

GND

Figure 1.

V

DD

AD5620/AD5640

OUTPUT
BUFFER

RESISTOR
NETWORK

V

FB

V

OUT

04781-0-001

AD5620/AD5640 Preliminary Technical Data

TABLE OF CONTENTS

AD5620/40x-2/3–Specifications..................................................... 3

Typical Perfor m a n c e C haracter i st ics ........................................... 11

AD5620/40x-1–Specifications ........................................................ 5

Timing Characteristics..................................................................... 7

Pin Configuration and Function Descriptions............................. 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Te r mi n ol o g y .................................................................................... 10

REVISION HISTORY

10/04—Revision 0: PrA

Theory of Operation ...................................................................... 14

Serial Interface............................................................................ 14

Microprocessor Interfacing....................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. PrA | Page 2 of 20

Preliminary Technical Data AD5620/AD5640

AD5620/40X-2/3–SPECIFICATIONS

VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 1.

Parameter A Grade B Grade C Grade Unit

STATIC PERFORMANCE

2

AD5620

Resolution 12 12 12 Bits min
Relative Accuracy ±6 ±1 ±1 LSB max See Figure 4.
Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5.

AD5640

Resolution 14 14 14 Bits min
Relative Accuracy ±8 ±4 ±4 LSB max See Figure 4.

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5.
Zero Code Error +5 +5 +5 mV typ All 0s loaded to DAC register.
+20 +20 +20 mV max
Offset Error ±10 ±10 ±10 mV typ
Full-Scale Error −0.15 −0.15 −0.15 % of FSR typ All 1s loaded to DAC register.

−1.25 −1.25 −1.25 % of FSR max
Gain Error ±1.25 ±1.25 ±1.25 % of FSR max
Zero Code Error Drift

3

±2 ±2 ±2 µV/°C typ
Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C
DC Power Supply Rejection Ratio −100 −100 −100 dB typ DAC code = midscale; VDD = 5 V ±10%

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 0 V min
V

DD

V

DD

V

DD

V max
Output Voltage Settling Time 8 8 8 µs typ To ±0.003% FSR 0x0200 to 0xFD00
10 10 10 µs max RL = 2 kΩ; 0 pF < CL < 200 pF
12 12 12 µs typ RL = 2 kΩ; CL = 500 pF
Slew Rate 1 1 1 V/µs typ
Capacitive Load Stability 2 2 2 nF typ RL = ∞
10 10 10 nF typ RL = 2 kΩ
Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10kHz
Output Noise (0.1 Hz to 10 Hz) 10 10 10 µVp-p typ DAC code = midscale
THD, Total Harmonic Distortion −80 −80 −80 dB typ V
Output Drift ppm/°C typ
Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry.
Digital Feedthrough 0.1 0.1 0.1 nV-s typ
DC Output Impedance 0.5 0.5 0.5 Ω typ
Short Circuit Current 30 30 30 mA typ VDD = 5 V
Power-Up Time 4 4 4

µs typ

REFERENCE OUTPUT

Output Voltage
AD5620/40x-2/3 2.495 2.495 2.495 V min

2.505 2.505 2.505 V max
Reference TC ±25 ±25 ±10 ppm/°C max

LOGIC INPUTS3

Input Current ±1 ±1 ±1 µA max

1

Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of 512 to 65024. Output unloaded.

3

Guaranteed by design and characterization, not production tested.

MIN

to T

, unless otherwise noted.

MAX

B Version

1

Conditions/Comments

= 2 V ± 300 mV p-p, f = 5 kHz

REF

Coming out of power-down mode. VDD = 5 V

Rev. PrA | Page 3 of 20

AD5620/AD5640 Preliminary Technical Data

Parameter A Grade B Grade C Grade Unit

V

, Input Low Voltage 0.8 0.8 0.8 V max VDD = 5 V

INL

V

, Input High Voltage 2 2 2 V min VDD = 5 V

INH

B Version
Conditions/Comments

1

Pin Capacitance 3 3 3 pF max

POWER REQUIREMENTS

V

DD

4.5 4.5 4.5 V min All digital inputs at 0 V or V

DD

IDD (Normal Mode) 5.5 5.5 5.5 V max DAC active and excluding load current
VDD = 4.5 V to 5.5 V 0.5 0.5 0.5 mA typ VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 1 1 1 mA max VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 1 1 1 µA max VIH = VDD and VIL = GND

POWER EFFICIENCY

I

OUT/IDD

89 89 89 % I

= 2 mA, VDD = 5 V

LOAD

Rev. PrA | Page 4 of 20

Preliminary Technical Data AD5620/AD5640

AD5620/40X-1–SPECIFICATIONS

VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 2.

Parameter A Grade B Grade C Grade Unit

STATIC PERFORMANCE

5

AD5620

Resolution 12 12 12 Bits min
Relative Accuracy ±6 ±1 ±1 LSB max See Figure 4.
Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5.

AD5640

Resolution 14 14 14 Bits min
Relative Accuracy ±8 ±4 ±4 LSB max See Figure 4.

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design. See Figure 5.
Zero Code Error +5 +5 +5 mV typ All 0s loaded to DAC register
+20 +20 +20 mV max
Offset Error ±10 ±10 ±10 mV typ
Full-Scale Error −0.15 −0.15 −0.15 % of FSR typ All 1s loaded to DAC register.

−1.25 −1.25 −1.25 % of FSR max
Gain Error ±1.25 ±1.25 ±1.25 % of FSR max
Zero Code Error Drift

6

±20 ±20 ±20 µV/°C typ
Gain Temperature Coefficient ±5 ±5 ±5 ppm typ Of FSR/°C
DC Power Supply Rejection Ratio −100 −100 −100 dB typ DAC code = midscale; VDD = 3 V ±10%

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 0 V min
V

DD

V

DD

V

DD

V max
Output Voltage Settling Time 8 8 8 µs typ To ±0.003% FSR 0200H to FD00
10 10 10 µs max RL = 2 kΩ; 0 pF < CL < 200 pF.
12 12 12 µs typ RL = 2 kΩ; CL = 500 pF
Slew Rate 1 1 1 V/µs typ
Capacitive Load Stability 2 2 2 nF typ RL = ∞
10 10 10 nF typ RL = 2 kΩ
Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz
Output Noise (0.1 Hz to 10 Hz) 10 10 10 µVp-p typ DAC code = midscale
THD, Total Harmonic Distortion −80 −80 −80 dB typ V
Output Drift tbd ppm/°C typ
Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry.
Digital Feedthrough 0.1 0.1 0.1 nV-s typ
DC Output Impedance 0.5 0.5 0.5

Ω typ
Short Circuit Current 30 30 30 mA typ VDD = 3 V
Power-Up Time 10 10 10

µs typ

REFERENCE OUTPUT

Output Voltage
AD5620/40x-1 1.248 1.248 1.248 V min

1.252 1.252 1.252 V max
Reference TC ±25 ±25 ±10 ppm/°C max

4

Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.

5

Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.

6

Guaranteed by design and characterization, not production tested.

MIN

to T

, unless otherwise noted.

MAX

B Version

4

Conditions/Comments

H

= 2 V ± 300 mV p-p, f = 5 kHz

REF

Coming out of power-down mode. VDD = 3 V

Rev. PrA | Page 5 of 20

AD5620/AD5640 Preliminary Technical Data

Parameter A Grade B Grade C Grade Unit

B Version
Conditions/Comments

4

LOGIC INPUTS3
Input Current ±1 ±1 ±1 µA max
V

, Input Low Voltage 0.8 0.8 0.8 V max VDD = 3 V

INL

V

, Input High Voltage 2 2 2 V min VDD = 3 V

INH

Pin Capacitance 3 3 3 pF max

POWER REQUIREMENTS

V

DD

2.7 2.7 2.7 V min All digital inputs at 0 V or V

DD

IDD (Normal Mode) 3.6 3.6 3.6 V max DAC active and excluding load current
VDD = 2.7 V to 3.6 V 0.5 0.5 0.5 mA typ VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 1 1 1 mA max VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 2.7 V to 3.6 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 1 1 1 µA max VIH = VDD and VIL = GND

POWER EFFICIENCY

I

OUT/IDD

I

= 2 mA, VDD = 3 V

LOAD

Rev. PrA | Page 6 of 20