ANALOG DEVICES AD5601, AD5611, AD5621 Service Manual

2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit

nano

AD5601/AD5611/AD5621

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2005–2012 Analog Devices, Inc. All rights reserved.

AD5601/AD5611/AD5621

V

DD

V

OUT

GND

POWER-ON

RESET

DAC

REGISTER

12-/10-/8-BIT

DAC

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL LOGIC

OUTPUT
BUFFER

RESISTOR
NETWORK

REF(+)

SCLK SDIN

06853-001

SYNC

Data Sheet

FEATURES

6-lead SC70 and LFCSP packages
Micropower operation: 100 µA maximum at 5 V
Power-down typically to 0.2 µA at 3 V

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation

interrupt facility

SYNC
Minimized zero-code error
AD5601 buffered 8-bit DAC

B version: ±0.5 LSB INL

AD5611 buffered 10-bit DAC

B version: ±0.5 LSB INL
A version: ±4 LSB INL

AD5621 buffered 12-bit DAC

B version: ±1 LSB INL
A version: ±6 LSB INL

APPLICATIONS

Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5601/AD5611/AD5621, members of the nanoDAC®
family, are single, 8-/10-/12-bit, buffered voltage output DACs
that operate from a single 2.7 V to 5.5 V supply, consuming
typically 75 µA at 5 V. The parts come in tiny LFCSP and SC70
packages. Their on-chip precision output amplifier allows rail­to-rail output swing to be achieved. The AD5601/AD5611/
AD5621 utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP interface standards.

The reference for the AD5601/AD5611/AD5621 is derived
from the power supply inputs and, therefore, gives the widest
dynamic output range. The parts incorporate a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write to the device takes place.

The AD5601/AD5611/AD5621 contain a power-down feature
that reduces current consumption to typically 0.2 µA at 3 V.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without n otice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DAC, SPI Interface in LFCSP and SC70

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Table 1. Related Devices

Part Number Description

AD5641 2.7 V to 5.5 V, <100 µA, 14-bit nanoDAC in

SC70 and LFCSP packages

They also provide software-selectable output loads while in
power-down mode. The parts are put into power-down mode
over the serial interface.

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip­ment. The combination of small package and low power makes
these nanoDAC devices ideal for level-setting requirements,
such as generating bias or control voltages in space-constrained
and power-sensitive applications.

PRODUCT HIGHLIGHTS

1. Available in 6-lead LFCSP and SC70 packages.

2. Low power, single-supply operation. The AD5601/

AD5611/AD5621 operate from a single 2.7 V to 5.5 V
supply with a maximum current consumption of 100 µA,
making them ideal for battery-powered applications.

3. The on-chip output buffer amplifier allows the output of

the DAC to swing rail-to-rail with a typical slew rate of

0.5 V/µs.

4. Reference is derived from the power supply.

5. High speed serial interface with clock speeds up to

30 MHz. Designed for very low power consumption.
The interface powers up only during a write cycle.

6. Power-down capability. When powered down, the DAC

typically consumes 0.2 µA at 3 V. Power-on reset with
brownout detection.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5601/AD5611/AD5621 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

DAC Section ................................................................................ 14

Resistor String ............................................................................. 14

Output Amplifier ........................................................................ 14

Serial Interface ............................................................................ 14

Input Shift Register .................................................................... 14

SYNC

Interrupt .......................................................................... 14

Power-On Reset .......................................................................... 16

Power-Down Modes .................................................................. 16

Microprocessor Interfacing ....................................................... 16

Applications ..................................................................................... 18

Choosing a Reference as Power Supply for the

AD5601/AD5611/AD5621 ....................................................... 18

Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18

Using the AD5601/AD5611/AD5621 with a Galvanically

Isolated Interface ........................................................................ 19

Power Supply Bypassing and Grounding ................................ 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 21

REVISION HISTORY

2/12—Rev. E to Rev. F

Added 6-Lead LFCSP ......................................................... Universal

Changes to Features Section, General Description Section,

Table 1, and Product Highlights Section ....................................... 1

Changes to Table 4 ............................................................................ 5

Added Figure 4; Renumbered Sequentially .................................. 6

Changes to Table 5 ............................................................................ 6

Changes to Choosing a Reference as Power Supply for the

AD5601/AD5611/AD5621 Section .............................................. 18

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 21

7/10—Rev. D to Rev. E

Changes to Figure 1 .......................................................................... 1

5/08—Rev. C to Rev. D

Changes to General Description Section ...................................... 1

Changes to Table 2 ............................................................................ 3

Changes to Choosing a Reference as Power Supply for the

AD5601/AD5611/AD5621 Section .............................................. 18

Changes to Ordering Guide .......................................................... 20

12/07—Rev. B to Rev. C

Changes to Features .......................................................................... 1

Changes to Table 2 ............................................................................. 3

Changes to AD5601/AD5611/AD5621 to ADSP-2101

Interface Section ............................................................................. 16

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 20

7/05—Rev. A to Rev. B

Changes to Figure 48...................................................................... 17

Changes to Galvanically Isolated Interface Section ................... 19

Changes to Figure 52...................................................................... 19

3/05—Rev. 0 to Rev. A

Changes to Timing Characteristics ................................................. 4

Changes to Absolute Maximum Ratings ........................................ 5

Changes to Full Scale Error Section ................................................ 7

Changes to Figure 20...................................................................... 10

Changes to Theory of Operation .................................................. 14

Changes to Power Down Modes .................................................. 15

1/05—Revision 0: Initial Version

Rev. F | Page 2 of 24

Data Sheet AD5601/AD5611/AD5621

AD5621

Short-Circuit Current

15

15 mA

VDD = 3 V/5 V

DC Output Impedance

0.5

0.5 Ω

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
for A/B grades is −40°C to +125°C, typical at 25°C.

Table 2.

A Grade B Grade
Parameter Min Ty p Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

AD5601

Resolution 8 Bits
Relative Accuracy1 (INL) ±0.5 LSB
Differential Nonlinearity (DNL) ±0.5 LSB Guaranteed monotonic by design

AD5611

Resolution 10 Bits
Relative Accuracy1 (INL) ±4 ±0.5 LSB
Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design

Resolution 12 Bits
Relative Accuracy1 (INL) ±6 ±1 LSB

Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register
Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register
Offset Error ±0.063 ±10 ±0.063 ±10 mV
Gain Error ±0.0004 ±0.037 ±0.0004 ±0.037 %FSR
Zero-Code Error Drift 5.0 5.0 µV/°C

Gain Temperature Coefficient 2.0 2.0 ppm

OUTPUT CHARACTERISTICS2

Output Voltage Range 0 V

DD

0 VDD V
Output Voltage Settling Time 6 10 6 10 µs Code ¼ scale to ¾ scale
Slew Rate 0.5 0.5 V/µs
Capacitive Load Stability 470 470 pF RL = ∞
1000 1000 pF RL = 2 kΩ
Output Noise Spectral Density 120 120

Noise 2 2 µV DAC code = midscale,

Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 0.2 nV-s

MIN

to T

, unless otherwise noted. Temperature range

MAX

FSR/°C

nV/√Hz

DAC code = midscale,1 kHz

0.1 Hz to 10 kHz bandwidth

LOGIC INPUTS

Input Current
Input High Voltage, V

1.4 1.4 V VDD = 2.7 V to 3.6 V
Input Low Voltage, V

0.6 0.6 V VDD = 2.7 V to 3.6 V
Pin Input Capacitance 3 3 pF

3

1.8 1.8 V VDD = 4.7 V to 5.5 V

INH

0.8 0.8 V VDD = 4.7 V to 5.5 V

INL

±2 ±2 µA

Rev. F | Page 3 of 24

AD5601/AD5611/AD5621 Data Sheet

VDD = ±2.7 V to ±3.6 V

0.2

0.2 µA

VIH = VDD and VIL = GND

t2 5 ns min

SCLK high time

t8

20

ns min

Minimum

high time

t

4

t

3

t

2

t

5

t

7

t

6

D0D1

D2D14D15

SYNC

SCLK

06853-002

t

9

t

1

t

8

D15 D14

SDIN

A Grade B Grade
Parameter Min Ty p Max Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD
IDD for Normal Mode DAC active and excluding load

current
VDD = ±4.5 V to ±5.5 V 75 100 75 100 µA VIH = VDD and VIL = GND
VDD = ±2.7 V to ±3.6 V 60 90 60 90 µA VIH = VDD and VIL = GND

IDD for All Power-Down Modes VIH = VDD and VIL = GND

VDD = ±4.5 V to ±5.5 V 0.5 0.5 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

96 96 % I

OUT/IDD

1

Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.

2

Guaranteed by design and characterization, not production tested.

3

Total current flowing into all pins.

= 2 mA and VDD = ±5 V

LOAD

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 3.

Parameter Limit1 Unit Test Conditions/Comments

2

t

33 ns min SCLK cycle time

1

MIN

to T

, unless otherwise noted. See Figure 2.

MAX

t3 5 ns min SCLK low time
t4 10 ns min

to SCLK falling edge setup time

SYNC
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 0 ns min SCLK falling edge to

SYNC

rising edge

SYNC

t9 13 ns min

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

rising edge to next SCLK falling edge ignored

SYNC

Figure 2. Timing Diagram

Rev. F | Page 4 of 24

Data Sheet AD5601/AD5611/AD5621

Maximum Junction Temperature

150°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A/B Grades) −40°C to +125°C

Storage Temperature Range −65°C to +160°C

SC70 Package

θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W

LFCSP Package

θJA Thermal Impedance 95°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD (Human Body Model) 2.0 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 5 of 24

AD5601/AD5611/AD5621 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16

SYNC

SDIN

AD5601/
AD5611/

25

AD5621

TOP VIEW

34

(Not to Scale)

V

OUT

GNDSCLK

V

DD

06853-003

Figure 3. 6-Lead SC70 Pin Configuration

1V

DD

2SCLK

3SDIN

NOTES:

1. CONNECT THE EXPOSED PAD TO GND.

Figure 4. 6-Lead LFCSP Pin Configuration

AD5601/
AD5611/
AD5621

TOP VIEW

(Not to Scale)

6V

5GND

4SYNC

Table 5. Pin Function Descriptions

SC70
Pin No.

1 4

LFCSP
Pin No.

Mnemonic Description

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input

SYNC

data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC.

2 2 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.

3 3 SDIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.

4 1 VDD

Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. V
decoupled to GND.

5 5 GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621.
6 6 V

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

OUT

EP Exposed Pad. Connect to GND.

OUT

DD

06853-053

should be

Rev. F | Page 6 of 24

Data Sheet AD5601/AD5611/AD5621

–1.0

–0.5

0

0.5

1.0

DAC CODE

INL ERROR (LSB)

06853-004

64 564 1064 1564 2064 2564 3064 3564 4064

VDD = V

REF

= 5V

T

A

= 25°C

0

16 116 216 316 416 516 616 716 816 916

DAC CODE

INL ERROR (LSB)

V

DD

= V

REF

= 5V

T

A

=

25°C

06853-005

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

0

4 54 104 154 204

DAC CODE

INL ERROR (LSB)

VDD = V

REF

= 5V

T

A

= 25°C

06853-006

–0.100

–0.075

–0.050

–0.025

0.025

0.050

0.075

0.100

–2.5

–1.5

–0.5

0.5

1.5

2.5

64 564 1064 1564 2064 2564 3064 3564

DAC CODE

TOTAL UNADJUS TED ERROR (LS B)

06853-007

0

1.0

2.0

–2.0

–1.0

V

DD

= V

REF

= 5V

T

A

= 25°C

4064

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

16 116 216 316 416 516 616 716 816 916

DAC CODE

TOTAL UNADJUS TED ERROR (LS B)

06853-008

V

DD

= V

REF

= 5V

T

A

= 25°C

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15

0.20

4 54 104 154 204

DAC CODE

TOTAL UNADJUS TED ERROR (LS B)

0

VDD = V

REF

= 5V

T

A

= 25°C

06853-009

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Typical AD5621 INL

Figure 6. Typical AD5611 INL

Figure 8. AD5621 Total Unadjusted Error (TUE)

Figure 9. AD5611 Total Unadjusted Error (TUE)

Figure 7. Typical AD5601 INL

Figure 10. AD5601 Total Unadjusted Error (TUE)

Rev. F | Page 7 of 24

AD5601/AD5611/AD5621 Data Sheet

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

0.20

64 564 1064 1564 2064 2564 3064 3564

DAC CODE

DNL ERROR (LS B)

VDD = 5V
T

A

= 25°C

0

06853-010

–0.05

–0.04

–0.03

–0.02

–0.01

0

0.01

0.02

0.03

0.04

0.05

16 116 216 316 416 516 616 716 816 916

DAC CODE

DNL ERROR (LSB)

V

DD

= 5V

T

A

= 25°C

06853-011

–0.010

–0.008

–0.006

–0.004

–0.002

0

0.002

0.004

0.006

0.008

0.010

4 54 104 154 204

DAC CODE

DNL ERROR (LSB)

06853-012

V

DD

= 5V

T

A

= 25°C

0

2

4

6

8

10

12

0.05456

0.05527

0.05599

0.05671

0.05742

0.05814

0.05885

0.06648

0.06710

0.06773

0.06835

0.06897

0.06960

0.07022

0.07084

0.07147

0.07209

0.07271

0.07334

IDD (mA)

NUMBER OF DEV ICES

06853-013

VDD = 5V
V

IH

= DV

DD

VIL = GND
T

A

= 25°C

V

DD

= 3V

V

IH

= DV

DD

V

IL

= GND

T

A

= 25°C

CH1 = 5V/DIV CH2 = 1V /DIV TI M E BAS E = 2µs/DIV

CH1 = SCLK

CH2 = V

OUT

06853-014

TA = 25°C
V

DD

= 5V

CH1 = 5V/DIV CH2 = 1V /DIV TI M E BAS E = 2µs/DIV

CH1 = SCLK

CH2 = V

OUT

TA = 25°C
V

DD

= 5V

06853-015

Figure 11. Typical AD5621 DNL

Figure 12. Typical AD5611 DNL

Figure 14. IDD Histogram (3 V/5 V)

Figure 15. Full-Scale Settling Time

Figure 13. Typical AD5601 DNL

Figure 16. Half-Scale Settling Time

Rev. F | Page 8 of 24