Analog Devices AD5304, AD5324, AD5314 Datasheet

2.5 V to 5.5 V, 500 ␮A, Quad Voltage Output

a

8-/10-/12-Bit DACs in 10-Lead microSOIC

FEATURES
AD5304

Four Buffered 8-Bit DACs in 10-Lead microSOIC

AD5314

Four Buffered 10-Bit DACs in 10-Lead microSOIC

AD5324

Four Buffered 12-Bit DACs in 10-Lead microSOIC

Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0–V

REF

Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Low Power, SPI™, QSPI™, MICROWIRE™, and

DSP-Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control

FUNCTIONAL BLOCK DIAGRAM

AD5304/AD5314/AD5324*

GENERAL DESCRIPTION

The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500 µA at 3 V. Their on-chip output amplifiers allow rail-to­rail output swing to be achieved with a slew rate of 0.7 V/µs.
A 3-wire serial interface is used which operates at clock rates
up to 30 MHz and is compatible with standard SPI, QSPI,
MICROWIRE and DSP interface standards.

The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. The parts contain a power-down feature that
reduces the current consumption of the device to 200 nA @ 5 V
(80 nA @ 3 V).

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.

V

DD

LDAC

INPUT

REGISTER

SCLK

SYNC

DIN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

INTERFACE

LOGIC

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

AD5304/AD5314/AD5324

GND

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REFIN

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

POWER-DOWN

LOGIC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

BUFFER

V

A

OUT

BBUFFER

V

OUT

V

CBUFFER

OUT

V

DBUFFER

OUT

AD5304/AD5314/AD5324–SPECIFICATIONS

GND; CL = 200 pF to GND; All specifications T

Parameter

1

DC PERFORMANCE

3, 4

B Version
Min Typ Max Unit Conditions/Comments

MIN

to T

unless otherwise noted.)

MAX

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5304

Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design Over All Codes

AD5314

Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design Over All Codes

AD5324

Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB

Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic by Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR See Figures 2 and 3
Gain Error ± 0.15 ± 1 % of FSR See Figures 2 and 3
Lower Deadband 20 60 mV Lower Deadband Exists Only If Offset Error Is Negative
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 0.25 V

REF

V

Input Impedance 37 45 kΩ Normal Operation

REF

5

5

5

5

5

–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR

DD

V

= 2 kΩ to GND or V

L

DD

>10 MΩ Power-Down Mode

Reference Feedthrough –90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 V This is a measure of the minimum and maximum drive

VDD – 0.001 V capability of the output amplifier.
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V

16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V

5 µs Coming Out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS

5

Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ± 10%

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V

VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V

Pin Capacitance 3 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

7

VDD = 4.5 V to 5.5 V 600 900 µAV
VDD = 2.5 V to 3.6 V 500 700 µAV

2.5 5.5 V

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 µAV
VDD = 2.5 V to 3.6 V 0.08 1 µAV

NOTES

1

See Terminology.

2

Temperature range: B Version: –40°C to +105°C; typical at 25°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,

= VDD and “Offset plus Gain” Error must be positive.

V

REF

7

IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Specifications subject to change without notice.

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

–2–

REV. B

AD5304/AD5314/AD5324

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time V

2

1

otherwise noted.)

B Version
Min Typ Max Unit Conditions/Comments

3

= VDD = 5 V

REF

AD5304 6 8 µs 1/4 Scale to 3/4 Scale
AD5314 7 9 µs 1/4 Scale to 3/4 Scale
AD5324 8 10 µs 1/4 Scale to 3/4 Scale

Change
Change
Change

to T

MIN

(40 Hex to C0 Hex)
(100 Hex to 300 Hex)

(400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology.

3

Temperature range: B Version: –40°C to +105°C

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

; typical at 25°C.

1, 2, 3

(VDD = 2.5 V to 5.5 V. All specifications T

, T

MIN

MAX

= 2 V ± 0.1 V p-p

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

unless otherwise noted)

MAX

Parameter VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 1.

Specifications subject to change without notice.

40 33 ns min SCLK Cycle Time
16 13 ns min SCLK High Time
16 13 ns min SCLK Low Time
0 0 ns min SYNC to SCLK Rising Edge Setup Time
5 5 ns min Data Setup Time

4.5 4.5 ns min Data Hold Time
0 0 ns min SCLK Falling Edge to SYNC Rising Edge
80 33 ns min Minimum SYNC High Time

MAX

unless

REV. B

SCLK

SYNC

DIN

t

1

t

t

t

8

DB15

t

4

t

6

t

5

3

2

DB0

t

7

Figure 1. Serial Interface Timing Diagram

–3–

AD5304/AD5314/AD5324

TOP VIEW

(Not to Scale)

10

9

8

7

6

1

2

3

4

5

V

DD

V

OUT

A

GND

DIN

SCLK

SYNC

V

OUT

D

AD5304/
AD5314/

AD5324

V

OUT

B

V

OUT

C

REFIN

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1, 2

PIN CONFIGURATION

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

A–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . 150°C

J

10-Lead microSOIC Package

Power Dissipation . . . . . . . . . . . . . . . . . . (T

max – TA)/θ

J

JA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W

θ

JC

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V
3V
4V

DD

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
6V

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.

.

DD

7 GND Ground Reference Point for All Circuitry on the Part.
8 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input. The DIN input buffer is powered down after each write cycle.

9 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

10 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is
taken high before the sixteenth falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

AD5304BRM –40°C to +105°C 10-Lead microSOIC RM-10 DBB
AD5314BRM –40°C to +105°C 10-Lead microSOIC RM-10 DCB
AD5324BRM –40°C to +105°C 10-Lead microSOIC RM-10 DDB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5304/AD5314/AD5324 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD5304/AD5314/AD5324

TERMINOLOGY
RELATIVE ACCURACY

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono­tonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dBs. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

DC CROSSTALK

This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated. It is expressed in dBs.

DIGITAL CROSSTALK

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.

DAC-TO-DAC CROSSTALK

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.

GAIN ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

(1mV)

NEGATIVE

OFFSET

ERROR

IDEAL

DAC CODE

DEADBAND CODES

OFFSET ERROR

ACTUAL

PLUS

Figure 2. Transfer Function with Negative Offset

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the device
when the DAC output is not being written to (SYNC held high). It
is specified in nV-secs and is measured with a worst-case change on
the digital input pins, e.g., from all 0s to all 1s or vice versa.

REV. B

–5–

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ACTUAL

IDEAL

DAC CODE

Figure 3. Transfer Function with Positive Offset