ANALOG DEVICES AD5317R Service Manual

with 2 ppm/°C Reference, SPI Interface

AD5317R

Rev. 0

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Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

V

V

GNDV

10800-001

Data Sheet

FEATURES

Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment
Programmable attenuators
Industrial automation
Data acquisition systems

LOGIC

SCLK

SYNC

SDIN

SDO

Quad, 10-Bit nanoDAC

FUNCTIONAL BLOCK DIAGRAM

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN
×1/×2

REFERENCE

AD5317R

INTERFACE LOGIC

LDAC RESET

DD

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

POWER-ON

RESET

RSTSEL GAIN

Figure 1.

2.5V

BUFFER

BUFFER

BUFFER

BUFFER

POWER-

DOWN
LOGIC

®

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

GENERAL DESCRIPTION

The AD5317R, a member of the nanoDAC® family, is a low
power, quad, 10-bit buffered voltage output DAC. The device
includes a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The device operates from a single

2.7 V to 5.5 V supply, is guaranteed monotonic by design, and
exhibits less than 0.1% FSR gain error and 1.5 mV offset error
performance. The device is available in a 3 mm × 3 mm LFCSP
and a TSSOP package.

The AD5317R also incorporates a power-on reset circuit and a
RSTSEL pin that ensures that the DAC outputs power up to
zero scale or midscale and remain at that level until a valid write
takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.

The AD5317R employs a versatile SPI interface that operates at
clock rates up to 50 MHz and contains a V

1.8 V/3 V/5 V logic.

pin intended for

LOGIC

Table 1. Related Devices

Interface Reference 12-Bit 10-Bit

SPI Internal AD5684R
External AD5684 AD53171
I2C Internal AD5694R AD5316R
External AD5694 AD5316

1

The AD5317 and AD5317R are not pin-to-pin or software compatible.

PRODUCT HIGHLIGHTS

1. Precision DC Performance.

Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without n otice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5317R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 5

Timing Characteristics ................................................................ 6

Daisy-Chain and Readback Timing Characteristics................ 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 19

Digital-to-Analog Converter .................................................... 19

Transfer Function ....................................................................... 19

DAC Architecture ....................................................................... 19

Serial Interface ............................................................................ 20

Standalone Operation ................................................................ 21

Write and Update Commands .................................................. 21

Daisy-Chain Operation ............................................................. 21

Readback Operation .................................................................. 22

Power-Down Operation ............................................................ 22

Load DAC (Hardware
LDAC

Mask Register ................................................................. 23

Hardware Reset (

Reset Select Pin (RSTSEL) ........................................................ 24

Internal Reference Setup ........................................................... 25

Solder Heat Reflow ..................................................................... 25

Long-Term Temperature Drift ................................................. 25

Thermal Hysteresis .................................................................... 25

Applications Information .............................................................. 26

Microprocessor Interfacing ....................................................... 26

AD5317R to ADSP-BF531 Interface ....................................... 26

AD5317R to SPORT Interface .................................................. 26

Layout Guidelines....................................................................... 26

Galvanically Isolated Interface ................................................. 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

LDAC

Pin) ........................................... 23

) .......................................................... 24

RESET

REVISION HISTORY

7/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

Data Sheet AD5317R

Full-Scale Error

+0.01

±0.1

% of FSR

All 1s loaded to DAC register

REF

REF

10 nF

RL = 1 kΩ

7, 8

Output Voltage Noise Density2

240 nV/√Hz

At ambient; f = 10 kHz, CL = 10 nF

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE1

Resolution 10 Bits
Relative Accuracy ±0.12 ±0.5 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register
Offset Error +0.1 ±1.5 mV

Gain Error ±0.02 ±0.1 % of FSR
Total Unadjusted Error ±0.01 ±0.1 % of FSR External reference; gain = 2; TSSOP
±0.2 % of FSR Internal reference; gain = 1; TSSOP
Offset Error Drift
Gain Temperature Coefficient2 ±1 ppm Of FSR/°C
DC Power Supply Rejection Ratio2 0.15 mV/V DAC code = mi dscale; VDD = 5 V ± 10%
DC Crosstalk2 ±2 µV Due to single channel, full-scale output change
±3 µV/mA Due to load current change
±2 µV Due to power-down (per channel)

OUTPUT CHARACTERISTICS2

Output Voltage Range 0 V
0 2 × V
Capacitive Load Stability 2 nF RL = ∞

= 2.5 V; 1.8 V ≤ V

REF

2

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

±1 µV/°C

V Gain = 1

V Gain = 2, see Figure 29

, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.

MAX

Resistive Load3 1 kΩ
Load Regulation 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ I

+30 mA

80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ I

+20 mA
Short-Circuit Current4 40 mA
Load Impedance at Rails5 25 Ω See Figure 29
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT

Output Voltage6 2.4975 2.5025 V At ambient
Reference TC

2 5 ppm/°C See the Terminology section
Output Impedance2 0.04 Ω
Output Voltage Noise2 12 µV p-p 0.1 Hz to 10 Hz

Load Regulation, Sourcing2 20 µV/mA At ambient
Load Regulation, Sinking2 40 µV/mA At ambient
Output Current Load Capability2

±5

mA VDD ≥ 3 V
Line Regulation2 100 µV/V At ambient
Long-Term Stability/Drift2 12 ppm After 1000 hours at 125°C
Thermal Hysteresis2 125 ppm First cycle
25 ppm Additional cycles

OUT

OUT

≤

≤

Rev. 0 | Page 3 of 28

AD5317R Data Sheet

INL

LOGIC

INH

LOGIC

Pin Capacitance

2

pF

SINK

LOGIC

SOURCE

LOGIC

LOGI C

REF

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS2

Input Current ±2 µA Per pin
Input Low Voltage, V
Input High Voltage, V

LOGIC OUTPUTS (SDO)2

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH V
Floating State Output

Capacitance

POWER REQUIREMENTS

V
I
VDD 2.7 5.5 V Gain = 1
V
IDD VIH = VDD, VIL = G ND, VDD = 2.7 V to 5.5 V

Normal Mode9 0.59 0.7 mA Internal reference off

1.1 1.3 mA Internal reference on, at full scale
All Power-Down Modes10 1 4 µA −40°C to +85°C

6 µA −40°C to +105°C

1

DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when V

with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.

V

DD

2

Guaranteed by design and characterization; not production tested.

3

Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to

30 mA up to a junction temperature of 110°C.

4

VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.

5

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 29).

6

Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Terminology section.

7

Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.

8

Reference temperature coefficient calculated as per the box method. See the Terminology section for more information.

9

Interface inactive. All DACs active. DAC outputs unloaded.

10

All DACs powered down.

0.3 × V

0.7 × V

V

− 0.4 V I

4 pF

1.8 5.5 V
3 µA

+ 1.5 5.5 V Gain = 2

V

= 200 μA

= 200 μA

= VDD with gain = 1 or when V

REF

/2 =

REF

Rev. 0 | Page 4 of 28

Data Sheet AD5317R

OUT

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; V
otherwise noted.

1

Table 3.

Parameter2 Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±1 LSB
Slew Rate 0.8 V/µs
Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry
Digital Feedthrough 0.13 nV-sec
Digital Crosstalk 0.1 nV-sec
Analog Crosstalk 0.2 nV-sec
DAC-to-DAC Crosstalk 0.3 nV-sec
Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, VDD = 5 V, f
Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz, gain = 2
Output Noise 6 µV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical @ 25°C.

4

Digitally generated sine wave @ 1 kHz.

= 2.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ V

REF

≤ 5.5 V; all specifications T

LOGIC

to T

MIN

= 1 kHz

MAX

, unless

Rev. 0 | Page 5 of 28

AD5317R Data Sheet

LOGIC

LOGIC

Data Setup Time

t5 8 5

ns

t

4

t

3

SCLK

SYNC

SDIN

t

1

t

2

t

5

t

6

t

7

t

8

DB23

t

9

t

10

t

11

LDAC

1

LDAC

2

t

12

1

ASYNCHRONOUS LDAC UPDATE MODE .

2

SYNCHRONOUS LDAC UPDATE MODE .

RESET

t

13

t

14

V

OUT

DB0

10800-002

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 2.7 V to 5.5 V, 1.8 V ≤ V

DD

Table 4.

1.8 V ≤ V
Parameter1 Symbol Min Max Min Max Unit

SCLK Cycle Time t1 33 20 ns
SCLK High Time t2 16 10 ns
SCLK Low Time t3 16 10 ns

to SCLK Falling Edge Setup Time t4 15 10 ns

SYNC

Data Hold Time t6 8 5 ns
SCLK Falling Edge to

Minimum

Falling Edge to SCLK Fall Ignore t9 16 10 ns

SYNC

Pulse Width Low t10 25 15 ns

LDAC

High Time t8 20 20 ns

SYNC

SCLK Falling Edge to
SCLK Falling Edge to

Minimum Pulse Width Low t13 30 30 ns

RESET

Pulse Activation Time t14 30 30 ns

RESET

Rising Edge t7 15 10 ns

SYNC

Rising Edge t11 30 20 ns

LDAC

Falling Edge t12 20 20 ns

LDAC

Power-Up Time2 4.5 4.5 µs

1

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V

2

Time to exit power-down to normal mode of AD5317R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.

LOGIC

≤ 5.5 V; V

= 2.5 V. All specifications T

REF

≤ VDD. Guaranteed by design and characterization; not production tested.

LOGIC

MIN

to T

, unless otherwise noted.

MAX

< 2.7 V 2.7 V ≤ V

≤ 5.5 V

Figure 2. Serial Write Operation

Rev. 0 | Page 6 of 28

Data Sheet AD5317R

LOGIC

LOGIC

200µA I

OL

200µA I

OH

VOH (MIN)

TO OUTPUT

PIN

C

L

20pF

10800-003

t

4

t

5

t

6

t

8

SDO

SDIN

SYNC

SCLK

4824

DB23 DB0 DB23 DB0

DB23

INPUT WORD FOR DAC NUNDEFINED

INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N

DB0

t

11

t

12

t

10

10800-004

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. V

Table 5.

1.8 V ≤ V
Parameter1 Symbol Min Max Min Max Unit

SCLK Cycle Time t1 66 40 ns
SCLK High Time t2 33 20 ns
SCLK Low Time t3 33 20 ns

to SCLK Falling Edge t4 33 20 ns

SYNC
Data Setup Time t5 5 5 ns

Data Hold Time t6 5 5 ns
SCLK Falling Edge to
Minimum
Minimum

SDO Data Valid from SCLK Rising Edge t10 36 25 ns
SCLK Falling Edge to

Rising Edge to SCLK Rising Edge t12 15 10 ns

SYNC

1

Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V

Circuit and Timing Diagrams

= 2.7 V to 5.5 V, 1.8 V ≤ V

DD

Rising Edge t7 15 10 ns

SYNC

High Time t8 60 30 ns

SYNC

High Time t9 60 30 ns

SYNC

Rising Edge t11 15 10 ns

SYNC

LOG IC

≤ 5.5 V; V

= 2.5 V. All specifications T

REF

< 2.7 V 2.7 V ≤ V

≤ VDD. Guaranteed by design and characterization; not production tested.

LOGIC

MIN

to T

, unless otherwise noted.

MAX

≤ 5.5 V

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Figure 4. Daisy-Chain Timing Diagram

Rev. 0 | Page 7 of 28

AD5317R Data Sheet

SYNC

t

8

t

6

SCLK

24

1

24

1

t

9

t

4

t

2

t

7

t

3

t

1

DB23 DB0 DB23 DB0

SDIN

NOP CONDITIONINPUT WORD SPECIFIES

REGIST E R TO BE READ

t

5

DB23 DB0 DB23 DB0

SDO

SELECTED REGISTER DATA

CLOCKED OUT

UNDEFINED

t

10

10800-005

Figure 5. Readback Timing Diagram

Rev. 0 | Page 8 of 28

Data Sheet AD5317R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to +7 V

LOGI C

V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 125°C
16-Lead TSSOP, θJA Thermal

Impedance, 0 Airflow (4-Layer Board)

16-Lead LFCSP, θJA Thermal

Impedance, 0 Airflow (4-Layer Board)

Reflow Soldering Peak

Temperature, Pb Free (J-STD-020)

ESD

HBM1 4 kV
FICDM 1.5 kV

1

Human body model (HBM) classification.

112.6°C/W

70°C/W

260°C

LOGI C

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 9 of 28