ANALOG DEVICES AD5313 Service Manual

2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail

V

FEATURES

AD5303: 2 buffered 8-bit DACs in 1 package

A version: ±1 LSB INL, B version: ±0.5 LSB INL

AD5313: 2 buffered 10-bit DACs in 1 package

A version: ±4 LSB INL, B version: ±2 LSB INL

AD5323: 2 buffered 12-bit DACs in 1 package

A version: ±16 LSB INL, B version: ±8 LSB INL 16-lead TSSOP package Micropower operation: 300 μA @ 5 V (including reference

current)

Power-down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to V Power-on-reset to 0 V SDO daisy-chaining option Simultaneous update of DAC outputs via Asynchronous

CLR Low power serial interface with Schmitt-triggered inputs On-chip rail-to-rail output buffer amplifiers

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

or 0 V to 2 V

REF

facility

REF

LDAC

Voltage Output 8-/10-/12-Bit DACs

AD5303/AD5313/AD5323

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-torail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference pins (one per DAC). These reference inputs may be configured as buffered or unbuffered inputs. The parts incorporate a poweron reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low clears both DACs to 0 V. The outputs of both DACs may be updated simultaneously using the asynchronous The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software-selectable output loads while in power-down mode. The parts may also be used in daisychaining applications using the SDO pin.

The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 1.5 mW at 5 V and 0.7 mW at 3 V, reducing to 1 μW in power-down mode.

CLR

LDAC

pin that

input.

FUNCTIONAL BLOCK DIAGRAM

DD

BUF A

POWER-ON

RESET

INPUT

REGISTER

SYNC

INTERFACE

DCEN

LOGIC

LDAC

INPUT

REGISTER

CLR PD

SCLK

DIN

SDO

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DAC

REGISTER

DAC

REGISTER

BUF B

V

A

REF

AD5303/AD5313/AD5323

STRING

DAC

POWER-DOWN

LOGIC

STRING

DAC

B

REF

Figure 1.

BUFFER

GAIN-SELECT

LOGIC

RESISTOR NETWORK

GNDV

A

V

OUT

B

V

OUT

00472-001

AD5303/AD5313/AD5323

REVISION HISTORY

6/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Table 4............................................................................ 8

Changes to the Ordering Guide.................................................... 25

8/03—Rev. 0 to Rev. A

Added A Version.................................................................Universal

Changes to Features.......................................................................... 1

Changes to Specifications................................................................ 2

Changes to Absolute Maximum Ratings....................................... 5

Changes to Ordering Guide............................................................ 5

Updated Outline Dimensions....................................................... 18

4/99—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD5303/AD5313/AD5323

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 1.

A Version

Parameter

DC PERFORMANCE

2

3, 4

Min Typ Max Min Typ Max Unit Conditions/Comments

1

B Version

AD5303

Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ± 0.15 ±0.5 LSB Differential Nonlinearity ±0.02 ±0.25 ± 0.02 ±0.25 LSB Guaranteed monotonic by design over

AD5313

Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ± 0.5 ±2 LSB Differential Nonlinearity ±0.05 ±0.5 ± 0.05 ±0.5 LSB Guaranteed monotonic by design over

AD5323

Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±8 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over

Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR

Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR

Lower Dead Band 10 60 10 60 mV

Offset Error Drift Gain Error Drift

Power Supply Rejection Ratio

DC Crosstalk5

DAC REFERENCE INPUTS

Input Range

REF

V

Input Impedance

REF

5

−12 −12 ppm of FSR/°C

−5 −5 ppm of FSR/°C

5

−60 −60 dB ΔVDD = ±10%

30 30 μV

5

1 VDD 1 VDD V Buffered reference mode V 0 V

0 VDD V Unbuffered reference mode

DD

>10 >10 MΩ Buffered reference mode 180 180 kΩ Unbuffered reference mode 0 V to V

90 90 kΩ Unbuffered reference mode 0 V to 2 V

Reference Feedthrough −90 −90 dB Frequency = 10 kHz Channel-to-Channel Isolation −80 −80 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage Maximum Output Voltage

5

6

0.001 0.001 V min

6

VDD − 0.001 VDD − 0.001 V max

DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 50 50 mA VDD = 5 V 20 20 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down mode;

5 5 μs Coming out of power-down mode;

1

all codes

all codes See

Figure 2 and Figure 3

See

Figure 2 and Figure 3

See

Figure 2 and Figure 3

output range, input

REF

impedance = R

DAC

output range, input

REF

DAC

This is a measure of the minimum and maximum drive capability of the output amplifier

= 5 V

V

DD

= 3 V

V

DD

Rev. B | Page 3 of 28

AD5303/AD5313/AD5323

A Version

Parameter

LOGIC INPUTS

2

5

Min Typ Max Min Typ Max Unit Conditions/Comments

1

B Version

1

Input Current ±1 ±1 μA

Input Low Voltage, VIL

0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V VDD = 3 V ± 10%

0.5 0.5 V VDD = 2.5 V

Input High Voltage, VIH

2.4 2.4 V VDD = 5 V ± 10%

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V VDD = 2.5 V

Pin Capacitance 2 3.5 2 3.5 pF

LOGIC OUTPUT (SDO)

5

VDD = 5 V ± 10%

Output Low Voltage 0.4 0.4 V I Output High Voltage 4.0 4.0 V I

SINK

SOURCE

= 2 mA

VDD = 3 V ± 10%

Output Low Voltage 0.4 0.4 V I Output High Voltage 2.4 2.4 V I

= 2 mA

SINK

SOURCE

= 2 mA Floating-State Leakage Current 1 1 μA DCEN = GND Floating-State Output

3 3 pF DCEN = GND

Capacitance

POWER REQUIREMENTS

VDD 2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes IDD (Normal Mode) Both DACs active and excluding load

currents VDD = 4.5 V to 5.5 V 300 450 300 450 μA VDD = 2.5 V to 3.6 V 230 350 230 350 μA

Both DACs in unbuffered mode;

= VDD and VIL = GND; in buffered

V

IH

mode, extra current is typically x μA

per DAC, where x = 5 μA + V

REF/RDAC

IDD (Full Power-Down)

VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 μA

1

Temperature range for Version A, Version B: −40°C to +105°C.

2

See the Terminology section.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V

and offset plus gain error must be positive.

REF

= VDD

Rev. B | Page 4 of 28

AD5303/AD5313/AD5323

R

V

GAIN ERROR

OUTPUT

VOLTAGE

IDEAL

PLUS

OFFSET ERRO

OUTPUT OLTAGE

ACTUAL

GAIN ERROR

PLUS

OFFSET ERROR

ACTUAL

POSITIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

(1mV)

NEGATIVE

OFFSET

ERROR

DAC CODE

DEAD BAND

Figure 2. Transfer Function with Negative Offset

IDEAL

POSITIVE

OFFSET

ERROR

Figure 3. Transfer Function with Positive Offset

DAC CODE

00472-006

0472-005

Rev. B | Page 5 of 28

AD5303/AD5313/AD5323

AC CHARACTERISTICS

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

1

MIN

to T

, unless otherwise noted.

MAX

Table 2.

A, B Version

Parameter

2

Min Typ Max

Output Voltage Settling Time V

3

Unit Conditions/Comments

= VDD = 5 V

REF

AD5303 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xc0) AD5313 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300)

AD5323 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xc00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry (011 . . . 11 to 100 . . . 00) Digital Feedthrough 0.10 nV-s Analog Crosstalk 0.01 nV-s DAC-to-DAC Crosstalk 0.01 nV-s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion −70 dB V

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range for Version A and Version B: −40°C to +105°C.

= 2 V ± 0.1 V p-p, unbuffered mode

REF

= 2.5 V ± 0.1 V p-p, frequency = 10 kHz

REF

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V; all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

1, 2, 3

Limit at T

(A, B Version)

MIN, TMAX

Unit Conditions/Comments

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 0 ns min

SYNC to SCLK rising edge setup time t5 5 ns min Data setup time t6 4.5 ns min Data hold time t7 0 ns min t8 100 ns min t9 20 ns min t10 20 ns min t11 20 ns min

4, 5

t

12

4, 5

t

20 ns max SCLK falling edge to SDO valid

13

5

t

14

5

t

15

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 4 and Figure 5.

4

These are measured with the load circuit of Figure 4.

5

Daisy-chain mode only (see Figure 47).

5 ns min SCLK falling edge to SDO invalid

0 ns min 10 ns min

SCLK falling edge to

Minimum

SYNC high time LDAC pulse width SCLK falling edge to CLR pulse width

SCLK falling edge to SYNC rising edge to SCLK rising edge

SYNC rising edge

LDAC rising edge

SYNC rising edge

Rev. B | Page 6 of 28

AD5303/AD5313/AD5323

S

2mA I

OL

TO OUTPUT

50pF

C

L

2mA I

1.6V

OH

00472-002

Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications

t

1

SCLK

t

8

YNC

DIN* DB15

LDAC

CLR

*

SEE THE INPUT SHIFT REGISTER SECTION.

t

4

t

6

t

5

t

3

Figure 5. Serial Interface Timing Diagram

2

DB0

t

7

t

9

t

10

t

11

00472-003

Rev. B | Page 7 of 28

AD5303/AD5313/AD5323

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V V

A, V

OUT

Operating Temperature Range

Industrial (A, B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ Max) 150°C 16-Lead TSSOP Package

Power Dissipation (TJ max − TA)/θJA

θJA Thermal Impedance 160°C/W

Lead Temperature JEDEC Industry Standard

1

Transient currents of up to 100 mA do not cause SCR latch-up.

B to GND −0.3 V to VDD + 0.3 V

OUT

Soldering J-STD-020

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 8 of 28

AD5303/AD5313/AD5323

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLR

LDAC

V

REF

V

REF

OUT

BUF A

BUF B

DD

B

A

1

2

AD5303/

3

AD5313/

4

AD5323

5

TOP VIEW

(Not to Scale)

6

7

8

16

SDO

15

GND

14

DIN

13

SCLK

12

SYNC

11

B

V

OUT

10

PD

9

DCEN

00472-004

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 2

CLR LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing

Active Low Control Input. Loads all zeros to both input and DAC registers.

this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows

the simultaneous update of both DAC outputs. 3 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. 4 V

5 V

6 V 7 BUF A

B

REF

A

REF

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state

of the BUF B pin. It has an input range from 0 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state

of the BUF A pin. It has an input range from 0 to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the

reference input is unbuffered. If it is tied high, the reference input is buffered. 8 BUF B

Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the

reference input is unbuffered. If it is tied high, the reference input is buffered. 9 DCEN

This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy

chain. The pin should be tied low if it is being used in standalone mode. 10

PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down

option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high

impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V). 11 V 12

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling

edges of the following 16 clocks. If

SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts

as an interrupt and the write sequence is ignored by the device. 13 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 14 DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input. The DIN input buffer is powered down after each write cycle. 15 GND Ground Reference Point for All Circuitry on the Part. 16 SDO

Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the

data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.

Rev. B | Page 9 of 28

ANALOG DEVICES AD5313 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS