Analog Devices AD5301 11 21 a Datasheet

2.5 V to 5.5 V, 120 ␮A, 2-Wire Interface,

a

FEATURES
AD5301: Buffered Voltage Output 8-Bit DAC
AD5311: Buffered Voltage Output 10-Bit DAC
AD5321: Buffered Voltage Output 12-Bit DAC
6-Lead SOT-23 and 8-Lead MSOP Packages
Micropower Operation: 120 ␮A @ 3 V
2-Wire (I
Data Readback Capability

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 50 nA @ 3 V
Reference Derived from Power Supply
Power-On Reset to 0 V
On-Chip Rail-to-Rail Output Buffer Amplifier
3 Power-Down Functions

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

2C®

Compatible) Serial Interface

Voltage Output 8-/10-/12-Bit DACs

AD5301/AD5311/AD5321

GENERAL DESCRIPTION

The AD5301/AD5311/AD5321 are single 8-bit, 10-bit, and 12-bit
buffered voltage-output DACs that operate from a single 2.5 V
to 5.5 V supply, consuming 120 µA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of

0.7 V/µs. It uses a 2-wire (I
operates at clock rates up to 400 kHz. Multiple devices can
share the same bus.

The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on reset circuit, which ensures that
the DAC output powers-up to 0 V and remains there until a
valid write takes place. The parts contain a power-down feature
that reduces the current consumption of the device to 50 nA
at 3 V and provides software-selectable output loads while in
power-down mode.

The low power consumption in normal operation make these
DACs ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 µW in all power-down modes.

2

C compatible) serial interface that

*

FUNCTIONAL BLOCK DIAGRAM

SCL

SDA

A0

A1*

*Protected by U.S. Patent No. 5684481, other patent pending.

INTERFACE

LOGIC

POWER-ON

RESET

GND

*AVAILABLE ON 8-LEAD VERSION ONLY

DAC

REGISTER

V

DD

REF

8-/10-/12-BIT
DAC

AD5301/AD5311/AD5321

BUFFER

POWER-DOWN

LOGIC

RESISTOR
NETWORK

PD*

V

OUT

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5301/AD5311/AD5321–SPECIFICATIONS

CL = 200 pF to GND; All specifications T

Parameter

DC PERFORMANCE

1

3, 4

to T

MIN

, unless otherwise noted.

MAX

B Version

2

Min Typ Max Unit Conditions/Comments

VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND;

AD5301

Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design over All Codes.

AD5311

Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design over All Codes.

AD5321

Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB

Differential Nonlinearity ± 0.3 ± 0.8 LSB Guaranteed Monotonic by Design over All Codes.
Zero-Code Error 5 20 mV All Zeros Loaded to DAC, See Figure 9.
Full-Scale Error ± 0.15 ± 1.25 % of FSR All Ones Loaded to DAC, See Figure 9.
Gain Error ± 0.15 ± 1% of FSR
Zero-Code Error Drift
Gain Error Drift

OUTPUT CHARACTERISTICS

5

5

5

–20 µV/°C
–5 ppm of FSR/°C

Minimum Output Voltage 0.001 V min This is a measure of the minimum and maximum drive
Maximum Output Voltage VDD– 0.001 V max capability of the output amplifier.
DC Output Impedance 1 Ω
Short-Circuit Current 50 mA VDD = 5 V.

20 mA VDD = 3 V.

Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V.

6 µs Coming Out of Power-Down Mode. VDD = 3 V.

LOGIC INPUTS (A0, A1, PD)

5

Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ± 10%.

0.6 V VDD = 3 V ± 10%.

0.5 V VDD = 2.5 V.

VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%.

2.1 V VDD = 3 V ± 10%.

2.0 V VDD = 2.5 V.

Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)

VIH, Input High Voltage 0.7 V
VIL, Input Low Voltage –0.3 0.3 V
IIN, Input Leakage Current ±1 µAV
V

, Input Hysteresis 0.05 V

HYST

CIN, Input Capacitance 6 pF
Glitch Rejection

6

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V I

5

DD

DD

VDD + 0.3 V

DD

V

= 0 V to VDD.

IN

V

50 ns Pulse Width of Spike Suppressed.

5

= 3 mA.

0.6 V I

SINK

SINK

= 6 mA.
Three-State Leakage Current ± 1 µA
Three-State Output Capacitance 6 pF

POWER REQUIREMENTS

V

DD

2.5 5.5 V IDD Specification Is Valid for All DAC Codes.

IDD (Normal Mode) DAC Active and Excluding Load Current.

VDD = 4.5 V to 5.5 V 150 250 µAV
VDD = 2.5 V to 3.6 V 120 220 µAV

= VDD and VIL = GND.

IH

= VDD and VIL = GND.

IH

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 µAV
VDD = 2.5 V to 3.6 V 0.05 1 µAV

NOTES

1

See Terminology.

2

Temperature range is as follows: B Version: –40°C to +105°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000).

5

Guaranteed by design and characterization, not production tested.

6

Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

= VDD and VIL = GND.

IH

= VDD and VIL = GND.

IH

Specifications subject to change without notice.

–2–

REV. A

AD5301/AD5311/AD5321

VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; All specifications T

AC CHARACTERISTICS

Parameter

2

1

otherwise noted.

B Version

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

DD

= 5 V

MIN

to T

MAX

, unless

AD5301 6 8 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5311 7 9 µs 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)

AD5321 8 10 µs 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Change Glitch Impulse 12 nV-s 1 LSB Change around Major Carry
Digital Feedthrough 0.3 nV-s

NOTES

1

See Terminology section.

2

Guaranteed by design and characterization, not production tested.

3

Temperature range is as follows: B Version: –40°C to +105°C.

Specifications subject to change without notice.

1

TIMING CHARACTERISTICS

Limit at T

MIN

, T

MAX

VDD = 2.5 V to 5.5 V. All specifications T

MIN

to T

, unless otherwise noted.

MAX

Parameter2(B Version) Unit Conditions/Comments

f
t
t
t
t
t
t

SCL

1

2

3

4

5

3

6

400 kHz max SCL Clock Frequency

2.5 µs min SCL Cycle Time

0.6 µs min t

1.3 µs min t

0.6 µs min t
100 ns min t

0.9 µs max t

, SCL High Time

HIGH

, SCL Low Time

LOW

, Start/Repeated Start Condition Hold Time

HD,STA

, Data Setup Time

SU,DAT

, Data Hold Time

HD,DAT

0 µs min

t

7

t

8

t

9

t

10

0.6 µs min t

0.6 µs min t

1.3 µs min t
300 ns max tR, Rise Time of Both SCL and SDA when Receiving

, Setup Time for Repeated Start

SU,STA

, Stop Condition Setup Time

SU,STO

, Bus Free Time Between a STOP Condition and a START Condition

BUF

0 ns min May be CMOS Driven

t

11

C

b

NOTES

1

See Figure 1.

2

Guaranteed by design and characterization, not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

SCL’s falling edge.

4

Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Specifications subject to change without notice.

250 ns max tF, Fall Time of SDA when Receiving
300 ns max t
20 + 0.1C

4

b

ns min

, Fall Time of Both SCL and SDA when Transmitting

F

400 pF max Capacitive Load for Each Bus Line

of the SCL signal) in order to bridge the undefined region of

IH MIN

REV. A –3–

AD5301/AD5311/AD5321

WARNING!

ESD SENSITIVE DEVICE

SDA

SCL

t

9

t

4

START

CONDITION

t

3

t

10

t

6

t

t

11

2

t

5

REPEATED

CONDITION

t

7

START

t

4

t

1

STOP

CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

SCL, SDA to GND . . . . . . . . . . . . . . . . –0.3 V to V

PD, A1, A0 to GND . . . . . . . . . . . . . . . –0.3 V to V

V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . . . 150°C

J

SOT-23 Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

max – TA)/θ

J

ΜSOP Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

max – TA)/θ

J

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

JA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6°C/W

ORDERING GUIDE

Temperature Package Package

Model Range Description Option Branding

AD5301BRM-REEL –40°C to +105°C MSOP RM-8 D8B
AD5301BRM-REEL7 –40°C to +105°C MSOP RM-8 D8B
AD5301BRT-500RL7 –40°C to +105°C SOT-23 RT-6 D8B
AD5301BRT-REEL –40°C to +105°C SOT-23 RT-6 D8B
AD5301BRT-REEL7 –40°C to +105°C SOT-23 RT-6 D8B
AD5301BRTZ-500RL7* –40°C to +105°C SOT-23 RT-6 D8B
AD5301BRTZ-REEL* –40°C to +105°C SOT-23 RT-6 D8B
AD5301BRTZ-REEL7* –40°C to +105°C SOT-23 RT-6 D8B
AD5311BRM-REEL –40°C to +105°C MSOP RM-8 D9B
AD5311BRM-REEL7 –40°C to +105°C MSOP RM-8 D9B
AD5311BRT-500RL7 –40°C to +105°C SOT-23 RT-6 D9B
AD5311BRT-REEL –40°C to +105°C SOT-23 RT-6 D9B
AD5311BRT-REEL7 –40°C to +105°C SOT-23 RT-6 D9B
AD5321BRM-REEL –40°C to +105°C MSOP RM-8 DAB
AD5321BRM-REEL7 –40°C to +105°C MSOP RM-8 DAB
AD5321BRT-500RL7 –40°C to +105°C SOT-23 RT-6 DAB
AD5321BRT-REEL –40°C to +105°C SOT-23 RT-6 DAB
AD5321BRT-REEL7 –40°C to +105°C SOT-23 RT-6 DAB

*Z = Pb-free part.

t

8

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5301/AD5311/AD5321 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

PIN CONFIGURATIONS

AD5301/AD5311/AD5321

6-Lead SOT-23

(RT-6)

1

GND

AD5301/
AD5311/

2

SDA

SCL

AD5321

3

TOP VIEW

(Not to Scale)

6

V

DD

5

A0

4

V

OUT

8-Lead MSOP

(RM-8)

V

1

DD

AD5301/

2

A0

AD5311/

AD5321

3

A1

TOP VIEW

4

V

OUT

(Not to Scale)

8

GND

7

SDA

6

SCL

5

PD

PIN FUNCTION DESCRIPTION

MSOP SOT-23
Pin No. Pin No. Mnemonic Function

16V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply

should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to GND.
25A0 Address Input. Sets the least significant bit of the 7-bit slave address.
3 N/A A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
44V

OUT

Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
5 N/A PD Active Low Control Input that Acts as a Hardware Power-Down Option. This pin overrides any

software power-down option. The DAC output goes three-state and the current consumption

of the part drops to 50 nA @ 3 V (200 nA @ 5 V).
63SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit

input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I

2

C compat-

ible interface. SCL may be CMOS/TTL driven.
72SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit

input shift register during the write cycle and to read back one or two bytes of data

(one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is

a bidirectional open-drain data line that should be pulled to the supply with an external

pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven.
81GND Ground Reference Point for All Circuitry on the Part.

REV. A

–5–