ANALOG DEVICES AD5301 Service Manual

2.5 V to 5.5 V, 120 μA, 2-Wire Interface,

V

A

FEATURES

AD5301: buffered voltage output 8-bit DAC
AD5311: buffered voltage output 10-bit DAC
AD5321: buffered voltage output 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 120 μA @ 3 V
2-wire (I
Data readback capability

2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 50 nA @ 3 V
Reference derived from power supply
Power-on reset to 0 V
On-chip rail-to-rail output buffer amplifier
3 power-down functions

APPLICATIONS

Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

2

C®-compatible) serial interface

Voltage-Output 8-/10-/12-Bit DACs

AD5301/AD5311/AD5321

GENERAL DESCRIPTION

The AD5301/AD5311/AD53211 are single 8-/10-/12-bit, buff­ered, voltage-output DACs that operate from a single 2.5 V to

5.5 V supply, consuming 120 μA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of

0.7 V/μs. It uses a 2-wire (I
operates at clock rates up to 400 kHz. Multiple devices can share
the same bus.

The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on reset circuit, which ensures that
the DAC output powers up to 0 V and remains there until a
valid write takes place. The parts contain a power-down feature
that reduces the current consumption of the device to 50 nA at
3 V and provides software-selectable output loads while in
power-down mode.

The low power consumption in normal operation makes these
DACs ideally suited to portable battery-operated equipment. The
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 μW in all power-down modes.

1

Protected by U.S. Patent No. 5684481.

2

C-compatible) serial interface that

FUNCTIONAL BLOCK DIAGRAM

SCL

SD

A0

A1*

*AVAILABLE O N 8-LEAD VERSI ON ONLY

INTERFACE

LOGIC

POWER-ON

RESET

GND

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

DAC

REGISTER

DD

REF

8-/10-/12-BIT

DAC

Figure 1.

AD5301/AD5311/AD5321

BUFFER

POWER-DOWN

LOGIC

RESISTOR
NETWORK

PD*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1999–2007 Analog Devices, Inc. All rights reserved.

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OUT

00927-001

AD5301/AD5311/AD5321

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Terminology ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 13

Digital-to-Analog .......................................................................13

Resistor String............................................................................. 13

Output Amplifier........................................................................ 13

Power-On Reset.......................................................................... 13

Serial Interface ................................................................................ 14

2-Wire Serial Bus........................................................................ 14

Input Shift Register .................................................................... 14

Write Operation.......................................................................... 15

Read Operation........................................................................... 16

Power-Down Modes .................................................................. 17

Application Notes........................................................................... 18

Using REF19x as a Power Supply ............................................. 18

Bipolar Operation Using the AD5301/AD5311/AD5321..... 18

Multiple Devices on One Bus ................................................... 18

CMOS Driven SCL and SDA Lines.......................................... 18

Power Supply Decoupling......................................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 21

REVISION HISTORY

3/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Table 4............................................................................ 6

Changes to Figure 4 Caption........................................................... 7

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 21

11/03—Rev. 0 to Rev. A

Changes to Ordering Guide............................................................ 4

Updated Outline Dimensions....................................................... 15

7/99—Revision 0: Initial Version

Rev. B | Page 2 of 24

AD5301/AD5311/AD5321

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

B Version
Parameter

DC PERFORMANCE

2

3, 4

Min Typ Max Unit Conditions/Comments

1

AD5301

Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes.

AD5311

Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes.

AD5321

Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB

Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed monotonic by design over all codes.
Zero-Code Error 5 20 mV All zeros loaded to DAC, see Figure 12.
Full-Scale Error ±0.15 ±1.25 % of FSR All ones loaded to DAC, see Figure 12.
Gain Error ±0.15 ±1 % of FSR
Zero-Code Error Drift
Gain Error Drift

OUTPUT CHARACTERISTICS

Minimum Output Voltage 0.001 V
Maximum Output Voltage VDD − 0.001 V

5

5

–20 μV/°C

−5 ppm of FSR/°C

5

This is a measure of the minimum and maximum
drive capability of the output amplifier.

DC Output Impedance 1 Ω
Short-Circuit Current 50 mA VDD = 5 V.
20 mA VDD = 3 V.
Power-Up Time 2.5 μs Coming out of power-down mode. VDD = 5 V.
6 μs Coming out of power-down mode. VDD = 3 V.

5

LOGIC INPUTS (A0, A1, PD)

Input Current ±1 μA
Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%.

0.6 V VDD = 3 V ± 10%.

0.5 V VDD = 2.5 V.

Input High Voltage, VIH 2.4 V VDD = 5 V ± 10%.

2.1 V VDD = 3 V ± 10%.

2.0 V VDD = 2.5 V.
Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)5

Input High Voltage, VIH 0.7 × VDD VDD + 0.3 V
Input Low Voltage, VIL −0.3 +0.3 × VDD V
Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD.
Input Hysteresis, V

0.05 × VDD V

HYST

Input Capacitance, CIN 6 pF
Glitch Rejection

6

50 ns Pulse width of spike suppressed.

Rev. B | Page 3 of 24

AD5301/AD5311/AD5321

B Version1
Parameter

LOGIC OUTPUT (SDA)

Output Low Voltage, VOL 0.4 V I

0.6 V I
Three-State Leakage

Current
Three-State Output

POWER REQUIREMENTS

VDD 2.5 5.5 V IDD specification is valid for all DAC codes.
IDD (Normal Mode) DAC active and excluding load current.

IDD (Power-Down Mode)

1

Temperature range is as follows: B Version: −40°C to +105°C.

2

See the Terminology section.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000).

5

Guaranteed by design and characterization, not production tested.

6

Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

2

5

Min Typ Max Unit Conditions/Comments

= 3 mA.

SINK

= 6 mA.

SINK

±1 μA

6 pF

Capacitance

VDD = 4.5 V to 5.5 V 150 250 μA VIH = VDD and VIL = GND.
VDD = 2.5 V to 3.6 V 120 220 μA VIH = VDD and VIL = GND.

VDD = 4.5 V to 5.5 V 0.2 1 μA VIH = VDD and VIL = GND.
VDD = 2.5 V to 3.6 V 0.05 1 μA VIH = VDD and VIL = GND.

Rev. B | Page 4 of 24

AD5301/AD5311/AD5321

AC CHARACTERISTICS

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 2.

B Version
Parameter

3

Output Voltage Settling Time VDD = 5 V

AD5301 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5311 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5321 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)

Slew Rate 0.7 V/μs
Major-Code Change Glitch Impulse 12 nV-s 1 LSB change around major carry
Digital Feedthrough 0.3 nV-s

1

See the Terminology section.

2

Temperature range for the B Version is as follows: –40°C to +105°C.

3

Guaranteed by design and characterization, not production tested.

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V; all specifications T

Table 3.

Limit at T

Parameter2(B Version) Unit Conditions/Comments

f

400 kHz max SCL clock frequency

SCL

t1 2.5 μs min SCL cycle time
t2 0.6 μs min t
t3 1.3 μs min t
t4 0.6 μs min t
t5 100 ns min t

3

t

6

0 μs min
t7 0.6 μs min t
t8 0.6 μs min t
t9 1.3 μs min t
t10 300 ns max tR, rise time of both SCL and SDA when receiving
0 ns min May be CMOS driven
t11 250 ns max tF, fall time of SDA when receiving
300 ns max tF, fall time of both SCL and SDA when transmitting
20 + 0.1C
Cb 400 pF max Capacitive load for each bus line

1

See Figure 2.

2

Guaranteed by design and characterization, not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the V

falling edge.

4

tR and tF measured between 0.3 VDD and 0.7 VDD.

5

Cb is the total capacitance of one bus line in picofarads.

0.9 μs max t

1

to T

MIN

2

, unless otherwise noted.

MAX

Min Typ Max Unit Conditions/Comments

1

to T

MIN

, T

MIN

5

b

MAX

ns min

, unless otherwise noted.

MAX

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD,STA

data setup time

SU,DAT,

, data hold time

HD,DAT

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a stop condition and a start condition

BUF

4

4

4

of the SCL signal) in order to bridge the undefined region of SCL’s

IH MIN

SDA

SCL

t

9

t

4

START

CONDIT ION

t

3

t

10

t

6

Figure 2. 2-Wire Serial Interface Timing Diagram

t

11

t

2

t

t

5

7

REPEATED

START

CONDITIO N

t

4

t

1

t

8

STOP

CONDITION

00927-002

Rev. B | Page 5 of 24

AD5301/AD5311/AD5321

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V
SCL, SDA to GND −0.3 V to VDD + 0.3 V
PD, A1, A0 to GND
V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
SOT-23 Package

Power Dissipation (TJ max − TA)/θJA

θJA Thermal Impedance 229.6°C/W
MSOP Package

Power Dissipation (TJ max – TA)/θJA

θJA Thermal Impedance 206°C/W
Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

1

Transient currents of up to 100 mA do not cause SCR latch-up.

−0.3 V to V

+ 0.3 V

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 6 of 24

AD5301/AD5311/AD5321

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

DD

1

AD5301/
AD5311/

2

A0

AD5321

3

A1

TOP VIEW

4

OUT

(Not to Scale)

Figure 3. 8-Lead MSOP

(RM-8) Pin Configuration

1

SCL

AD5301/
AD5311/

2

AD5321

TOP VIEW

(Not to Scale)

3

8

GND

7

SDA

6

SCL

5

PD

00927-004

SDA

Figure 4. 6-Lead SOT-23

(RJ-6) Pin Configuration

6

5

4

GND

Table 5. Pin Function Descriptions

MSOP
Pin No.

1 6 VDD

SOT-23
Pin No.

Mnemonic Description

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 μF in parallel with a 0.1 μF capacitor to GND.
2 5 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
3 N/A A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
4 4 V
5 N/A

Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

OUT

PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software

power-down option. The DAC output goes three-state and the current consumption of the part

drops to 50 nA @ 3 V (200 nA @ 5 V).
6 3 SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift

register. Clock rates of up to 400 kbps can be accommodated in the I

2

C-compatible interface. SCL may

be CMOS/TTL driven.
7 2 SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift

register during the write cycle and to read back one or two bytes of data (one byte for the AD5301,

two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain data line that

should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may

be CMOS/TTL driven.
8 1 GND Ground Reference Point for All Circuitry on the Part.

V

DD

A0

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OUT

0927-003

Rev. B | Page 7 of 24

AD5301/AD5311/AD5321

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL vs. code plots can be seen in
Figure 7.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonic­ity. These DACs are guaranteed monotonic by design over all
codes. Typical DNL vs. code plots can be seen in
Figure 10.

Zero-Code Error

Zero-code error is a measure of the output error when zero
code (0x00) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error of the AD5301/AD5311/
AD5321 is always positive because the output of the DAC
cannot go below 0 V, due to a combination of the offset errors
in the DAC and output amplifier. It is expressed in millivolts,
see

Figure 12.

Full-Scale Error (FSR)

Full-scale error is a measure of the output error when full
scale is loaded to the DAC register. Ideally, the output should
be V

– 1 LSB. Full-scale error is expressed in percent of FSR.

DD

A plot can be seen in

Figure 12.

Figure 5 to

Figure 8 to

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.

Major Code Transition Glitch Energy

Major code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB
at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00
to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s and vice versa.

Rev. B | Page 8 of 24