ANALOG DEVICES AD5262 Service Manual
1-/2-Channel
S
S
R
WB
R
WA
CODE – Decimal
100
064128192 256
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % R
AB
75
50
25
0
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a
FEATURES
256 Positions
AD5260 – 1-Channel
AD5262 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20 k⍀, 50 k⍀, 200 k⍀
Low Temperature Coefficient 35 ppm/ⴗC
4-Wire SPI-Compatible Serial Data Input
5 V to 15 V Single-Supply; ⴞ5.5 V Dual-Supply Operation
Power ON Mid-Scale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Stereo Channel Audio Level Control
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Low Resolution DAC Replacement
GENERAL DESCRIPTION
The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device.* These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5260/
AD5262 contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by a digital code loaded
into the SPI-compatible serial-input register. The resistance between
the wiper and either end point of the fixed resistor varies linearly
with respect to the digital code transferred into the VR latch. The
variable resistor offers a completely programmable value of resistance,
between the A terminal and the wiper or the B terminal and the wiper.
The fixed A to B terminal resistance of 20 kW, 50 kW, or 200 kW has
a nominal temperature coefficient of 35 ppm/∞C. Unlike the majority
of the digital potentiometers in the market, these devices can operate
up to 15 V or ± 5 V provided proper supply voltages are furnished.
Each VR has its own VR latch, which holds its programmed resistance
value. These VR latches are updated from an internal serial-to-parallel
shift register, which is loaded from a standard 3-wire serial-input
digital interface. The AD5260 contains an 8-bit serial register
while the AD5262 contains a 9-bit serial register. Each bit is clocked
into the register on the positive edge of the CLK. The AD5262
address bit determines the corresponding VR latch to be loaded
with the last 8 bits of the data word during the positive edging of
CS strobe. A serial data output pin at the opposite end of the serial
register enables simple daisy chaining in multiple VR applications
without additional external decoding logic. An optional reset pin
(PR) forces the wiper to the mid-scale position by loading 80
the VR latch.
*The terms digital potentiometers, VR, and RDAC are used interchangeably.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
15 V Digital Potentiometers
AD5260/AD5262
FUNCTIONAL BLOCK DIAGRAMS
AWB
HDN
V
DD
V
SS
V
L
CS
CLK
SDI
GND
HDN
V
DD
V
SS
V
L
CS
CLK
SDI
GND
into
H
RDAC
REGISTER
LOGIC
SERIAL INPUT REGISTER
A1 W1 B1
RDAC1 REGISTER
LOGIC
SERIAL INPUT REGISTER
AD5262
Figure 1. RWA and RWB vs. Code
The AD5260/AD5262 are available in thin surface-mount TSSOP-14
and TSSOP-16 packages. All parts are guaranteed to operate over
the extended industrial temperature range of –40∞C to +85∞C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD5260
POWER-ON
RESET
8
A2 W2 B2
RDAC2 REGISTER
POWER-ON
RESET
8
PR
SDO
PR
SDO
(VDD = +15 V, VSS = 0 V or, VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +5 V,
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AD5260/AD5262–SPECIFICATIONS
VB = 0 V, – 40ⴗC < TA < +85ⴗC unless otherwise noted.)
ELECTRICAL CHARACTERISTICS 20 kW, 50 kW, 200 kW VERSIONS
Parameter Symbol Conditions Min Typ
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R
Channel Resistance Matching (AD5262 only) R
Resistance Drift R
2
2
3
R-DNL RWB, VA=NC –1 ± 1/4 +1 LSB
R-INL RWB, VA=NC –1 ± 1/2 +1 LSB
R
AB
/TWiper = No Connect 35 ppm/∞C
AB
W
WB/RWB
AB
TA = 25∞C –30 30 %
IW = 1 V/R
Ch 1 and 2 R
AB
WB, DX = 80H
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution N 8 Bits
Differential Nonlinearity
Integral Nonlinearity
Voltage Divider Temperature Coefficient DV
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
Capacitance
5
6
Ax, Bx C
Capacitance6 Wx C
Common-Mode Leakage Current I
Shut Down Current
4
4
7
DNL –1 ± 1/4 +1 LSB
INL –1 ± 1/2 +1 LSB
/DTCode = 80
WFSE
WZSE
V
A, B, W
A,B
W
CM
I
SHDN
W
Code = FF
Code = 00
f = 5 MHz, 25 pF
measured to GND, Code = 80
f = 1 MHz, 55 pF
measured to GND, Code = 80
VA =VB = V
H
H
H
H
/2 1 nA
DD
H
–2 –1 +0 LSB
01 2LSB
V
SS
DIGITAL INPUTS and OUTPUTS
Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High (SDO) V
Output Logic Low (SDO) V
Input Current
Input Capacitance
8
6
IH
IL
IH
IL
OH
OL
I
IL
C
IL
VL = 3 V, VSS = 0 V 2.1 V
VL = 3 V, VSS = 0 V 0.6 V
R
IOL = 1.6 mA, V
= 2 kW to 5 V 4.9 V
PULL-UP
= 5 V 0.4 V
LOGIC
VIN = 0 V or 5 V ± 1 mA
2.4 V
POWER SUPPLIES
Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V
Logic Supply Current I
Positive Supply Current I
Negative Supply Current I
Power Dissipation
9
L
DD RANGE
DD/SS RANGE
L
DD
SS
P
DISS
VSS = 0 V 4.5 16.5 V
VL =5 V 60 mA
VIH = 5 V or VIL = 0 V 1 mA
VSS = –5 V 1 mA
VIH = 5 V or VIL = 0 V, 0.3 mW
= +5 V, VSS = –5 V
V
DD
2.7 5.5 V
± 4.5 ± 5.5 V
Power Supply Sensitivity PSS DVDD = +5 V, ± 10% 0.003 0.01 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW RAB = 20 kW/50 kW/200 kW 310/130/30 kHz
Total Harmonic Distortion THD
V
Settling Time t
W
Crosstalk
11
S
C
T
W
VA = 1 V
f=1 kHz, R
VA = +5 V, VB = –5 V, 5 ms
± 1 LSB error band, R
VA = VDD, VB=0 V,
Measure V
, VB = 0 V, 0.014 %
RMS
= 20 kW
AB
= 20 kW
AB
with Adjacent
W
RDAC Making Full-Scale 1 nV–s
Code Change (AD5262 only)
Analog Crosstalk C
Resistor Noise Voltage e
TA
N_WB
VA1= VDD, VB1= 0V,
Measure V
= 5 V p-p @ f = 10 kHz, –64 dB
V
W2
R
= 20 kW/200 kW (AD5262 only)
AB
W1
with
RWB = 20 kW 13 nV/÷Hz
f = 1 kHz
1
Max Unit
60 150 W
0.1 %
0.05 %
5 ppm/∞C
V
DD
5 mA
0.8 V
5pF
V
–2–
REV. 0
AD5260/AD5262
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Parameter Symbol Conditions Min Typ Max Unit
INTERFACE TIMING CHARACTERISTICS apply to all parts
Clock Frequency f
Input Clock Pulsewidth t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay
13
CS Setup Time t
CS High Pulsewidth t
Reset Pulsewidth t
CLK Fall to CS Rise Hold Time t
CS Rise to Clock Rise Setup t
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
1
Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
3
VAB = VDD, Wiper (VW) = No connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9
P
is calculated from (IDD ⫻ VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
10
All dynamic characteristics use VDD = +5 V, VSS = –5 V, VL = +5 V.
11
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
12
See timing diagram for location of measured values. All input control voltages are specified with tR=tF= 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V.
13
Propagation delay depends on value of VDD, RL, and CL.
Specifications subject to change without notice.
CLK
CH
DS
DH
t
PD
CSS
CSW
RS
CSH
CS1
, t
CL
6, 12
25 MHz
Clock level high or low 20 ns
10 ns
10 ns
RL = 1 kΩ, CL < 20pF 1 160 ns
5ns
20 ns
50 ns
0ns
10 ns
= VDD/R for both VDD= +5 V, VSS=–5V.
W
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted.)
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
SS
V
to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
DD
V
, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V
A
AX – BX, AX – WX, BX – W
X
DD
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
) . . . . . . . . . . . 150°C
J MAX
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance
3
θ
JA
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3
Package Power Dissipation = (T
J MAX
– TA)/ θ
JA
REV. 0
–3–
AD5260/AD5262
WARNING!
ESD SENSITIVE DEVICE
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ORDERING GUIDE
Package Package No. of Parts Branding
Model R
AD5260BRU20 20 –40∞C to +85∞CTSSOP-14 RU-14 96 AD5260B20
AD5260BRU20-REEL7 20 –40∞C to +85∞CTSSOP-14 RU-14 1000 AD5260B20
AD5260BRU50 50 –40∞C to +85∞CTSSOP-14 RU-14 96 AD5260B50
AD5260BRU50-REEL7 50 –40∞C to +85∞CTSSOP-14 RU-14 1000 AD5260B50
AD5260BRU200 200 –40∞C to +85∞CTSSOP-14 RU-14 96 AD5260B200
AD5260BRU200-REEL7 200 –40∞C to +85∞CTSSOP-14 RU-14 1000 AD5260B200
AD5262BRU20 20 –40∞C to +85∞CTSSOP-16 RU-16 96 AD5262B20
AD5262BRU20-REEL7 20 –40∞C to +85∞CTSSOP-16 RU-16 1000 AD5262B20
AD5262BRU50 50 –40∞C to +85∞CTSSOP-16 RU-16 96 AD5262B50
AD5262BRU50-REEL7 50 –40∞C to +85∞CTSSOP-16 RU-16 1000 AD5262B50
AD5262BRU200 200 –40∞C to +85∞CTSSOP-16 RU-16 96 AD5262B200
AD5262BRU200-REEL7 200 –40∞C to +85∞CTSSOP-16 RU-16 1000 AD5262B200
*
Line 1 contains part number, line 2 contains differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5260/AD5262 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
(kW) Temperature Description Option per Container Information
AB
*
–4–
REV. 0
AD5260/AD5262
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Table I. AD5260 8-Bit Serial-Data Word Format
DATA
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
7
2
1
CLK
V
OUT
SDI
CS
0
1
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 2a. AD5260 Timing Diagram
1
CLK
V
SDI
CS
OUT
0
1
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0A0
RDAC REGISTER LOAD
Figure 2b. AD5262 Timing Diagram
Table II. AD5262 9-Bit Serial-Data Word Format
ADDR DATA
B8 B7 B6 B5 B4 B3 B2 B1 B0
A0 D7 D6 D5 D4 D3 D2 D1 D0
0
2
8
2
(DATA OUT)
MSB LSB
7
2
1
SDI
(DATA IN)
SDO
CLK
CS
V
OUT
Ax OR Dx Dx
0
1
ⴕ
x OR DⴕxDⴕx
A
0
1
0
1
0
V
DD
0V
t
DH
t
DS
t
CH
t
CL
t
CSS
ⴞ1 LSB ERROR BAND
t
PD_MAX
t
CS1
t
CSH
0
2
t
CSW
t
S
ⴞ1 LSB
Figure 2c. Detail Timing Diagram
PR
V
OUT
1
0
V
DD
0V
ⴞ1 LSB ERROR BAND
t
RS
t
S
ⴞ1 LSB
Figure 2d. Preset Timing Diagram
REV. 0
–5–
AD5260/AD5262
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
A2
A1
W1
V
DD
SHDN
CLK
SDI
SDO
V
L
V
SS
AD5262
16
15
14
13
12
11
10
9
GND
PR
CS
B1
B2
W2
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AD5260 PIN CONFIGURATION
SDO
14
NC
13
V
12
L
V
11
SS
10
GND
9
PR
8
CS
V
SHDN
CLK
SDI
A
W
B
DD
1
2
3
AD5260
4
TOP VIEW
5
(Not to Scale)
6
7
AD5260 PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic Description
1A A Terminal
2W Wiper Terminal
3B B Terminal
4V
DD
Positive power supply, specified
for operation at both 5 V or 15 V.
(Sum of |V
| + |VSS| £ 15 V)
DD
5 SHDN Active low input. Terminal A
open-circuit. Shutdown controls.
Variable Resistors of RDAC.
6 CLK Serial Clock Input, positive edge
triggered.
7 SDI Serial Data Input
8 CS Chip Select Input, Active Low.
When CS returns high, data will
be loaded into the RDAC register.
9 PR Active low preset to mid-scale; sets
RDAC registers to 80
.
H
10 GND Ground
11 V
SS
Negative Power Supply, specified
for operation from 0 V to –5 V.
12 V
L
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5260.
13 NC No Connect (Users should not
connect anything other than dummy
pad on this pin)
14 SDO Serial Data Output, Open Drain
transistor requires pull-up resistor.
AD5262 PIN CONFIGURATION
AD5262 PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic Description
1SDO Serial Data Output, Open Drain
transistor requires pull-up resistor.
2A1A Terminal RDAC #1
3W1 Wiper RDAC #1, address A0 = 0
2
4B1B Terminal RDAC #1
5V
DD
Positive power supply, specified for
operation at both 5 V or 15 V.
(Sum of |V
|+|VSS|£ 15 V)
DD
6 SHDN Active low input. Terminal A
open-circuit. Shutdown controls
Variable Resistors #1 through #2.
7 CLK Serial Clock Input, positive edge
triggered.
8 SDI Serial Data Input.
9 CS Chip Select Input, Active Low.
When CS returns high, data in
the serial input register is decoded,
based on the address Bit A0, and
loaded into the target RDAC register.
10 PR Active low preset to mid-scale sets
RDAC registers to 80
.
H
11 GND Ground
12 V
SS
Negative Power Supply, specified
for operation at both 0 V or –5 V
13 V
(Sum of |V
L
Logic Supply Voltage, needs to be
| + |VSS| <15 V).
DD
same voltage as the digital logic
controlling the AD5262.
14 B2 B Terminal RDAC #2
15 W2 Wiper RDAC #2, address A0 = 1
2
16 A2 A Terminal RDAC #2
–6–
REV. 0
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