Analog Devices AD5255 Datasheet

3-Channel Digital Potentiometer with

FEATURES

3 channels:

Dual 512-position

Single 128-position
25 kΩ or 250 kΩ full-scale resistance
Low temperature coefficient:

Potentiometer divider 15 ppm/°C

Rheostat mode 35 ppm/°C
Nonvolatile memory retains wiper settings
Permanent memory write protection
Linear increment/decrement
±6 dB increment/decrement

2

C-compatible serial interface

I

2.7 V to 5.5 V single-supply operation
±2.25 V to ±2.75 V dual-supply operation
Power-on reset time
256 bytes general-purpose user EEPROM
11 bytes RDAC user EEPROM
GBIC and SFP compliant EEPROM
100-year typical data retention at T

APPLICATIONS

Mechanical potentiometer replacement
RGB LED backlight control
White LED brightness adjustment
Programmable gain and offset control
Programmable filters

GENERAL DESCRIPTION

The AD5255 provides dual 512-position and a single
128-position digitally controlled variable resistors
TSSOP package. This device performs the same electronic
adjustment function as a potentiometer, trimmer, or variable
resistor. Each VR offers a completely programmable value of
resistance between the A terminal and the wiper or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
25 kΩ or 250 kΩ has a 1% channel-to-channel matching
tolerance and a nominal temperature coefficient of 35 ppm/°C.

Wiper position programming, EEPROM
writing is conducted via the standard 2-wire I
vious/default wiper position settings can be stored in memory,
and refreshed upon system power-up.

= 55°C

A

1

(VR) in a

2

reading, and EEPROM

2

C interface. Pre-

Nonvolatile Memory

AD5255

FUNCTIONAL BLOCK DIAGRAM

V
V

GND

SCL

SDA
A0_RDAC
A1_RDAC

A0_E
A1_E

WP

DD
SS

RS

2

I

C

SERIAL

INTERFACE

POWER-ON

RESET

256 BYTES

USER

EEPROM

32 BYTES

RDAC

EEPROM

DATA
CONTROL

COMMAND

DECODE

LOGIC

ADDRESS

DECODE

LOGIC

DECODE

LOGIC

Figure 1.

Additional features of the AD5255 include preprogrammed
linear and logarithmic increment/decrement wiper changing.
The actual resistor tolerances are stored in EEPROM so that the
actual end-to-end resistance is known, which is valuable for
calibration in precision applications.

The AD5255 is available in a 24-lead TSSOP package. All parts
are guaranteed to operate over the extended industrial tempera­ture range of −40°C to +85°C.

1

The terms programmable resistor, variable resistor, RDAC, and digital

potentiometer are used interchangeably.

2

The terms nonvolatile memory, EEMEM, and EEPROM are used

interchangeably.

RDAC0

REGISTER

RDAC1

REGISTER

RDAC2

REGISTER

RDAC0

9 BIT

RDAC1

9 BIT

RDAC2

7 BIT

A0

A0

A0
W0

W0

W0
B0

B0

B0

A1

A1

A1
W1

W1

W1
B1

B1

B1

A2

A2

A2
W2

W2

W2
B2

B2

B2

04555-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5255

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Digital Input/Output Configuration........................................ 16

Electrical Characteristics ................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Interface Descriptions.................................................................... 10

2

I

C Interface ................................................................................ 10

EEPROM Interface..................................................................... 11

RDAC I

Theory of Operation ...................................................................... 15

Linear Increment and Decrement Commands ......................15

Logarithmic Taper Mode Adjustment (±6 dB/step).............. 15

Using Additional Internal Nonvolatile EEPROM.................. 16

2

C Interface.................................................................... 12

REVISION HISTORY

Multiple Devices on One Bus ................................................... 16

Level Shift for Bidirectional Communication ........................ 16

Terminal Voltage Operation Range ......................................... 16

Power-Up Sequence ................................................................... 17

Layout and Power Supply Biasing ............................................ 17

RDAC Structure.......................................................................... 17

Calculating the Programmable Resistance ............................. 17

Programming the Potentiometer Divider............................... 18

Applications..................................................................................... 19

Laser Diode Driver (LDD) Calibration................................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

7/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD5255

ELECTRICAL CHARACTERISTICS

Single supply: VDD = 2.7 V to 5.5 V and −40°C < TA < +85°C, unless otherwise noted.
Dual supply: V

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS,
RHEOSTAT MODE

Resistor Differential Nonlinearity

Resistor Integral Nonlinearity

Resistance Temperature Coefficent
Wiper Resistance R

Channel Resistance Matching ∆R
Nominal Resistor Tolerance ∆RAB/R

DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE

Differential Nonlinearity

Integral Nonlinearity

Voltage Divider Temperature
Coefficent

Full-Scale Error V

Zero-Scale Error V

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance5 Ax, Bx C

Capacitance5 Wx C

Common-Mode Leakage Current

DIGITAL INPUTS AND OUTPUTS

Input Logic High V

Input Logic Low V

Output Logic High (SDA) V

Output Logic Low V

WP Leakage Current
A0 Leakage Current I

= +2.25 V or +2.75 V, VSS = −2.25 V or −2.75 V and −40°C < TA < +85°C, unless otherwise noted.

DD

2

R-DNL RWB, 7-bit channel −0.75

RWB, 9-bit channels −2.5

2

R-INL RWB, 7-bit channel −0.5
R-INL RWB, 9-bit channels, VDD = 5.5 V −2.0
R-INL RWB, 9-bit channels, VDD = 2.7 V −4.0

6

(∆RWB/RWB)/∆T × 10

W

/∆R

AB1

AB2

AB

VDD = 5 V, IW = 1 V/R
VDD = 3 V, IW = 1 V/R

WB

WB

Ch 1 and 2 RWB, Dx = 0x1FF
Dx = 0x3FF −15

3

DNL 7-bit channel −0.5 +0.5 LSB
DNL 9-bit channels −2.0 +2.0 LSB

3

INL 7-bit channel −0.5 +0.5 LSB
INL 9-bit channels −2.0 +2.0 LSB

)/∆T × 106Code = half-scale

(∆V

W/VW

WFSE

7-bit channel/9-bit channel,

−1/−2.75

0/0 LSB

code = full-scale

WZSE

7-bit channel/9-bit channel,

0/0

code = zero-scale

4

V

A, B, W

A,B

f = 1 kHz, measured to GND,

V

SS

code = half-scale

W

f = 1 kHz, measured to GND,
code = half-scale

5, 8

I

CM

IH

VW = VDD/2

VDD = 5 V, VSS = 0 V 2.4
VDD/VSS = +2.7 V/0 V or

V

= ±2.5 V

DD/VSS

IL

VDD = 5 V, VSS = 0 V
VDD/VSS = +2.7 V/0 V or

= ±2.5 V

V

DD/VSS

R

OH

OL

I

WP

A0

= 2.2 kΩ to VDD = 5 V,

PULL-UP

= 0 V

V

SS

R

= 2.2 kΩ to VDD = 5 V,

PULL-UP

V

= 0 V

SS

WP = V

DD

A0 = GND

2.1

4.9

1

Max Unit

35

+0.75 LSB
+2.5 LSB

+0.5 LSB
+2.0 LSB
+4.0 LSB

ppm/°C
100 150 Ω
250 400 Ω

0.1

15

85

95

%

+15 %

ppm/°C

1/2.0 LSB

V

DD

V

pF

pF

0.01 1 µA

V

V

0.8 V

0.6 V

V

0.4 V

9 µA
3 µA

Rev. 0 | Page 3 of 20

AD5255

A

Parameter Symbol Conditions Min Typ

Input Leakage Current (Excluding WP

I

I

VIN = 0 V or V

DD

1

Max Unit

±1 µA

and A0)

Input Capacitance

5

C

I

5

pF

POWER SUPPLIES

Single-Supply Power Range V
Dual-Supply Power Range VDD/V
Positive Supply Current I
Negative Supply Current I

EEMEM Data Storing Mode Current I
EEMEM Data Restoring Mode Current I
Power Dissipation
Power Supply Sensitivity

See the footnotes after Table 2.

6

5

DD

SS

DD

SS

DD_STORE

DD_RESTORE

P

DISS

P

SS

VSS = 0 V 2.7

VIH = VDD or VIL = GND, VSS = 0 V
VIH = VDD or VIL = GND,

V

= 2.5 V, VSS = −2.5 V

DD

VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD = 5 V or VIL = GND
∆VDD = 5 V ± 10%

±2.25

5.5 V
±2.75 V

5 15 µA

−5 −15 µA

35

2.5

mA
mA

25 75 µW

0.01 0.025 %/%

t

8

SD

t

1

t

6

t

7

t

10

04555-0-015

SCL

t

8

t

2

t

PS SP

3

Figure 2. I

t

9

t

4

2

C Timing Diagram

t

5

Rev. 0 | Page 4 of 20

AD5255

ELECTRICAL CHARACTERISTICS

Single Supply: VDD = 3 V to 5.5 V and −40°C < TA< +85°C, unless otherwise noted.
Dual Supply: V

Table 2.

Parameter Symbol Conditions Min Typ

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ
Total Harmonic Distortion THD
VW Settling Time t

Resistor Noise Spectral Density e
Digital Crosstalk C

Analog Crosstalk C

INTERFACE TIMING CHARACTERISTICS
(apply to all parts) (Notes

SCL Clock Frequency f
t

Bus Free Time between Stop and

BUF

Start
t

Hold Time (Repeated Start) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time for Start Condition t

SU;STA

t

Data Hold Time t

HD;DAT

t

Data Setup Time t

SU;DAT

tR Rise Time of Both SDA and SCL
Signals

tF Fall Time of Both SDA and SCL
Signals

t

Setup Time for Stop Condition t

SU;STO

EEMEM Data Storing Time t
EEMEM Data Restoring Time at

Power-On
EEMEM Data Restoring Time on

Restore
Command or Reset Operation
EEMEM Data Rewritable Time t

FLASH/EE MEMORY RELIABILITY

Endurance
Data Retention

1

Typical represent average readings at 25°C, VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

4

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

All dynamic characteristics use VDD = 5 V.

8

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

9

See the timing diagram for location of measured values.

10

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +85°C, typical endurance at 25°C is 700,000 cycles.

11

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
derates with junction temperature.

= +2.25 V or +2.75 V , VSS = −2.25 V or −2.75 V and −40°C < TA < + 85°C, unless otherwise noted.

DD

5, 7

W

S

VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,

V

= 0.50% error band,

W

code 0x000 to 0x100, RAB = 25 kΩ/250 kΩ

N_WB

T

RAB = 25 kΩ/250 kΩ, TA = 25°C
VA = VDD, VB = 0 V, measure VW with

adjacent RDAC making full-scale
change

AT

Signal input at A0 and measure output
at W1, f = 1 kHz

8, 9

)

SCL

t

1

2

After this period the first clock pulse is
generated

3

4

5

6

7

t

8

t

9

10

EEMEM_STORE

t

EEMEM_RESTORE1

t

EEMEM_RESTORE2

EEMEM_REWRITE

10

11

55°C

1

Max Unit

125/12 kHz

0.05 %
4/36 µs

14/45 nV√Hz

−80 dB

−72 dB

400 kHz

1.3 µs

600 ns

1.3 µs

0.6 50 µs
600 ns
900 ns
100 ns
300 ns

300 ns

600 ns
26 ms
360 µs

360 µs

540 µs

100

kcycles

100 years

Rev. 0 | Page 5 of 20

AD5255

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to V

SS

VA, VB, VW to GND
IA, IB, I

W

Intermittent

1

7 V

VSS − 0.3 V, VDD + 0.3 V

±20 mA

Continuous ±2 mA
Digital Inputs and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range

2

−40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Thermal Resistance Junction-to-Ambient

, TSSOP-24

θ

JA

_______________________ ________________________________

1

Includes programming of nonvolatile memory.

2

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

143°C/W

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20