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MAX 10 FPGA Configuration User Guide
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101 Innovation Drive |
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2015.05.04 |
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San Jose, CA 95134 |
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www.altera.com |
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TOC-2
Contents
MAX 10 FPGA Configuration Overview............................................................ |
1-1 |
MAX 10 FPGA Configuration Schemes and Features....................................... |
2-1 |
Configuration Schemes............................................................................................................................... |
2-1 |
JTAG Configuration........................................................................................................................ |
2-1 |
Internal Configuration.................................................................................................................... |
2-2 |
Configuration Features............................................................................................................................... |
2-8 |
Remote System Upgrade in Dual Compressed Images.............................................................. |
2-8 |
Configuration Design Security..................................................................................................... |
2-15 |
SEU Mitigation and Configuration Error Detection................................................................ |
2-18 |
Configuration Data Compression............................................................................................... |
2-22 |
Configuration Details................................................................................................................................ |
2-23 |
Configuration Sequence................................................................................................................ |
2-23 |
MAX 10 Configuration Pins......................................................................................................... |
2-25 |
MAX 10 FPGA Configuration Design Guidelines............................................. |
3-1 |
Dual-Purpose Configuration Pins............................................................................................................. |
3-1 |
Guidelines: Dual-Purpose Configuration Pin.............................................................................. |
3-1 |
Enabling Dual-purpose Pin............................................................................................................ |
3-2 |
Configuring MAX 10 Devices using JTAG Configuration.................................................................... |
3-2 |
JTAG Configuration Setup............................................................................................................. |
3-3 |
ICB Settings in JTAG Configuration............................................................................................. |
3-4 |
Configuring MAX 10 Devices using Internal Configuration................................................................ |
3-4 |
Selecting Internal Configuration Modes...................................................................................... |
3-5 |
.pof and ICB Settings....................................................................................................................... |
3-5 |
Programming .pof into Internal Flash.......................................................................................... |
3-7 |
Accessing the Remote System Upgrade Block Through User Interface.............................................. |
3-8 |
Error Detection............................................................................................................................................ |
3-8 |
Verifying Error Detection Functionality...................................................................................... |
3-8 |
Enabling Error Detection................................................................................................................ |
3-9 |
Accessing Error Detection Block Through User Interface........................................................ |
3-9 |
Enabling Data Compression..................................................................................................................... |
3-10 |
Enabling Compression Before Design Compilation................................................................. |
3-11 |
Enabling Compression After Design Compilation................................................................... |
3-11 |
AES Encryption.......................................................................................................................................... |
3-11 |
Generating .ekp File and Encrypt Configuration File.............................................................. |
3-12 |
Generating .jam/.jbc/.svf file from .ekp file................................................................................ |
3-13 |
Programming .ekp File and Encrypted POF File...................................................................... |
3-14 |
Encryption in Internal Configuration......................................................................................... |
3-15 |
Altera Corporation
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TOC-3 |
MAX 10 FPGA Configuration IP Core Implementation Guides...................... |
4-1 |
Altera Unique Chip ID IP Core................................................................................................................. |
4-1 |
Instantiating the Altera Unique Chip ID IP Core....................................................................... |
4-1 |
Resetting the Altera Unique Chip ID IP Core............................................................................. |
4-1 |
Altera Dual Configuration IP Core........................................................................................................... |
4-1 |
Instantiating the Altera Dual Configuration IP Core................................................................. |
4-2 |
Altera Dual Configuration IP Core References.................................................. |
5-1 |
Altera Dual Configuration IP Core Avalon-MM Address Map............................................................ |
5-1 |
Altera Dual Configuration IP Core Parameters...................................................................................... |
5-3 |
Altera Unique Chip ID IP Core References........................................................ |
6-1 |
Altera Unique Chip ID IP Core Ports....................................................................................................... |
6-1 |
Additional Information for MAX 10 FPGA Configuration User Guide.......... |
A-1 |
Document Revision History for MAX 10 FPGA Configuration User Guide..................................... |
A-2 |
Altera Corporation
MAX 10 FPGA Configuration Overview 1
2015.05.04
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You can configure MAX® 10 configuration RAM (CRAM) using the following configuration schemes:
•JTAG configuration—using JTAG interface.
•Internal configuration—using internal flash.
Supported Configuration Features
Table 1-1: Configuration Schemes and Features Supported by MAX 10 Devices
Configuration Scheme |
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Remote System |
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Compression |
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Design Security |
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SEU Mitigation |
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Upgrade |
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JTAG configuration |
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— |
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— |
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Yes |
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Internal configuration |
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Yes |
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Yes |
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Yes |
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Yes |
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Related IP Cores
•Altera Dual Configuration IP Core—used in the remote system upgrade feature.
•Altera Unique Chip ID IP Core—retrieves the chip ID of MAX 10 devices.
Related Information
•MAX 10 FPGA Configuration Schemes and Features on page 2-1 Provides information about the configuration schemes and features.
•MAX 10 FPGA Configuration Design Guidelines on page 3-1
Provides information about using the configuration schemes and features.
•Altera Unique Chip ID IP Core on page 2-16
•Altera Dual Configuration IP Core on page 2-14
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
ISO 9001:2008 Registered
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101 Innovation Drive, San Jose, CA 95134
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MAX 10 FPGA Configuration Schemes and |
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Features |
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Configuration Schemes
Figure 2-1: High-Level Overview of JTAG Configuration and Internal Configuration for MAX 10 Devices
JTAG Configuration |
MAX 10 Device |
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Configuration Data |
CRAM |
.sof |
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Internal |
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Configuration |
.pof |
CFM |
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JTAG In-System Programming |
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JTAG Configuration
In MAX 10 devices, JTAG instructions take precedence over the internal configuration scheme.
Using the JTAG configuration scheme, you can directly configure the device CRAM through the JTAG interface—TDI, TDO, TMS, and TCK pins. The Quartus® II software automatically generates an SRAM Object File (.sof). You can program the .sof using a download cable with the Quartus II software programmer.
Related Information
Configuring MAX 10 Devices using JTAG Configuration on page 3-2
Provides more information about JTAG configuration using download cable with Quartus II software programmer.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
ISO 9001:2008 Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
2-2 |
JTAG Pins |
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JTAG Pins |
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Table 2-1: JTAG Pin |
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Description |
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TDI |
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Serial input pin for: |
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• TDI is sampled on the rising edge of TCK |
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instructions |
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• TDI pins have internal weak pull-up resistors. |
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test data |
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programming data |
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TDO |
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Serial output pin for: |
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• TDO is sampled on the falling edge of TCK |
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instructions |
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• The pin is tri-stated if data is not shifted out |
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test data |
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of the device. |
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programming data |
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TMS |
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Input pin that provides the control |
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• TMS is sampled on the rising edge of TCK |
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signal to determine the transitions of |
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• TMS pins have internal weak pull-up resistors. |
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the TAP controller state machine. |
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TCK |
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Clock input to the BST circuitry. |
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— |
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All the JTAG pins are powered by the VCCIO 1B. In JTAG mode, the I/O pins support the LVTTL/ LVCMOS 3.3-1.5V standards.
Related Information
•MAX 10 Device Datasheet
Provides more information about supported I/O standard in MAX 10 devices.
•Guidelines: Dual-Purpose Configuration Pin on page 3-1
•Enabling Dual-purpose Pin on page 3-2
Internal Configuration
You need to program the configuration data into the configuration flash memory (CFM) before internal configuration can take place. The configuration data to be written to CFM will be part of the programmer object file (.pof). Using JTAG In-System Programming (ISP), you can program the .pof into the internal flash.
During internal configuration, MAX 10 devices load the CRAM with configuration data from the CFM.
Internal Configuration Modes
The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following modes:
•Dual Compressed Images—configuration image is stored as image 0 and image 1 in the CFM
•Single Compressed Image
•Single Compressed Image with Memory Initialization
•Single Uncompressed Image
•Single Uncompressed Image with Memory Initialization
In dual compressed images mode, you can use the CONFIG_SEL pin to select the configuration image.
Altera Corporation |
MAX 10 FPGA Configuration Schemes and Features |
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Configuration Flash Memory |
2-3 |
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The internal configuration scheme for 10M02 device supports the following mode:
•Single Compressed Image
•Single Uncompressed Image
Related Information
•Configuring MAX 10 Devices using Internal Configuration on page 3-4
•Remote System Upgrade in Dual Compressed Images on page 2-8
Configuration Flash Memory
The CFM is a non-volatile internal flash that is used to store configuration images. The CFM may store up to two compressed configuration images, depending on the compression and the MAX 10 devices. The compression ratio for the configuration image should be at least 30% for the device to be able store two configuration images.
Table 2-2: Maximum Number of Compressed Configuration Image for MAX 10 Devices
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10M02 |
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10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 |
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Related Information
Configuration Flash Memory Permissions on page 2-18
Configuration Flash Memory Sectors
All CFM in MAX 10 devices consist of three sectors, CFM0, CFM1, and CFM2 except for the 10M02. The sectors are programmed differently depending on the internal configuration mode you select.
The 10M02 device consists of only CFM0. The CFM0 sector in 10M02 devices is programmed similarly when you select single compressed image or single uncompressed image.
MAX 10 FPGA Configuration Schemes and Features |
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2-4 |
Configuration Flash Memory Total Programming Time |
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Figure 2-2: Configuration Flash Memory Sectors Utilization for all MAX 10 Devices Except for the 10M02 Device
Unutilized CFM1 and CFM2 sectors can be used for additional user flash memory (UFM).
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Configuration Flash Memory Sectors |
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Mode |
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Dual Compressed Image |
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Compressed |
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Image 1 |
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Compressed Image 0 |
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Single Uncompressed Image |
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Single Uncompressed Image |
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Single Compressed Image |
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Compressed Image 0 with Memory Initialization |
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Single Compressed Image |
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Related Information
CFM and UFM Array Size
Configuration Flash Memory Total Programming Time
Table 2-3: Configuration Flash Memory Total Programming Time for Sectors in MAX 10 Devices
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Programming Time (s) |
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CFM2 |
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10M02 |
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10M16 and 10M25 |
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10M40 and 10M50 |
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52.9 |
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In-System Programming
You can program the internal flash including the CFM of MAX 10 devices with ISP through industry standard JTAG interface. ISP offers the capability to program, erase, and verify the CFM. The JTAG circuitry and ISP instructions for MAX 10 devices are compliant to the IEEE-1532-2002 programming specification.
During ISP, the MAX 10 receives the IEEE Std. 1532 instructions, addresses, and data through the TDI input pin. Data is shifted out through the TDO output pin and compared with the expected data.
Altera Corporation |
MAX 10 FPGA Configuration Schemes and Features |
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Real-Time ISP |
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The following are the generic flow of an ISP operation:
1.Check ID—the JTAG ID is checked before any program or verify process. The time required to read this JTAG ID is relatively small compared to the overall programming time.
2.Enter ISP—ensures the I/O pins transition smoothly from user mode to the ISP mode.
3.Sector Erase—shifting in the address and instruction to erase the device and applying erase pulses.
4.Program—shifting in the address, data, and program instructions and generating the program pulse to program the flash cells. This process is repeated for each address in the internal flash sector.
5.Verify—shifting in addresses, applying the verify instruction to generate the read pulse, and shifting out the data for comparison. This process is repeated for each internal flash address.
6.Exit ISP—ensures that the I/O pins transition smoothly from the ISP mode to the user mode.
You can also use the Quartus II Programmer to program the CFM.
Related Information
Programming .pof into Internal Flash on page 3-7
Provides the steps to program the .pof using Quartus II Programmer.
Real-Time ISP
In a normal ISP operation, to update the internal flash with a new design image, the device exits from user mode and all I/O pins remain tri-stated. After the device completes programing the new design image, it resets and enters user mode.
The real-time ISP feature updates the internal flash with a new design image while operating in user mode. During the internal flash programming, the device continues to operate using the existing design. After the new design image programming process completes, the device will not reset. The new design image update only takes effect in the next reconfiguration cycle.
ISP and Real-Time ISP Instructions
Table 2-4: ISP and Real-Time ISP Instructions for MAX 10 Devices
Instruction |
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Instruction Code |
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Description |
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CONFIG_IO |
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• Allows I/O reconfiguration through JTAG ports using |
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the IOCSR for JTAG testing. This is executed after or |
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during configurations. |
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• nSTATUS pin must go high before you can issue the |
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CONFIG_IO instruction. |
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PULSE_NCONFIG |
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Emulates pulsing the nCONFIG pin low to trigger reconfi |
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MAX 10 FPGA Configuration Schemes and Features |
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ISP and Real-Time ISP Instructions |
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Instruction |
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ISC_ENABLE_HIZ (1) |
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10 1100 1100 |
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and drives all core drivers, logic, and registers. |
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• Device remains in the ISP mode until the ISC_ |
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DISABLE instruction is loaded and updated. |
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• The ISC_ENABLE instruction is a mandatory instruc |
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CLAMP or ISC_ENABLE_HIZ instruction. |
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ISC_ENABLE_CLAMP (1) |
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follow the contents of the JTAG boundary-scan |
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register. |
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• When this instruction is activated, all core drivers, |
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logics, and registers are frozen. The I/O pins remain |
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clamped until the device exits ISP mode successfully. |
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ISC_DISABLE |
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• Successful completion of the ISC_DISABLE instruction |
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happens immediately after waiting 200 µs in the Run- |
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Test/Idle state. |
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ISC_PROGRAM(2) |
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Sets the device up for in-system programming. Program |
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ming occurs in the run-test or idle state. |
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ISC_NOOP(2) |
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leaving the ISP mode and targets the ISC_Default |
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register. |
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• two or more ISP-compliant devices are being |
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accessed in ISP mode and; |
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• a subset of the devices perform some instructions |
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while other more complex devices are completing |
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extra steps in a given process. |
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ISC_ADDRESS_SHIFT(2) |
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ISC_ERASE(2) |
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• Issue after ISC_ADDRESS_SHIFT instruction. |
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ISC_READ(2) |
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under normal user bias conditions. |
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• The ISC_READ instruction supports explicit |
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addressing and auto-increment, also known as the |
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Burst mode. |
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(1)Do not issue the ISC_ENABLE_HIZ and ISC_ENABLE_CLAMP instructions from the core logic.
(2)All ISP and real-time ISP instructions are disabled when the device is not in the ISP or real-time ISP mode, except for the enabling and disabling instructions.
Altera Corporation |
MAX 10 FPGA Configuration Schemes and Features |
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Send Feedback
UG-M10CONFIG |
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Initialization Configuration Bits |
2-7 |
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2015.05.04 |
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Instruction |
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Instruction Code |
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Description |
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BGP_ENABLE |
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01 1001 1001 |
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• Sets the device to the real-time ISP mode. |
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• Allows access to the internal flash configuration |
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sector while the device is still in user mode. |
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BGP_DISABLE |
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01 0110 0110 |
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• Brings the device out of the real-time ISP mode. |
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• The device has to exit the real-time ISP mode using |
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the BGP_DISABLE instruction after it is interrupted by |
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reconfiguration. |
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Caution: Do not use unsupported JTAG instructions. It will put the device into an unknown state and requires a power cycle to recover the operation.
Initialization Configuration Bits
Initialization Configuration Bits (ICB) stores the configuration feature settings of the MAX 10 device. You can set the ICB settings during Convert Programming File.
Table 2-5: Initialization Configuration Bits for MAX 10 Devices
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Configuration Settings |
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Description |
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Default State/Value |
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Power On Reset Scheme |
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Instant ON |
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Instant ON |
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Fast POR delay |
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Slow POR delay |
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Set I/O to weak pull-up prior |
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• Enable: I/O will set to week pull-up prior to |
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Enable |
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usermode |
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usermode. |
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• Disable: I/O will be input tri-stated. |
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Auto-reconfigure from |
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Enable: |
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Enable |
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secondary image when initial |
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image fails. |
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• Device will automatically load secondary image |
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if initial image fails. |
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Disable: |
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• device will automatically load image 0. |
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• device will not load image 1 if image 0 fails. |
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• CONFIG_SEL pin setting is ignored. |
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Use secondary image ISP data |
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• Disable: Use ISP data from image 0 |
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Disable |
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as default setting when |
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• Enable: Use ISP data from image 1 |
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available. |
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ISP data contains the information about state of |
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the pin during ISP. This can be either tri-state with |
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weak pull-up or clamp the I/O state. You can set |
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the ISP clamp through Device and Pin Option, or |
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Pin Assignment tool. |
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Verify Protect |
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To disable or enable the Verify Protect feature. |
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Disable |
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MAX 10 FPGA Configuration Schemes and Features |
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Altera Corporation |
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Send Feedback |
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2-8 |
Configuration Features |
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UG-M10CONFIG |
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2015.05.04 |
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Configuration Settings |
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Description |
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Default State/Value |
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Allow encrypted POF only |
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If enabled, configuration error will occur if |
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Disable |
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unencrypted .pof is used. |
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JTAG Secure(3) |
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To disable or enable the JTAG Secure feature. |
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Disable |
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Enable Watchdog |
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To disable or enable the watchdog timer for |
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Enable |
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remote system upgrade. |
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Watchdog value |
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To set the watchdog timer value for remote system |
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0x1FFF(4) |
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upgrade. |
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Related Information
•.pof and ICB Settings on page 3-5
•.pof Generation through Convert Programming Files on page 3-6
Provides more information about setting the ICB during .pof generation using Convert Programming File.
•Instant-on on page 2-24
Provides more information about Instant ON and other power on reset scheme.
•Verify Protect on page 2-17
•JTAG Secure Mode on page 2-16
•ISP and Real-Time ISP Instructions on page 2-5
•User Watchdog Timer on page 2-14
Configuration Features
Remote System Upgrade in Dual Compressed Images
MAX 10 devices support the remote system upgrade feature. By default, the remote system upgrade feature is enabled in all MAX 10 devices when you select the dual compressed image internal configuration mode.
The remote system upgrade feature in MAX 10 devices offers the following capabilities:
•Manages remote configuration
•Provides error detection, recovery, and information
•Supports direct-to-application configuration image
•Supports compressed and encrypted .pof
You can use the Altera Dual Configuration IP core or the remote system upgrade circuitry to access the remote system upgrade block in MAX 10 devices.
(3)The JTAG Secure feature will be disabled by default in Quartus II. If you are interested in using the JTAG Secure feature, contact Altera for support.
(4)The watchdog timer value depends on the MAX 10 you are using. Refer to the Watchdog Timer section for more information.
Altera Corporation |
MAX 10 FPGA Configuration Schemes and Features |
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Send Feedback
UG-M10CONFIG |
Remote System Upgrade Flow |
2-9 |
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2015.05.04 |
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Remote System Upgrade Flow
Both the application configuration images, image 0 and image 1, are stored in the CFM. The MAX 10 device loads either one of the application configuration image from the CFM.
Figure 2-3: Remote System Upgrade Flow for MAX 10 Devices
Power-up
Flow when Auto-reconfigure from secondary image when initial image fails is disabled.
Reconfiguration
Sample CONFIG_SEL pin
Reconfiguration
CONFIG_SEL=0 CONFIG_SEL=1
Power-up
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First Error Occurs |
Image 0 |
Image 1 |
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First Error Occurs |
Second Error Occurs |
Second Error Occurs |
Error
ReconfigurationOccurs
Wait for Reconfiguration
Reconfiguration
The remote system upgrade feature detects errors in the following sequence:
1.After power-up, the device samples the CONFIG_SEL pin to determine which application configuration image to load. The CONFIG_SEL pin setting can be overwritten by the input register of the remote system upgrade circuitry for the subsequent reconfiguration.
2.If an error occurs, the remote system upgrade feature reverts by loading the other application configu ration image. These errors cause the remote system upgrade feature to load another application configuration image:
•Internal CRC error
•User watchdog timer time-out
3.Once the revert configuration completes and the device is in user mode, you can use the remote system upgrade circuitry to query the cause of error and which application image failed.
4.If a second error occurs, the device waits for a reconfiguration source. If the Auto-restart configura tion after error is enabled, the device will reconfigure without waiting for any reconfiguration source.
5.Reconfiguration is triggered by the following actions:
•Driving the nSTATUS low externally.
•Driving the nCONFIG low externally.
•Driving RU_nCONFIG low.
MAX 10 FPGA Configuration Schemes and Features |
Altera Corporation |
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Send Feedback
2-10 |
Remote System Upgrade Circuitry |
UG-M10CONFIG |
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2015.05.04 |
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Remote System Upgrade Circuitry
Figure 2-4: Remote System Upgrade Circuitry
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Status Register (SR) |
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Internal Oscillator |
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Previous |
Previous |
Current |
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Control Register |
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State |
State |
State |
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Bit [38..0] |
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Register 2 |
Register 1 |
Logic |
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Bit[31..0] |
Bit[31..0] |
Bit[33..0] |
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Logic |
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Input Register |
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Bit [38..0] |
update |
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RU |
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Master |
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State |
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Logic |
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Machine |
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Shift Register |
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RU |
timeout |
User |
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Reconfiguration |
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din |
dout |
din |
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dout |
State |
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Watchdog |
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Machine |
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Timer |
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Bit [40..39] |
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Bit [38..0] |
capture |
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clkout |
capture |
update |
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Logic |
clkin |
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RU_DIN |
RU_SHIFTnLD |
RU_CAPTnUPDT |
RU_CLK |
RU_DOUT |
RU_nCONFIG |
RU_nRSTIMER |
Logic Array
The remote system upgrade circuitry does the following functions:
•Tracks the current state of configuration
•Monitors all reconfiguration sources
•Provides access to set up the application configuration image
•Returns the device to fallback configuration if an error occurs
•Provides access to the information on the failed application configuration image
Remote System Upgrade Circuitry Signals
Table 2-6: Remote System Upgrade Circuitry Signals for MAX 10 Devices
Core Signal Name |
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Logical |
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Input/ |
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Description |
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Signal |
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Output |
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Name |
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Use this signal to write data to the shift register on the rising |
RU_DIN |
regin |
Input |
edge of RU_CLK. To load data to the shift register, assert RU_ |
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SHIFTnLD. |
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Altera Corporation |
MAX 10 FPGA Configuration Schemes and Features |
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Send Feedback
UG-M10CONFIG |
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Remote System Upgrade Circuitry Input Control |
2-11 |
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2015.05.04 |
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Core Signal Name |
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Logical |
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Input/ |
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Signal |
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Output |
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Name |
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Use this signal to get output data from the shift register. Data |
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RU_DOUT |
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regout |
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Output |
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is clocked out on each rising edge of RU_CLK if RU_SHIFTnLD is |
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asserted. |
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RU_nRSTIMER |
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rsttimer |
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Input |
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Use this signal to reset the user watchdog timer. A falling edge |
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of this signal triggers a reset of the user watchdog timer. |
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Use this signal to reconfigure the device. Driving this signal |
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RU_nCONFIG |
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rconfig |
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Input |
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low triggers the device to reconfigure if you enable the remote |
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system upgrade feature. |
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The clock to the remote system upgrade circuitry. All registers |
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RU_CLK |
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clk |
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in this clock domain are enabled in user mode if you enable |
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the remote system upgrade. Shift register and input register |
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are positive edge flip-flops. |
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RU_SHIFTnLD |
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shiftnld |
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Input |
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Control signals that determine the mode of remote system |
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upgrade circuitry. |
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• When RU_SHIFTnLD is driven low and RU_CAPTnUPDT is |
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driven low, the input register is loaded with the contents of |
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the shift register on the rising edge of RU_CLK. |
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RU_CAPTnUPDT |
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captnupdt |
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Input |
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• When RU_SHIFTnLD is driven low and RU_CAPTnUPDT is |
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driven high, the shift register captures values from the |
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input_cs_ps module on the rising edge of RU_CLK. |
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• When RU_SHIFTnLD is driven high, the RU_CAPTnUPDT will |
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be ignored and the shift register shifts data on each rising |
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edge of RU_CLK. |
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Related Information
•Accessing the Remote System Upgrade Block Through User Interface on page 3-8
Provides more information about accessing the remote system upgrade through user interface atom.
•MAX 10 Device Datasheet
Provides more information about Remote System Upgrade timing specifications.
Remote System Upgrade Circuitry Input Control
The remote system upgrade circuitry has three modes of operation.
•Update—loads the values in the shift register into the input register.
•Capture—loads the shift register with data to be shifted out.
•Shift—shifts out data to the user logic.
MAX 10 FPGA Configuration Schemes and Features |
Altera Corporation |
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Send Feedback
2-12 |
Remote System Upgrade Input Register |
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UG-M10CONFIG |
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2015.05.04 |
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Table 2-7: Control Inputs to the Remote System Upgrade Circuitry |
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Remote System Upgrade Circuitry Control Inputs |
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Input Settings for Registers |
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RU_SHIFTnLD |
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RU_CAPTnUPDT |
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Shift register |
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Shift register |
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Shift |
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[40] |
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Register[38:0] |
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Register[38:0] |
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0 |
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0 |
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Don't Care |
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Don't Care |
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Update |
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Shift Register |
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Shift Register |
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Capture |
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Current State |
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Register[38:0] |
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{8’b0, |
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0 |
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1 |
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1 |
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Capture |
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Previous State |
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Register[38:0] |
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Application1} |
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{8’b0, |
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0 |
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0 |
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Capture |
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Previous State |
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Application2} |
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Capture |
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Register[38:0] |
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{ru_din, Shift |
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1 |
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Don't Care |
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Don't Care |
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Shift |
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[38:1]} |
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The following shows examples of driving the control inputs in the remote system upgrade circuitry:
•When you drive RU_SHIFTnLD high to 1’b1, the shift register shifts data on each rising edge of RU_CLK and RU_CAPTnUPDT has no function.
•When you drive both RU_SHIFTnLD and RU_CAPTnUPDT low to 1’b0, the input register is loaded with the contents of the shift register on the rising edge of RU_CLK.
•When you drive RU_SHIFTnLD low to 1’b0 and RU_CAPTnUPDT high to 1’b1, the shift register captures values on the rising edge of RU_DCLK.
Remote System Upgrade Input Register
Table 2-8: Remote System Upgrade Input Register for MAX 10 Devices
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Name |
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Description |
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38:14 |
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Reserved |
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Reserved—set to 0. |
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• 0: Load configuration image 0 |
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13 |
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ru_config_sel |
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• 1: Load configuration image 1 |
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This bit will only work if the ru_config_sel_overwrite bit is set |
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to 1. |
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12 |
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ru_config_sel_ |
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• 0: Disable overwrite CONFIG_SEL pin |
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overwrite |
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• 1: Enable overwrite CONFIG_SEL pin |
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Altera Corporation |
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|
MAX 10 FPGA Configuration Schemes and Features |
||
|
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UG-M10CONFIG |
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Remote System Upgrade Status Registers |
2-13 |
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2015.05.04 |
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Bits |
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Name |
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Description |
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11:0 |
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Reserved |
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Reserved—set to 0. |
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Remote System Upgrade Status Registers
Table 2-9: Remote System Upgrade Status Register—Current State Logic Bit for MAX 10 Devices
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Name |
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Description |
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33:30 |
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msm_cs |
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The current state of the master state machine (MSM). |
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29 |
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ru_wd_en |
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The current state of the enabled user watchdog timer. The default |
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state is active high. |
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28:0 |
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wd_timeout_value |
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The current, entire 29-bit watchdog time-out value. |
Table 2-10: Remote System Upgrade Status Register—Previous State Bit for MAX 10 Devices |
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Bits |
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Name |
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Description |
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31 |
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nconfig |
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An active high field that describes the reconfiguration sources |
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which caused the MAX 10 device to leave the previous application |
30 |
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crcerror |
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configuration. In the event of a tie, the higher bit order takes |
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29 |
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nstatus |
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precedence. For example, if the nconfig and the ru_nconfig |
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triggered at the same time, the nconfig takes precedence over the |
28 |
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wdtimer |
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ru_nconfig. |
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27:26 |
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Reserved |
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Reserved—set to 0. |
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The state of the MSM when a reconfiguration event occurred. The |
25:22 |
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msm_cs |
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reconfiguration will cause the device to leave the previous applica |
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tion configuration. |
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21:0 |
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Reserved |
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Reserved—set to 0. |
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Master State Machine
The master state machine (MSM) tracks current configuration mode and enables the user watchdog timer.
Table 2-11: Remote System Upgrade Master State Machine Current State Descriptions for MAX 10 Devices
msm_cs Values |
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State Description |
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0010 |
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Image 0 is being loaded. |
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0011 |
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Image 1 is being loaded after a revert in application image happens. |
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0100 |
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Image 1 is being loaded. |
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0101 |
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Image 0 is being loaded after a revert in application image happens. |
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MAX 10 FPGA Configuration Schemes and Features |
Altera Corporation |
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