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Introduction to Avalon Verification IP Suite
User Guide
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2014.06.30 |
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TOC-2 Introduction to Avalon Verification IP SuiteUser Guide
Contents
Introduction to Avalon Verification IP Suite .................................................... |
1-1 |
Advantages of Using BFMs and Monitors .............................................................................................. |
1-1 |
BFM Implementation ................................................................................................................................. |
1-1 |
Application Programming Interface ........................................................................................................ |
1-3 |
Application Example of BFMs .................................................................................................................. |
1-3 |
Clock Source BFM .............................................................................................. |
2-1 |
Parameters .................................................................................................................................................... |
2-1 |
Clock Source API......................................................................................................................................... |
2-1 |
Clock_stop() .................................................................................................................................... |
2-2 |
get_run_state() ................................................................................................................................ |
2-2 |
get_version() .................................................................................................................................... |
2-2 |
Reset Source BFM ............................................................................................... |
3-1 |
Parameters .................................................................................................................................................... |
3-1 |
Reset Source API.......................................................................................................................................... |
3-1 |
reset_deassert ................................................................................................................................... |
3-2 |
get_version() .................................................................................................................................... |
3-2 |
Avalon Interrupt Source and Interrupt Sink BFMs .......................................... |
4-1 |
Parameters .................................................................................................................................................... |
4-1 |
Interrupt Source and Sink API................................................................................................................... |
4-2 |
get_irq() ............................................................................................................................................ |
4-2 |
get_version() .................................................................................................................................... |
4-2 |
set_irq() ............................................................................................................................................ |
4-3 |
Avalon-MM Master BFM ................................................................................... |
5-1 |
Timing .......................................................................................................................................................... |
5-2 |
Block Diagram ............................................................................................................................................. |
5-5 |
Parameters .................................................................................................................................................... |
5-6 |
Avalon-MM Master BFM API................................................................................................................... |
5-9 |
event_all_transactions_complete() ............................................................................................... |
5-9 |
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Introduction to Avalon Verification IP SuiteUser Guide |
TOC-3 |
event_command_issued()............................................................................................................. |
5-10 |
event_max_command_queue_size() ......................................................................................... |
5-10 |
event_min_command_queue_size() .......................................................................................... |
5-10 |
event_read_response_complete() ............................................................................................... |
5-10 |
event_response_complete() ......................................................................................................... |
5-11 |
event_write_response_complete()............................................................................................... |
5-11 |
get_command_issued_queue_size() .......................................................................................... |
5-11 |
get_command_pending_queue_size() ....................................................................................... |
5-12 |
get_read_response_queue_size() ................................................................................................ |
5-12 |
get_response_address() ................................................................................................................ |
5-12 |
get_response_byte_enable() ........................................................................................................ |
5-13 |
get_response_burst_size() ........................................................................................................... |
5-13 |
get_response_data() ...................................................................................................................... |
5-13 |
get_response_latency() ................................................................................................................. |
5-14 |
get_response_queue_size() .......................................................................................................... |
5-14 |
get_response_read_id() ................................................................................................................ |
5-14 |
get_response_read_response() .................................................................................................... |
5-15 |
get_response_request() ................................................................................................................ |
5-15 |
get_response_wait_time() ............................................................................................................ |
5-15 |
get_response_write_id() .............................................................................................................. |
5-16 |
get_response_write_response() .................................................................................................. |
5-16 |
get_write_response_queue_size() ............................................................................................... |
5-16 |
get_version() .................................................................................................................................. |
5-17 |
init() ................................................................................................................................................ |
5-17 |
pop_response() .............................................................................................................................. |
5-17 |
push_command() .......................................................................................................................... |
5-18 |
set_clken() ...................................................................................................................................... |
5-18 |
set_command_address() .............................................................................................................. |
5-18 |
set_command_arbiterlock() ........................................................................................................ |
5-19 |
set_command_byte_enable() ...................................................................................................... |
5-19 |
set_command_burst_count() ...................................................................................................... |
5-19 |
set_command_burst_size() ......................................................................................................... |
5-20 |
set_command_data() .................................................................................................................... |
5-20 |
set_command_debugaccess() ...................................................................................................... |
5-20 |
set_command_idle() ..................................................................................................................... |
5-21 |
set_command_init_latency() ...................................................................................................... |
5-21 |
set_command_lock() .................................................................................................................... |
5-21 |
set_command_request() .............................................................................................................. |
5-22 |
set_command_timeout() ............................................................................................................. |
5-22 |
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Introduction to Avalon Verification IP SuiteUser Guide |
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set_command_transaction_id() .................................................................................................. |
5-22 |
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set_command_write_response_request() ................................................................................. |
5-23 |
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set_max_command_queue_size() .............................................................................................. |
5-23 |
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set_min_command_queue_size() .............................................................................................. |
5-23 |
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set_response_timeout() ................................................................................................................ |
5-24 |
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signal_all_transactions_complete ............................................................................................... |
5-24 |
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signal_command_issued .............................................................................................................. |
5-24 |
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signal_fatal_error .......................................................................................................................... |
5-25 |
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signal_max_command_queue_size ............................................................................................ |
5-25 |
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signal_min_command_queue_size ............................................................................................ |
5-25 |
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signal_read_response_complete ................................................................................................. |
5-26 |
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signal_response_complete ........................................................................................................... |
5-26 |
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signal_write_response_complete ................................................................................................ |
5-26 |
Avalon-MM Slave BFM ...................................................................................... |
6-1 |
Timing .......................................................................................................................................................... |
6-2 |
Block Diagram ............................................................................................................................................. |
6-6 |
Parameters .................................................................................................................................................... |
6-7 |
Avalon-MM Slave BFM API.................................................................................................................... |
6-10 |
event_command_received() ........................................................................................................ |
6-10 |
event_response_issued() .............................................................................................................. |
6-10 |
event_max_response_queue_size() ............................................................................................ |
6-11 |
event_min_response_queue_size() ............................................................................................ |
6-11 |
get_clken() ..................................................................................................................................... |
6-11 |
get_command_address() ............................................................................................................. |
6-11 |
get_command_arbiterlock() ........................................................................................................ |
6-12 |
get_command_burst_count() ..................................................................................................... |
6-12 |
get_command_burst_cycle() ....................................................................................................... |
6-12 |
get_command_byte_enable() ...................................................................................................... |
6-13 |
get_command_data() ................................................................................................................... |
6-13 |
get_command_debugaccess() ..................................................................................................... |
6-13 |
get_command_queue_size() ....................................................................................................... |
6-14 |
get_command_lock() ................................................................................................................... |
6-14 |
get_command_request() .............................................................................................................. |
6-14 |
get_command_transaction_id() ................................................................................................. |
6-15 |
get_command_write_response_request() ................................................................................. |
6-15 |
get_pending_read_latency_cycle() ............................................................................................. |
6-15 |
get_pending_write_latency_cycle() ............................................................................................ |
6-16 |
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Introduction to Avalon Verification IP SuiteUser Guide |
TOC-5 |
get_response_queue_size() .......................................................................................................... |
6-16 |
vget_slave_bfm_status .................................................................................................................. |
6-16 |
get_version() .................................................................................................................................. |
6-17 |
init() ................................................................................................................................................ |
6-17 |
pop_command() ........................................................................................................................... |
6-17 |
push_response() ............................................................................................................................ |
6-18 |
set_command_transaction_mode() ........................................................................................... |
6-18 |
set_interface_wait_time() ............................................................................................................ |
6-18 |
vset_max_response_queue_size() .............................................................................................. |
6-19 |
set_min_response_queue_size() ................................................................................................. |
6-19 |
set_read_response_id() ................................................................................................................ |
6-19 |
set_read_response_status() ......................................................................................................... |
6-19 |
set_response_burst_size() ............................................................................................................ |
6-20 |
set_response_data() ...................................................................................................................... |
6-20 |
set_response_latency() ................................................................................................................. |
6-20 |
set_response_request() ................................................................................................................. |
6-21 |
set_response_timeout() ................................................................................................................ |
6-21 |
set_write_response_id() ............................................................................................................... |
6-21 |
set_write_response_status() ........................................................................................................ |
6-22 |
signal_command_received() ....................................................................................................... |
6-22 |
signal_error_exceed_max_pending_reads ................................................................................ |
6-22 |
signal_max_response_queue_size .............................................................................................. |
6-23 |
signal_min_command_queue_size ............................................................................................ |
6-23 |
signal_fatal_error .......................................................................................................................... |
6-23 |
signal_response_issued ................................................................................................................ |
6-24 |
Avalon-MM Monitor .......................................................................................... |
7-1 |
Parameters .................................................................................................................................................... |
7-2 |
Avalon-MM Monitor Assertion Checking API ...................................................................................... |
7-4 |
set_enable_a_address_align_with_data_width() ....................................................................... |
7-4 |
set_enable_a_beginbursttransfer_exist() ..................................................................................... |
7-5 |
set_enable_a_beginbursttransfer_legal() ..................................................................................... |
7-5 |
set_enable_a_beginbursttransfer_single_cycle() ........................................................................ |
7-5 |
set_enable_a_begintransfer_exist() .............................................................................................. |
7-6 |
set_enable_a_begintransfer_legal() .............................................................................................. |
7-6 |
set_enable_a_begintransfer_single_cycle() ................................................................................. |
7-6 |
set_enable_a_burst_legal() ............................................................................................................ |
7-7 |
set_enable_a_byteenable_legal() ................................................................................................... |
7-7 |
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set_enable_a_constant_during_burst() ....................................................................................... |
7-7 |
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set_enable_a_constant_during_clk_disabled() .......................................................................... |
7-8 |
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set_enable_a_constant_during_waitrequest() ............................................................................ |
7-8 |
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set_enable_a_exclusive_read_write() ........................................................................................... |
7-8 |
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set_enable_a_half_cycle_reset_legal() ......................................................................................... |
7-9 |
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set_enable_a_less_than_burstcount_max_size() ....................................................................... |
7-9 |
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set_enable_a_less_than_maximumpendingreadtransactions() ............................................... |
7-9 |
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set_enable_a_no_readdatavalid_during_reset() ...................................................................... |
7-10 |
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set_enable_a_no_read_during_reset() ...................................................................................... |
7-10 |
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set_enable_a_no_write_during_reset() ..................................................................................... |
7-10 |
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set_enable_a_readid_sequence() ................................................................................................ |
7-11 |
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set_enable_a_read_response_sequence() .................................................................................. |
7-11 |
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set_enable_a_read_response_timeout() .................................................................................... |
7-11 |
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set_enable_a_register_incoming_signals() ............................................................................... |
7-12 |
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set_enable_a_waitrequest_during_reset() ................................................................................. |
7-12 |
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set_enable_a_waitrequest_timeout() ......................................................................................... |
7-12 |
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set_enable_a_write_burst_timeout() ......................................................................................... |
7-13 |
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set_enable_a_writeid_sequence() ............................................................................................... |
7-13 |
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Coverage Group ............................................................................................................................ |
7-13 |
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Transaction Monitoring ............................................................................................................... |
7-24 |
Avalon-ST Source BFM ...................................................................................... |
8-1 |
Timing .......................................................................................................................................................... |
8-1 |
Block Diagram ............................................................................................................................................. |
8-2 |
Parameters .................................................................................................................................................... |
8-3 |
Avalon-ST Source API................................................................................................................................ |
8-4 |
event_min_transaction_queue_size() .......................................................................................... |
8-5 |
event_response_done() .................................................................................................................. |
8-5 |
event_src_driving_transaction() ................................................................................................... |
8-5 |
event_src_not_ready() ................................................................................................................... |
8-5 |
event_src_ready() ............................................................................................................................ |
8-6 |
event_src_transaction_complete() ............................................................................................... |
8-6 |
get_response_latency() ................................................................................................................... |
8-6 |
get_response_queue_size() ............................................................................................................ |
8-7 |
get_src_ready() ................................................................................................................................ |
8-7 |
get_src_transaction_complete() ................................................................................................... |
8-7 |
get_transaction_queue_size() ........................................................................................................ |
8-7 |
get_version() .................................................................................................................................... |
8-8 |
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TOC-7 |
init() .................................................................................................................................................. |
8-8 |
pop_response() ................................................................................................................................ |
8-8 |
push_transaction() .......................................................................................................................... |
8-9 |
set_max_transaction_queue_size() .............................................................................................. |
8-9 |
set_min_transaction_queue_size() ............................................................................................... |
8-9 |
set_response_timeout() ................................................................................................................ |
8-10 |
set_transaction_channel() ........................................................................................................... |
8-10 |
set_transaction_data() .................................................................................................................. |
8-10 |
set_transaction_idles() ................................................................................................................. |
8-11 |
set_transaction_eop() ................................................................................................................... |
8-11 |
set_transaction_empty() .............................................................................................................. |
8-11 |
set_transaction_error() ................................................................................................................ |
8-11 |
set_transaction_sop() ................................................................................................................... |
8-12 |
signal_fatal_error .......................................................................................................................... |
8-12 |
signal_max_transaction_queue_size .......................................................................................... |
8-12 |
signal_min_transaction_queue_size .......................................................................................... |
8-12 |
signal_response_done .................................................................................................................. |
8-13 |
signal_src_driving_transaction ................................................................................................... |
8-13 |
signal_src_not_ready .................................................................................................................... |
8-13 |
signal_src_ready ............................................................................................................................ |
8-13 |
signal_src_transaction_complete ............................................................................................... |
8-14 |
Avalon-ST Sink BFM .......................................................................................... |
9-1 |
Timing .......................................................................................................................................................... |
9-1 |
Block Diagram ............................................................................................................................................. |
9-2 |
Parameters .................................................................................................................................................... |
9-3 |
Application Program Interface.................................................................................................................. |
9-4 |
event_sink_ready_assert() ............................................................................................................. |
9-5 |
event_sink_ready_deassert() ......................................................................................................... |
9-5 |
get_transaction_channel() ............................................................................................................. |
9-5 |
get_transaction_data() ................................................................................................................... |
9-5 |
get_transaction_idles() ................................................................................................................... |
9-6 |
get_transaction_eop() ..................................................................................................................... |
9-6 |
get_transaction_empty() ................................................................................................................ |
9-6 |
get_transaction_error() .................................................................................................................. |
9-7 |
get_transaction_queue_size() ........................................................................................................ |
9-7 |
get_transaction_sop() ..................................................................................................................... |
9-7 |
get_version() .................................................................................................................................... |
9-8 |
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init() .................................................................................................................................................. |
9-8 |
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pop_transaction() ............................................................................................................................ |
9-8 |
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set_ready() ........................................................................................................................................ |
9-9 |
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signal_fatal_error ............................................................................................................................ |
9-9 |
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signal_sink_ready_assert ............................................................................................................... |
9-9 |
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signal_sink_ready_deassert ......................................................................................................... |
9-10 |
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signal_transaction_received ........................................................................................................ |
9-10 |
Avalon-ST Monitor ........................................................................................... |
10-1 |
Parameters ................................................................................................................................................. |
10-2 |
Avalon-ST Monitor Assertion Checking API........................................................................................ |
10-3 |
set_enable_a_empty_legal() ........................................................................................................ |
10-3 |
set_enable_a_less_than_max_channel() ................................................................................... |
10-3 |
set_enable_a_no_data_outside_packet() ................................................................................... |
10-4 |
set_enable_a_non_missing_endofpacket() ............................................................................... |
10-4 |
set_enable_a_non_missing_startofpacket() .............................................................................. |
10-4 |
set_enable_a_valid_legal() ........................................................................................................... |
10-5 |
Coverage Group ............................................................................................................................ |
10-5 |
Transaction Monitoring ............................................................................................................ |
10-14 |
Conduit BFM .................................................................................................... |
11-1 |
Parameters ................................................................................................................................................. |
11-2 |
Conduit BFM API...................................................................................................................................... |
11-2 |
event_reset_asserted ..................................................................................................................... |
11-3 |
get_<role name>()......................................................................................................................... |
11-3 |
get_version() .................................................................................................................................. |
11-3 |
set_<role name>() ......................................................................................................................... |
11-4 |
set_<role name>_oe() ................................................................................................................... |
11-4 |
signal_input_<role name>_change ............................................................................................ |
11-4 |
Tri-State Conduit BFM..................................................................................... |
12-1 |
Parameters ................................................................................................................................................. |
12-2 |
Tri-State Conduit BFM API..................................................................................................................... |
12-2 |
event_interface_granted() ............................................................................................................ |
12-3 |
event_grant_deasserted_while_request_remain_asserted ...................................................... |
12-3 |
event_max_transaction_queue_size() ....................................................................................... |
12-3 |
event_min_transaction_queue_size() ........................................................................................ |
12-4 |
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TOC-9 |
get_input_transaction_queue_size()........................................................................................... |
12-4 |
get_output_transaction_queue_size() ....................................................................................... |
12-4 |
get_transaction_<role name>_in() ............................................................................................. |
12-4 |
get_transaction_latency() ............................................................................................................ |
12-5 |
get_version() .................................................................................................................................. |
12-5 |
pop_transaction() ......................................................................................................................... |
12-5 |
push_transaction() ........................................................................................................................ |
12-6 |
set_max_transaction_queue_size() ............................................................................................ |
12-6 |
set_min_transaction_queue_size() ............................................................................................. |
12-6 |
set_num_of_transactions() .......................................................................................................... |
12-7 |
set_transaction_<role name>_out() ........................................................................................... |
12-7 |
set_transaction_<role name>_outen() ...................................................................................... |
12-7 |
set_transaction_idles() ................................................................................................................. |
12-7 |
set_valid_transaction_<role name>_out() ................................................................................ |
12-8 |
signal_all_transactions_complete ............................................................................................... |
12-8 |
signal_fatal_error .......................................................................................................................... |
12-8 |
signal_grant_deasserted_while_request_remain_asserted ..................................................... |
12-9 |
signal_interface_granted .............................................................................................................. |
12-9 |
signal_max_transaction_queue_size .......................................................................................... |
12-9 |
signal_min_transaction_queue_size ........................................................................................ |
12-10 |
External Memory BFM ..................................................................................... |
13-1 |
Using the External Memory BFM .......................................................................................................... |
13-2 |
Parameters ................................................................................................................................................. |
13-2 |
External Memory BFM API..................................................................................................................... |
13-5 |
read() ............................................................................................................................................... |
13-5 |
signal_api_call ............................................................................................................................... |
13-6 |
write() ............................................................................................................................................. |
13-6 |
Nios II Custom Instruction Master BFM ......................................................... |
14-1 |
Parameters ................................................................................................................................................. |
14-2 |
Nios II Custom Instruction API.............................................................................................................. |
14-3 |
event_result_received() ................................................................................................................ |
14-3 |
Nios II Custom Instruction Slave BFM ............................................................ |
15-1 |
Parameters ................................................................................................................................................. |
15-2 |
Nios II Custom Instruction Slave BFM API.......................................................................................... |
15-3 |
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event_instruction_inconsistent() ................................................................................................ |
15-3 |
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event_instruction_unchanged() ................................................................................................. |
15-3 |
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event_result_driven() ................................................................................................................... |
15-4 |
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event_result_done() ...................................................................................................................... |
15-4 |
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event_unknown_instruction_received() ................................................................................... |
15-4 |
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get_ci_clk_en() .............................................................................................................................. |
15-5 |
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get_instruction_a() ....................................................................................................................... |
15-5 |
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get_instruction_b() ....................................................................................................................... |
15-5 |
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get_instruction_c() ....................................................................................................................... |
15-5 |
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get_instruction_dataa() ................................................................................................................ |
15-6 |
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get_instruction_datab() ............................................................................................................... |
15-6 |
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get_instruction_idle() ................................................................................................................... |
15-6 |
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get_instruction_n() ....................................................................................................................... |
15-6 |
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get_instruction_readra() .............................................................................................................. |
15-7 |
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get_instruction_readrb() .............................................................................................................. |
15-7 |
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get_instruction_writerc() ............................................................................................................. |
15-7 |
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get_version() .................................................................................................................................. |
15-8 |
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insert_result() ................................................................................................................................ |
15-8 |
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retrieve_instruction() ................................................................................................................... |
15-9 |
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set_clock_enable_timeout() ........................................................................................................ |
15-9 |
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set_instruction_a() ...................................................................................................................... |
15-10 |
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set_instruction_b() ..................................................................................................................... |
15-10 |
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set_instruction_c() ...................................................................................................................... |
15-10 |
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set_instruction_timeout() .......................................................................................................... |
15-10 |
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set_result_delay() ........................................................................................................................ |
15-11 |
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set_result_err_inject() ................................................................................................................ |
15-11 |
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set_result_value() ........................................................................................................................ |
15-11 |
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signal_fatal_error ........................................................................................................................ |
15-11 |
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signal_instructions_inconsistent .............................................................................................. |
15-12 |
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signal_known_instruction_received ........................................................................................ |
15-12 |
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signal_result_done ...................................................................................................................... |
15-12 |
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signal_result_driven ................................................................................................................... |
15-13 |
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signal_unknown_instruction_received ................................................................................... |
15-13 |
Avalon-ST Verilog HDL Testbench ................................................................. |
16-1 |
Verifying Avalon-ST DUT ...................................................................................................................... |
16-1 |
Understanding the Test Steps ................................................................................................................. |
16-2 |
Setting up the Test ........................................................................................................................ |
16-3 |
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TOC-11 |
Running the Simulation ............................................................................................................... |
16-5 |
Observing the Results ................................................................................................................... |
16-6 |
Avalon-MM Verilog HDL and VHDL Testbenches......................................... |
17-1 |
Avalon-MM Verilog HDL Testbench Description............................................................................... |
17-1 |
Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave |
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Pair.............................................................................................................................................. |
17-2 |
Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves.......... |
17-4 |
Avalon-MM VHDL Testbench Description.......................................................................................... |
17-6 |
Running the Testbench for a Single Avalon-MM Master and Slave Pair.............................. |
17-7 |
Running the Testbench for Two Avalon-MM Masters Slaves................................................ |
17-9 |
Using the VHDL BFMs ......................................................................................................................... |
17-10 |
Document Revision History ............................................................................. |
18-1 |
How to Contact Altera ............................................................................................................................. |
18-2 |
Typographic Conventions ....................................................................................................................... |
18-2 |
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Introduction to Avalon Verification IP Suite |
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The Avalon® Verification IP Suite provides bus functional models (BFMs) to simulate the behavior and facilitate the verification of IP. The Verification IP Suite includes BFMs for the following interfaces and components:
•Avalon Memory-Mapped (Avalon-MM) master and slave interfaces
•Avalon Streaming (Avalon-ST) source and sink interfaces
•Conduit interfaces and Avalon Tri-State conduit (Avalon-TC) interfaces
•Clock source and reset source
•Interrupt source and sink
•Custom instruction master and slave
•External memory
This suite also provides the following monitors to verify the respective Avalon protocols:
•Avalon-MM monitor
•Avalon-ST monitor
Advantages of Using BFMs and Monitors
Using the Altera-provided BFMs and monitors has the following advantages:
•It accelerates the verification process by providing key components of the verification testbench.
•It provides Avalon BFM components that implement the standard Avalon-MM and Avalon-ST protocols, serving as a reference for those protocols.
•For SystemVerilog users, the verification suite provides a platform that you can use to implement constraint-driven randomized tests. For example, you can implement the following modules for random testing:
•Traffic scenario drivers
•Scoreboard and coverage facilities
•Assertion checkers
BFM Implementation
Most components in the Avalon Verification IP Suite BFMs are implemented in SystemVerilog. The exceptions are the Clock Source and Reset Source BFMs that are written in VHDL. The BFM components use primarily
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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1-2 BFM Implementation
Verilog HDL with a few basic SystemVerilog constructs that are supported by ModelSim®-Altera Edition (AE).
The Quartus II software version 13.0 and higher extends VHDL BFM support in Qsys. The VHDL BFMs wrap the SystemVerilog implementation and include additional logic to support VDHL.
Table 1-1: BFM Language Support
BFM |
Verilog HDL |
VHDL Support |
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Support |
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Clock Source and Reset Source |
Yes |
Yes |
Avalon Interrupt Source and Sink |
Yes |
Version 13.0 and higher |
Avalon-MM Master, Slave, and Monitor |
Yes |
Version 13.0 and higher |
Avalon-ST Source, Sink, and Monitor |
Yes |
Version 13.0 and higher |
Conduit and Tri-State Conduit |
Yes |
Version 14.0 and higher |
External Memory |
Yes |
Version 13.0 and higher |
Nios II Custom Instruction Master and Slave |
Yes |
Version 13.0 and higher |
The VHDL BFM has four parts as shown in the figure below.
•SystemVerilog BFM—Contains the BFM implementation and behavioral model, and the SystemVerilog API. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
•VHDL package—Provides the VHDL API used to control the BFM and interface with your test program. The package contains VHDL procedures and events.
•API handler logic—SystemVerilog logic block that translates your test program’s VHDL API calls to SystemVerilog API calls. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
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Introduction to Avalon Verification IP Suite |
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Application Programming Interface |
1-3 |
• API communication interface—Bridges the VHDL API to the API handler logic.
Figure 1-1: VHDL Component BFM
VHDL BFM
BFM Interface
SystemVerilog
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API Handler
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The monitor components use the SystemVerilog Assertion (SVA) language and are supported only by simulators that support SVA, including:
•Modelsim-Altera Starter Edition (ASE)
•Synopsys VCS
•Mentor Graphics® Questa.
Application Programming Interface
Altera provides you with a set of application programming interfaces (API) for each Avalon Verification IP Suite BFM. You can use the APIs to construct, instantiate, control, and query signals in all BFM components. Your test programs must use only these public access methods and events to communicate with each BFM.
Note: You can design custom verification environments that do not take advantage of the API. However, Altera does not guarantee continued support or backwards compatibility custom methods.
Application Example of BFMs
The figure below shows an Avalon-MM design with the following components:
•An Avalon-MM device under test (DUT) that includes both Avalon-MM master and slave interfaces
•An Avalon-ST DUT that includes both source and sink interfaces, although typical components might include a single Avalon interface.
This figure illustrates it is possible to write a testbench using a traditional VerilogHDL implementation or using SystemVerilog with VMM.
Introduction to Avalon Verification IP Suite |
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1-4 Application Example of BFMs
Figure 1-2: Avalon Verification IP Suite Testbench for Avalon-MM and Avalon-ST Interfaces
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To verify a component with Avalon-MM interfaces, insert a monitor between the master BFM and the slave interface. To verify a component with Avalon-ST interfaces, insert a monitor between the source BFM and sink interface. You can insert a second monitor between the slave or sink BFM and the master or source interface of the DUT. You can inserted monitors anywhere in the system to provide protocol assertion checking and functional coverage reporting.
The test program drives the stimulus to the DUTs. The test program also determines whether the DUT behavior is correct, by analyzing the responses. The BFMs translate the test program stimuli. The BFMs create the signalling for the Avalon-MM and Avalon-ST protocols. The monitors verify Avalon protocol compliance and provide test coverage reports.
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Clock Source BFM 2
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The Avalon Verification IP Suite includes a Clock Source BFM that you can use to generate a clock signal for your testbench.
Note: The Clock Source BFM is only supported in Qsys.
Parameters
Table 2-1: Clock Source BFM Parameter Settings
Option |
Default Value |
Legal Values |
Description |
Clock rate |
10 |
N/A |
Specifies the clock rate in MHz. |
Clock Source API
clock_start()
Prototype: |
clock_start() |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
void |
Description: |
Turns on the clock. |
Language Support: |
Verilog HDL |
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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2-2 Clock_stop()
Clock_stop()
Prototype: |
clock_stop() |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
void |
Description: |
Turns off the clock. |
Language support: |
Verilog HDL |
get_run_state()
Prototype: |
get_run_state() |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
bit |
Description: |
Returns the state of the clock source; 1=running, 0=stop. |
Language support: |
Verilog HDL |
get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
string |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, |
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version 10.1 sp1 is encoded as "10.1.1". |
Language support: |
Verilog HDL |
Altera Corporation |
Clock Source BFM |
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Reset Source BFM 3
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The Avalon Verification IP Suite includes a Reset Source BFM that you can use to generate a reset signal in your testbench.
Parameters
Table 3-1: Reset Source BFM Parameter Settings
Option |
Default Value |
Legal Values |
Description |
Assert reset high |
On |
On/Off |
Specifies the polarity of the reset signal. Turn on |
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this option to set the reset signal active high. |
Cycles of initial |
0 |
N/A |
Specifies the number of cycles that the reset signal |
reset |
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is asserted at the initial stage of the simulation. |
Reset Source API
reset_assert
Prototype: |
reset_assert |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
void. |
Description: |
Asserts the reset signal. |
Language support: |
Verilog HDL |
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
ISO 9001:2008 Registered
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3-2 reset_deassert
reset_deassert
Prototype: |
reset_deassert |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
void. |
Description: |
Deasserts the reset signal. |
Language support: |
Verilog HDL |
get_version()
Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
String. |
Description: |
Returns BFM version as a string of three integers separated by periods. For example, |
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version 10.1 sp1 is encoded as "10.1.1". |
Language support: |
Verilog HDL |
Altera Corporation |
Reset Source BFM |
Send Feedback
Avalon Interrupt Source and Interrupt Sink BFMs |
4 |
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Subscribe |
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The Avalon Verification IP Suite includes Avalon Interrupt Source and Avalon Interrupt Sink BFMs for you to generate interrupt signals in your testbench.
Parameters
Table 4-1: Clock Source BFM Parameter Settings
Option |
Default Value |
Legal Values |
Description |
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Interrupt Source |
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Assert IRQ high |
On |
On/Off |
Specifies the polarity of the interrupt source signal. |
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Turn on this option to change the name of the |
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interrupt source signal port from irq to irq_n. |
IRQ width |
1 |
1–32 |
Specifies the width of the interrupt source signal. |
Asynchronous |
Off |
On/Off |
Specifies whether the interrupt signal is asserted |
IRQ |
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or deasserted immediately after an API call or one |
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clock cycle after an API call. Turn on this option |
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to allow changes to the interrupt signal |
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immediately after an API call. Turn off this option |
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next clock edge. |
VHDL BFM ID |
0 |
1–1023 |
For VHDL BFMs only. Use this option to assign |
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design. |
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Assert IRQ high |
On |
On/Off |
Specifies the polarity of the interrupt sink signal. |
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Turn on this option to change the name of the |
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interrupt source signal port from irq to irq_n. |
IRQ width |
1 |
1–32 |
Specifies the width of the interrupt source signal. |
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
ISO 9001:2008 Registered
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4-2 Interrupt Source and Sink API
Interrupt Source and Sink API
clear_irq()
Prototype: |
int clear_irq() |
Arguments: |
Verilog HDL: interrupt_bit |
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VHDL: interrupt_bit, bfm_id, req_if(bfm_id) |
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void |
Description: |
Asserts the interrupt signal and sets the interrupt signal to 0, |
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regardless of the value you set for Assert IRQ high in the parameter |
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editor. |
Language Support: |
Verilog HDL, VHDL |
get_irq()
get_irq() |
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Prototype: |
get_irq() |
Arguments: |
Verilog HDL: None |
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VHDL: irq, bfm_id, req_if(bfm_id) |
Returns: |
logic[AV_IRQ_W-1:0]void |
Description: |
Returns the current value of the register holding the latched |
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interrupt signal. |
Language Support: |
Verilog HDL, VHDL |
get_version() |
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get_version() |
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Prototype: |
string get_version() |
Arguments: |
Verilog HDL: None |
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VHDL: N.A. |
Returns: |
String |
Description: |
Returns BFM version as a string of three integers separated by |
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periods. For example, version 13.1 sp1 is encoded as "13.1.1". |
Language Support: |
Verilog HDL |
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Avalon Interrupt Source and Interrupt Sink BFMs |
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|
set_irq() |
4-3 |
set_irq() |
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set_irq() |
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Prototype: |
set_irq() |
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Description: |
Asserts the interrupt signal and sets the interrupt signal to 1, |
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regardless of the value you set for Assert IRQ high in the parameter |
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editor. |
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Language Support: |
Verilog HDL, VHDL |
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Avalon Interrupt Source and Interrupt Sink BFMs |
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Avalon-MM Master BFM 5
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The Avalon-MM Master BFM implements the Avalon-MM interface protocol, including: read, write, burst read, and burst write. The figure below shows the top-level modules for a testbench using the Avalon-MM BFM to verify an Avalon-MM slave component. The typical testbench includes the folowing components:
•The Avalon-MM Master BFM
•A test program
•The DUT that includes an Avalon-MM slave interface
Using the Avalon-MM BFM created by Altera, third-party, has the following advantage. It highlights any misinterpretation of the Avalon-MM protocol that might be missed in a testbench designed by a single engineer.
Note: The BFMs allow illegal transactions so that you can test the error-handling functionality of your DUT. Consequently, the BFMs cannot be relied upon to guarantee protocol compliance. The Avalon Monitor components verify protocol compliance.
Figure 5-1: Top-Level Module to Verify an Avalon-MM Slave Device
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Related Information
Avalon Interface Specifications
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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5-2 Timing
Timing
The following timing diagram illustrates the sequence of events for an Avalon-MM Master BFM. The Master BFM drives interleaved writes and reads when the readdatavalid signal is present. This diagram serves as a reference for the following discussion of API and events.
Figure 5-2: Avalon-MM Master Driving Interleaved Write and Read Transactions
transaction1 |
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Altera Corporation |
Avalon-MM Master BFM |
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Timing 5-3
Table 5-1: Key to the Annotations
The following table lists the annotations used in the figure.
Symbol
Tinit
Twt_1
Description
The initial command latency, which is two cycles for transactions 1 and 2. This time is set by the API command set_command_init_latency.
The response wait time, which is three cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_ response_wait_time command.
Twr
Tidle
Trl_1
Trl_2
Twrl_1
waitrequest is always sampled #1 after the falling edge of clk.
The idle time after each transaction. This time is set by the command set_command_idle.
The response latency for the first read, which is 3 cycles. This is the time between the read command acceptance and the read response provided by the slave. The program gets this time using the get_response_latency command.
If an Avalon-MM slave component defines the readLatency interface property, the readdatavalid signal is not used. The readdatavalid signal is not necessary because the slave component has a fixed read latency.
For more information refer to the Avalon Interface Specifications.
The response latency for the second read, which is 3 cycles. The program gets this time using the get_response_latency command.
The write response latency for the first write, which is 3 cycles. This is the time between when the write command acceptance and the write response is provided by the slave. The program gets this time using the get_response_latency command.
Sci_1–Sci_4
Src_1,Src_3
Src_2,Src_4
Satc
TID_1–TID_
4
Signals when write or read commands are presented on the interface. The event name is signal_ command_issued.
Signals write responses. The event name is signal_response_complete.
Signals read responses. The event name is signal_response_complete.
Signals the end of the test. The event name is signal_all_transactions_complete
Reference number to identify each read or write transaction.
ID_1, ID_3 
Reference number to identify each write transaction.
ID_2, ID_4 Reference number to identify each read transaction.
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5-4 Timing
Figure 5-3: Avalon-MM Master Driving Write and Read Transactions with No readdatavalid Signal
The timing in the following figure shows the sequence of events for an Avalon-MM Master BFM. The Avalon-MM Master BFM drives a write followed by a read when the readdatavalid signal is not present.
transaction5 transaction6
CLK
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Table 5-2: Key to the Annotations
The following table lists the annotations used in this figure.
Symbol
Tinit
Twt_1
Description
The initial command latency, which is 2 cycles for transactions 1 and 2. This time is set by the API command set_command_init_latency.
The response wait time, which is 3 cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_ response_wait_time command.
Twt_2
Twr
Tidle
The response wait time for the first read, which is 2 cycles. This time is determined by the number of cycles that the waitrequest signal is asserted by the slave.The program gets this value using the get_response_wait_time command.
waitrequest is always sampled #1 after the falling edge of clk.
The idle time after a transaction. This time is set by the command set_command_idle.
Altera Corporation |
Avalon-MM Master BFM |
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Symbol
Sci_1–Sci_2
Src_1
Satc
Block Diagram |
5-5 |
Description
Signals when write and read commands are presented on the interface. The event name is signal_command_issued.
Signals the first read response. The event name is signal_response_complete.
Signals the end of the test. The event name is signal_all_transactions_complete.
Block Diagram
The following figure provides a block diagram of the Avalon-MM Master BFM. As this figure illustrates, the BFM includes the following major blocks:
•Avalon-MM Master API—Provides methods to create Avalon-MM transactions and query the state of all queues.
•Command Descriptor—Accumulates the fields of an Avalon-MM command transaction using the set_command API call. Inserts completed commands onto the pending command queue.
•Avalon-MM Interface Driver—Issues transfers to the system interconnect fabric and holds each transfer until waitrequest is deasserted. For burst transfers, there is a separate transfer for each word of the burst. The system interconnect fabric can assert waitrequest for each word of the burst, as necessary.
•Timestamp Counter—Records a timestamp with commands for use in timing calculations. The driver and monitor both use the timestamp counter for timing calculations.
•Avalon-MM Interface Monitor—Monitors the system interconnect fabric and records responses for read transfers in the response queue.
•Response Descriptor—Collects information about completed transactions using the get_response_<rolename> API calls. The testbench uses this information for further analysis.
Avalon-MM Master BFM |
Altera Corporation |
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5-6 Parameters
•Public Events—Provides status response that arrives together with the data. The public event signals indicate the status of the Master’s request, such as successful completion, timeout, or error.
Figure 5-4: Block Diagram of the Avalon-MM Master BFM
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(Transaction Level Commands |
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Command Descriptor |
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Response Descriptor |
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Public Events |
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Pending |
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Pending |
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Timestamp |
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Read and Write |
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Command |
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Counter |
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Response Queue |
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Queue |
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Issued |
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Avalon-MM Interface |
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Command |
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Avalon-MM Interface |
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Driver |
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Queue |
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Receiver |
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command |
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waitrequest |
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response |
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waitrequest |
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Transfer Level |
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MAvalon-MM Master Port
SAvalon-MM Slave Port
SystemVerilog
Parameters
The Avalon-MM BFM supports the full range of signals defined for the Avalon-MM master interface. You can customize the Avalon-MM master interface using the parameters described in the following table.
Altera Corporation |
Avalon-MM Master BFM |
Send Feedback
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Parameters |
5-7 |
Table 5-3: Parameters for the Avalon-MM Master BFM |
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Parameter |
Default |
Legal Values |
Description |
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Value |
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Port Widths |
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Address width |
32 |
N/A |
Address width in bits. |
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Symbol width |
8 |
N/A |
Data symbol width in bits. The symbol width should be |
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8 for byte-oriented interfaces. |
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Read Response width |
8 |
N/A |
Read response signal width in bits. |
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Write Response width |
8 |
N/A |
Write response signal width in bits. |
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Parameters |
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Number of symbols |
4 |
N/A |
Number of symbols per word. |
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Burstcount width |
3 |
N/A |
The width of the burst count in bits. |
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Port Enables |
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Use the read signal |
On |
On/Off |
When On, the interface includes a read pin. |
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Use the write signal |
On |
On/Off |
When On, the interface includes a write pin. |
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Use the address signal |
On |
On/Off |
When On, the interface includes address pins. |
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Use the byteenable |
On |
On/Off |
When On, the interface includes byteenable pins. |
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signal |
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Use the burstcount |
On |
On/Off |
When On, the interface includes burstcount pins. |
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signal |
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Use the readdata signal |
On |
On/Off |
When On, the interface includes a readdata pin. |
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Use the readdatavalid |
On |
On/Off |
When On, the interface includes a readdatavalid pin. |
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signal |
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Use the writedata signal |
On |
On/Off |
When On, the interface includes a writedata pin. |
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Use the begintransfer |
Off |
On/Off |
When On, the interface includes writedata pins |
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signal |
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Use the beginburst- |
Off |
On/Off |
When On, the interface includes a beginbursttransfer |
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transfer signal |
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pins. |
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Use the arbiterlock |
Off |
On/Off |
When On, the interface includes an arbiterlock pin. |
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signal |
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Use the lock signal |
Off |
On/Off |
When On, the interface includes a lock pin. |
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Use the debugaccess |
Off |
On/Off |
When On, the interface includes a debugaccess pin. |
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signal |
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Use the waitrequest |
On |
On/Off |
When On, the interface includes a waitrequest pin. |
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signal |
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Use the transactionid |
Off |
On/Off |
When On, the interface includes a transactionid pin. |
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signal |
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Avalon-MM Master BFM |
Altera Corporation |
Send Feedback
5-8 |
Parameters |
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Parameter |
Default |
Legal Values |
Description |
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Value |
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Use the write response |
Off |
On/Off |
When On, the interface includes a writeresponse pin. |
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signals |
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Use the read response |
Off |
On/Off |
When On, the interface includes a readresponse pin. |
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signals |
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Use the clken signals |
Off |
On/Off |
When On, the interface includes a clken pin. |
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Port Polarity |
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Assert reset high |
On |
On/Off |
When On, reset is asserted high. |
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Assert waitrequest high |
On |
On/Off |
When On, waitrequest is asserted high. |
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Assert read high |
On |
On/Off |
When On, read is asserted high. |
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Assert write high |
On |
On/Off |
When On, write is asserted high. |
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Assert byteenable high |
On |
On/Off |
When On, byteenable is asserted high. |
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Assert readdatavalid |
On |
On/Off |
When On, readdatavalid is asserted high. |
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high |
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Assert arbiterlock high |
On |
On/Off |
When On, arbiterlock is asserted high. |
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Assert lock high |
On |
On/Off |
When On, lock is asserted high. |
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Burst Attributes |
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Linewrap burst |
On |
On/Off |
When On, the address for bursts wraps instead of |
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incrementing. With a wrapping burst, when the address |
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reaches a burst boundary, it wraps back to the previous |
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burst boundary. Consequently, only the low order bits |
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are used for addressing. |
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Burst on burst |
On |
On/Off |
When On, memory bursts are aligned to the address size. |
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boundaries only |
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Miscellaneous |
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Maximum pending |
1 |
N/A |
The maximum number of pending reads that can be |
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reads |
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queued by the slave. |
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Fixed read latency |
1 |
N/A |
Sets the read latency for fixed-latency slaves. Not used on |
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(cycles) |
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interfaces that include the readdatavalid signal. |
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VHDL BFM ID |
0 |
0–1023 |
For VHDL BFMs only. Use this option to assign a unique |
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number to each BFM in the testbench design. |
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Timing |
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Fixed read wait time |
1 |
N/A |
For master interfaces that do not use the waitrequest |
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(cycles) |
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signal. The read wait time indicates the number of cycles |
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before the master responds to a read. The timing is as if |
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the master asserted waitrequest for this number of |
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cycles. |
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Fixed write wait time |
0 |
N/A |
For master interfaces that do not use the waitrequest |
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(cycles) |
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signal. The write wait time indicates the number of cycles |
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before the master accepts a write. |
Altera Corporation |
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Avalon-MM Master BFM |
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Send Feedback |
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