ALTERA Cyclone V User Guide

5. I/O Features in Cyclone V Devices

CV-52005-2.0

This chapter provides details about the features of the Cyclone® V I/O elements (IOEs) and how the IOEs work in compliance with current and emerging I/O standards and requirements.

Cyclone V I/Os support a wide range of features:

■Single-ended, non voltage-referenced, and voltage-referenced I/O standards

■Low-voltage differential signaling (LVDS), scalable low-voltage signaling (SLVS),

RSDS, mini-LVDS, HSTL, HSUL, and SSTL I/O standards

■Serializer/deserializer (SERDES)

■Programmable output current strength

■Programmable slew-rate

■Programmable bus-hold

■Programmable pull-up resistor

■Programmable pre-emphasis

■Programmable I/O delay

■Programmable voltage output differential (VOD)

■Open-drain output

■On-chip series termination (RS OCT)

■On-chip parallel termination (RT OCT)

■On-chip differential termination (RD OCT)

■High-speed differential I/O support

1The information in this chapter is applicable to all Cyclone V variants, unless noted otherwise.

This chapter contains the following sections:

■“I/O Standards Support” on page 5–2

■“Design Considerations” on page 5–4

■“I/O Banks” on page 5–8

■“IOE Features” on page 5–13

■“Programmable IOE Features” on page 5–16

■“OCT Schemes” on page 5–19

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Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

June 2012

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5–2	Chapter 5: I/O Features in Cyclone V Devices
	I/O Standards Support

■“I/O Standards Termination Schemes” on page 5–27

■“High-Speed Differential I/O Interfaces” on page 5–36

■“LVDS Channels and Dedicated Circuitry” on page 5–40

■“Fractional PLLs and Cyclone V Clocking” on page 5–44

■“Differential Transmitter” on page 5–45

■“Differential Receiver” on page 5–49

■“Source-Synchronous Timing Budget” on page 5–56

I/O Standards Support

Table 5–1 lists the supported I/O standards and typical power supply values

Table 5–1. Cyclone V I/O Standards and Voltage Levels (1) (Part 1 of 2)

		VCCIO (V)		VCCPD (V)	VREF (V)		VTT (V)
I/O Standard	Standard Support			(Pre-Driver			(Board
		Input	Output	Voltage)	(Input Ref		Termination
					Voltage)
		Operation	Operation				Voltage)
3.3-V LVTTL/3.3-V LVCMOS (2)	JESD8-B	3.3/3.0/2.5	3.3	3.3	—		—
3.0-V LVTTL/3.0-V LVCMOS (2)	JESD8-B	3.0/2.5	3.0	3.0	—		—
2.5-V LVCMOS (2)	JESD8-5	3.0/2.5	2.5	2.5	—		—
1.8-V LVCMOS (2), (3)	JESD8-7	1.8/1.5	1.8	2.5	—		—
1.5-V LVCMOS (2)	JESD8-11	1.8/1.5	1.5	2.5	—		—
1.2-V LVCMOS	JESD8-12	1.2	1.2	2.5	—		—
3.0-V PCI (4)	PCI Rev. 2.2	3.0	3.0	3.0	—		—
3.0-V PCI-X (4), (5)	PCI-X Rev. 1.0	3.0	3.0	3.0	—		—
SSTL-2 Class I	JESD8-9B	(6)	2.5	2.5	1.25		1.25
SSTL-2 Class II	JESD8-9B	(6)	2.5	2.5	1.25		1.25
SSTL-18 Class I (3)	JESD8-15	(6)	1.8	2.5	0.90		0.90
SSTL-18 Class II (3)	JESD8-15	(6)	1.8	2.5	0.90		0.90
SSTL-15 Class I (3)	—	(6)	1.5	2.5	0.75		0.75
SSTL-15 Class II (3)	—	(6)	1.5	2.5	0.75		0.75
SSTL-15	JESD79-3D	(6)	1.5	2.5	0.75		— (7)
SSTL-135 (3)	—	(6)	1.35	2.5	0.675		— (7)
SSTL-125 (3)	—	(6)	1.25	2.5	0.625		— (7)
1.8-V HSTL Class I	JESD8-6	(6)	1.8	2.5	0.90		0.90
1.8-V HSTL Class II	JESD8-6	(6)	1.8	2.5	0.90		0.90
1.5-V HSTL Class I (2)	JESD8-6	(6)	1.5	2.5	0.75		0.75
1.5-V HSTL Class II (2)	JESD8-6	(6)	1.5	2.5	0.75		0.75
1.2-V HSTL Class I	JESD8-16A	(6)	1.2	2.5	0.6		0.6
1.2-V HSTL Class II	JESD8-16A	(6)	1.2	2.5	0.6		0.6
HSUL-12 (3)	—	(6)	1.2	2.5	0.6		— (7)
Differential SSTL-2 Class I	JESD8-9B	(6)	2.5	2.5	—		1.25
Cyclone V Device Handbook					June 2012	Altera Corporation

Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices	5–3
I/O Standards Support

Table 5–1. Cyclone V I/O Standards and Voltage Levels (1)			(Part 2 of 2)
			VCCIO (V)		VCCPD (V)	VREF (V)	VTT (V)
I/O Standard	Standard Support				(Pre-Driver		(Board
		Input		Output	Voltage)	(Input Ref	Termination
						Voltage)
		Operation		Operation			Voltage)
Differential SSTL-2 Class II	JESD8-9B		(6)	2.5	2.5	—	1.25
Differential SSTL-18 Class I	JESD8-15		(6)	1.8	2.5	—	0.90
Differential SSTL-18 Class II	JESD8-15		(6)	1.8	2.5	—	0.90
Differential SSTL-15 Class I	—		(6)	1.5	2.5	—	0.75
Differential SSTL-15 Class II	—		(6)	1.5	2.5	—	0.75
Differential 1.8-V HSTL Class I	JESD8-6		(6)	1.8	2.5	—	0.90
Differential 1.8-V HSTL Class II	JESD8-6		(6)	1.8	2.5	—	0.90
Differential 1.5-V HSTL Class I	JESD8-6		(6)	1.5	2.5	—	0.75
Differential 1.5-V HSTL Class II	JESD8-6		(6)	1.5	2.5	—	0.75
Differential 1.2-V HSTL Class I	JESD8-16A		(6)	1.2	2.5	—	0.60
Differential 1.2-V HSTL Class II	JESD8-16A		(6)	1.2	2.5	—	0.60
Differential SSTL-15	JESD79-3D		(6)	1.5	2.5	—	— (7)
Differential SSTL-135	—		(6)	1.35	2.5	—	— (7)
Differential SSTL-125	—		(6)	1.25	2.5	—	— (7)
Differential HSUL-12	—		(6)	1.2	2.5	—	— (7)
LVDS	ANSI/TIA/EIA-644		(6)	2.5	2.5	—	—
RSDS	—		(6)	2.5	2.5	—	—
Mini-LVDS	—		(6)	2.5	2.5	—	—
LVPECL (8)	—		(6)	—	2.5	—	—
SLVS (9)	JESD8-13		(6)	—	2.5	—	—

Notes to Table 5–1:

(1)You cannot assign SSTL, HSTL, and HSUL outputs on VREF pins, even if there are no SSTL, HSTL, and HSUL inputs in the bank.

(2)Supported in the hard processor system (HPS) column I/Os.

(3)Supported in the HPS row I/Os.

(4)The 3.3 V PCI and PCI-X I/O standards are not supported.

(5)PCI-X does not meet the PCI-X I-V curve requirement at the linear region.

(6)Single-ended HSTL/SSTL/HSUL, differential SSTL/HSTL/HSUL, and LVDS input buffers are powered by VCCPD.

(7)This I/O standard typically does not require board termination.

(8)The support for the LVPECL I/O standard is only for input clock operation.

(9)The support for the SLVS I/O standard is only for input operation.

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5–4	Chapter 5: I/O Features in Cyclone V Devices
	Design Considerations

Design Considerations

There are several considerations that require your attention to ensure the success of your designs.

fFor more information about absolute maximum rating and maximum allowed overshoot during transitions, refer to the Cyclone V Device Datasheet.

I/O Bank Restrictions

The following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in the devices.

Non-Voltage-Referenced Standards

Each Cyclone V I/O bank has its own VCCIO pins and supports only one VCCIO (1.2, 1.25, 1.35, 1.5, 1.8, 2.5, 3.0, or 3.3 V). An I/O bank can simultaneously support any

number of input signals with different I/O standard assignments if the I/O standards support the VCCIO level of the I/O bank.

For output signals, a single I/O bank supports non-voltage-referenced output signals

that drive at the same voltage as VCCIO. Because an I/O bank can only have one VCCIO value, it can only drive out the value for non-voltage-referenced signals.

For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V standard inputs and outputs, and 3.0-V LVCMOS inputs only.

Voltage-Referenced Standards

To accommodate voltage-referenced I/O standards, each Cyclone V I/O bank

contains a dedicated VREF pin. Each bank can have only a single VCCIO voltage level and a single voltage reference (VREF) level.

An I/O bank featuring single-ended or differential standards can support different voltage-referenced standards if the VCCIO and VREF are the same levels.

Voltage-referenced bidirectional and output signals must be the same as the VCCIO voltage of the I/O bank.

For example, you can place only SSTL-2 output pins in an I/O bank with a 2.5-V VCCIO.

Mixing Voltage-Referenced and Non-Voltage-Referenced Standards

An I/O bank can support voltage-referenced and non-voltage-referenced pins by applying each of the rule sets individually.

First example: an I/O bank can support SSTL-18 inputs and outputs, and 1.8-V inputs and outputs with a 1.8-V VCCIO and a 0.9-V VREF.

Second example: an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs), and 1.5-V HSTL I/O standards with a 1.5-V VCCIO and 0.75-V VREF.

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices	5–5
Design Considerations

VCCPD Restriction

One VCCPD pin is shared in a group of I/O banks. The VCCPD grouping on Cyclone V are as follows. Each line item is a separate group:

■BANK 3A

■BANK3B + BANK4A

■BANK5A

■BANK5B

■BANK6A

■BANK7A + BANK8A

First example: if one I/O bank in a group uses 3.0-V VCCPD, other I/O banks in the same group must also use 3.0-V VCCPD. This would also require each I/O bank in the same group to also use a 3.0-V VCCIO.

Second example: if one I/O bank in a group uses a 2.5-V VCCPD, other I/O banks in the same group must also use 2.5-V VCCPD. However, each I/O bank can use different VCCIO voltages provided they are 1.2, 1.25, 1.35, 1.5, 1.8, or 2.5 V.

VCCIO Restriction

When planning the I/O bank usage, you must ensure the VCCIO voltage is compatible with the VCCPD voltage of the same bank. Some banks may share the same VCCPD power pin. This limits the possible VCCIO voltages that can be used on banks that share VCCPD power pins.

First example: if VCCPD3B is connected to 2.5 V, then the VCCIO pins for banks 3B and 4A can be connected to any of the following voltages: 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, or 2.5 V.

Second example: if VCCPD3B is connected to 3.0 V, then the VCCIO pins for banks 3B and 4A must also be connected to 3.0 V.

VREF Pin Restriction

You cannot assign shared VREF pins as LVDS or external memory interface pins.

SSTL, HSTL, and HSUL I/O standards do not support shared VREF pins.

For example, if a particular B1p or B1n pin is a shared VREF pin, the corresponding B1p/B1n pin pair do not have LVDS transmitter support.

Shared VREF pins will have reduced performance when used as normal I/Os. You must perform SI analysis using your board design to determine the FMAX for your system.

3.3-V I/O Interface

To ensure device reliability and proper operation when you use the Cyclone V device for 3.3-V I/O interfacing, do not violate the absolute maximum ratings of the device.

For a transmitter, use slow slew-rate and series termination to limit the overshoot and undershoot at the I/O pins.

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5–6	Chapter 5: I/O Features in Cyclone V Devices
	Design Considerations

For a receiver, use the on-chip clamp diode to limit the overshoot and undershoot voltage at the I/O pins.

fFor more information about absolute maximum rating and maximum allowed overshoot during transitions, refer to the Cyclone V Device Datasheet.

1Altera recommends that you perform IBIS or SPICE simulations to make sure the overshoot and undershoot voltages are within the specifications.

LVDS Channels

For LVDS applications, you must use the phase-locked loops (PLLs) in integer PLL mode.

Differential Pin Placement

When you use LVDS channels, adhere to the guidelines in the following sections.

The Quartus® II compiler automatically checks the design and issues an error message if the guidelines are not followed to ensure proper high-speed operation.

For more information about the Cyclone V device high-speed differential I/O interfaces, refer to “High-Speed Differential I/O Interfaces” on page 5–36.

LVDS Channel Driving Distance

Each PLL can drive all the LVDS channels in the entire quadrant.

Using Corner and Center PLLs

You can use a corner PLL to drive all transmitter channels and a center PLL to drive all LVDS receiver channels in the same I/O bank.

A corner PLL and a center PLL can drive duplex channels in the same I/O quadrant if the channels that are driven by each PLL are not interleaved.

You do not require separation between the group of channels that are driven by the corner and center, left and right PLLs.

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices	5–7
Design Considerations

Figure 5–1 shows two different PLLs driving a transmitter channel and a receiver channel in the same LVDS module.

3

Figure 5–1. Corner and Center PLLs Driving LVDS Differential I/Os in the Same Quadrant

Corner PLL

Corner PLL

Reference CLK

Reference CLK

Diff RX

Diff TX

LVDS I/O

Channels Driven

Diff RX

Diff TX

LVDS I/O

by Corner PLL

Diff RX

Diff TX

LVDS I/O

Diff RX

Diff TX

LVDS I/O

Diff RX

Diff TX

LVDS I/O

No Separation

Buffer Needed

Diff RX

Diff TX

LVDS I/O

Diff RX

Diff TX

LVDS I/O

Diff RX

Diff TX

LVDS I/O

Channels Driven

Diff RX

Diff TX

LVDS I/O

by Center PLL

Diff RX

Diff TX

LVDS I/O

Reference CLK

Reference CLK

Center PLL

Center PLL

Figure 5–2. shows invalid placement of the LVDS I/Os.

Figure 5–2. Invalid Placement of LVDS I/Os Due to Interleaving of Channels Driven by the Corner and Center PLLs

Corner PLL

Reference CLK

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

LVDS I/O

Reference CLK

Center PLL

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5–8	Chapter 5: I/O Features in Cyclone V Devices
	I/O Banks

I/O Banks

The number of Cyclone V I/O banks in a particular device depends on the device density.

Each I/O bank can simultaneously support multiple I/O standards.

Figure 5–3 shows the I/O banks in Cyclone V E devices.

Figure 5–3. I/0 Banks for Cyclone V E Devices (1)

		Bank 8A			Bank 7A
						Bank 6A
Bank 2A
						Bank 5B
						Bank 5A
		Bank 3A		Bank 3B	Bank 4A

Note to Figure 5–3:

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

Figure 5–4 shows the I/O banks in Cyclone V GX and GT devices.

Figure 5–4. I/0 Banks for Cyclone V GX and GT Devices (1)

		Bank 8A			Bank 7A
Block						Bank 6A
Transceiver
						Bank 5B
						Bank 5A
		Bank 3A		Bank 3B	Bank 4A

Note to Figure 5–4:

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices	5–9
I/O Banks

Figure 5–5 shows the I/O banks in Cyclone V SE devices.

Figure 5–5. I/0 Banks for Cyclone V SE Devices (1)

Bank 8A	HPS Column I/O

HPS Core

Bank 3A	Bank 3B	Bank 4A

Note to Figure 5–5:

Bank 5A Bank 5B HPS Row I/O

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

Figure 5–6 shows the I/O banks in Cyclone V SX and ST devices.

Figure 5–6. I/0 Banks for Cyclone V SX and ST Devices (1)

Bank 8A	HPS Column I/O

HPS Core

Transceiver Block

Bank 3A	Bank 3B	Bank 4A

Note to Figure 5–6:

Bank 5A Bank 5B HPS Row I/O

(1) This is a top view of the silicon die that corresponds to a reverse view of the device package.

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5–10	Chapter 5: I/O Features in Cyclone V Devices
	I/O Banks

Modular I/O Banks

The I/O pins in Cyclone V devices are arranged in groups called modular I/O banks. Table 5–2 list the modular I/O banks for Cyclone V E devices.

Table 5–2. Modular I/O Banks for Cyclone V E Devices —Preliminary

	Member	Package				FPGA I/O Bank						Total
	Code		2A	3A	3B	4A	5A	5B	6A	7A	8A
		F256	16	16	16	16	16	16	—	16	16	128
	A2	U324	32	16	16	32	16	16	—	32	16	176
		U484	16	16	32	48	16	16	—	48	32	224
		F484	16	16	32	48	16	16	—	48	32	224
		F256	16	16	16	16	16	16	—	16	16	128
	A4	U324	32	16	16	32	16	16	—	32	16	176
		U484	16	16	32	48	16	16	—	48	32	224
		F484	16	16	32	48	16	16	—	48	32	224
	A5	U484	—	16	32	48	16	32	—	48	32	224
		F484	—	16	32	48	16	16	—	80	32	240
		U484	—	16	32	48	16	48	—	48	32	240
	A7	F484	—	16	32	48	16	16	—	80	32	240
		F672	—	16	32	80	16	64	16	80	32	336
		F896	—	32	48	80	32	48	80	80	80	480
		F484	—	16	32	48	16	16	—	64	32	224
	A9	F672	—	16	32	80	16	32	48	80	32	336
		F896	—	32	48	80	32	48	80	80	80	480

Table 5–3 list the modular I/O banks for Cyclone V GX devices.

Table 5–3. Modular I/O Banks for Cyclone V GX Devices (Part 1 of 2)—Preliminary

Member	Package				FPGA I/O Bank					Total
Code		3A	3B	4A	5A	5B	6A	7A	8A
	U324	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD
C3	U484	16	32	48	16	16	—	48	32	208
	F484	16	32	48	16	16	—	48	32	208
	U484	16	32	48	16	32	—	48	32	224
C4	F484	16	32	48	16	16	—	80	32	240
	F672	16	32	80	16	64	16	80	32	336
	U484	16	32	48	16	32	—	48	32	224
C5	F484	16	32	48	16	16	—	80	32	240
	F672	16	32	80	16	64	16	80	32	336

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Chapter 5: I/O Features in Cyclone V Devices	5–11
I/O Banks

Table 5–3. Modular I/O Banks for Cyclone V GX Devices (Part 2 of 2)—Preliminary

	Member	Package				FPGA I/O Bank					Total
	Code		3A	3B	4A	5A	5B	6A	7A	8A
		U484	16	32	48	16	48	—	48	32	240
	C7	F484	16	32	48	16	16	—	80	32	240
		F672	16	32	80	16	64	16	80	32	336
		F896	32	48	80	32	48	80	80	80	480
		F484	16	32	48	16	16	—	64	32	224
	C9	F672	16	32	80	16	32	48	80	32	336
		F896	32	48	80	32	48	80	80	80	480
		F1152	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD

Table 5–4 list the modular I/O banks for Cyclone V GT devices.

Table 5–4. Modular I/O Banks for Cyclone V GT Devices —Preliminary

	Member	Package				FPGA I/O Bank					Total
	Code		3A	3B	4A	5A	5B	6A	7A	8A
		U484	16	32	48	16	32	—	48	32	224
	D5	F484	16	32	48	16	16	—	80	32	240
		F672	16	32	80	16	64	16	80	32	336
		U484	16	32	48	16	48	—	48	32	240
	D7	F484	16	32	48	16	16	—	80	32	240
		F672	16	32	80	16	64	16	80	32	336
		F896	32	48	80	32	48	80	80	80	480
		F484	16	32	48	16	16	—	64	32	224
	D9	F672	16	32	80	16	32	48	80	32	336
		F896	32	48	80	32	48	80	80	80	480
		F1152	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD

Table 5–5 list the modular I/O banks for Cyclone V SE devices.

Table 5–5. Modular I/O Banks for Cyclone V SE Devices (Part 1 of 2)—Preliminary

	Member			FPGA I/O Bank					HPS Row		HPS Column I/O				FPGA I/O
		Package							I/O Bank			Bank			Bank	Total
	Code
			3A	3B	4A	5A		5B	6A	6B	7A	7B	7C	7D	8A
	A2	U484	16	6	22	16		—	52	23	19	21	8	14	6	203
		U672	16	32	68	16		—	56	44	19	22	12	14	13	312
	A4	U484	16	6	22	16		—	52	23	19	21	8	14	6	203
		U672	16	32	68	16		—	56	44	19	22	12	14	13	312
		U484	16	6	22	16		—	52	23	19	21	8	14	6	203
	A5	U672	16	32	68	16		—	56	44	19	22	12	14	13	312
		F896	32	48	80	32		16	56	44	19	22	12	14	80	455
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5–12	Chapter 5: I/O Features in Cyclone V Devices
	I/O Banks

Table 5–5. Modular I/O Banks for Cyclone V SE Devices (Part 2 of 2)—Preliminary

Member			FPGA I/O Bank					HPS Row		HPS Column I/O				FPGA I/O
	Package							I/O Bank			Bank			Bank	Total
Code
		3A	3B	4A	5A		5B	6A	6B	7A	7B	7C	7D	8A
	U484	16	6	22	16		—	52	23	19	21	8	14	6	203
A6	U672	16	32	68	16		—	56	44	19	22	12	14	13	312
	F896	32	48	80	32		16	56	44	19	22	12	14	80	455

Table 5–6 list the modular I/O banks for Cyclone V SX devices.

Table 5–6. Modular I/O Banks for Cyclone V SX Devices —Preliminary

Member			FPGA I/O Bank					HPS Row		HPS Column I/O				FPGA I/O
	Package							I/O Bank			Bank			Bank	Total
Code
		3A	3B	4A	5A		5B	6A	6B	7A	7B	7C	7D	8A
C2	U672	16	32	68	16		—	56	44	19	22	12	14	13	312
C4	U672	16	32	68	16		—	56	44	19	22	12	14	13	312
C5	U672	16	32	68	16		—	56	44	19	22	12	14	13	312
	F896	32	48	80	32		16	56	44	19	22	12	14	80	455
C6	U672	16	32	68	16		—	56	44	19	22	12	14	13	312
	F896	32	48	80	32		16	56	44	19	22	12	14	80	455

Table 5–7 list the modular I/O banks for Cyclone V ST devices.

Table 5–7. Modular I/O Banks for Cyclone V ST Devices —Preliminary

Member			FPGA I/O Bank					HPS Row		HPS Column I/O				FPGA I/O
	Package							I/O Bank			Bank			Bank	Total
Code
		3A	3B	4A	5A		5B	6A	6B	7A	7B	7C	7D	8A
D5	F896	32	48	80	32		16	56	44	19	22	12	14	80	455
D6	F896	32	48	80	32		16	56	44	19	22	12	14	80	455

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices

5–13

IOE Features

IOE Features

The IOEs in Cyclone V devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.

The IOEs are located in I/O blocks around the periphery of the Cyclone V device.

Figure 5–7 shows the Cyclone V IOE structure.

Figure 5–7. IOE Structure for Cyclone V Devices (1), (2)

From Core

DQS Logic Block

OE

2

OE Register

D5_OCT

Half Data

PRN

Dynamic OCT Control (2)

from

Core

Rate Block

D

Q

OE Register

PRN

D5 Delay

D

Q

VCCIO

								Programmable
								Pull-Up Resistor
Write			Output Register			Programmable		From OCT
							Current
Data	4	Half Data		PRN		Strength and		Calibration
from		Rate Block	D	Q		Slew Rate		Block
Core							Control
					D5 Delay		Output Buffer	On-Chip
								Termination
			Output Register
							Open Drain
				PRN
			D	Q			Input Buffer
				D3_0
clkout				Delay
To								Bus-Hold
Core				D1				Circuit
To			D3_1
				Delay
Core			Delay
				Input Register
					PRN
				D	Q
Read
Data	4		Read
to
			FIFO
Core
				Input Register		Input Register
					PRN		PRN
				D	Q	D	Q
DQS		D4 Delay
CQn
clkin

Notes to Figure 5–7:

(1)The D3_0 and D3_1 delays have the same available settings in the Quartus II software.

(2)One dynamic OCT control is available for each DQ/DQS group.

June 2012 Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

5–14	Chapter 5: I/O Features in Cyclone V Devices
	IOE Features

Current Strength

You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane.

The output buffer for each Cyclone V device I/O pin has a programmable current strength control for the following I/O standards.

Table 5–8 lists the programmable current strength settings for Cyclone V devices.

Table 5–8. Programmable Current Strength Settings —Preliminary

I/O Standard	I	/ I	OL	Current Strength Setting (mA) (1)
	OH
3.3-V LVTTL (2)				16 (3), 8, 4
3.3-V LVCMOS (2)				2
3.0-V LVTTL (2)				16, 12, 8, 4
3.0-V LVCMOS (2)				16, 12, 8, 4
2.5-V LVCMOS (2)				16, 12, 8, 4
1.8-V LVCMOS (2)				12, 10, 8, 6, 4, 2
1.5-V LVCMOS (2)				12, 10, 8, 6, 4, 2
1.2-V LVCMOS				8, 6, 4, 2
SSTL-2 Class I				12, 10, 8
SSTL-2 Class II				16
SSTL-18 Class I (2)				12, 10, 8, 6, 4
SSTL-18 Class II (2)				16
SSTL-15 Class I (2)				12, 10, 8, 6, 4
SSTL-15 Class II (2)				16
1.8-V HSTL Class I				12, 10, 8, 6, 4
1.8-V HSTL Class II				16
1.5-V HSTL Class I (2)				12, 10, 8, 6, 4
1.5-V HSTL Class II (2)				16
1.2-V HSTL Class I				12, 10, 8, 6, 4
1.2-V HSTL Class II				16

Notes to Table 5–8:

(1)The default current strength setting in the Quartus II software is the current strength shown in bold.

(2)Supported in HPS.

(3)Not Supported in HPS.

1Altera recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices

5–15

IOE Features

MultiVolt I/O Interface

The MultiVolt I/O interface feature that allows Cyclone V devices in all packages to interface with systems of different supply voltages.

Table 5–9 lists Cyclone V MultiVolt I/O support.

Table 5–9. MultiVolt I/O Support in Cyclone V Devices (1), (2)

VCCIO				Input Signal (V)							Output Signal (V)
(V)	1.2	1.25	1.35	1.5	1.8	2.5	3.0	3.3	1.2	1.25	1.35	1.5	1.8		2.5	3.0	3.3
1.2	Y	—	—	—	—	—	—	—	Y	—	—	—	—	—		—	—
1.25	—	Y	—	—	—	—	—	—	—	Y	—	—	—	—		—	—
1.35	—	—	Y	—	—	—	—	—	—	—	Y	—	—	—		—	—
1.5	—	—	—	Y	Y	—	—	—	—	—	—	Y	—	—		—	—
1.8	—	—	—	Y	Y	—	—	—	—	—	—	—	Y	—		—	—
2.5	—	—	—	—	—	Y	Y (3)	Y (3)	—	—	—	—	—	Y		—	—
3.0	—	—	—	—	—	Y	Y (3)	Y (3)	—	—	—	—	—	—		Y	—
3.3	—	—	—	—	—	Y	Y (3)	Y (3)	—	—	—	—	—		—	—	Y

Notes to Table 5–9:

(1)The pin current may be slightly higher than the default value. Verify that the VOL maximum and VOH minimum voltages of the driving device do not violate the applicable VIL maximum and VIH minimum voltage specifications of the Cyclone V device.

(2)For VCCIO = 1.2, 1.25, 1.35, 1.5, 1.8, and 2.5 V, VCCPD = 2.5 V. For VCCIO = 3.0 V, VCCPD = 3.0 V. For VCCIO = 3.3 V, VCCPD = 3.3 V.

(3)Altera recommends using the on-chip clamp diode on the I/O pins when the input signal is 3.0 V or 3.3 V.

June 2012 Altera Corporation	Cyclone V Device Handbook
	Volume 1: Device Interfaces and Integration

5–16	Chapter 5: I/O Features in Cyclone V Devices
	Programmable IOE Features

Programmable IOE Features

The Cyclone V I/O supports programmable features, as listed in Table 5–10.

Table 5–10. Supported I/O Features and Settings (1)

	Feature	Setting	Condition
	Slew Rate Control	0 = Slow, 1 = Fast (default)	Disabled when you use the RS OCT feature.
	I/O Delay	(1)	—
	Open-Drain Output	On, Off (default)	—
	Bus-Hold	On, Off (default)	Disabled when you use the weak pull-up resistor feature.
	Weak Pull-up Resistor	On, Off (default)	Disabled when you use the bus-hold feature.
	Pre-Emphasis	0 = Disabled, 1 = Enabled (default)	For LVDS I/O standard only. Not supported for
			differential HSTL and SSTL I/O standards.
	Differential Output Voltage	0 = low, 1 = medium (default),	—
		2 = high
	On-Chip Clamp Diode (2)	On, Off (default)	Recommended to turn on for 3.3-V I/O standards

Notes to Table 5–10:

(1)For information about the programmable IOE features, refer to the Cyclone V Device Datasheet.

(2)The PCI on-chip clamp diode is available on all general purpose I/O (GPIO) pins in all Cyclone V device variants.

Slew-Rate Control

The programmable output slew-rate control in the output buffer of each regularand dual-function I/O pin allows you to configure the following:

■Fast slew rate—provides high-speed transitions for high-performance systems.

■Slow slew rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

You can specify the slew rate on a pin-by-pin basis because each I/O pin contains a slew-rate control.

1Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application.

I/O Delay

The following sections describe the programmable IOE delay and the programmable output buffer delay.

Programmable IOE Delay

You can activate the programmable delays to ensure zero hold times, minimize setup times, or increase clock-to-output times.

This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.

Each pin can have a different input delay from pin-to-input register or a delay from output register-to-output pin values to ensure that the signals within a bus have the same delay going into or out of the device.

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration

Chapter 5: I/O Features in Cyclone V Devices

5–17

Programmable IOE Features

fFor more information about programmable IOE delay specifications, refer to the

Cyclone V Device Datasheet.

Programmable Output Buffer Delay

The device supports delay chains built inside the single-ended output buffer. There are four levels of output buffer delay settings. By default, there is no delay.

The following actions allow you to independently control the rising and falling edge delays of the output buffer:

■Adjust the output-buffer duty cycle

■Compensate channel-to-channel skew

■Reduce simultaneous switching output (SSO) noise by deliberately introducing channel-to-channel skew

■Improve high-speed memory-interface timing margins

fFor more information about programmable output buffer delay specifications, refer to the Cyclone V Device Datasheet.

Open-Drain Output

The optional open-drain output for each I/O pin is equivalent to an open collector output.

When configured as an open drain, the logic value of the output is either high-Z or logic low.

Use an external resistor to pull the signal to a logic high.

Bus-Hold

Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.

The bus-hold circuitry uses a resistor with a nominal resistance (RBH), approximately 7 kΩ, to weakly pull the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO level.

If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature.

June 2012 Altera Corporation	Cyclone V Device Handbook
	Volume 1: Device Interfaces and Integration

5–18	Chapter 5: I/O Features in Cyclone V Devices
	Programmable IOE Features

Pull-Up Resistor

The pull-up resistor weakly holds the I/O to the VCCIO level.

The Cyclone V device supports programmable weak pull-up resistors only on user I/O pins but not on dedicated configuration pins, JTAG pins, or dedicated clock pins.

Each I/O pin provides an optional programmable pull-up resistor during user mode.

If you enable this option, you cannot use the bus-hold feature.

Pre-Emphasis

Pre-emphasis boosts the output current momentarily.

The overshoot introduced by the extra current happens only during a change of state switching to increase the output slew rate and does not ring, unlike the overshoot caused by signal reflection.

The VOD setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level before the next edge, producing pattern-dependent jitter.

The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.

For more information, refer to “Programmable Pre-Emphasis” on page 5–48.

Differential Output Voltage

The Cyclone V LVDS transmitters support programmable VOD.

The programmable VOD settings allow you to adjust the output eye opening to optimize the trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller VOD swing reduces power consumption.

For more information, refer to “Programmable VOD” on page 5–47.

f For the weak pull-up resistor value, refer to the Cyclone V Device Datasheet.

Cyclone V Device Handbook	June 2012 Altera Corporation
Volume 1: Device Interfaces and Integration