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Cyclone V SoC Development Kit
User Guide
101 Innovation Drive San Jose, CA 95134 www.altera.com
UG-01135-1.1
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying |
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November 2013 Altera Corporation |
Cyclone V SoC Development Kit |
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User Guide |
Contents
Chapter 1. About This Kit
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Inspect the Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Software Installation
Installing the Quartus II Web Edition Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Installing the Altera SoC EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Installing the Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Installing the USB-Blaster II Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Chapter 3. Development Board Setup
Setting Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Factory Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Restoring the MAX V CPLD to the Factory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Restoring the CFI Flash Device to the Factory Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Chapter 4. Board Update Portal
Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4–1 |
Chapter 5. Board Test System
Preparing the Board for the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Running the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 The System Info Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 The I2C Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 Number of Addresses to Write and Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 The SDI Video Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11 The HSMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13 Start, Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
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Contents |
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XCVR, LVDS, CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14 The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 U34 and U26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 The Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 fXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 Target Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19 Before Configuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19 Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Appendix A. Programming Flash Memory
CFI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 Programming CFI Flash Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 Converting .sof Files to a .pof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 quad SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 Programming quad SPI Flash Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 SD Card Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4 Programming the SD Card Boot Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
Info–1 |
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
Info–1 |
Cyclone V SoC Development Kit |
November 2013 Altera Corporation |
User Guide |
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1. About This Kit
The Altera® Cyclone® V system on a chip (SoC) Development Kit is a complete design environment that includes both the hardware and software you need to develop Cyclone V SoC designs.
Kit Features
This section briefly describes the kit contents.
fFor a complete list of this kit’s contents and capabilities, refer to the Cyclone V SoC Development Kit page.
The Cyclone V SoC Development Kit includes the following hardware:
■Cyclone V development board—A development platform that allows you to develop and prototype hardware designs running on the Cyclone V SoC.
f For detailed information about the board components and interfaces, refer to the Cyclone V SoC Development Board Reference Manual.
■microSD flash memory card.
■Debug header breakout board high-speed mezzanine card (HSMC).
■Loopback daughtercard HSMC.
■Power supply and cables—The kit includes the following items:
■Power supply and AC adapters for North America/Japan, Europe, and the United Kingdom.
■USB cable.
■Ethernet cable.
■SMB cable.
Before You Begin
Before using the kit or installing the software, check the kit contents and inspect the boards to verify that you received all of the items listed in Quick Start Guide printout in the box. If any of the items are missing, contact Altera before you proceed.
Inspect the Boards
To inspect each board, perform these steps:
1.Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment.
c Without proper anti-static handling, you can damage the board.
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References |
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2. Verify that all components on the boards appear in place and intact.
1In typical applications with the Cyclone V development board, a heat sink is not necessary. However, under extreme conditions or for engineering sample silicon, the board might require additional cooling to stay within operating temperature guidelines. The board has two holes near the FPGA that accommodate many different heat sinks, including the Dynatron V31G. You can perform power consumption and thermal modeling to determine whether your application requires additional cooling. For information about measuring board and FPGA power in real time, refer to “The Power Monitor” on page 5–15.
fFor more information about power consumption and thermal modeling, refer to AN 358: Thermal Management for FPGAs.
References
Use the following links in Table 1–1 to check the Altera website for other related information:
Table 1–1. Related Links and Documents
Altera Website Link |
Information |
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Cyclone V SoC Development Kit page |
Latest board design files, reference designs, kit |
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installation for Windows and Linux. |
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Open-source community website supporting SoC |
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RocketBoards.org |
development including Altera and Partner SoC |
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development kit targets and related designs and |
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documentation. |
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ARM Cortex-A (SoC) |
On the dual-core ARM Cortex-A9 MPCore processor. |
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Getting Started for Software Developers |
Developing software for the Cyclone V SoC. |
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Cyclone V SoC Development Kit Hardware |
Developing SoC Hardware designs on the |
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Developer Resource Center |
development kit. |
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Altera SoC Embedded Design Suite User |
Installing the SoC EDS and ARM DS-5. Preloader |
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user guide. Hard Processor System (HPS) Flash |
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Guide |
programmer. Bare Metal and Linux Compiler. Yocto |
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plugin. Debugging. |
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The Golden System Reference Design (GSRD) |
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GSRD User Manual page |
demonstrates the HPS features and the ability to |
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communicate between HPS to the FPGA logic via the |
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AXI Bridge interfaces. |
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Cyclone V SoC Development Board |
Complete information about the development board. |
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Reference Manual |
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Development Board Daughtercards |
Additional daughter cards available for purchase. |
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Documentation: Cyclone V Devices |
Cyclone V device documentation. |
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Devices |
Purchase devices from the eStore. |
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Capture CIS Symbols |
Cyclone V OrCAD symbols. |
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Embedded Processing |
Nios II 32-bit embedded processor solutions. |
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Cyclone V SoC Development Kit |
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2. Software Installation
This chapter explains how to install the following software:
■Quartus II Web Edition Software (optional)
■Altera SoC Embedded Development Suite (EDS)
■Cyclone V SoC Development Kit software
■On-Board USB-Blaster™ II driver
1If you do not need to develop FPGA designs, you do not need to download the Quartus II software. For example, when you only want to write software for the SoC HPS. Installing the SoC EDS software, along with USB-II Blaster drivers, can provide your development kit JTAG programming environment.
Installing the Quartus II Web Edition Software
Perform these steps:
1.Download the Quartus II Web Edition Software from the Quartus II Subscription Edition Software page of the Altera website.
Alternatively, you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website.
2.Run the Quartus II Web Edition Software installer.
3.Follow the on-screen instructions to complete the installation process.
fFor a list of the Web Edition capabilities and features, refer to the Detailed Comparison sheet.
fIf you have difficulty installing the Quartus II software, refer to the Altera Software Installation and Licensing Manual.
Licensing Considerations
The Quartus II Web Edition Software is license-free and supports Cyclone V devices without any additional licensing requirement. This kit also works in conjunction with the Quartus II Subscription Edition Software, once you obtain the proper license file. To purchase a subscription, contact your Altera sales representative.
Installing the Altera SoC EDS
The Altera SoC EDS is a comprehensive tool suite for embedded software development on Altera SoC devices. The Altera SoC EDS contains the following:
■Development tools
■Utility programs
■Run-time software
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■ Application examples that enable firmware and application software development
The SoC EDS includes an exclusive offering of the ARM Development Studio™ 5 (DS-5™) Altera Edition Toolkit. The ARM DS-5 combines advanced multicore debugging capabilities with FPGA adaptivity. With Altera’s SignalTap™ II Logic Analyzer, embedded software developers have full-chip visibility and control.
fFor the steps to install the SoC EDS Design Suite, refer to the Altera SoC Embedded Design Suite User Guide.
Installing the Development Kit
Perform these steps:
1.Download the Cyclone V SoC Development Kit installer from the Cyclone V SoC Development Kit page of the Altera website. Alternatively, you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website.
2.Start the Cyclone V SoC Development Kit installer.
3.Choose an installation directory that is relative to the Quartus II software installation directory. Follow the on-screen instructions to complete the installation process.
4.For the latest issues and release notes, Altera recommends that you review the readme.txt located in the root directory of the kit installation.
The installation program creates the Cyclone V SoC Development Kit directory structure shown in Figure 2–1.
Figure 2–1. Cyclone V SoC Development Kit Installed Directory Structure (1)
<install dir>
The default Windows installation directory is C:\altera\<version>\.
kits
cycloneVSX_5csxfc6df31_soc
board_design_files
demos 
documents
examples
factory_recovery
Note to Figure 2–1:
(1) Early-release versions might have slightly different directory names.
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Installing the USB-Blaster II Driver
Table 2–1 lists the file directory names and a description of their contents.
Table 2–1. Installed Directory Contents
Directory Name |
Description of Contents |
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board_design_files |
Contains schematic, layout, assembly, and bill of material board design files. Use these files as a |
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starting point for a new prototype board design. |
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demos |
Contains demonstration applications, if available. |
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documents |
Contains the kit documentation. |
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examples |
Contains the sample design files for the Cyclone V SoC Development Kit. |
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factory_recovery |
Contains the original data programmed onto the board before shipment. Use this data to restore |
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the board with its original factory contents. |
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Installing the USB-Blaster II Driver
The Cyclone V development board includes integrated USB-Blaster circuitry for FPGA programming. However, for the host computer and board to communicate, you must install the On-Board USB-Blaster II driver on the host computer.
fInstallation instructions for the On-Board USB-Blaster II driver for your operating system are available on the Altera website. On the Altera Programming Cable Driver Information page of the Altera website, locate the table entry for your configuration and click the link to access the instructions.
f For USB-Blaster II configuration details, refer to the On-Board USB-Blaster II page.
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Installing the USB-Blaster II Driver |
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Cyclone V SoC Development Kit |
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3. Development Board Setup
This chapter explains how to set up the Cyclone V SoC development board and restore default settings.
Setting Up the Board
To prepare the board, perform these steps:
1.The development board ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be currently configured with the default settings, follow the instructions in “Factory Default Switch and Jumper Settings” on page 3–1 to return the board to its factory settings before proceeding.
The development board ships with the Golden System Reference Design binaries stored in the microSD card.
The microSD card also includes the following:
■Hardware reference design FPGA image, Raw Binary File (.rbf) file
■HPS image preloader U-Boot and Linux images
■File system and software examples
2.Power up the development board by using the included laptop power supply plugged into J22 on the board.
c Use only the supplied power supply. Power regulation circuitry on the board can be damaged by power supplies with greater voltage, and a lower-rated power supply may not be able to provide enough power for the board.
Alternatively, you can use the an ATX power from a PC by plugging a 4-pin output from that supply to J20 on the development board.
c Make sure that the ATX supply is off when connecting to the board. Hotswap is not supported and may damage the board's power supplies and other downstream devices.
When configuration is complete, the Config Done LED (D38) illuminates, signaling that the Cyclone V device configured successfully.
Factory Default Switch and Jumper Settings
This section shows the factory settings (Figure 3–1) for the Cyclone V SoC development board. These settings ensure that the Board Update Portal and Golden System Reference design function properly.
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User Guide |
3–2 |
Chapter 3: Development Board Setup |
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Factory Default Switch and Jumper Settings |
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1The SD card, Max V system controller, and common flash interface (CFI) flash are already programmed with the factory default files. For more information, refer to Appendix A, Programming Flash Memory.
Figure 3–1. Switch Locations and Default Settings
SW2
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2 |
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ON |
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SECURITY FACT LOAD Si570 CLK125A
0 1 2 3 4 |
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SW1 |
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3 2 1 0 |
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ON |
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8 |
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34 |
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SW3 |
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1 |
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ON |
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MSEL |
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FPGA |
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HPS |
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ENABLE |
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SW4 |
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ON |
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9V |
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1 |
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JTAG |
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HPS |
FPGA HSMC |
MAX |
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J5 |
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JTAG |
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J6 |
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HPS SEL |
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J7 |
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JTAG |
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SEL |
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OSC1_CLK_SEL
J13
JTAG_MIC_SEL
J16
J26 |
J27 |
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J28 |
J29 |
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J30 |
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CLKSEL0 |
CLKSEL1 |
BOOTSEL0 |
BOOTSEL1 |
BOOTSEL2 |
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SPI |
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I2C |
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J31 |
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To restore the switches to their factory default settings, perform these steps:
1.Set the DIP switch bank (SW2) to match Table 3–1 and Figure 3–1.
In the following table, ON indicates the switch is to the left according to the board orientation as shown in Figure 3–1.
Table 3–1. SW2 DIP Switch Settings (Part 1 of 2)
Switch |
Board |
Function |
Default |
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Label |
Position |
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Switch 1 has the following options: |
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1 |
CLK125A |
■ ON (0) = On-board oscillator is disabled. |
OFF |
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■ OFF (1) = On-board oscillator is enabled. |
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Switch 2 has the following options: |
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■ ON (0) = On-board programmable oscillator is |
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2 |
Si570 |
enabled. |
ON |
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■ OFF (1) = On-board programmable oscillator is |
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disabled. |
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Cyclone V SoC Development Kit |
November 2013 Altera Corporation |
User Guide |
|
Chapter 3: Development Board Setup |
3–3 |
Factory Default Switch and Jumper Settings |
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Table 3–1. SW2 DIP Switch Settings (Part 2 of 2)
Switch |
Board |
Function |
Default |
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Label |
Position |
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Switch 3 has the following options: |
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3 |
FACT LOAD |
■ ON (0) = Load the factory design starting at |
OFF |
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0x20000 at power up. |
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■ OFF (1) = Parallel flash loader (PFL) disabled. |
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Switch 4 has the following options: |
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4 |
Security |
■ ON (0) = On-Board USB Blaster II sends |
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FACTORY command at power up |
OFF |
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■ OFF (1) = On-Board USB Blaster II does not |
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send FACTORY command at power up |
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2.Set the DIP switch bank (SW3) to match Table 3–2 and Figure 3–1.
In the following table, up and down indicates the position of the switch with the board orientation as shown in Figure 3–1.
Important: The default MSEL pin settings are set to all zeroes (ON) to select the fast passive parallel x16 mode. For power-up configuration from MAX V and CFI flash, ensure that the MAX V design uses this same mode as does in the design in the <install dir>\kits\cycloneVSX_5csxfc6df31_soc\examples\max5 directory.
Table 3–2. SW3 DIP Switch Settings
Switch |
Board |
Function |
Default |
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Label |
Position |
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Switch 1 has the following options: |
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1 |
MSEL0 |
■ ON (up) = MSEL0 is 0. |
ON |
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■ OFF (down) = MSEL0 is 1. |
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Switch 2 has the following options: |
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2 |
MSEL1 |
■ ON (up) = MSEL1 is 0. |
ON |
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■ OFF (down) = MSEL1 is 1. |
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Switch 3 has the following options: |
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3 |
MSEL2 |
■ ON (up) = MSEL2 is 0. |
ON |
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■ OFF (down) = MSEL2 is 1. |
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Switch 4 has the following options: |
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4 |
MSEL3 |
■ ON (up) = MSEL3 is 0. |
ON |
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■ OFF (down) = MSEL3 is 1. |
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Switch 5 has the following options: |
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5 |
MSEL4 |
■ ON (up) = MSEL4 is 0. |
ON |
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■ OFF (down) = MSEL4 is 1. |
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November 2013 Altera Corporation |
Cyclone V SoC Development Kit |
|
User Guide |
3–4 |
Chapter 3: Development Board Setup |
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Factory Default Switch and Jumper Settings |
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3.Set the DIP switch bank (SW4) to match Table 3–3 and Figure 3–1.
In the following table, up and down indicates the position of the switch with the board orientation as shown in Figure 3–1.
Table 3–3. SW4 JTAG DIP Switch Settings
Switch |
Board |
Function |
Default |
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Label |
Position |
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1 |
HPS |
■ ON (up) = Do not Include HPS in the JTAG chain. |
OFF |
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■ OFF (down) = Include HPS in the JTAG chain |
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■ ON (up) = Do not Include the FPGA in the JTAG |
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2 |
FPGA |
chain. |
OFF |
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■ OFF (down) = Include the FPGA in the JTAG chain. |
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■ ON (up) = Do not include the HSMC connector in the |
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3 |
HSMC |
JTAG chain. |
ON |
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■ OFF (down) = Include the HSMC connector in the |
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JTAG chain. |
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■ ON (up) = Do not include the MAX V system |
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4 |
MAX |
controller in the JTAG chain. |
OFF |
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■ OFF (down) = Include the MAX V system controller in |
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the JTAG chain. |
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4. Set the following jumper blocks to match Table 3–4 and Figure 3–1.
Table 3–4. Default Jumper Settings
Board |
Board Label |
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Description |
Default |
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Reference |
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Position |
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■ SHORT: Powers the CFI flash memory device |
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using a 9 V supply for fast write in |
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J5 |
9V |
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manufacturing. |
OPEN |
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■ OPEN: Powers CFI flash memory from the |
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default 3 V supply. |
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■ SHORT: Controls the HPS from On-Board USB |
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Blaster II JTAG master. |
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J6 |
JTAG HPS SEL |
■ OPEN: Controls the HPS from MICTOR-based |
SHORT |
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JTAG master, such as DSTREAM or Lauterbach |
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programming cables. Also, set SW4.1 to ON to |
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remove the On-Board USB Blaster II from |
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driving the HPS JTAG input port in this mode. |
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■ SHORT: The USB Blaster II is the source of the |
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J7 |
JTAG SEL |
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JTAG chain. |
SHORT |
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■ OPEN: The Mictor is the source of the JTAG |
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chain. |
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J13 |
OSC1_CLK_SEL |
■ SHORT: Selects the on board 25MHz clock. |
SHORT |
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OPEN: Selects SMA. |
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■ |
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Cyclone V SoC Development Kit |
November 2013 Altera Corporation |
User Guide |
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