Agilent Technologies FS2331 User Manual

FuturePlus

®

Systems Corporation

DDR SDRAM Analysis Probe

For use with Agilent Technologies Logic Analyzers

Copyright 2003 FuturePlus Systems Corporation

FS2331

Users Manual

Revision 1.4

orporation

2

How to reach us.......................................................................................................................4

Product Warranty....................................................................................................................5

Limitation of warranty ...................................................................................................................5

Exclusive Remedies .........................................................................................................................5

Assistance.........................................................................................................................................5

Introduction.............................................................................................................................6

Definitions........................................................................................................................................6

DDR Bus Speed...........................................................................................................................................6

Probe Cable, Connector Numbering.........................................................................................................6

Logic Analyzer Modules.............................................................................................................................6

Logic Analyzer Machines...........................................................................................................................6

FS2331 Probe Description......................................................................................................8

Probe Feature Summary.................................................................................................................8

Probe Components..........................................................................................................................8

Probe Design....................................................................................................................................9

State Clock Generation...................................................................................................................9

DDR Commands.........................................................................................................................................9

DDR Data....................................................................................................................................................9

Probe Pod Assignment..................................................................................................................11

Probe Switch Settings....................................................................................................................12

Logic Analyzer Signal Threshold Voltage Settings....................................................................13

Connecting the Probe to the Logic Analyzer..............................................................................13

Connecting Power to the FS2331 Probe......................................................................................13

Card Requirements for PC2700 Systems....................................................................................14

Logic Analyzer Card Requirements............................................................................................15

Software Requirements.................................................................................................................16

System Software........................................................................................................................................16

Setting up the 167xx Analyzer.................................................................................................................16

Setting up the 169xx Analyzer.................................................................................................................16

169xx Licensing.........................................................................................................................................16

Loading 169xx configuration files and define probes feature...............................................................16

Configuration Files........................................................................................................................17

Timing Analysis (All DDR speeds and supported analyzer cards).......................................................17

3 card Configurations for State Analysis................................................................................................18

Probing multiple DDR busses – Interleaved memory................................................................19

Connecting to your Target System – Chip Select.......................................................................20

Chip Select Jumpers.................................................................................................................................20

1) Wiring Chip Select from a DIMM module to the FS2331.....................................................................20

2) Dedicating a DIMM slot to the FS2331 .................................................................................................21

3) FS1024 or FS1025 Interposer.................................................................................................................23

3

Unused Pods...................................................................................................................................23

Offline Analysis .............................................................................................................................24

Filtering..........................................................................................................................................25

Timing Analysis Operation...................................................................................................26

Loading the Inverse Assembler and Decoding DDR Commands .............................................26

Taking a Trace, Triggering, and Seeing Measurement Results................................................26

State Analysis Operation.......................................................................................................26

Minimizing intermodule skew......................................................................................................26

The Inverse Assembler and Decoding DDR Commands...........................................................27

Taking a Trace, Triggering, and Seeing Measurement Results................................................27

Tracing the Serial Presence Detect Signals.........................................................................28

Using Eye Finder with the FS2331 DDR Probe..................................................................29

Using EyeScan with the FS2331 Probe ...............................................................................30

Using the FS2331 DDR Probe with an Interposer (FS1024/25) ................................................31

DIMM Signal Loading Option.....................................................................................................31

FS2331 Calibration .......................................................................................................................32

Step 1 – Set Command sample position..................................................................................................34

Step 2 – Write Burst Data Valid Position...............................................................................................37

Step 3 – Read Burst Data Valid Position................................................................................................41

Step 4 – Adjust the delay line value to maximize R/W overlap ............................................................45

Step 5 – Set the final analyzer sample position ......................................................................................45

General Information.............................................................................................................47

Probe Interface design capability............................................................................................................47

Standards supported ................................................................................................................................47

Power requirements..................................................................................................................................47

Logic Analyzer Requirements .................................................................................................................47

Minimum Clock Period............................................................................................................................47

Signal Loading ..........................................................................................................................................47

Environmental Operating Limits............................................................................................................47

Servicing....................................................................................................................................................47

Signal Connections...............................................................................................................48

4

How to reach us

For Technical Support:

FuturePlus Systems Corporation
15 Constitution Drive
Bedford, NH 03110
TEL:[phone]
FAX:[phone]
On the Web: www.futureplus.com

For Sales and Marketing Support:
TEL:[phone]
FAX:[phone]
On the Web: www.futureplus.com

FuturePlus Systems is represented in Japan by:
ANDOR Systems Support Co., LTD.
15-8, Minami-Shinagawa, 2-chome,
Shinagawa-ku
Tokyo 140
TEL:[phone]
FAX:[phone]
Contact : Mr. Takashi Ugajin

Outside of Japan, FuturePlus Systems is represented world wide
by Agilent Technologies. Please contact your nearest Agilent
Sales office.

5

Product Warranty

Due to the complex nature of the FS2331 and the wide variety of possible
customer target implementations, the FS2331 has a 30 day acceptance period by
the customer from the date of receipt. If the customer does not contact
FuturePlus Systems within 30 days of the receipt of the product it will be said that
the customer has accepted the product. If the customer is not satisfied with the
FS2331 they may return the FS2331 within 30 days for a refund.

This FuturePlus Systems product has a warranty against defects in material and
workmanship for a period of 1 year from the date of shipment. During the warranty
period, FuturePlus Systems will, at its option, either replace or repair products proven to
be defective. For warranty service or repair, this product must be returned to the factory.

For products returned to FuturePlus Systems for warranty service, the Buyer shall
prepay shipping charges to FuturePlus Systems and FuturePlus Systems shall pay
shipping charges to return the product to the Buyer. However, the Buyer shall pay all
shipping charges, duties, and taxes for products returned to FuturePlus Systems from
another country.

FuturePlus Systems warrants that its software and hardware designated by FuturePlus
Systems for use with an instrument will execute its programming instructions when
properly installed on that instrument. FuturePlus Systems does not warrant that the
operation of the hardware or software will be uninterrupted or error-free.

Limitation of warranty

The foregoing warranty shall not apply to defects resulting from improper or inadequate
maintenance by the Buyer, Buyer-supplied software or interfacing, unauthorized
modification or misuse, operation outside of the environmental specifications for the
product, or improper site preparation or maintenance. NO OTHER WARRANTY IS
EXPRESSED OR IMPLIED. FUTUREPLUS SYSTEMS SPECIFICALLY DISCLAIMS
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.

Exclusive Remedies

THE REMEDIES PROVIDED HEREIN ARE BUYER’S SOLE AND EXCLUSIVE
REMEDIES. FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT,
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER
BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL THEORY.

Product maintenance agreements and other customer assistance agreements are
available for FuturePlus Systems products. For assistance, contact the factory.

6

Introduction

Definitions

Thank you for purchasing the FuturePlus Systems FS2331 DDR SDRAM Logic Analyzer
Probe. We believe you will find the FS2331, along with your Agilent Technologies Logic
Analyzer, a valuable tool for helping to characterize and debug your DDR-based
systems. This User Manual will provide the information you need to install, configure,
and use the FS2331 Probe. If you have any questions about this User Manual or use of
the FS2331 Probe, please contact FuturePlus Systems Corporation.

DDR Bus Speed

This document will use the following definitions when describing DDR memory speeds:

PC1600 or 200Mhz describes DDR DIMMs running at a clock rate on the memory

•

bus differential clock of 100Mhz, which results in a data transfer rate of 200Mhz (or

1.6 GBytes/sec throughput). DDR commands are issued at a 100Mhz rate.
PC2100 or 266Mhz describes DDR DIMMs running at a clock rate on the memory

•

bus differential clock of 133Mhz, which results in a data transfer rate of 266Mhz (or

2.1 GBytes/sec throughput). DDR commands are issued at a 133Mhz rate.
PC2700 or 333Mhz describes DDR DIMMs running at a clock rate on the memory

•

bus differential clock of 167Mhz, which results in a data transfer rate of 333Mhz (or

2.7 GBytes/sec throughput). DDR commands are issued at a 167Mhz rate.

Probe Cable, Connector Numbering

The FS2331 has 4 connectors that connect to the logic analyzer through 4 logic
analyzer adapter cables. These connectors are described as "J1" through "J4". When
"Pod <n>" is referenced in this manual it is the logic analyzer cable end that is plugged
into "J <n>" of the FS2331 per figure on page 7.

Logic Analyzer Modules

"Module" - A set of logic analyzer cards that have been configured (via internal cables
connecting the cards) to operate as a single logic analyzer whose total available
channels is the sum of the channels on each card. A trigger within a module can be
specified using all of the channels of that module. Each module may be further broken
up into "Machines”. A single module may not extend beyond a single 5 card frame.

Logic Analyzer Machines

"Machine" - A set of logic analyzer pods from a logic analyzer module grouped together
to operate as a single state or timing analyzer. Each logic analyzer module may be
partitioned into up to two independent "Machines" (either two state machines, or a state
and a timing machine), and the pods of a module may be assigned freely to either
machine. Each state analyzer machine has its own state clock. Turbo mode (333Mhz
for 1671x, 400Mhz for 16750/1/2, 600Mhz for 16753/4/5 cards) operation restricts a
module to having only one machine. Cross triggering between modules or machines is
done via the Intermodule Bus or via the Flag bits, which will communicate across a
16700 frame and its expander, or across multiple frames if the Multiframe product is
used.

7

POD 2

POD 3 (odd)

POD 4

POD 5 (odd)

POD 6

POD 7 (odd)

POD 8

Four 100 pin SAMTEC

connectors on the FS2331

FS2331 100 pin Connector to Pod Diagram

Four - E5385A or E5378A adapter cables

connecting to the logic analyzer

J1

J2

J3

J4

POD 1 (odd)

E5385A adapter cables (FS1015) are used to

connect to the following logic analyzer
cards:

1671X, 16750/1/2/3

E5378A adapter cables (FS1014) are used to

connect to the following logic analyzer
cards:

1676X, 16754/5/6

8

FS2331 Probe Description

The FS2331 DDR DIMM Probe allows you to perform state and timing analysis
measurements on Double Data Rate DRAM DIMM busses using an Agilent logic
analyzer.

Probe Feature Summary

Quick and easy connection between the DDR 184 pin DIMM connector and Agilent

•

Logic Analyzers.
Complete and accurate state analysis up to 333Mhz (PC2700).

•

Complete and accurate 4 GHz timing analysis.

•

Compatible with all 184-pin, 2.5V DDR SDRAM DIMM's up to 333 MHz.

•

Built-in support for probing Chip Select lines of other DIMM slots.

•

Data groups and their strobes matched to better than 50ps, address and commands

•

matched to better than 180ps.
All signals are provided to the logic analyzer unbuffered.

•

Registered and non-registered DIMMS are supported.

•

User configurable capacitor pads allow modeling of 1, 2, and 4 rank (stacked)

•

DIMMS for signal integrity validation with EyeScan.
DDR Commands are always visible. Switches select state analysis acquisition of

•

data writes only, reads only, or both writes and reads.
Uses Agilent "Eye Finder" technology to locate tight DDR data valid windows for

•

optimal state data capture and to help identify bus signals with marginal timing
needing closer examination.
Probe can be used with Agilent EyeScan technology to provide eye diagram of DDR

•

and address/command signals.
Both x4 and x8 SDRAMS are supported.

•

Read and write burst type is tracked in real time and each cycle of a burst (in both

•

state and timing mode) is sent to the analyzer.

Probe Components

The following components have been shipped with your FS2331 DDR Probe:

FS2331 DDR DIMM Probe with 3 extra jumpers and 1700 ps delay line.

•

Dedicated power supply for the FS2331 probe.

•

Floppy disk(s) with inverse assembler and configuration files for 167xx.

•

CD with inverse assembler and configuration files for 169xx

•

This User Manual on CD.

•

Quick Start Sheet.

•

Software Entitlement Certificate. This is for 169xx or Off-Line Analysis only.

•

9

Probe Design

This probe uses discrete ECL logic in order to operate at the speed necessary to
provide DDR333 signal decode. Because ECL logic operates in linear mode it dissipates
more heat than other logic designs.

BE ADVISED – THE PROBE IS HOT TO THE TOUCH. . If the user believes that the

FS2331’s temperature is above 80°C, then a fan should be used to provide
additional cooling.

In order to support source synchronous data capture the FS2331 DDR probe monitors
the clock (CK0/CK0n) and control (DQS0, CAS, RAS, WE, S0:3) signals on the DIMM
connector where the probe is inserted. In some cases the probe may also need access
to the chip select signals for other DIMM slots to enable source synchronous data
capture. There may be situations where these signals are not provided by the target
system. For instance, some systems may turn off CK0 to slots where no DIMM module
is detected. In other systems, the unique Chip Select signals for each DIMM may need
to be connected to the probe.

If there is any reason to suspect that these conditions are present on your target,
contact FuturePlus Technical Support.

State Clock Generation

The FS2331 DDR probe uses one logic analyzer machine to capture DDR commands
(using the common clock CK0) and another machine to capture DDR burst data (using
the source synchronous strobe DQS0). The logic analyzer automatically combines the
trace data from both machines into a single time correlated trace of DDR bus activity.
The circuitry on the probe is used to generate the proper state analysis clocks for the
command and data analysis machines.

DDR Commands

Since the DDR bus global clock is differential it is converted to a single ended clock for
the analyzer using a differential line receiver. DDR Commands are sampled on the
rising edge of this clock.

DDR Data

The FS2331 supports state analysis of DDR busses by combining a specially processed
version of the DQS0 strobe with Agilent's Eye Finder technology. This allows the
analyzer/probe combination to accurately locate (much as a DDR controller chipset
does) the read and write data valid windows for each data bus signal and sample the
data at the proper time for reliable state analysis.

Each DDR bus implementation will have different timing due to trace length variation on
the motherboard, variations in bus loading for each DIMM configuration, and sensitivity
to dynamic factors such as crosstalk or simultaneous switching noise. Therefore, the
precise position of the DDR data eye will vary from system to system and even within a
system as DIMM configurations or data access patterns change. To achieve the most
reliable data capture the location of the data eye must be determined on a given system
using worst case data access patterns. The logic analyzers Eye Finder feature is used
to measure the location of the eye for each data signal over millions of burst cycles and
so achieve the most reliable state capture. By using the proper stimulus when running
Eye Finder the worst-case data valid window boundaries are found and the analyzer is
set to sample data at the center of the actual data valid window of each signal for each
specific DDR implementation and DIMM configuration.

10

Because strobe edges are centered on the data valid window for writes, and straddle it
for reads, the analyzer cannot simply use the raw DQS0 to sample data. If it did, then
even in the ideal case, only half of the data valid window would be usable. In practice, it
would almost completely disappear. To deal with this, the DDR Probe adjusts the timing
of DQS0 before sending it to the analyzer state clock input by delaying it a fixed amount
for reads. This is done using a socketed delay line, which is set at the factory and
should be sufficient. If EyeFinder results show good eyes when the probe is set to pass
Reads only and Writes only (SW #6 off), but the eyes are significantly reduced when the
probe passes BOTH Reads and Writes (SW #6 on), then the delay value on the probe
may need adjustment. The calibration procedure documented in this User Manual
describes how to set the probe delay line and analyzer sample position for reliable state
analysis operation.

Because the strobes are tristated between bursts their logic value is undefined. Some
systems will terminate the DDR bus to a voltage close to the Vref voltage, causing the
strobes to sit right at the switching threshold. During read bursts, because read data
(and strobes) are actually not valid until the reflected wave reaches the probe, DQS0
may also spend a significant amount of time at Voh/2 (close to Vref) between arrival of
the incident wave and the reflected wave. Therefore, simply comparing the DQS0 signal
to Vref will result in spurious analysis clocks being generated between bursts and during
read bursts. The DDR probe deals with these factors by recognizing valid DQS0 edges
only when they are closer to Vih than Vref as well as by inhibiting the state clock
between bursts. In actual operation enough noise immunity is added by the special
DQS0 receiver circuit to eliminate almost all spurious data strobes without inhibiting the
clock.

All of these factors combine to add jitter to the read and write strobes sensed by the
DDR probe. This jitter reduces the data valid window available to the logic analyzer. In
some systems and DIMM configurations that have tight bus timing this may make it
difficult to find an appropriate point to sample state data. This is especially true for read
bursts that usually have more complex strobe and data waveforms. Eye Finder will
measure the data valid window available to the analyzer for each signal and clearly
indicate which ones may have difficulty reliably sampling state data given actual DDR
bus timing.

11

Probe Pod Assignment

The FS2331 DDR Probe uses 8 pods. Two are used to capture traffic on the DDR
Command bus, and 6 are used for the Data bus, strobes, check bits, masks, and Serial
Presence Detect signals. The signals are mapped to pods as follows:

Pod Clock Domain

SIGNAL GROUP

(Clock Rate)

1 Odd

2 Even

3 Odd

Data (2x) State Analysis Clock (on JCLK), DQ0-3, DQ8-11,

DQ16-19, DQS0-2, SA0

Data (2x) Read/Write status (on KCLK), DQ4-7, DQ12-15,

DQ20-23, DQS9-11, SA1

Data (2x) Burst Valid status (on JCLK), CB0-5, DQ24-31,

DQS3, DQS12

4 Even Command (1x) CK0 (on KCLK), A0-15

Command (1x) Buffered Command Clock (on JCLK), BA0-2, S0-

5 Odd

3, CKE0-1, WE, RAS, CAS, Reset, FETEN.
Spare

6 Even

7 Odd

8 Even

Data (2x) Buffered Command Clock (on KCLK), CB6-7,

SA2, WP, DQS4, 8, 13, 17. DQ32-39.

Data (2x) (Spare – J10on JCLK), SDA, DQS5-7, DQ40-43,

DQ48-51, DQ56-59

Data (2x) (Spare – J11on JCLK), SCL, DQS14-16, DQ44-

47, DQ52-55, DQ60-63.

The overlap in the bit ranges for signals between pods occurs because the bits are
assigned to pods in the order that they appear physically on the DIMM connector, which
is not strictly in logical bit order. This allows the probe layout to better match stub
lengths among all DQxx signals.

See the Appendix for a detailed list of how Logic Analyzer Channels are mapped to
signals and DIMM pins.

12

1 2 3 4 5 6

Probe Switch Settings

A switch bank of 6 independent SPST switches is provided on the FS2331 for user
selection of a number of probe features. These are detailed below.

Switch # Default (factory

position)

1 Open Not available
2 Open Not available
3 Open Not available

4

CS_Gate_CK0

5. Write or
Read Only

6 R/W Filter Closed

Open

Open

Function

When SW4 is closed the Buffered

Command Clock signal to the logic

analyzer is passed only when there is a

valid (low) S0:3 signal to the probe. This

is useful for EyeScan of Command

signals.

SW5 is dependent on SW6. When SW6

is open, SW5 open will pass a state

clock signal only during a Read

command. SW5 closed will pass only

on a Write.

When SW6 is closed, the probe

provides a state clock during both

Reads and Writes. When SW6 is open

it engages SW5.

13

Logic Analyzer Signal Threshold Voltage Settings

Threshold voltage settings are set at SSTL-2 levels (1.25 V) for all pods in the format
specification of the analyzer. The user may have to adjust this setting for optimal
performance for their specific target. Eye Finder and/or EyeScan may have to be run to
find out if adjusting the threshold levels will optimize the data valid windows.

Connecting the Probe to the Logic Analyzer

The FS2331 requires two or three logic analyzer cards depending on the DIMM bus
speed, whether state or timing measurements are being used, and the type of logic
analyzer card being used. For timing measurements only two cards (configured as a
single logic analysis module using one analyzer “machine”) are necessary.

Whether using a 2 card or a 3 card configuration, the cards must all be the same model.
Because the DDR bus clocks commands on one clock and strobes data on a separate

set of strobes, state analysis requires that two separate analyzer “machines” be used,
one for Commands and one for Data. For 200Mhz operation 16750/1/2 (200/400Mhz)
cards provide sufficient speed in their normal mode to capture Data and Commands, so
a two card module configured into one machine for Commands and one for Data is
sufficient. When running at higher speeds, the analyzer capturing Data bursts may need
to be configured to run in its high speed (Turbo) mode, which requires it to be in a
module of its own. A third card configured as a separate module is then needed to
capture and trigger on DDR Commands. Six pods of the data module are used for data
capture (two are reserved for time tags). However, only two pods in the module used to
capture DDR Commands are used for Command capture. The other two may be used
for any other purpose (such as to probe chip select signals of a separate DDR memory
bank). If 16760 cards are being used for both Command and Data analyzers, then 5
cards are required. One card for commands, 4 cards for data. The reason 4 cards are
required for data, is because the cards must be run in 400 Mb/s mode with time tags
turned on for time correlation with the Command machine; with time tags turned on 1
pod per machine cannot be used. With 4 cards connected together as one machine
with time tags on at 400 Mb/s or greater there are 7 pods out of 8 available to use.
Without the 4th card only 5 pods would be available, when 6 are needed. A summary of
this information appears on the following table.

Triggering on a combination of commands and data is accomplished by using the
Intermodule Bus, which sends an "Arm" signal between all analyzer modules. You can
also use the "Flag" bits to communicate between the DDR Command and DDR Data
triggering systems.

Connecting Power to the FS2331 Probe

After connecting the probe to the logic analyzer cables, insert it into the target system.
After the probe is in the target system and connected to the logic analyzer, connect the

external power supply provided with the FS2331 to the probe. Do this step last and only
use the power supply provided with the FS2331.

14

Card Requirements for PC2700 Systems

In order to insure that the FS2331 and the logic analyzer work properly with PC2700
systems it is recommended that the 16753/4/5/6 cards be used when probing at DDR
rates of 333Mhz or greater. This recommendation is based on several factors.

First, the setup and hold requirement for PC2700 is specified as a minimum of 900 ps.
Some combination of target systems and DIMMs may operate with a setup and hold
time greater than this, but to insure accurate data capture the higher performance of the
16753/4/5/6 cards is needed.

Second, the loading on the target system presented by the 16753/4/5/6 combined with
the E5378A adapter cables is significantly lower than the loading of the 1671x or
16750/1/2 and the E5385A cables. This may affect target system performance or
measurements.

15

Logic Analyzer Card Requirements

DDR Bus

Speed

16700 Analyzer

Type

Timing Analysis State Analysis

200MHz
(PC1600)

266MHz
(PC2100)

16717/8/9 2 cards configured

as one module with
one timing machine

1675X 2 cards configured

as one module with
one timing machine

16717/8/9 2 cards configured

as one module, one
machine

1675X 2 cards configured

as one module, one
machine

3 cards:

1 card module with one

•

167Mhz state machine for
Commands
2 card module with one

•

333Mhz state machine for

Data
2 cards configured into one
module having two 200Mhz
machines, one with 2 pods for
commands, one with 6 pods for
Data.

3 cards:

1 card module with one

•

167Mhz state machine for

Commands

2 card module with one

•

333Mhz state machine for

Data
3 cards:

1 card module with one

•

200Mhz state machine for

Commands

2 card module with one

•

400Mhz state machine for
Data

16760 4 cards configured

as one module, one
machine

333MHz
(PC2700)

16753/4/5/6
recommended

2 cards configured
as one module, one
machine

5 cards:

§ 1 card module at 200 Mb/s
for commands.

4 card module at 400 Mb/s

•

for Data.

3 cards:

1 card module with one

•

200Mhz state machine for
Commands

2 card module with one

•

400Mhz state machine for
Data

16

Software Requirements

System Software

The FS2331 Probe requires version A.02.70.00 (or later) of the 16700 System Operating
Software. You can check to see if you already have the correct version by opening the
“System Administration” dialog and selecting the “Show Version” button. If you do not
have the correct version then you must update your system software. Please consult
16700 system documentation for the SW update procedure.

Setting up the 167xx Analyzer

The floppy disk(s) supplied with the FS2331 DDR Probe contains the software required
to operate the FS2331. Install the Inverse Assembler and Configuration files from the
floppy using the 16700 software installation procedure. This will install an inverse
assembler called “IFS2331E” in the standard location for inverse assemblers, and will
install several configuration files in the /logic/configs/FuturePlus/FS2331 directory that
allow you to easily configure the analyzer for timing or state operation with the FS2331.
See the sections below for information on which configuration file to use for your
application.

Setting up the 169xx Analyzer

A CD containing the 16900 software is included in the FS2331 package. The CD
contains a setup file that will automatically install the configuration files and protocol
decoder onto a PC containing the 16900 operating system or onto a 16900 analyzer
itself.

To install the software simply double click the .exe file on the CD containing the 16900
software. After accepting the license agreement the software should install within a
couple of minutes.

169xx Licensing

Once the software has been successfully installed you must license the software.
Please refer to the entitlement certificate for instructions on licensing the software. The
software can only be installed on one machine. If you need to install the software on
more than one machine you must contact the FuturePlus sales department to purchase
additional licenses.

Loading 169xx configuration files and define probes feature

When the software has been licensed you should be ready to load a configuration file.
You can access the configuration files by clicking on the folder that was placed on the
desktop. When you click on the folder it should open up to display all the configuration
files to choose from. If you put your mouse cursor on the name of the file a description
will appear telling you what the setup consists of, once you choose the configuration file
that is appropriate for your configuration the 169xx operating system should execute.
The protocol decoder automatically loads when the configuration file is loaded. If the
decoder does not load, you may load it by selecting tools from the menu bar at the top of
the screen and select the decoder from the list.

After loading the configuration file of choice, go into the format specification of the
configuration by choosing Setup from the menu bar and then selecting Bus/Signal in the
drop down menu. When the format specification appears press Define Probes at the
bottom of the screen. The Define Probes feature will describe how to hook the analyzer
cards to the connections on the target. The following figure shows what the Define
Probes screen looks like. The figure below may differ from your display; this is an
example of how the display looks in general.

17

Note: In the above picture under Logic analyzer pods, the first pod goes to the Odd pod
and the second goes to the Even pod of the termination adapter (e.g. Pod B1 goes to
odd termination adapter pod and B2 goes to the even termination adapter pod).

Configuration Files

167xx Analyzer 169xx Analyzer State/Timing Comment

16717/8/9, 1675x 1675x, 1695x, 1691x DR231_1 2 card timing
16717/8/9, 1675x 1675x, 1695x, 1691x DR231_2 3 card state analysis

16717/8/9, 1675x

1675x, 1695x, 1691x

DR231_3

Two Interleaved DDR Banks, 5 cards

required

Timing Analysis (All DDR speeds and supported analyzer cards)

For timing analysis operation you need only two cards (except for the 16760, which
requires four) regardless of supported card type or bus speed. These must be
configured via the cables supplied with the cards as a single logic analyzer module.
Refer to the appropriate Agilent Technologies manual for information on how to connect