eMachines G520
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Size Document Number Rev
Date: Sheet
of
Block Diagram
1A
140Thursday, August 28, 2008
Size Document Number Rev
Date: Sheet
of
Block Diagram
1A
140Thursday, August 28, 2008
Size Document Number Rev
Date: Sheet
of
Block Diagram
1A
140Thursday, August 28, 2008
Azalia
ODD (SATA)
FSB
P31
X'TAL
32.768K
P3
P25
SATA4
X'TAL
14.318MHZ
X'TAL
32.768KHZ
P25
PCI-Express
X4 DMI interface
Fan Header
P25
USB Port x 4
P32
EC (WPC8769LDG)
LPC
Penryn 479
uFCPGA
USB 2.0
P12,P13,P14,P15
P2
ICS: ICS9LPRS365BGLFT
SELGO: SLG8SP512K05
P5,P6,P7,P8,P9,P10,P11
HDD (SATA)*2
Thermal Sensor
ICH9M
P3,P4
SPI ROM
Cantiga
Touch Pad
P19USB7
CCD
10/100/1G LAN
P21
BROADCOM
X'TAL
25M
P32
P22
Transformer
USB0~3
SATA0
NB
SB
667/800/1067 Mhz
CPU
K/B COON.
CLOCK GENERATOR
SATA1
PCIE-6
P32
P32
5764M
RJ45
P22
P28P28
ZY6D SYSTEM BLOCK DIAGRAM
PM965
BOM MARK
E@ EXT VGA
I@ INT VGA
268@ AUDIO 268
888@ AUDIO 888
ND@ NON DOCK
D3@ DDR3
667/800 MHz
DDRII
SO-DIMM 0
SO-DIMM 1
Dual Channel DDR2
P27
P27 & 28
P28
Speaker
Audio Amplifier
Phone Jack Line in
P27
Azalia Audio
Controller
ALC268 & 888
Connector
Int MIC
D2@ DDR2
SP@
(EXT VGA OR DDR2)
D@ DOCK
P16
WLAN
P23
SWITCH CIRCUIT
Page:22
Page: 33
LAN
PCIE-4
P28
MIC Jack
P28
SPDIF
ED2@ EXT VGA & DDR2
ID2@ INT VGA & DDR2
ED3@ EXT VGA & DDR3
ID3@ INT VGA & DDR3
ASF@ ASF
NCB@ NON CARDBUS
CB@ CARDBUS
Page:19
LVDS
CRT
Page:19
NSF@ Non ASF
LOW COST
1. MINI CARD 1 SLOT
2. NON DOCK
3. NON CARDBUS
4. NON ASF
5. NON HDMI
Quanta Computer Inc.
PROJECT : ZY6D
Quanta Computer Inc.
PROJECT : ZY6D
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http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CGCLK_SMB
CGDAT_SMB
+3V_CLK
NEW_CLKREQ#_R
CLK_PCIE_SATA_R
CLK_PCIE_SATA#_R
PECLK_VGA_R
PECLK_VGA#_R
PCLK_ICH_R
MCH_BSEL1
CG_XOUT
CLK_MCH_BCLK_R
CLK_MCH_BCLK#_R
PCLK_PCM_R
CLK_PCIE_ICH_R
CLK_PCIE_ICH#_R
CLK_CPU_BCLK#_R
CLK_CPU_BCLK_R
FSA
CGCLK_SMB
CGDAT_SMB
CG_XIN
PCLK_ICH
CLK_PCIE_3GPLL_R
CLK_PCIE_3GPLL#_R
PCLK_MINI_R
PCLK_591_R
SATACLKREQ#_R
FSC
DREFCLK_R
DREFCLK#_R
CG_XOUT
CG_XIN
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_DREFSSCLK#_R
CLK_DREFSSCLK_R
CPU_BSEL2
CPU_BSEL0
PCLK_ICH_R
PCLK_PCM_R
CLK_PCIE_TV_R
CLK_PCIE_TV#_R
CLK_PCIE_CARD_R
CLK_PCIE_CARD#_R
+1V05_CLK
CLK_PCIE_NEW_C_R
CLK_PCIE_NEW_C#_R
CLK_PCIE_MINI1#_R
CLK_PCIE_MINI1_R
SATACLKREQ#_R
NEW_CLKREQ#_R
PCLK_MINI_R
MCH_BSEL0 <6>
MCH_BSEL1 <6>
MCH_BSEL2 <6>
PCLK_SMB<14,16,20,21,23,29>
PDAT_SMB<14,16,20,21,23,29>
CLK_PCIE_SATA# <12>
CLK_PCIE_SATA <12>
CLK_MXM# <18>
CLK_MXM <18>
PCLK_DEBUG<23>
14M_ICH<14>
CLK_MCH_BCLK <5>
CLK_MCH_BCLK# <5>
CLK_PCIE_ICH <13>
CLK_PCIE_ICH# <13>
CLK_CPU_BCLK <3>
CLK_CPU_BCLK# <3>
PCLK_ICH<13>
PCLK_591<32>
SATACLKREQ#<14>
CLKUSB_48<14>
CLK_DREFCLK<6>
CLK_DREFCLK#<6>
CK_PWRGD <14>
PM_STPCPU# <14>
PM_STPPCI# <14>
CLK_PCIE_LAN# <21>
CLK_PCIE_LAN <21>
CLK_PCIE_3GPLL <6>
CLK_PCIE_3GPLL# <6>
CLK_DREFSSCLK# <6>
CLK_DREFSSCLK <6>
CLK_PCIE_TV# <23>
CLK_PCIE_TV <23>
CLK_PCIE_CARD <28>
CLK_PCIE_CARD# <28>
CPU_BSEL0<3>
CPU_BSEL1<3>
CPU_BSEL2<3>
PCLK_PCM<27>
NEW_CLKREQ#<29>
CLK_PCIE_NEW_C <29>
CLK_PCIE_NEW_C# <29>
CLK_PCIE_MINI1 <23>
CLK_PCIE_MINI1# <23>
+3V
+3V
+3V +1.05V
+3V
Size Document Number Rev
Date: Sheet
of
CLOCK GENERATOR CK505 W/REGULATOR
1A
240Thursday, August 28, 2008
Size Document Number Rev
Date: Sheet
of
CLOCK GENERATOR CK505 W/REGULATOR
1A
240Thursday, August 28, 2008
Size Document Number Rev
Date: Sheet
of
CLOCK GENERATOR CK505 W/REGULATOR
1A
240Thursday, August 28, 2008
0
0
0
0
0
0
0
0
0
0
Clock Generator
BSEL Frequency Select Table
1
1
1
1
1
1
1
1
1
01
1
1
CPU Clock select
Clock Gen I2C
133Mhz
166Mhz
200Mhz
400Mhz
Reserved
100Mhz
333Mhz
FSC FSB FSA Frequency
266Mhz0
CLK VDD power range 1.05V~3.3V
Pin 56 : It acts as a
level sensitive strobe
to latch the FS pins
and other multiplexed
inputs.
Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internalgraphic controller support
1 = 27M & 27M_SS &SRC_0 for external graphic controller support
Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
0 = SRC_8
Pin 10/57/62 : For Pin CPU frequency selection
CRB Rev0.7 : 110(CBA)
Strap table
R254 Change from 33 to 475
Rev:B Swap SRC9 & SRC4
Rev:B for vendor requestSLG8SP512
ICS9LPRS365BGLFT
QCI P/N
AL8SP512K05
ALPRS365K13
Rev:C Change C 205 & C204 P/N to CH03306JB04
C267
.1U/10V_4
C267
.1U/10V_4
R261 33_4R261 33_4
3
2
1
Q26
RHU002N06
Q26
RHU002N06
Y8
14.318MHz
Y8
14.318MHz
2
4
1
3
RP13 0X2_4RP13 0X2_4
2
4
1
3
RP20 *0X2_4RP20 *0X2_4
2
4
1
3
RP11 *0X2_4RP11 *0X2_4
R260 10K_4R260 10K_4
R219BKP1608HS181-T R219BKP1608HS181-T
C265
.1U/10V_4
C265
.1U/10V_4
Quanta Computer Inc.
PROJECT : ZY2 & ZY6
Quanta Computer Inc.
PROJECT : ZY2 & ZY6
R229 33_4R229 33_4
2
4
1
3
RP17 0X2_4RP17 0X2_4
R231 0_4R231 0_4
3
2
1
Q27
RHU002N06
Q27
RHU002N06
R475 10K_4R475 10K_4
2
4
1
3
RP14 0X2_4RP14 0X2_4
R259 10K_4R259 10K_4
R531 *10K_4R531 *10K_4
R532 10K_4R532 10K_4
2
4
1
3
RP18 0X2_4RP18 0X2_4
R254 *475/F_4R254 *475/F_4
C215
.1U/10V_4
C215
.1U/10V_4
R253 33_4R253 33_4
R226 0_4R226 0_4
C263
*10U/6.3V_8
C263
*10U/6.3V_8
C212
.1U/10V_4
C212
.1U/10V_4
C204 33P/50V_4C204 33P/50V_4
R258 2.2K_4R258 2.2K_4
R243
10K_4
R243
10K_4
R230 10K_4R230 10K_4
2
4
1
3
RP10 *E@0X2RP10 *E@0X2
C272
10U/6.3V_8
C272
10U/6.3V_8
C214
.1U/10V_4
C214
.1U/10V_4
C260
.1U/10V_4
C260
.1U/10V_4
2
4
1
3
RP15 I@0X2RP15 I@0X2
2
4
1
3
RP9 0X2_4RP9 0X2_4
2
4
1
3
RP12 0X2_4RP12 0X2_4
C205 33P/50V_4C205 33P/50V_4
C261
.1U/10V_4
C261
.1U/10V_4
C216
.1U/10V_4
C216
.1U/10V_4
PCI_0/CLKREQ_A#
1
VDD_PCI
2
PCI_1/CLKREQ_B#
3
PCI_2
4
PCI_3
5
^PCI_4/LCDCLK_SEL
6
PCIF_5/ITP_EN
7
VSS_PCI
8
VDD_48
9
USB_48MHz/FS_A
10
VSS_48
11
VDD_I/O
12
SRC_0/DOT_96
13
SRC_0#/DOT_96#
14
VSS_I/O
15
VDD_PLL3
16
LCDCLK/27M
17
LCDCLK#/27M_SS
18
VSS_PLL3
19
VDD_PLL3_I/O
20
SRC_2
21
SRC_2#
22
VSS_SRC_1
23
SRC_3/CLKREQ_C#
24
SRC_3#/CLKREQ_D#
25
VDD_SRC_I/O_1
26
SRC_4
27
SRC_4#
28
VSS_SRC_2
29
SRC_9
30
SRC_9#
31
SRC_11#/CLKREQ_G#
32
SCL
64
SDA
63
REF/FS_C/TEST_SEL
62
VDD_REF
61
XTAL_IN
60
XTAL_OUT
59
VSS_REF
58
FS_B/TEST_MODE
57
CKPWRGD/PD#
56
VDD_CPU
55
CPU_0
54
CPU_0#
53
VSS_CPU
52
CPU_1_MCH
51
CPU_1_MCH#
50
VDD_CPU_I/O
49
NC
48
SRC_8/CPU_ITP
47
SRC_8#/CPU_ITP#
46
VDD_SRC_I/O_3
45
SRC_7/CLKREQ_F#
44
SRC_7#/CLKREQ_E#
43
VSS_SRC_3
42
SRC_6
41
SRC_6#
40
VDD_SRC
39
PCI_STOP#
38
CPU_STOP#
37
VDD_SRC_I/O_2
36
SRC_10#
35
SRC_10
34
SRC_11/CLKREQ_H#
33
U25
SLG8SP512
U25
SLG8SP512
C213
.1U/10V_4
C213
.1U/10V_4
2
4
1
3
RP8 0X2_4RP8 0X2_4
R237
10K_4
R237
10K_4
C257
.1U/10V_4
C257
.1U/10V_4
2
4
1
3
RP16 I@0X2RP16 I@0X2
R263 33_4R263 33_4
R252 33_4R252 33_4
C209*30P/50V_4 C209*30P/50V_4
R262 0_4R262 0_4
2
4
1
3
RP19 *0X2_4RP19 *0X2_4
R246 475/F_4R246 475/F_4
R264 *33_4R264 *33_4
R255 BKP1608HS181-TR255 BKP1608HS181-T
C262
.1U/10V_4
C262
.1U/10V_4
C219
.1U/10V_4
C219
.1U/10V_4
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_A#3
H_A#4
H_A#5
H_A#7
H_A#6
H_A#9
H_A#8
H_A#11
H_A#12
H_A#14
H_A#13
H_A#16
H_A#15
H_A#10
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#35
H_A#25
H_A#34
H_IERR#
XDP_BPM#1
H_RS#0
H_RS#1
H_RS#2
XDP_TDO
XDP_BPM#0
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
PM_THRMTRIP#
H_D#13
H_D#3
H_D#8
H_D#10
H_D#0
H_D#5
H_D#12
H_D#7
H_D#6
H_D#11
H_D#4
H_D#14
H_D#2
H_D#1
H_D#15
H_D#9
H_D#[0..15]
H_D#[16..31]
H_D#22
H_D#26
H_D#25
H_D#16
H_D#19
H_D#23
H_D#29
H_D#20
H_D#21
H_D#17
H_D#28
H_D#18
H_D#30
H_D#27
H_D#24
H_D#31
CPU_TEST6
CPU_TEST2
H_GTLREF
CPU_TEST1
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST7
H_D#[32..47]
H_D#35
H_D#37
H_D#43
H_D#44
H_D#38
H_D#33
H_D#39
H_D#42
H_D#34
H_D#32
H_D#47
H_D#46
H_D#40
H_D#36
H_D#41
H_D#45
H_D#58
H_D#56
H_D#50
H_D#61
H_D#57
H_D#59
H_D#53
H_D#51
H_D#52
H_D#48
H_D#55
H_D#63
H_D#54
H_D#62
H_D#60
H_D#49
H_D#[48..63]
COMP3
COMP2
COMP1
COMP0
XDP_TDI
XDP_TMS
XDP_BPM#5
XDP_TCK
XDP_TRST#
H_PROCHOT#_D
XDP_DBRESET#
H_THERMDA
CPUFAN#_ON
H_THERMDC
PM_THRMTRIP#
H_PROCHOT#_D
XDP_TDO
XDP_DBRESET#
LM86VCC
H_A#[3..16]<5>
H_ADSTB#0<5>
H_REQ#[0..4]<5>
H_A#[17..35]<5>
H_ADSTB#1<5>
H_FERR#<12>
H_INTR<12>
H_STPCLK#<12>
H_SMI#<12>
H_NMI<12>
H_A20M#<12>
H_IGNNE#<12>
H_BPRI# <5>
H_BNR# <5>
H_DEFER# <5>
H_BREQ# <5>
H_DBSY# <5>
H_DRDY# <5>
H_ADS# <5>
H_LOCK# <5>
H_HIT# <5>
H_INIT# <12>
H_TRDY# <5>
H_HITM# <5>
CLK_CPU_BCLK <2>
CLK_CPU_BCLK# <2>
H_D#[0..15]<5>
H_DSTBP#0<5>
H_DINV#0<5>
H_DSTBN#0<5>
H_DSTBP#1<5>
H_DINV#1<5>
H_DSTBN#1<5>
CPU_BSEL2<2>
CPU_BSEL1<2>
CPU_BSEL0<2>
H_DSTBP#2 <5>
H_DSTBN#2 <5>
H_DINV#2 <5>
H_DSTBP#3 <5>
H_DSTBN#3 <5>
H_DINV#3 <5>
H_DPSLP# <12>
PSI# <35>
ICH_DPRSTP# <6,12,35>
H_DPWR# <5>
H_PWRGD <12>
H_CPUSLP# <5>
SYS_RST# <14>
THERM_ALERT#<14,18>
2ND_MBDATA<32>
CPUFAN#_ON<31>
2ND_MBCLK<32>
SYS_SHDN# <34,38>
PM_THRMTRIP# <6,12>
DELAY_VR_PWRGOOD<6,14,32,35>
H_PROCHOT# <35>
H_D#[16..31]<5>
H_D#[32..47] <5>
H_D#[48..63] <5>
H_CPURST# <5>
H_RS#[0..2] <5>
+1.05V
+1.05V
+5V
+3V
+3V
+1.05V
+1.05V
+1.05V
+1.05V
+3V
+3V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
CPU Host Bus
1A
340Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
CPU Host Bus
1A
340Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
CPU Host Bus
1A
340Thursday, August 28, 2008
ZY2 & ZY6
CPU Thermal monitor
ADDRESS: 98H
Thermal Trip
Processor hot
No use PROCHOT CPU side still PU 56ohm.
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
side
XDP PU/PD
Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"
Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
XDP_DBRESET# and XDP_TDO
reserve for XDP
Layout note:
H_GTLREF: Zo=55 ohm
L<0.5", 2/3*VCCP+-2%
No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side
Connect it to CPU DBR# is for ITP debug port
or CPU interposer (like ICE) to reset the system
Rev:B Add R540
R128 *54.9/F_4R128 *54.9/F_4
R501 54.9/F_4R501 54.9/F_4
T18T18
R491 0_4R491 0_4
R124 54.9/F_4R124 54.9/F_4
R465 *0_4R465 *0_4
T19T19
R164 *0_4R164 *0_4
R162 56.2/F_4R162 56.2/F_4
COMP[0]
R26
COMP[1]
U26
COMP[2]
AA1
COMP[3]
Y1
D[0]#
E22
D[1]#
F24
D[10]#
J24
D[11]#
J23
D[12]#
H22
D[13]#
F26
D[14]#
K22
D[15]#
H23
D[16]#
N22
D[17]#
K25
D[18]#
P26
D[19]#
R23
D[2]#
E26
D[20]#
L23
D[21]#
M24
D[22]#
L22
D[23]#
M23
D[24]#
P25
D[25]#
P23
D[26]#
P22
D[27]#
T24
D[28]#
R24
D[29]#
L25
D[3]#
G22
D[30]#
T25
D[31]#
N25
D[32]#
Y22
D[33]#
AB24
D[34]#
V24
D[35]#
V26
D[36]#
V23
D[37]#
T22
D[38]#
U25
D[39]#
U23
D[4]#
F23
D[40]#
Y25
D[41]#
W22
D[42]#
Y23
D[43]#
W24
D[44]#
W25
D[45]#
AA23
D[46]#
AA24
D[47]#
AB25
D[48]#
AE24
D[49]#
AD24
D[5]#
G25
D[50]#
AA21
D[51]#
AB22
D[52]#
AB21
D[53]#
AC26
D[54]#
AD20
D[55]#
AE22
D[56]#
AF23
D[57]#
AC25
D[58]#
AE21
D[59]#
AD21
D[6]#
E25
D[60]#
AC22
D[61]#
AD23
D[62]#
AF22
D[63]#
AC23
D[7]#
E23
D[8]#
K24
D[9]#
G24
TEST5
AF1
DINV[0]#
H25
DINV[1]#
N24
DINV[2]#
U22
DINV[3]#
AC20
DPRSTP#
E5
DPSLP#
B5
DPWR#
D24
DSTBN[0]#
J26
DSTBN[1]#
L26
DSTBN[2]#
Y26
DSTBN[3]#
AE25
DSTBP[0]#
H26
DSTBP[1]#
M26
DSTBP[2]#
AA26
DSTBP[3]#
AF24
GTLREF
AD26
PSI#
AE6
PWRGOOD
D6
SLP#
D7
TEST3
C24
BSEL[0]
B22
BSEL[1]
B23
BSEL[2]
C21
TEST2
D25
TEST4
AF26
TEST6
A26
TEST1
C23
TEST7
C3
DATA GRP 0
DATA GRP 1
DATA GRP 2DATA GRP 3
MISC
U40B
Penryn
DATA GRP 0
DATA GRP 1
DATA GRP 2DATA GRP 3
MISC
U40B
Penryn
T10T10
T12T12
R113
1K/F_4
R113
1K/F_4
T71T71
T14T14
R127 54.9/F_4R127 54.9/F_4
3
2
1
Q39
RHU002N06
Q39
RHU002N06
3
2
1
Q38
RHU002N06
Q38
RHU002N06
R144 27.4/F_6R144 27.4/F_6
VCC
1
DXP
2
DXN
3
GND
5
SCLK
8
SDA
7
ALERT#
6
OVERT#
4
U39
G780
U39
G780
2
1 3
Q40
MMBT3904
Q40
MMBT3904
R500 27.4/F_6R500 27.4/F_6
A[10]#
N3
A[11]#
P5
A[12]#
P2
A[13]#
L2
A[14]#
P4
A[15]#
P1
A[16]#
R1
A[17]#
Y2
A[18]#
U5
A[19]#
R3
A[20]#
W6
A[21]#
U4
A[22]#
Y5
A[23]#
U1
A[24]#
R4
A[25]#
T5
A[26]#
T3
A[27]#
W2
A[28]#
W5
A[29]#
Y4
A[3]#
J4
A[30]#
U2
A[31]#
V4
RSVD[01]
M4
RSVD[02]
N5
RSVD[03]
T2
RSVD[04]
V3
RSVD[05]
B2
RSVD[06]
D2
RSVD[07]
D22
A[4]#
L5
A[5]#
L4
A[6]#
K5
A[7]#
M3
A[8]#
N2
A[9]#
J1
A20M#
A6
ADS#
H1
ADSTB[0]#
M1
ADSTB[1]#
V1
RSVD[08]
D3
BCLK[0]
A22
BCLK[1]
A21
BNR#
E2
BPM[0]#
AD4
BPM[1]#
AD3
BPM[2]#
AD1
BPM[3]#
AC4
BPRI#
G5
BR0#
F1
DBR#
C20
DBSY#
E1
DEFER#
H5
DRDY#
F21
FERR#
A5
HIT#
G6
HITM#
E4
IERR#
D20
IGNNE#
C4
INIT#
B3
LINT0
C6
LINT1
B4
LOCK#
H4
PRDY#
AC2
PREQ#
AC1
PROCHOT#
D21
REQ[0]#
K3
REQ[1]#
H2
REQ[2]#
K2
REQ[3]#
J3
REQ[4]#
L1
RESET#
C1
RS[0]#
F3
RS[1]#
F4
RS[2]#
G3
SMI#
A3
STPCLK#
D5
TCK
AC5
TDI
AA6
TDO
AB3
THERMTRIP#
C7
THERMDA
A24
THERMDC
B25
TMS
AB5
TRDY#
G2
TRST#
AB6
A[32]#
W3
A[33]#
AA4
A[34]#
AB2
A[35]#
AA3
RSVD[09]
F6
ADDR GROUP_0
ADDR GROUP_1
CONTROL
XDP/ITP SIGNALS
H CLK
THERMAL
RESERVED
ICH
U40A
Penryn
ADDR GROUP_0
ADDR GROUP_1
CONTROL
XDP/ITP SIGNALS
H CLK
THERMAL
RESERVED
ICH
U40A
Penryn
R149 54.9/F_4R149 54.9/F_4
C551
100P/X7R/50V_4
C551
100P/X7R/50V_4
T16T16
R121 54.9/F_4R121 54.9/F_4
R467
10K_4
R467
10K_4
T17T17
T13T13
T72T72
C552
.1U/10V_4
C552
.1U/10V_4
T15T15
R495
56.2/F_4
R495
56.2/F_4
R492 *1K_4R492 *1K_4
R115
2K/F_6
R115
2K/F_6
T70T70
R466
10K_4
R466
10K_4
R131 54.9/F_4R131 54.9/F_4
R494 0_4R494 0_4
R493 *10K_4R493 *10K_4
3
2
1
Q41
FDV301N
Q41
FDV301N
R163
56_4
R163
56_4
R540
10K_4
R540
10K_4
R147 54.9/F_4R147 54.9/F_4
R490
200_6
R490
200_6
T11T11
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_VID0 <35>
H_VID1 <35>
H_VID2 <35>
H_VID3 <35>
H_VID4 <35>
H_VID5 <35>
H_VID6 <35>
VCCSENSE <35>
VSSSENSE <35>
VCC_CORE VCC_CORE
+1.05V
VCC_CORE
+1.5V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
CPU Power
1A
440Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
CPU Power
1A
440Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
CPU Power
1A
440Thursday, August 28, 2008
ZY2 & ZY6
Layout Note:
Inside CPU center cavity in 2 rows
Layout Note:
Z0=27.4,PU/PD L<1"
Layout Note:
VCCA CAP closr to Pin
VCCA : 2.5A(Supply after VCC Stable)
4.5A(Supply before VCC Stable)
Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
stuff 22U*34, NC 22U*2
stuff 330U*2, NC330U*2
VCC:38A
VCCP:130mA
VCCA : 2.5A(Supply after VCC Stable)
4.5A(Supply before VCC Stable)
Layout Note:
Place these parts
reference to Intel demo
board.
10/12 :Modify BOM
C147
.1U/16V_6
C147
.1U/16V_6
R77
100/F_6
R77
100/F_6
C560
10U/6.3V_8
C560
10U/6.3V_8
C573
*10U/6.3V_8
C573
*10U/6.3V_8
C157
*10U/6.3V_8
C157
*10U/6.3V_8
+
C575
330U/2V_7
+
C575
330U/2V_7
+
C80
*330U/2V_7343
+
C80
*330U/2V_7343
C153
*10U/6.3V_8
C153
*10U/6.3V_8
C565
10U/6.3V_8
C565
10U/6.3V_8
C121
10U/6.3V_8
C121
10U/6.3V_8
C562
.01U/16V_4
C562
.01U/16V_4
C158
*10U/6.3V_8
C158
*10U/6.3V_8
C141
*10U/6.3V_8
C141
*10U/6.3V_8
VSS[082]
P6
VSS[148]
AE11
VSS[002]
A8
VSS[003]
A11
VSS[004]
A14
VSS[005]
A16
VSS[006]
A19
VSS[007]
A23
VSS[008]
AF2
VSS[009]
B6
VSS[010]
B8
VSS[011]
B11
VSS[012]
B13
VSS[013]
B16
VSS[014]
B19
VSS[015]
B21
VSS[016]
B24
VSS[017]
C5
VSS[018]
C8
VSS[019]
C11
VSS[020]
C14
VSS[021]
C16
VSS[022]
C19
VSS[023]
C2
VSS[024]
C22
VSS[025]
C25
VSS[026]
D1
VSS[027]
D4
VSS[028]
D8
VSS[029]
D11
VSS[030]
D13
VSS[031]
D16
VSS[032]
D19
VSS[033]
D23
VSS[034]
D26
VSS[035]
E3
VSS[036]
E6
VSS[037]
E8
VSS[038]
E11
VSS[039]
E14
VSS[040]
E16
VSS[041]
E19
VSS[042]
E21
VSS[043]
E24
VSS[044]
F5
VSS[045]
F8
VSS[046]
F11
VSS[047]
F13
VSS[048]
F16
VSS[049]
F19
VSS[050]
F2
VSS[051]
F22
VSS[052]
F25
VSS[053]
G4
VSS[054]
G1
VSS[055]
G23
VSS[056]
G26
VSS[057]
H3
VSS[058]
H6
VSS[059]
H21
VSS[060]
H24
VSS[061]
J2
VSS[062]
J5
VSS[063]
J22
VSS[064]
J25
VSS[065]
K1
VSS[066]
K4
VSS[067]
K23
VSS[068]
K26
VSS[069]
L3
VSS[070]
L6
VSS[071]
L21
VSS[072]
L24
VSS[073]
M2
VSS[074]
M5
VSS[075]
M22
VSS[076]
M25
VSS[077]
N1
VSS[078]
N4
VSS[079]
N23
VSS[080]
N26
VSS[081]
P3
VSS[162]
A25
VSS[161]
AF21
VSS[160]
AF19
VSS[159]
AF16
VSS[158]
AF13
VSS[157]
AF11
VSS[156]
AF8
VSS[155]
AF6
VSS[154]
A2
VSS[153]
AE26
VSS[152]
AE23
VSS[151]
AE19
VSS[083]
P21
VSS[084]
P24
VSS[085]
R2
VSS[086]
R5
VSS[087]
R22
VSS[088]
R25
VSS[089]
T1
VSS[090]
T4
VSS[091]
T23
VSS[092]
T26
VSS[093]
U3
VSS[094]
U6
VSS[095]
U21
VSS[096]
U24
VSS[097]
V2
VSS[098]
V5
VSS[099]
V22
VSS[100]
V25
VSS[101]
W1
VSS[102]
W4
VSS[103]
W23
VSS[104]
W26
VSS[105]
Y3
VSS[107]
Y21
VSS[108]
Y24
VSS[109]
AA2
VSS[110]
AA5
VSS[111]
AA8
VSS[112]
AA11
VSS[113]
AA14
VSS[114]
AA16
VSS[115]
AA19
VSS[116]
AA22
VSS[117]
AA25
VSS[118]
AB1
VSS[119]
AB4
VSS[120]
AB8
VSS[121]
AB11
VSS[122]
AB13
VSS[123]
AB16
VSS[124]
AB19
VSS[125]
AB23
VSS[126]
AB26
VSS[127]
AC3
VSS[128]
AC6
VSS[129]
AC8
VSS[130]
AC11
VSS[131]
AC14
VSS[132]
AC16
VSS[133]
AC19
VSS[134]
AC21
VSS[135]
AC24
VSS[136]
AD2
VSS[137]
AD5
VSS[138]
AD8
VSS[139]
AD11
VSS[140]
AD13
VSS[141]
AD16
VSS[142]
AD19
VSS[143]
AD22
VSS[144]
AD25
VSS[145]
AE1
VSS[146]
AE4
VSS[106]
Y6
VSS[001]
A4
VSS[149]
AE14
VSS[150]
AE16
VSS[147]
AE8
VSS[163]
AF25
U40D
Penryn
.
U40D
Penryn
.
C556
10U/6.3V_8
C556
10U/6.3V_8
+
C576
330U/2V_7343
+
C576
330U/2V_7343
C572
10U/6.3V_8
C572
10U/6.3V_8
+
C577
*330U/2V_7343
+
C577
*330U/2V_7343
C142
*10U/6.3V_8
C142
*10U/6.3V_8
C569
*10U/6.3V_8
C569
*10U/6.3V_8
C135
.1U/16V_6
C135
.1U/16V_6
C152
10U/6.3V_8
C152
10U/6.3V_8
C156
10U/6.3V_8
C156
10U/6.3V_8
C148
.1U/16V_6
C148
.1U/16V_6
C129
.1U/16V_6
C129
.1U/16V_6
C567
10U/6.3V_8
C567
10U/6.3V_8
C557
*10U/6.3V_8
C557
*10U/6.3V_8
R84 100/F_6R84 100/F_6
C574
10U/6.3V_8
C574
10U/6.3V_8
C139
*10U/6.3V_8
C139
*10U/6.3V_8
C566
*10U/6.3V_8
C566
*10U/6.3V_8
C571
*10U/6.3V_8
C571
*10U/6.3V_8
VCC[001]
A7
VCC[002]
A9
VCC[003]
A10
VCC[004]
A12
VCC[005]
A13
VCC[006]
A15
VCC[007]
A17
VCC[008]
A18
VCC[009]
A20
VCC[010]
B7
VCC[011]
B9
VCC[012]
B10
VCC[013]
B12
VCC[014]
B14
VCC[015]
B15
VCC[016]
B17
VCC[017]
B18
VCC[018]
B20
VCC[019]
C9
VCC[020]
C10
VCC[021]
C12
VCC[022]
C13
VCC[023]
C15
VCC[024]
C17
VCC[025]
C18
VCC[026]
D9
VCC[027]
D10
VCC[028]
D12
VCC[029]
D14
VCC[030]
D15
VCC[031]
D17
VCC[032]
D18
VCC[033]
E7
VCC[034]
E9
VCC[035]
E10
VCC[036]
E12
VCC[037]
E13
VCC[038]
E15
VCC[039]
E17
VCC[040]
E18
VCC[041]
E20
VCC[042]
F7
VCC[043]
F9
VCC[044]
F10
VCC[045]
F12
VCC[046]
F14
VCC[047]
F15
VCC[048]
F17
VCC[049]
F18
VCC[050]
F20
VCC[051]
AA7
VCC[052]
AA9
VCC[053]
AA10
VCC[054]
AA12
VCC[055]
AA13
VCC[056]
AA15
VCC[057]
AA17
VCC[058]
AA18
VCC[059]
AA20
VCC[060]
AB9
VCC[061]
AC10
VCC[062]
AB10
VCC[063]
AB12
VCC[064]
AB14
VCC[065]
AB15
VCC[066]
AB17
VCC[067]
AB18
VCC[068]
AB20
VCC[069]
AB7
VCC[070]
AC7
VCC[071]
AC9
VCC[072]
AC12
VCC[073]
AC13
VCC[074]
AC15
VCC[075]
AC17
VCC[076]
AC18
VCC[077]
AD7
VCC[078]
AD9
VCC[079]
AD10
VCC[080]
AD12
VCC[081]
AD14
VCC[082]
AD15
VCC[083]
AD17
VCC[084]
AD18
VCC[085]
AE9
VCC[086]
AE10
VCC[087]
AE12
VCC[088]
AE13
VCC[089]
AE15
VCC[090]
AE17
VCC[091]
AE18
VCC[092]
AE20
VCC[093]
AF9
VCC[094]
AF10
VCC[095]
AF12
VCC[096]
AF14
VCC[097]
AF15
VCC[098]
AF17
VCC[099]
AF18
VCC[100]
AF20
VCCA[01]
B26
VCCP[03]
J6
VCCP[04]
K6
VCCP[05]
M6
VCCP[06]
J21
VCCP[07]
K21
VCCP[08]
M21
VCCP[09]
N21
VCCP[10]
N6
VCCP[11]
R21
VCCP[12]
R6
VCCP[13]
T21
VCCP[14]
T6
VCCP[15]
V21
VCCP[16]
W21
VCCSENSE
AF7
VID[0]
AD6
VID[1]
AF5
VID[2]
AE5
VID[3]
AF4
VID[4]
AE3
VID[5]
AF3
VID[6]
AE2
VSSSENSE
AE7
VCCA[02]
C26
VCCP[01]
G21
VCCP[02]
V6
U40C
Penryn
.
U40C
Penryn
.
C564
*10U/6.3V_8
C564
*10U/6.3V_8
C553
*10U/6.3V_8
C553
*10U/6.3V_8
C136
.1U/16V_6
C136
.1U/16V_6
C563
10U/6.3V_8
C563
10U/6.3V_8
C554
10U/6.3V_8
C554
10U/6.3V_8
C568
*10U/6.3V_8
C568
*10U/6.3V_8
C120
*10U/6.3V_8
C120
*10U/6.3V_8
C140
*10U/6.3V_8
C140
*10U/6.3V_8
C559
*10U/6.3V_8
C559
*10U/6.3V_8
C128
.1U/16V_6
C128
.1U/16V_6
C151
*10U/6.3V_8
C151
*10U/6.3V_8
C154
10U/6.3V_8
C154
10U/6.3V_8
C558
10U/6.3V_8
C558
10U/6.3V_8
C570
10U/6.3V_8
C570
10U/6.3V_8
C118
10U/6.3V_8
C118
10U/6.3V_8
C561
10U/6.3V_8
C561
10U/6.3V_8
C155
*10U/6.3V_8
C155
*10U/6.3V_8
C119
*10U/6.3V_8
C119
*10U/6.3V_8
C555
*10U/6.3V_8
C555
*10U/6.3V_8
+
C81
330U/2V_7343
+
C81
330U/2V_7343
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#34
H_A#33
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_RCOMP
H_SWING
H_AVREF
H_SWING
H_RCOMP
H_D#[0..63]<3>
H_A#[3..35] <3>
H_TRDY# <3>
H_HIT# <3>
H_HITM# <3>
H_LOCK# <3>
H_ADS# <3>
H_BNR# <3>
H_BREQ# <3>
H_DBSY# <3>
H_DRDY# <3>
H_DPWR# <3>
H_BPRI# <3>
H_DEFER# <3>
CLK_MCH_BCLK <2>
CLK_MCH_BCLK# <2>
H_DINV#[3..0] <3>
H_DSTBN#[3..0] <3>
H_DSTBP#[3..0] <3>
H_REQ#[0..4] <3>
H_RS#[0..2] <3>H_CPUSLP#<3>
H_CPURST#<3>
H_ADSTB#0 <3>
H_ADSTB#1 <3>
+1.05V
+1.05V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH HOST
1A
540Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH HOST
1A
540Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH HOST
1A
540Thursday, August 28, 2008
ZY2 & ZY6
0.3125*VCCP
WIDE(10):SPACING(20) ,
L<0.5"
2/3*VCCP
WIDE(10):SPACING(20),
L<0.5"
WIDE(10):SPACING(20) ,
L<0.5"
Capacitor close
to the pin
Intel Cantiga (G)M
Intel Cantiga (P)M
QCI P/N
AJSLB940T04
AJSLB970T06
H_A#_10
P16
H_A#_11
R16
H_A#_12
N17
H_A#_13
M13
H_A#_14
E17
H_A#_15
P17
H_A#_16
F17
H_A#_17
G20
H_A#_18
B19
H_A#_19
J16
H_A#_20
E20
H_A#_21
H16
H_A#_22
J20
H_A#_23
L17
H_A#_24
A17
H_A#_25
B17
H_A#_26
L16
H_A#_27
C21
H_A#_28
J17
H_A#_29
H20
H_A#_3
A14
H_A#_30
B18
H_A#_31
K17
H_A#_4
C15
H_A#_5
F16
H_A#_6
H13
H_A#_7
C18
H_A#_8
M16
H_A#_9
J13
H_ADS#
H12
H_ADSTB#_0
B16
H_ADSTB#_1
G17
H_BNR#
A9
H_BPRI#
F11
H_BREQ#
G12
HPLL_CLK#
AH6
H_CPURST#
C12
HPLL_CLK
AH7
H_D#_0
F2
H_REQ#_2
F13
H_REQ#_3
B13
H_D#_1
G8
H_D#_10
M9
H_D#_20
L6
H_D#_30
N10
H_D#_40
AA8
H_D#_50
AA2
H_D#_60
AE11
H_D#_8
D4
H_D#_9
H3
H_DBSY#
B10
H_D#_11
M11
H_D#_12
J1
H_D#_13
J2
H_D#_14
N12
H_D#_15
J6
H_D#_16
P2
H_D#_17
L2
H_D#_18
R2
H_D#_19
N9
H_D#_2
F8
H_D#_21
M5
H_D#_22
J3
H_D#_23
N2
H_D#_24
R1
H_D#_25
N5
H_D#_26
N6
H_D#_27
P13
H_D#_28
N8
H_D#_29
L7
H_D#_3
E6
H_D#_31
M3
H_D#_32
Y3
H_D#_33
AD14
H_D#_34
Y6
H_D#_35
Y10
H_D#_36
Y12
H_D#_37
Y14
H_D#_38
Y7
H_D#_39
W2
H_D#_4
G2
H_D#_41
Y9
H_D#_42
AA13
H_D#_43
AA9
H_D#_44
AA11
H_D#_45
AD11
H_D#_46
AD10
H_D#_47
AD13
H_D#_48
AE12
H_D#_49
AE9
H_D#_5
H6
H_D#_51
AD8
H_D#_52
AA3
H_D#_53
AD3
H_D#_54
AD7
H_D#_55
AE14
H_D#_56
AF3
H_D#_57
AC1
H_D#_58
AE3
H_D#_59
AC3
H_D#_6
H2
H_D#_61
AE8
H_D#_62
AG2
H_D#_63
AD6
H_D#_7
F6
H_DEFER#
E9
H_DINV#_0
J8
H_DINV#_1
L3
H_DINV#_2
Y13
H_DINV#_3
Y1
H_DPWR#
J11
H_DRDY#
F9
H_DSTBN#_0
L10
H_DSTBN#_1
M7
H_DSTBN#_2
AA5
H_DSTBN#_3
AE6
H_DSTBP#_0
L9
H_DSTBP#_1
M8
H_DSTBP#_2
AA6
H_DSTBP#_3
AE5
H_AVREF
A11
H_DVREF
B11
H_TRDY#
C9
H_HIT#
H9
H_HITM#
E12
H_LOCK#
H11
H_REQ#_0
B15
H_REQ#_1
K13
H_REQ#_4
B14
H_A#_32
B20
H_A#_33
F21
H_A#_34
K21
H_A#_35
L20
H_SWING
C5
H_CPUSLP#
E11
H_RCOMP
E3
H_RS#_0
B6
H_RS#_1
F12
H_RS#_2
C8
HOST
U38A
SP@CANTIGA_1p2
HOST
U38A
SP@CANTIGA_1p2
C178
0.1U/10V_4
C178
0.1U/10V_4
R484
1K/F_4
R484
1K/F_4
R464
24.9/F_4
R464
24.9/F_4
R177
221/F_4
R177
221/F_4
R175
100/F_4
R175
100/F_4
R482
2K/F_4
R482
2K/F_4
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH_DPRSTP#_R
TSATN#
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
M_CLK0
M_CLK1
M_CLK2
M_CLK3
M_CLK#0
M_CLK#1
M_CLK#2
M_CLK#3
M_RCOMP#
M_RCOMP
SM_RCOMP_VOL
SM_RCOMP_VOH
SM_REXT
DDPC_DDCDATA
MCH_CLVREF_R
SM_VREF
CLK_DREFCLK
CLK_DREFSSCLK
CLK_PCIE_3GPLL#
CLK_PCIE_3GPLL
CLK_DREFCLK#
CLK_DREFCLK
CLK_DREFSSCLK#
CLK_DREFSSCLK
DMI_TXN2
DMI_TXN3
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN2
DMI_RXN3
DMI_RXN0
DMI_RXN1
DMI_RXP3
DMI_RXP2
DMI_RXP1
DMI_RXP0
DMI_TXN0
DMI_TXN1
DMI_TXP0
PM_SYNC#_R
DDPC_CTRLCLK
MCH_CFG_20
CLK_MCH_OE#
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
PM_EXTTS#0_1_EC_R
TS#DIMM0_1_R
DPRSLPVR_R
THRMTRIP#_R
RST_IN#_MCH
DDPC_DDCDATA
SDVO_CTRLDATA
SDVO_CTRLCLK
CLK_DREFCLK#
CLK_DREFSSCLK#
M_RCOMP#
M_RCOMP
MCH_CFG_5
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
DDPC_CTRLCLK
SM_RCOMP_VOL
SM_RCOMP_VOH
JTAG_TDO
JTAG_TMS
JTAG_TDI
JTAG_TCK
SM_VREF
SM_PWROK
SM_PWROK
HDA_SDIN_HDMI
HDA_RST#_HDMI
HDA_SYNC_HDMI
HDA_BIT_CLK_HDMI
HDA_SDOUT_HDMI
SM_RCOMP_VOL
DMI_RXP[3:0] <13>
DMI_TXP[3:0] <13>
DMI_TXN[3:0] <13>
DMI_RXN[3:0] <13>
CL_CLK0 <14>
CL_DATA0 <14>
CL_RST#0 <14>
MPWROK <14,32>
MCH_ICH_SYNC# <14>
MCH_BSEL0<2>
MCH_BSEL1<2>
MCH_BSEL2<2>
PM_THRMTRIP#<3,12>
DELAY_VR_PWRGOOD<3,14,32,35>
PLT_RST#<13>
PM_DPRSLPVR<14,35>
PM_SYNC#<14>
ICH_DPRSTP#<3,12,35>
M_CKE1 <16,17>
M_CKE0 <16,17>
M_CKE3 <16,17>
M_CKE2 <16,17>
M_CS#0 <16,17>
M_CS#1 <16,17>
M_CS#2 <16,17>
M_CS#3 <16,17>
M_ODT1 <16,17>
M_ODT0 <16,17>
M_ODT3 <16,17>
M_ODT2 <16,17>
PM_EXTTS#1<16,17>
PM_EXTTS#0<16,17>
CLK_DREFCLK# <2>
CLK_DREFSSCLK# <2>
CLK_DREFCLK <2>
CLK_DREFSSCLK <2>
CLK_PCIE_3GPLL# <2>
CLK_PCIE_3GPLL <2>
SDVO_CTRLDATA <20>
SDVO_CTRLCLK <20>
DDR3_DRAMRST# <17>
M_CLK0 <16,17>
M_CLK1 <16,17>
M_CLK2 <16,17>
M_CLK#0 <16,17>
M_CLK3 <16,17>
M_CLK#1 <16,17>
M_CLK#2 <16,17>
M_CLK#3 <16,17>
HWPG_VDR <32,37>
HDA_SDOUT_HDMI <12>
HDA_SDIN_HDMI <12>
HDA_BIT_CLK_HDMI <12>
HDA_SYNC_HDMI <12>
HDA_RST#_HDMI <12>
MCH_CFG_6_R <13>
MCH_CFG_6<13>
+1.05V
+VDR_SUS
+3V
+3V
+VDR_SUS
+VDR_SUS
+1.05V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH DMI
1A
640Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH DMI
1A
640Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH DMI
1A
640Thursday, August 28, 2008
ZY2 & ZY6
XOR
0 = XOR mode enable
1 = disable(Default)
SDVO_CTRLDATA SDVO Present
0 = No SDVO/HDMI Device Present(Default)
1 = SDVO/HDMI Device present
DDPC_CTRLDATA Digital Display Present
0 = Digital display(HDMI/DP) device
absent(Default)
1 = Digital display(HDMI/DP) device present
CFG13
CFG[15:14]
CFG16
CFG[18:17]
CFG19
CFG20
Reserved
FSB Dynamic ODT
DMI Lane Reversal
Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIE
Reserved
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = Normal (Default)
1 = Lanes Reversed
0 = Only Digital Display port (SDVO/DP/iHDMI)
or PCIE is operational (Default)
1 = Digital Display port (SDVO/DP/iHDMI) and
PCIE are operating simultaneously via PEG
port
0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is disabled(Default)
Reserved
0 = Enabled
1 = Disabled (Default)
ReservedCFG11
CFG12
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
Pin Name Strap description
FSB Frequency Select
Reserved
DMI X2 Select
iTPM Host Interface
ME TLS Confidentiality
PCIE Graphics Lane Reversal
PCIE Loopback enable
ALLZ
000= FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = AMT Firmware will use TLS cipher suite
with no confidentiality
1 = AMT Firmware will use TLS cipher suite
with confidentiality(Default)
0 = Reverse Lanes
1 = Normal operation(Default)
0 = ALLZ mode enable
1 = disable(Default)
Configuration
Strap table
Check list note : CL_REF=0.35VNB Thermal trip pin
No use Thermal trip NB side can
NC.(NB has ODT)
PM_DPRSTP#
The Daisy chain topology should
be routed from ICH9M to IMVP ,
then to (G)MCH and CPU, in that
order.
NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M
for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be
supplied with 3.3V if and only if (G)MCH's HDA is not
connected to ICH9M. Consequently, only 1.5V
audio/modem codecs can be used on the platform.
Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V
DDPC_CTRL for HDMI port C
SDVO_CTRL for HDMI port B
<Checklist ver0.8>
If TSATN# is not used, then it must be terminated
with a 56- pull-up resistor to VCCP.
<Pin out check issue>
Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN
If HDMI not support
HDA --> NC
VCC_HDA-->GND
Differential signal-->NC
SM_VREF.Default use voltage divider
for poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is
1K,But Check list PU/PD is 10K.
SM_VREF=0.5*VCC_SM
SM_PWROK only for
DDR3.DDR2 PD only
SM_DRAMRST# only
for DDR3.DDR2 NC.
Strap pin
INTEL FAE Suggest PD for Ext graphics
REV: E Modify TPM (R207)
R206 *2.21K/F_4R206 *2.21K/F_4
R457 80.6/F_4R457 80.6/F_4
T23T23
R207 *TPM@2.21K/F_4R207 *TPM@2.21K/F_4
R182 *E@0_4R182 *E@0_4
T21T21
R184 *I@2.21K/F_4R184 *I@2.21K/F_4
R213 0_4R213 0_4
R247 100/F_4R247 100/F_4
T30T30
R249 10K/F_4R249 10K/F_4
T20T20
R453
3.01K/F_4
R453
3.01K/F_4
T29T29
R180 56_4R180 56_4
R217 *2.21K/F_4R217 *2.21K/F_4
R221 *0_4R221 *0_4
R4541K/F_4 R4541K/F_4
SA_CK_0
AP24
SA_CK_1
AT21
SB_CK_0
AV24
SA_CK#_0
AR24
SA_CK#_1
AR21
SB_CK#_0
AU24
SA_CKE_0
BC28
SA_CKE_1
AY28
SB_CKE_0
AY36
SB_CKE_1
BB36
SA_CS#_0
BA17
SA_CS#_1
AY16
SB_CS#_0
AV16
SB_CS#_1
AR13
SM_DRAMRST#
BC36
SA_ODT_0
BD17
SA_ODT_1
AY17
SB_ODT_0
BF15
SB_ODT_1
AY13
SM_RCOMP
BG22
SM_RCOMP#
BH21
CFG_18
P29
CFG_19
R28
CFG_2
P25
CFG_0
T25
CFG_1
R25
CFG_20
T28
CFG_3
P20
CFG_4
P24
CFG_5
C25
CFG_6
N24
CFG_7
M24
CFG_8
E21
CFG_9
C23
CFG_10
C24
CFG_11
N21
CFG_12
P21
CFG_13
T21
CFG_14
R20
CFG_15
M20
CFG_16
L21
CFG_17
H21
PM_SYNC#
R29
PM_EXT_TS#_0
N33
PM_EXT_TS#_1
P32
PWROK
AT40
RSTIN#
AT11
DPLL_REF_CLK
B38
DPLL_REF_CLK#
A38
DPLL_REF_SSCLK
E41
DPLL_REF_SSCLK#
F41
DMI_RXN_0
AE41
DMI_RXN_1
AE37
DMI_RXN_2
AE47
DMI_RXN_3
AH39
DMI_RXP_0
AE40
DMI_RXP_1
AE38
DMI_RXP_2
AE48
DMI_RXP_3
AH40
DMI_TXN_0
AE35
DMI_TXN_1
AE43
DMI_TXN_2
AE46
DMI_TXN_3
AH42
DMI_TXP_0
AD35
DMI_TXP_1
AE44
DMI_TXP_2
AF46
DMI_TXP_3
AH43
ME_JTAG_TCK
AL34
ME_JTAG_TDO
AN35
ME_JTAG_TDI
AK34
ME_JTAG_TMS
AM35
RSVD22
BG23
RSVD23
BF23
RSVD24
BH18
RSVD25
BF18
PM_DPRSTP#
B7
SB_CK_1
AU20
SB_CK#_1
AV20
RSVD20
AY21
RSVD5
AH9
RSVD6
AH10
RSVD7
AH12
RSVD8
AH13
RSVD1
M36
RSVD2
N36
RSVD3
R33
RSVD4
T33
GFX_VID_0
B33
GFX_VID_1
B32
GFX_VID_2
G33
GFX_VID_3
F33
GFX_VR_EN
C34
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
THERMTRIP#
T20
DPRSLPVR
R32
RSVD9
K12
CL_CLK
AH37
CL_DATA
AH36
CL_PWROK
AN36
CL_RST#
AJ35
CL_VREF
AH34
NC_1
BG48
NC_2
BF48
NC_3
BD48
NC_4
BC48
NC_5
BH47
NC_6
BG47
NC_7
BE47
NC_8
BH46
NC_9
BF46
NC_10
BG45
NC_11
BH44
NC_12
BH43
NC_13
BH6
NC_14
BH5
NC_15
BG4
SDVO_CTRLCLK
G36
SDVO_CTRLDATA
E36
CLKREQ#
K36
RSVD14
T24
ICH_SYNC#
H36
TSATN#
B12
PEG_CLK#
E43
PEG_CLK
F43
NC_16
BH3
GFX_VID_4
E33
RSVD15
B31
DDPC_CTRLCLK
N28
NC_17
BF3
NC_18
BH2
NC_19
BG2
NC_20
BE2
NC_21
BG1
NC_22
BF1
NC_23
BD1
NC_24
BC1
NC_25
F1
SM_VREF
AV42
SM_PWROK
AR36
SM_REXT
BF17
RSVD17
M1
HDA_BCLK
B28
HDA_RST#
B30
HDA_SDI
B29
HDA_SDO
C29
HDA_SYNC
A28
DDPC_CTRLDATA
M28
RSVD21
B2
PM
MISC
NC
DDR CLK/ CONTROL/COMPENSATION
CLK
DMI
CFG
RSVD
GRAPHICS VID
MEHDA
ME JTAG
U38B
SP@CANTIGA_1p2
PM
MISC
NC
DDR CLK/ CONTROL/COMPENSATION
CLK
DMI
CFG
RSVD
GRAPHICS VID
MEHDA
ME JTAG
U38B
SP@CANTIGA_1p2
R218 0_4R218 0_4
R212 0_4R212 0_4
R257 *D3@0_4R257 *D3@0_4
R174 *E@0_4R174 *E@0_4
R478 *4.02K/F_4R478 *4.02K/F_4
R470 0_4R470 0_4
T27T27
C515
0.01U/16V_4
C515
0.01U/16V_4
R224
1K/F_4
R224
1K/F_4
R200 *4.02K/F_4R200 *4.02K/F_4
R477 *4.02K/F_4R477 *4.02K/F_4
R251 *D3@10K/F_4R251 *D3@10K/F_4
R222 *4.02K/F_4R222 *4.02K/F_4
R487 *4.02K/F_4R487 *4.02K/F_4
R196 *4.02K/F_4R196 *4.02K/F_4
R183 *E@0_4R183 *E@0_4
R481 10K_4R481 10K_4
T28T28
R193 *E@0_4R193 *E@0_4
R250 10K/F_4R250 10K/F_4
T26T26
R256 499/F_4R256 499/F_4
T24T24
R485 10K_4R485 10K_4
R248 10K/F_4R248 10K/F_4
R233
511/F_4
R233
511/F_4
R483 0_4R483 0_4
T25T25
R216 *4.02K/F_4R216 *4.02K/F_4
C207
0.1U/10V_4
C207
0.1U/10V_4
R209 10K_4R209 10K_4
R458 80.6/F_4R458 80.6/F_4
R479 *4.02K/F_4R479 *4.02K/F_4
R488 *4.02K/F_4R488 *4.02K/F_4
C514
2.2U/6V_6
C514
2.2U/6V_6
R188 *I@2.21K/F_4R188 *I@2.21K/F_4
C517
0.01U/16V_4
C517
0.01U/16V_4
R452
1K/F_4
R452
1K/F_4
T22T22
T31T31
C516
2.2U/6V_6
C516
2.2U/6V_6
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN15
PEG_RXP0
PEG_RXN14
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP1
PEG_RXP5
PEG_RXP8
PEG_RXP6
PEG_RXP7
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP15
PEG_TXP1
PEG_TXP2
PEG_TXP6
PEG_TXP3
PEG_TXP9
PEG_TXP4
PEG_TXP5
PEG_TXP7
PEG_TXP12
PEG_TXP8
PEG_TXP14
PEG_TXP15
PEG_TXP10
PEG_TXP11
PEG_TXP13
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN5
C_PEG_TXN4
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN14
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN12
C_PEG_TXN11
C_PEG_TXN13
C_PEG_TXN8
C_PEG_TXN15
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP4
C_PEG_TXP14
C_PEG_TXP5
C_PEG_TXP1
C_PEG_TXP8
C_PEG_TXP3
C_PEG_TXP2
C_PEG_TXP12
C_PEG_TXP6
C_PEG_TXP13
C_PEG_TXP15
C_PEG_TXP7
C_PEG_TXP0
C_PEG_TXP11
PEG_TXN1
PEG_TXN0
PEG_TXN2
PEG_TXN4
PEG_TXN6
PEG_TXN5
PEG_TXN3
PEG_TXN14
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN13
PEG_TXN10
PEG_TXN12
PEG_TXN11
PEG_TXP0
PEG_TXN15
INT_TXLCLKOUT+
INT_TXLCLKOUT-
INT_TXLOUT0-
INT_TXLOUT0+
INT_TXLOUT2-
INT_TXLOUT2+
INT_TXLOUT1-
INT_TXLOUT1+
INT_TXUCLKOUT+
INT_TXUCLKOUT-
INT_TXUOUT0-
INT_TXUOUT0+
INT_TXUOUT2-
INT_TXUOUT2+
INT_TXUOUT1-
INT_TXUOUT1+
INT_CRT_RED
INT_CRT_GRN
INT_CRT_BLU
L_CTRL_CLK
HSYNC_G
VSYNC_G
CRTIREF
L_CTRL_DATA
EXP_A_COMPX
HSYNC_G
VSYNC_G
CRTIREF
INT_CRT_GRN
INT_CRT_RED
INT_CRT_BLU
INT_TV_Y/G
INT_TV_C/R
INT_TV_COMP
INT_LVDS_DIGON<19>
INT_LVDS_EDIDCLK<19>
INT_LVDS_EDIDDATA<19>
INT_CRT_RED<18>
INT_CRT_BLU<18>
INT_CRT_GRN<18>
PEG_RXN[15:0] <18>
PEG_RXP[15:0] <18>
PEG_TXN[15:0] <18>
PEG_TXP[15:0] <18>
INT_HSYNC<18>
INT_VSYNC<18>
INT_CRT_DDCDAT<18>
INT_CRT_DDCCLK<18>
INT_LVDS_BLON<19>
INT_TXUOUT2-<18>
INT_TXUOUT1+<18>
INT_TXLOUT1+<18>
INT_TXLOUT2+<18>
INT_TXUOUT0-<18>
INT_TXLOUT0+<18>
INT_TXUOUT0+<18>
INT_TXUOUT1-<18>
INT_TXLOUT0-<18>
INT_TXLOUT2-<18>
INT_TXLCLKOUT+<18>
INT_TXUOUT2+<18>
INT_TXUCLKOUT+<18>
INT_TXLCLKOUT-<18>
INT_TXLOUT1-<18>
INT_TXUCLKOUT-<18>
L_BKLT_CTRL<19>
+1.05V
+3V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VGA
1A
740Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VGA
1A
740Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VGA
1A
740Thursday, August 28, 2008
ZY2 & ZY6
CRTIREF pull down
for Teenah 1.3k ohm/F
for cantiga 1.02k ohm/F
If LVDS no use,all signal can NC
IV&EV Dis/Enable setting
L<0.5" , If PCIE not support
still connect to +VCC_PEG
Can support reversal routing.If CFG9=1, PCI
Express is normal operation. If CFG9=0,
then PEG_TXP0 becomes PEG_TXP15, PEG_TXP1
becomes PEG_TXP14, PEG_TXP2 becomes
PEG_TXP13, etc. similarly for PEG_RXP[15:0]
and PEG_RXN[15:0]
HSYNC/VSYNC serial R place close to NB
<check list>
For EV@
Connect to GND
CRT R/G/B
HSYNC/VSYNC
CRTIREF
<check list>
For IV@
Connect to 150ohm
CRT R/G/B
Connect to 1.02Kohm
CRTIREF
<5/31>Montevina_Schematics_Checklist_Rev0_8
a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But
design guide Rev0.7 show NC.What is correct.
b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA .
CRT_HSYNC, CRT_VSYNCThese signals should be connected to
GND. But design guide Rev0.7 show NC, Intel suggest follow
Design guide.
IV&EV Dis/Enable setting
IV&EV Dis/Enable setting
10/15: R178 Change to I@
Note :REV B: remove R475
& R471 short to GND
10/15: Change to SP@
11/28: Change R181 1.02K ohm P/N
Rev: B Change P/N
R195 75_4R195 75_4
R197 SP@150_4R197 SP@150_4
C256 *E@.1U/10V_4C256 *E@.1U/10V_4
C195 *.1U/10V_4C195 *.1U/10V_4
C276 *E@.1U/10V_4C276 *E@.1U/10V_4
C254 *E@.1U/10V_4C254 *E@.1U/10V_4
R181 SP@0 & 1.02K/F_4R181 SP@0 & 1.02K/F_4
C242 *E@.1U/10V_4C242 *E@.1U/10V_4
R186 SP@150_4R186 SP@150_4
PEG_COMPI
T37
PEG_COMPO
T36
PEG_RX#_0
H44
PEG_RX#_1
J46
PEG_RX#_2
L44
PEG_RX#_3
L40
PEG_RX#_4
N41
PEG_RX#_5
P48
PEG_RX#_6
N44
PEG_RX#_7
T43
PEG_RX#_8
U43
PEG_RX#_9
Y43
PEG_RX#_10
Y48
PEG_RX#_11
Y36
PEG_RX#_12
AA43
PEG_RX#_13
AD37
PEG_RX#_14
AC47
PEG_RX#_15
AD39
PEG_RX_0
H43
PEG_RX_1
J44
PEG_RX_2
L43
PEG_RX_3
L41
PEG_RX_4
N40
PEG_RX_5
P47
PEG_RX_6
N43
PEG_RX_7
T42
PEG_RX_8
U42
PEG_RX_9
Y42
PEG_RX_10
W47
PEG_RX_11
Y37
PEG_RX_12
AA42
PEG_RX_13
AD36
PEG_RX_14
AC48
PEG_RX_15
AD40
PEG_TX#_0
J41
PEG_TX#_10
Y40
PEG_TX#_3
M40
PEG_TX#_4
M42
PEG_TX#_5
R48
PEG_TX#_6
N38
PEG_TX#_7
T40
PEG_TX#_8
U37
PEG_TX#_9
U40
PEG_TX#_1
M46
PEG_TX#_11
AA46
PEG_TX#_12
AA37
PEG_TX#_13
AA40
PEG_TX#_14
AD43
PEG_TX#_15
AC46
PEG_TX#_2
M47
PEG_TX_0
J42
PEG_TX_1
L46
PEG_TX_2
M48
PEG_TX_3
M39
PEG_TX_4
M43
PEG_TX_5
R47
PEG_TX_6
N37
PEG_TX_7
T39
PEG_TX_8
U36
PEG_TX_9
U39
PEG_TX_10
Y39
PEG_TX_11
Y46
PEG_TX_12
AA36
PEG_TX_13
AA39
PEG_TX_14
AD42
PEG_TX_15
AD46
L_CTRL_CLK
M32
L_CTRL_DATA
M33
L_DDC_CLK
K33
L_DDC_DATA
J33
L_VDD_EN
M29
LVDS_IBG
C44
LVDS_VBG
B43
LVDS_VREFH
E37
LVDS_VREFL
E38
LVDSA_CLK#
C41
LVDSA_CLK
C40
LVDSA_DATA#_0
H47
LVDSA_DATA#_1
E46
LVDSA_DATA#_2
G40
LVDSA_DATA_1
D45
LVDSA_DATA_2
F40
LVDSB_CLK#
B37
LVDSB_CLK
A37
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
H38
LVDSB_DATA#_2
G37
LVDSB_DATA_1
G38
LVDSB_DATA_2
F37
L_BKLT_EN
G32
TVA_DAC
F25
TVB_DAC
H25
TVC_DAC
K25
TV_RTN
H24
CRT_BLUE
E28
CRT_DDC_CLK
H32
CRT_DDC_DATA
J32
CRT_GREEN
G28
CRT_HSYNC
J29
CRT_TVO_IREF
E29
CRT_RED
J28
CRT_IRTN
G29
CRT_VSYNC
L29
LVDSA_DATA_0
H48
LVDSB_DATA_0
B42
L_BKLT_CTRL
L32
TV_DCONSEL_0
C31
TV_DCONSEL_1
E32
LVDSA_DATA#_3
A40
LVDSA_DATA_3
B40
LVDSB_DATA#_3
J37
LVDSB_DATA_3
K37
LVDS
PCI-EXPRESS GRAPHICS
TV
VGA
U38C
SP@CANTIGA_1p2
LVDS
PCI-EXPRESS GRAPHICS
TV
VGA
U38C
SP@CANTIGA_1p2
C259 *E@.1U/10V_4C259 *E@.1U/10V_4
C230 *E@.1U/10V_4C230 *E@.1U/10V_4
R178 I@2.37K/F_4R178 I@2.37K/F_4
R468 *E@0_4R468 *E@0_4
C236 *E@.1U/10V_4C236 *E@.1U/10V_4
C269 *E@.1U/10V_4C269 *E@.1U/10V_4
R472 *E@0_4R472 *E@0_4
C197 *.1U/10V_4C197 *.1U/10V_4
R474 I@30.1_4R474 I@30.1_4
C228 *E@.1U/10V_4C228 *E@.1U/10V_4
C224 *E@.1U/10V_4C224 *E@.1U/10V_4
C270 *E@.1U/10V_4C270 *E@.1U/10V_4
R215 49.9/F_4R215 49.9/F_4
R469 I@10K_4R469 I@10K_4
C233 *E@.1U/10V_4C233 *E@.1U/10V_4
C252 *E@.1U/10V_4C252 *E@.1U/10V_4
R189 75_4R189 75_4
C188 *.1U/10V_4C188 *.1U/10V_4
C275 *E@.1U/10V_4C275 *E@.1U/10V_4
C271 *E@.1U/10V_4C271 *E@.1U/10V_4
R190 SP@150_4R190 SP@150_4
C208 *.1U/10V_4C208 *.1U/10V_4
C249 *E@.1U/10V_4C249 *E@.1U/10V_4
C194 *.1U/10V_4C194 *.1U/10V_4
C196 *.1U/10V_4C196 *.1U/10V_4
C206 *.1U/10V_4C206 *.1U/10V_4
C189 *.1U/10V_4C189 *.1U/10V_4
C218 *E@.1U/10V_4C218 *E@.1U/10V_4
C251 *E@.1U/10V_4C251 *E@.1U/10V_4
C220 *E@.1U/10V_4C220 *E@.1U/10V_4
C264 *E@.1U/10V_4C264 *E@.1U/10V_4
R473 I@30.1_4R473 I@30.1_4
C277 *E@.1U/10V_4C277 *E@.1U/10V_4
R203 I@10K_4R203 I@10K_4
C245 *E@.1U/10V_4C245 *E@.1U/10V_4
C274 *E@.1U/10V_4C274 *E@.1U/10V_4
C250 *E@.1U/10V_4C250 *E@.1U/10V_4
R205 75_4R205 75_4
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ0
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS2
M_A_DQS1
M_A_DQS0
M_A_DQS4
M_A_DQS3
M_A_DQS5
M_A_DQS7
M_A_DQS6
M_A_DQS#0
M_A_DQS#3
M_A_DQS#2
M_A_DQS#1
M_A_DQS#5
M_A_DQS#4
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A7
M_A_A5
M_A_A6
M_A_A4
M_A_A10
M_A_A11
M_A_A12
M_A_A8
M_A_A9
M_A_A13
M_A_A14
M_B_DQ38
M_B_DQ18
M_B_DQ58
M_B_DQ19
M_B_DQ39
M_B_DQ59
M_B_DQ20
M_B_DQ40
M_B_DQ1
M_B_DQ60
M_B_DQ21
M_B_DQ41
M_B_DQ61
M_B_DQ22
M_B_DQ42
M_B_DQ2
M_B_DQ62
M_B_DQ23
M_B_DQ43
M_B_DQ3
M_B_DQ63
M_B_DQ24
M_B_DQ44
M_B_DQ4
M_B_DQ25
M_B_DQ45
M_B_DQ5
M_B_DQ0
M_B_DQ26
M_B_DQ46
M_B_DQ6
M_B_DQ27
M_B_DQ47
M_B_DQ7
M_B_DQ28
M_B_DQ48
M_B_DQ8
M_B_DQ29
M_B_DQ9
M_B_DQ49
M_B_DQ30
M_B_DQ10
M_B_DQ50
M_B_DQ31
M_B_DQ11
M_B_DQ51
M_B_DQ32
M_B_DQ12
M_B_DQ52
M_B_DQ33
M_B_DQ13
M_B_DQ53
M_B_DQ34
M_B_DQ14
M_B_DQ54
M_B_DQ35
M_B_DQ15
M_B_DQ55
M_B_DQ36
M_B_DQ16
M_B_DQ56
M_B_DQ37
M_B_DQ17
M_B_DQ57
M_B_A7
M_B_DQS#2
M_B_A8
M_B_DQS#3
M_B_A0
M_B_A9
M_B_DQS#4
M_B_A10
M_B_DQS#5
M_B_DM4
M_B_A11
M_B_DQS#6
M_B_A12
M_B_DQS1
M_B_DQS#7
M_B_DM5
M_B_A13
M_B_DM6
M_B_DQS2
M_B_DM7
M_B_DM0
M_B_DQS3
M_B_A1
M_B_DQS4
M_B_DQS5
M_B_A2
M_B_DQS6
M_B_DM1
M_B_A3
M_B_DQS0
M_B_DQS7
M_B_A4
M_B_A5
M_B_DM2
M_B_DQS#1
M_B_DQS#0
M_B_A6
M_B_DM3
M_B_A14
M_A_DQ[63:0]<16,17>
M_A_BS0 <16,17>
M_A_DM[7:0] <16,17>
M_A_DQS[7:0] <16,17>
M_A_DQS#[7:0] <16,17>
M_A_A[14:0] <16,17>
M_A_RAS# <16,17>
M_A_CAS# <16,17>
M_A_WE# <16,17>
M_B_DQ[63:0]<16,17>
M_B_BS0 <16,17>
M_B_DM[7:0] <16,17>
M_B_DQS[7:0] <16,17>
M_B_DQS#[7:0] <16,17>
M_B_A[14:0] <16,17>
M_B_RAS# <16,17>
M_B_CAS# <16,17>
M_B_WE# <16,17>
M_A_BS1 <16,17>
M_A_BS2 <16,17>
M_B_BS1 <16,17>
M_B_BS2 <16,17>
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH DDRII
1A
840Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH DDRII
1A
840Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH DDRII
1A
840Thursday, August 28, 2008
ZY2 & ZY6
SB_DQ_0
AK47
SB_DQ_1
AH46
SB_DQ_10
BA48
SB_DQ_11
AY48
SB_DQ_12
AT47
SB_DQ_13
AR47
SB_DQ_14
BA47
SB_DQ_15
BC47
SB_DQ_16
BC46
SB_DQ_17
BC44
SB_DQ_18
BG43
SB_DQ_19
BF43
SB_DQ_2
AP47
SB_DQ_20
BE45
SB_DQ_21
BC41
SB_DQ_22
BF40
SB_DQ_23
BF41
SB_DQ_24
BG38
SB_DQ_25
BF38
SB_DQ_26
BH35
SB_DQ_27
BG35
SB_DQ_28
BH40
SB_DQ_29
BG39
SB_DQ_3
AP46
SB_DQ_30
BG34
SB_DQ_31
BH34
SB_DQ_32
BH14
SB_DQ_33
BG12
SB_DQ_34
BH11
SB_DQ_35
BG8
SB_DQ_36
BH12
SB_DQ_37
BF11
SB_DQ_38
BF8
SB_DQ_39
BG7
SB_DQ_4
AJ46
SB_DQ_40
BC5
SB_DQ_41
BC6
SB_DQ_42
AY3
SB_DQ_43
AY1
SB_DQ_44
BF6
SB_DQ_45
BF5
SB_DQ_46
BA1
SB_DQ_47
BD3
SB_DQ_48
AV2
SB_DQ_49
AU3
SB_DQ_5
AJ48
SB_DQ_50
AR3
SB_DQ_51
AN2
SB_DQ_52
AY2
SB_DQ_53
AV1
SB_DQ_54
AP3
SB_DQ_55
AR1
SB_DQ_56
AL1
SB_DQ_57
AL2
SB_DQ_58
AJ1
SB_DQ_59
AH1
SB_DQ_6
AM48
SB_DQ_60
AM2
SB_DQ_61
AM3
SB_DQ_62
AH3
SB_DQ_63
AJ3
SB_DQ_7
AP48
SB_DQ_8
AU47
SB_DQ_9
AU46
SB_BS_0
BC16
SB_BS_1
BB17
SB_BS_2
BB33
SB_CAS#
BG16
SB_DM_0
AM47
SB_DM_1
AY47
SB_DM_2
BD40
SB_DM_3
BF35
SB_DM_4
BG11
SB_DM_5
BA3
SB_DM_6
AP1
SB_DM_7
AK2
SB_DQS_0
AL47
SB_DQS_1
AV48
SB_DQS_2
BG41
SB_DQS_3
BG37
SB_DQS_4
BH9
SB_DQS_5
BB2
SB_DQS_6
AU1
SB_DQS_7
AN6
SB_DQS#_0
AL46
SB_DQS#_1
AV47
SB_DQS#_2
BH41
SB_DQS#_3
BH37
SB_DQS#_4
BG9
SB_DQS#_5
BC2
SB_DQS#_6
AT2
SB_DQS#_7
AN5
SB_MA_0
AV17
SB_MA_1
BA25
SB_MA_10
BB16
SB_MA_11
AW33
SB_MA_12
AY33
SB_MA_13
BH15
SB_MA_2
BC25
SB_MA_3
AU25
SB_MA_4
AW25
SB_MA_5
BB28
SB_MA_6
AU28
SB_MA_7
AW28
SB_MA_8
AT33
SB_MA_9
BD33
SB_MA_14
AU33
SB_RAS#
AU17
SB_WE#
BF14
DDR SYSTEM MEMORY B
U38E
SP@CANTIGA_1p2
DDR SYSTEM MEMORY B
U38E
SP@CANTIGA_1p2
SA_DQ_0
AJ38
SA_DQ_1
AJ41
SA_DQ_10
AU40
SA_DQ_11
AT38
SA_DQ_12
AN41
SA_DQ_13
AN39
SA_DQ_14
AU44
SA_DQ_15
AU42
SA_DQ_16
AV39
SA_DQ_17
AY44
SA_DQ_18
BA40
SA_DQ_19
BD43
SA_DQ_2
AN38
SA_DQ_20
AV41
SA_DQ_21
AY43
SA_DQ_22
BB41
SA_DQ_23
BC40
SA_DQ_24
AY37
SA_DQ_25
BD38
SA_DQ_26
AV37
SA_DQ_27
AT36
SA_DQ_28
AY38
SA_DQ_29
BB38
SA_DQ_3
AM38
SA_DQ_30
AV36
SA_DQ_31
AW36
SA_DQ_32
BD13
SA_DQ_33
AU11
SA_DQ_34
BC11
SA_DQ_35
BA12
SA_DQ_36
AU13
SA_DQ_37
AV13
SA_DQ_38
BD12
SA_DQ_39
BC12
SA_DQ_4
AJ36
SA_DQ_40
BB9
SA_DQ_41
BA9
SA_DQ_42
AU10
SA_DQ_43
AV9
SA_DQ_44
BA11
SA_DQ_45
BD9
SA_DQ_46
AY8
SA_DQ_47
BA6
SA_DQ_48
AV5
SA_DQ_49
AV7
SA_DQ_5
AJ40
SA_DQ_50
AT9
SA_DQ_51
AN8
SA_DQ_52
AU5
SA_DQ_53
AU6
SA_DQ_54
AT5
SA_DQ_55
AN10
SA_DQ_56
AM11
SA_DQ_57
AM5
SA_DQ_58
AJ9
SA_DQ_59
AJ8
SA_DQ_6
AM44
SA_DQ_60
AN12
SA_DQ_61
AM13
SA_DQ_62
AJ11
SA_DQ_63
AJ12
SA_DQ_7
AM42
SA_DQ_8
AN43
SA_DQ_9
AN44
SA_BS_0
BD21
SA_BS_1
BG18
SA_BS_2
AT25
SA_CAS#
BD20
SA_DM_0
AM37
SA_DM_1
AT41
SA_DM_2
AY41
SA_DM_3
AU39
SA_DM_4
BB12
SA_DM_5
AY6
SA_DM_6
AT7
SA_DQS_0
AJ44
SA_DQS_1
AT44
SA_DQS_2
BA43
SA_DQS_3
BC37
SA_DQS_4
AW12
SA_DQS_5
BC8
SA_DQS_6
AU8
SA_DQS_7
AM7
SA_DM_7
AJ5
SA_DQS#_0
AJ43
SA_DQS#_1
AT43
SA_DQS#_2
BA44
SA_DQS#_3
BD37
SA_DQS#_4
AY12
SA_DQS#_5
BD8
SA_DQS#_6
AU9
SA_DQS#_7
AM8
SA_MA_0
BA21
SA_MA_1
BC24
SA_MA_10
BC21
SA_MA_11
BG26
SA_MA_12
BH26
SA_MA_13
BH17
SA_MA_2
BG24
SA_MA_3
BH24
SA_MA_4
BG25
SA_MA_5
BA24
SA_MA_6
BD24
SA_MA_7
BG27
SA_MA_8
BF25
SA_MA_9
AW24
SA_RAS#
BB20
SA_WE#
AY20
SA_MA_14
AY25
DDR SYSTEM MEMORY A
U38D
SP@CANTIGA_1p2
DDR SYSTEM MEMORY A
U38D
SP@CANTIGA_1p2
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF6
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF7
VCC_SM_LF1
+1.05V
+1.05V_AXG
+1.05V_AXG
+1.05V
+1.05V_AXG
+1.05V_AXG
+1.05V +1.05V_AXG
+VDR_SUS
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VCC,NCTF
1A
940Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VCC,NCTF
1A
940Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VCC,NCTF
1A
940Thursday, August 28, 2008
ZY2 & ZY6
VCC_SM(1.8V)
DDR2(800M)
3000mA_S0 , 1mA_S3
DDR2(667M) : 2600mA_S0
DDR3(1067M) : 4140mA_S0
1.05V
Graphics core
VCC_AXG
VCC_AXG_NCTF
6326.84mA
VCC
VCC_NCTF
1210.34mA_EV
1930.4mA_IV
ME Engine
508.12mA
Total Max=2438.52mA
Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10
1.8V
Internal connect to power
Intel check list(Rev 0.8)
270U*1 near to power(+V1.05M).
270U*2 near to NB
Intel CRB(Rev 0.7)
270U*3 near to power(+V1.05M).
270U*1 near to NB
ESR=12m ohm
Place close to
the GMCH
Voltage regulator is
shared between the
Graphics Core Rail,
VCCA_HPLL, VCCA_MPLL,
VCCA_PEG_PLLVCCD_PEG_PLL,
VCCA_SM_CK, VCCA_DPLLA,
VCCA_DPLLB, VCCD_HPLL,
VCCA_SM, VCC_AXF
Place close to the GMCH Cavity Capacitors
Intel check list(Rev 0.8)
220U*2 near to NB(ESR=15m ohm)
Intel CRB(Rev 0.7)
270U*4 near to power(+V1.05S).
330U*2 near to NB
Design guide(Table 72)
For INT VGA diasble.VCC_AXG power can connect to GND
IV&EV Dis/Enablesetting
GM TDP 10.5~12W
GS TDP 7~8W
PM TDP 7W
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially
2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest
Intel check list(Rev 0.8)
No description for VCC_SM bulk CAP
Intel CRB(Rev 0.7)
330U*1 Reserve near to power
330U*1 near to NB
Place on the edga
SP@:INT 1 U
EXT 0 ohm
C238
.47U/6V_4
C238
.47U/6V_4
C266
1U/6V_4
C266
1U/6V_4
C237
SP@0_6
C237
SP@0_6
C217
I@10U/10V_8
C217
I@10U/10V_8
R242 I@10/F_4R242 I@10/F_4
R227 I@0_8R227 I@0_8
C244
0.1U/10V_4
C244
0.1U/10V_4
C258
1U/6V_4
C258
1U/6V_4
+
C192
I@330U/2.5V_7343
+
C192
I@330U/2.5V_7343
+
C191
I@330U/2.5V_7343
+
C191
I@330U/2.5V_7343
C247
I@.1U/10V_4
C247
I@.1U/10V_4
C203
I@.1U/10V_4
C203
I@.1U/10V_4
C521
22U/6V_8
C521
22U/6V_8
VCC_NCTF_1
AM32
VCC_NCTF_20
AC30
VCC_NCTF_29
AJ29
VCC_NCTF_42
AK25
VCC_NCTF_9
AA32
VCC_NCTF_10
Y32
VCC_NCTF_11
W32
VCC_NCTF_12
U32
VCC_NCTF_13
AM30
VCC_NCTF_14
AL30
VCC_NCTF_15
AK30
VCC_NCTF_17
AG30
VCC_NCTF_18
AF30
VCC_NCTF_19
AE30
VCC_NCTF_2
AL32
VCC_NCTF_24
W30
VCC_NCTF_25
V30
VCC_NCTF_3
AK32
VCC_NCTF_30
AH29
VCC_NCTF_31
AG29
VCC_NCTF_32
AE29
VCC_NCTF_38
AL28
VCC_NCTF_39
AK28
VCC_NCTF_40
AL26
VCC_NCTF_41
AK26
VCC_NCTF_4
AJ32
VCC_NCTF_43
AK24
VCC_NCTF_5
AH32
VCC_NCTF_6
AG32
VCC_NCTF_7
AE32
VCC_NCTF_8
AC32
VCC_NCTF_33
AC29
VCC_NCTF_34
AA29
VCC_NCTF_35
Y29
VCC_NCTF_36
W29
VCC_NCTF_37
V29
VCC_NCTF_26
U30
VCC_NCTF_27
AL29
VCC_NCTF_28
AK29
VCC_NCTF_16
AH30
VCC_NCTF_21
AB30
VCC_NCTF_22
AA30
VCC_NCTF_23
Y30
VCC_1
AG34
VCC_2
AC34
VCC_3
AB34
VCC_4
AA34
VCC_5
Y34
VCC_6
V34
VCC_7
U34
VCC_8
AM33
VCC_9
AK33
VCC_10
AJ33
VCC_11
AG33
VCC_12
AF33
VCC_13
AE33
VCC_14
AC33
VCC_15
AA33
VCC_16
Y33
VCC_17
W33
VCC_18
V33
VCC_19
U33
VCC_20
AH28
VCC_21
AF28
VCC_22
AC28
VCC_23
AA28
VCC_24
AJ26
VCC_25
AG26
VCC_26
AE26
VCC_27
AC26
VCC_28
AH25
VCC_29
AG25
VCC_30
AF25
VCC_31
AG24
VCC_32
AJ23
VCC_33
AH23
VCC_34
AF23
VCC_35
T32
VCC_NCTF_44
AK23
POWER
VCC NCTF
VCC CORE
U38F
SP@CANTIGA_1p2
POWER
VCC NCTF
VCC CORE
U38F
SP@CANTIGA_1p2
C255
.22U/6V_4
C255
.22U/6V_4
C200
I@.47U/6V_4
C200
I@.47U/6V_4
C201
I@22U/6V_8
C201
I@22U/6V_8
C210
22U/6V_8
C210
22U/6V_8
C519
22U/6V_8
C519
22U/6V_8
+
C524
330U/2V_7
+
C524
330U/2V_7
C231
.1U/10V_4
C231
.1U/10V_4
R238 I@10/F_4R238 I@10/F_4
R228 I@0_8R228 I@0_8
+
C518
330U/2V_7
+
C518
330U/2V_7
C226
.22U/6V_4
C226
.22U/6V_4
C253
.22U/6V_4
C253
.22U/6V_4
C225
.22U/6V_4
C225
.22U/6V_4
VCC_SM_10
AY32
VCC_SM_20
BF31
VCC_SM_30
AW29
VCC_SM_6
BD32
VCC_SM_7
BC32
VCC_SM_8
BB32
VCC_SM_9
BA32
VCC_SM_11
AW32
VCC_SM_12
AV32
VCC_SM_13
AU32
VCC_SM_14
AT32
VCC_SM_15
AR32
VCC_SM_16
AP32
VCC_SM_17
AN32
VCC_SM_18
BH31
VCC_SM_19
BG31
VCC_SM_2
AN33
VCC_SM_21
BG30
VCC_SM_22
BH29
VCC_SM_23
BG29
VCC_SM_24
BF29
VCC_SM_25
BD29
VCC_SM_26
BC29
VCC_SM_27
BB29
VCC_SM_28
BA29
VCC_SM_29
AY29
VCC_SM_3
BH32
VCC_SM_31
AV29
VCC_SM_32
AU29
VCC_SM_33
AT29
VCC_SM_34
AR29
VCC_AXG_NCTF_10
V23
VCC_AXG_NCTF_11
AM21
VCC_AXG_NCTF_12
AL21
VCC_AXG_NCTF_13
AK21
VCC_AXG_NCTF_14
W21
VCC_AXG_NCTF_15
V21
VCC_AXG_NCTF_16
U21
VCC_AXG_NCTF_17
AM20
VCC_AXG_NCTF_18
AK20
VCC_AXG_NCTF_19
W20
VCC_AXG_NCTF_2
V28
VCC_AXG_NCTF_20
U20
VCC_AXG_NCTF_21
AM19
VCC_AXG_NCTF_22
AL19
VCC_AXG_NCTF_23
AK19
VCC_AXG_NCTF_24
AJ19
VCC_AXG_NCTF_25
AH19
VCC_AXG_NCTF_26
AG19
VCC_AXG_NCTF_27
AF19
VCC_AXG_NCTF_28
AE19
VCC_AXG_NCTF_29
AB19
VCC_AXG_NCTF_3
W26
VCC_AXG_NCTF_30
AA19
VCC_AXG_NCTF_31
Y19
VCC_AXG_NCTF_32
W19
VCC_AXG_NCTF_33
V19
VCC_AXG_NCTF_34
U19
VCC_AXG_NCTF_35
AM17
VCC_AXG_NCTF_36
AK17
VCC_AXG_NCTF_37
AH17
VCC_AXG_NCTF_38
AG17
VCC_AXG_NCTF_39
AF17
VCC_AXG_NCTF_4
V26
VCC_AXG_NCTF_40
AE17
VCC_AXG_NCTF_41
AC17
VCC_AXG_NCTF_42
AB17
VCC_AXG_NCTF_43
Y17
VCC_AXG_NCTF_44
W17
VCC_AXG_NCTF_45
V17
VCC_AXG_NCTF_46
AM16
VCC_AXG_NCTF_47
AL16
VCC_AXG_NCTF_48
AK16
VCC_AXG_NCTF_49
AJ16
VCC_AXG_NCTF_5
W25
VCC_AXG_NCTF_50
AH16
VCC_AXG_NCTF_51
AG16
VCC_AXG_NCTF_52
AF16
VCC_AXG_NCTF_53
AE16
VCC_AXG_NCTF_54
AC16
VCC_AXG_NCTF_55
AB16
VCC_AXG_NCTF_56
AA16
VCC_AXG_NCTF_6
V25
VCC_AXG_NCTF_7
W24
VCC_AXG_NCTF_8
V24
VCC_AXG_NCTF_9
W23
VCC_SM_35
AP29
VCC_SM_4
BG32
VCC_SM_5
BF32
VCC_AXG_NCTF_1
W28
VCC_SM_1
AP33
VCC_AXG_1
Y26
VCC_AXG_2
AE25
VCC_AXG_3
AB25
VCC_AXG_4
AA25
VCC_AXG_5
AE24
VCC_AXG_6
AC24
VCC_AXG_7
AA24
VCC_AXG_8
Y24
VCC_AXG_9
AE23
VCC_AXG_10
AC23
VCC_AXG_11
AB23
VCC_AXG_12
AA23
VCC_AXG_13
AJ21
VCC_AXG_14
AG21
VCC_AXG_15
AE21
VCC_AXG_16
AC21
VCC_AXG_17
AA21
VCC_AXG_18
Y21
VCC_AXG_19
AH20
VCC_AXG_20
AF20
VCC_AXG_21
AE20
VCC_AXG_22
AC20
VCC_AXG_23
AB20
VCC_AXG_24
AA20
VCC_AXG_25
T17
VCC_AXG_27
AM15
VCC_AXG_28
AL15
VCC_AXG_30
AJ15
VCC_AXG_31
AH15
VCC_AXG_33
AF15
VCC_AXG_34
AB15
VCC_SM_LF1
AV44
VCC_SM_LF2
BA37
VCC_SM_LF3
AM40
VCC_SM_LF4
AV21
VCC_SM_LF5
AY5
VCC_SM_LF6
AM10
VCC_SM_LF7
BB13
VCC_AXG_26
T16
VCC_AXG_32
AG15
VCC_AXG_35
AA15
VCC_AXG_36
Y15
VCC_AXG_37
V15
VCC_AXG_38
U15
VCC_AXG_39
AN14
VCC_AXG_40
AM14
VCC_AXG_41
U14
VCC_AXG_42
T14
VCC_AXG_SENSE
AJ14
VSS_AXG_SENSE
AH14
VCC_AXG_NCTF_57
Y16
VCC_AXG_NCTF_58
W16
VCC_AXG_NCTF_59
V16
VCC_AXG_NCTF_60
U16
VCC_SM_36/NC
BA36
VCC_SM_37/NC
BB24
VCC_SM_38/NC
BD16
VCC_SM_39/NC
BB21
VCC_SM_40/NC
AW16
VCC_SM_41/NC
AW13
VCC_SM_42/NC
AT13
VCC_AXG_29
AE15
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC SM LF
U38G
SP@CANTIGA_1p2
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC SM LF
U38G
SP@CANTIGA_1p2
C239
.1U/10V_4
C239
.1U/10V_4
C268
.1U/10V_4
C268
.1U/10V_4
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3V_A_DAC_BG
+3V_A_CRT_DAC
+1.05VM_DPLLA
+1.05VM_DPLLB
+1.05VM_MCH_PLL2
+VCCA_PEG_BG
+1.05VM_PEGPLL
+1.05VM_MPLL_RC
+1.05VM_HPLL
+1.05VM_MPLL
+1.5V_TVDAC
+1.5V_QDAC
+1.05VM_MCH_PLL2
+1.05VM_PEGPLL
+VCC_HDA
+1.8VSUS_DLVDS
+1.8VSU S_TXLVDS
+1.05VM_PEGPLL_RC
+1.8VSU S_TXLVDS
+1.8VSUS_VCC_SM_CK
+1.8VSUS_SMCK_RC
+1.05VM_AXF
+1.05V_SD
+3V_TV_DAC
+1.05VM_A_SM_CK
+1.05VM_A_SM
+3V
+1.5V
+1.05V
+1.05V
+1.8V
+3V
+1.5V
+1.05V
+1.5V
+1.05V
+1.8V
+VDR_SUS
+1.05V
+1.05V
+1.05V
+1.05V
+1.05V
+3V
+1.05V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH POWER
1A
10 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH POWER
1A
10 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH POWER
1A
10 40Thursday, August 28, 2008
ZY2 & ZY6
1.05V
FSB-1067
852mA
1.05V
321.35mA
1.8V
DDR2-800
124mA
1.8V
118.8mA
3.3V
105.3mA
1.05V
456mA
3.3V
73mA
3.3V
2.68mA
1.05V
24mA
1.05V
139.2mA
1.05V
64.8mA for A/B
1.8V
13.2mA
1.5V
414uA
1.05V
50mA
1.05V
DDR2-800
720mA
1.05V
DDR2-800
26mA
1.5V
58.67mA
1.5V
48.363mA for CRT
5mA for TV
1.05V
157.2mA
1.05V
50mA
1.8V
60.31mA
Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10
1.05V
Internal connect to power
1.5V
50mA
3.3V
24.15mA for VCCA_TVA_DAC
39.48mA for VCCA_TVB_DAC
24.15mA for VCCA_TVC_DAC
Total 87.78mA
VCCD_QDAC share to TV and CRT
FB 180@100 MHz, 25% 1.5A
DCR_max=90 m
CRB no 10U
Check list need min 10U~100U for VCCA_TV_DAC
FB 180@100 MHz, 25% 1.5A
DCR_max=90 m
CRB no 10U
Check list need min 10U~100U
for VCCA_QDAC
IV&EV Dis/Enablesetting
IV&EV Dis/Enablesetting
Design guide table 72
VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V
Design guide Table 72
1210 10UH, 10%
0.45A DCR_max = 0.39
ESR=15 m
ESR=15 m
1210 10UH, 10%
0.45A DCR_max = 0.39
Design guide table 72
VCCA_DPLLA/B always keep to +1.05V(If no use IV dynamic core power)
0805 100 nH, DCR=160 m
IV&EV Dis/Enablesetting
IV&EV Dis/Enablesetting
IV&EV Dis/Enablesetting
ESR= 12m ohm
ESR = 60 m
Check list : 0.1UH
CRB : 0 ohm
1210 0.1 ?H, 20% 1A
DCR max = 78 m
0805 1UH , Rdc = 0.14 - 0.26.
Max rated current = 220 mA
1210 0.1uH, 20%, 1A,
DCR_max=0.078
3.9 nH, 0.2 nH, 1A
, DCR_max=32 m
FB 220 @100 MHz, 25%, 2A
ESR=60m ohm
VCCA_PEG_PLL
+1.25V for Teenah use(100mA)
Power Net Name
VCCA_PEG_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_SM_#
VCCA_HPLL
VCCA_MPLL
VCCA_SM_CK_#
VCCA_PEG_PLL
VCC_AXF_#
VCCD_HPLL
VCCD_PEG_PLL
Cantiga(V)
1.5V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
Tennah(V)
3.3V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
Tennah Current
400uA
100mA
100mA
1065mA
50mA
150mA
35mA
100mA
495mA
250mA
100mA
CRB : 0 ohm
Check list : 2.2nH
Power Rail Differences between
the Teenah and Cantiga Chipset Family
VCC_AXG_#
VCC_AXG_NCTF_#
1.05V 1.25V 6326.84mA
Cantiga use
External Graphics
(GMCH Integrated Graphics Disable)
VCC_TX_LVDS
VCCA_LVDS
VCCA_TVDAC
VCCD_QDAC
VCCSYNC_CRT
VCCA_CRT_DAC
VCCD_LVDS
VCCA_DAC_BG
VCC_AXG
VCC_AXG_NCTF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.05V
1782mA
ESL=2.4 nH
ESR =15 m
SP@:INT 0.01U
EXT 0 ohm
SP@:INT 0.01U
EXT 0 ohm
SP@:INT 0.1U
EXT 0 ohm
SP@:INT 0.01U
EXT 0 ohm
SP@:INT 1 U
EXT 0 ohm
SP@:INT 1000 P
EXT 0 ohm
SP@:INT 0.1U
EXT 0 ohm
C545
1U/6V_4
C545
1U/6V_4
C525
22U/6V_8
C525
22U/6V_8
C211
.47U/6V_4
C211
.47U/6V_4
C549
I@10U/6.3V_8
C549
I@10U/6.3V_8
C221
.1U/10V_4
C221
.1U/10V_4
C183
.01U/16V_4
C183
.01U/16V_4
C531
.1U/10V_4
C531
.1U/10V_4
C533
SP@.1U/10V_4
C533
SP@.1U/10V_4
R462 0_8R462 0_8
C530
4.7U/10V_6
C530
4.7U/10V_6
C198
.47U/6V_4
C198
.47U/6V_4
R4551/F_4 R4551/F_4
C542
I@.1U/10V_4
C542
I@.1U/10V_4
C234
.1U/10V_4
C234
.1U/10V_4
C223
.1U/10V_4
C223
.1U/10V_4
C199
4.7U/10V_6
C199
4.7U/10V_6
R240 0_6R240 0_6
C529
.1U/10V_4
C529
.1U/10V_4
C534
.47U/6V_4
C534
.47U/6V_4
L42 1UH_8L42 1UH_8
L44 I@10UH_8L44 I@10UH_8
R234 0.5/F_6R234 0.5/F_6
C528
.1U/10V_4
C528
.1U/10V_4
L45 I@0.1UH_1.5L45 I@0.1UH_1.5
R463 1/F_4R463 1/F_4
L46 1UH_8L46 1UH_8
C229
4.7U/10V_6
C229
4.7U/10V_6
VTT_19
V3
VTT_20
U3
VTT_21
V2
VTT_22
U2
VCCA_PEG_BG
AD48
VCCA_PEG_PLL
AA48
VCCA_CRT_DAC_1
B27
VCCA_CRT_DAC_2
A26
VCCA_DPLLA
F47
VCCA_DPLLB
L48
VCCA_HPLL
AD1
VCCA_LVDS
J48
VCCA_MPLL
AE1
VCCA_TV_DAC_1
B24
VCCA_TV_DAC_2
A24
VCCD_PEG_PLL
AA47
VTT_15
U6
VTT_16
T6
VTT_17
U5
VTT_18
T5
VTT_12
T8
VTT_13
U7
VTT_14
T7
VCCD_HPLL
AF1
VTT_1
U13
VTT_2
T13
VTT_4
T12
VTT_5
U11
VTT_6
T11
VTT_7
U10
VTT_8
T10
VTT_9
U9
VTT_10
T9
VTT_11
U8
VTT_3
U12
VCCA_SM_CK_1
AP28
VCCA_SM_CK_2
AN28
VCCA_DAC_BG
A25
VCCD_TVDAC
M25
VTTLF1
A8
VTTLF2
L1
VTTLF3
AB2
VCC_DMI_1
AH48
VCC_DMI_2
AF48
VCC_SM_CK_1
BF21
VCC_SM_CK_2
BH20
VCC_SM_CK_3
BG20
VCC_SM_CK_4
BF20
VCCD_LVDS_1
M38
VCCD_QDAC
L28
VCC_AXF_1
B22
VCC_AXF_2
B21
VCC_AXF_3
A21
VCCA_SM_1
AR20
VCCA_SM_2
AP20
VCCA_SM_3
AN20
VCCA_SM_4
AR17
VCCA_SM_5
AP17
VCCA_SM_7
AT16
VCCA_SM_8
AR16
VCCA_SM_9
AP16
VCC_TX_LVDS
K47
VSSA_LVDS
J47
VCC_HV_1
C35
VCC_HV_2
B35
VCC_PEG_1
V48
VCCD_LVDS_2
L37
VCC_PEG_2
U48
VCC_PEG_3
V47
VCC_PEG_4
U47
VCC_PEG_5
U46
VCCA_SM_6
AN17
VCCA_SM_CK_3
AP25
VCCA_SM_CK_4
AN25
VCCA_SM_CK_5
AN24
VCCA_SM_CK_NCTF_1
AM28
VCCA_SM_CK_NCTF_2
AM26
VCCA_SM_CK_NCTF_3
AM25
VCCA_SM_CK_NCTF_4
AL25
VCCA_SM_CK_NCTF_5
AM24
VCCA_SM_CK_NCTF_6
AL24
VCCA_SM_CK_NCTF_7
AM23
VTT_23
T2
VTT_24
V1
VTT_25
U1
VCC_HV_3
A35
VCC_DMI_3
AH47
VCC_DMI_4
AG47
VSSA_DAC_BG
B25
VCCA_SM_CK_NCTF_8
AL23
VCC_HDA
A32
POWER
CRTPLLA PEGASM
TV
D TV/CRT
LVDS
VTTLF
PEG
SM CK
AXF
VTT
DMI
HV
ACK
A LVDS
HDA
U38H
SP@CANTIGA_1p2
POWER
CRTPLLA PEGASM
TV
D TV/CRT
LVDS
VTTLF
PEG
SM CK
AXF
VTT
DMI
HV
ACK
A LVDS
HDA
U38H
SP@CANTIGA_1p2
C190
4.7U/10V_6
C190
4.7U/10V_6
C543
I@.1U/10V_4
C543
I@.1U/10V_4
C522
.1U/10V_4
C522
.1U/10V_4
C175
SP@0_4
C175
SP@0_4
C541
SP@0_4
C541
SP@0_4
C540
SP@0_4
C540
SP@0_4
L43 BLM18PG181SN1D_6L43 BLM18PG181SN1D_6
R241 0_6R241 0_6 C536
I@22U/6V_8
C536
I@22U/6V_8
+
C550
I@220U/2.5V_7343
+
C550
I@220U/2.5V_7343
C527
10U/10V_8
C527
10U/10V_8
C182
.1U/10V_4
C182
.1U/10V_4
C547
*10U/10V_8
C547
*10U/10V_8
C181
SP@0_4
C181
SP@0_4
R176 I@0_6R176 I@0_6
R179 0_6R179 0_6
C520 10U/10V_8C520 10U/10V_8
C539
.47U/6V_4
C539
.47U/6V_4
+
C535
I@220U/2.5V_7343
+
C535
I@220U/2.5V_7343
C185
.1U/10V_4
C185
.1U/10V_4
+
C532
220U/6_7343
+
C532
220U/6_7343
C184
I@.1U/10V_4
C184
I@.1U/10V_4
C193
2.2U/6V_6
C193
2.2U/6V_6
C179
SP@0_4
C179
SP@0_4
C526
.1U/10V_4
C526
.1U/10V_4
R476 I@0_6R476 I@0_6
C538
I@1000P/50V_4
C538
I@1000P/50V_4
C241
*2.2U/10V_6
C241
*2.2U/10V_6
L29 BLM18PG181SN1D_6L29 BLM18PG181SN1D_6
C243
.1U/10V_4
C243
.1U/10V_4
C187
SP@0_4
C187
SP@0_4
C544
I@.1U/10V_4
C544
I@.1U/10V_4
R244 0_6R244 0_6
21
D38 BAT54D38 BAT54
L47 I@BLM18PG181SN1D_6L47 I@BLM18PG181SN1D_6
L48 I@10UH_8L48 I@10UH_8
C227
22U/6V_8
C227
22U/6V_8
C248
22U/6V_8
C248
22U/6V_8
C546
SP@0_4
C546
SP@0_4
+
C180
330U/2.5V_7
+
C180
330U/2.5V_7
C537
SP@1000P/50V_4
C537
SP@1000P/50V_4
L49 I@BLM18PG181SN1D_6L49 I@BLM18PG181SN1D_6
R245 0_6R245 0_6
C246
4.7U/10V_6
C246
4.7U/10V_6
C240
1U/6V_4
C240
1U/6V_4
R489 10_4R489 10_4
R486 I@0_6R486 I@0_6
C548
10U/6.3V_8
C548
10U/6.3V_8
R480 I@0_6R480 I@0_6
C235
22U/6V_8
C235
22U/6V_8
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VSS
1A
11 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VSS
1A
11 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
GMCH VSS
1A
11 40Thursday, August 28, 2008
ZY2 & ZY6
VSS_1
AU48
VSS_198
A23
VSS_2
AR48
VSS_3
AL48
VSS_4
BB47
VSS_5
AW47
VSS_6
AN47
VSS_7
AJ47
VSS_8
AF47
VSS_9
AD47
VSS_10
AB47
VSS_11
Y47
VSS_12
T47
VSS_13
N47
VSS_14
L47
VSS_15
G47
VSS_16
BD46
VSS_17
BA46
VSS_19
AV46
VSS_20
AR46
VSS_21
AM46
VSS_22
V46
VSS_23
R46
VSS_24
P46
VSS_25
H46
VSS_26
F46
VSS_27
BF44
VSS_28
AH44
VSS_29
AD44
VSS_30
AA44
VSS_31
Y44
VSS_32
U44
VSS_33
T44
VSS_34
M44
VSS_35
F44
VSS_36
BC43
VSS_37
AV43
VSS_38
AU43
VSS_39
AM43
VSS_40
J43
VSS_41
C43
VSS_42
BG42
VSS_43
AY42
VSS_44
AT42
VSS_45
AN42
VSS_46
AJ42
VSS_47
AE42
VSS_48
N42
VSS_49
L42
VSS_50
BD41
VSS_51
AU41
VSS_52
AM41
VSS_53
AH41
VSS_54
AD41
VSS_55
AA41
VSS_56
Y41
VSS_57
U41
VSS_58
T41
VSS_59
M41
VSS_60
G41
VSS_61
B41
VSS_62
BG40
VSS_63
BB40
VSS_64
AV40
VSS_65
AN40
VSS_66
H40
VSS_67
E40
VSS_68
AT39
VSS_69
AM39
VSS_70
AJ39
VSS_71
AE39
VSS_72
N39
VSS_73
L39
VSS_74
B39
VSS_75
BH38
VSS_76
BC38
VSS_77
BA38
VSS_78
AU38
VSS_79
AH38
VSS_80
AD38
VSS_81
AA38
VSS_82
Y38
VSS_83
U38
VSS_84
T38
VSS_85
J38
VSS_86
F38
VSS_87
C38
VSS_97
BD36
VSS_100
AM36
VSS_101
AE36
VSS_102
P36
VSS_103
L36
VSS_104
J36
VSS_105
F36
VSS_106
B36
VSS_107
AH35
VSS_108
AA35
VSS_109
Y35
VSS_110
U35
VSS_111
T35
VSS_112
BF34
VSS_113
AM34
VSS_114
AJ34
VSS_115
AF34
VSS_116
AE34
VSS_117
W34
VSS_118
B34
VSS_119
A34
VSS_120
BG33
VSS_121
BC33
VSS_122
BA33
VSS_123
AV33
VSS_124
AR33
VSS_125
AL33
VSS_126
AH33
VSS_127
AB33
VSS_128
P33
VSS_129
L33
VSS_130
H33
VSS_131
N32
VSS_132
K32
VSS_133
F32
VSS_134
C32
VSS_135
A31
VSS_136
AN29
VSS_137
T29
VSS_138
N29
VSS_139
K29
VSS_140
H29
VSS_141
F29
VSS_142
A29
VSS_143
BG28
VSS_144
BD28
VSS_145
BA28
VSS_146
AV28
VSS_147
AT28
VSS_148
AR28
VSS_149
AJ28
VSS_150
AG28
VSS_151
AE28
VSS_152
AB28
VSS_153
Y28
VSS_154
P28
VSS_155
K28
VSS_156
H28
VSS_157
F28
VSS_158
C28
VSS_159
BF26
VSS_160
AH26
VSS_161
AF26
VSS_162
AB26
VSS_163
AA26
VSS_164
C26
VSS_165
B26
VSS_166
BH25
VSS_167
BD25
VSS_168
BB25
VSS_169
AV25
VSS_170
AR25
VSS_171
AJ25
VSS_172
AC25
VSS_173
Y25
VSS_174
N25
VSS_175
L25
VSS_176
J25
VSS_177
G25
VSS_178
E25
VSS_179
BF24
VSS_88
BF37
VSS_89
BB37
VSS_90
AW37
VSS_91
AT37
VSS_92
AN37
VSS_93
AJ37
VSS_94
H37
VSS_95
C37
VSS_96
BG36
VSS_99
AU36
VSS_182
AT24
VSS_184
AH24
VSS_186
AB24
VSS_188
L24
VSS_18
AY46
VSS_191
G24
VSS_193
E24
VSS_195
AG23
VSS_197
B23
VSS_181
AY24
VSS_183
AJ24
VSS_185
AF24
VSS_187
R24
VSS_189
K24
VSS_190
J24
VSS_192
F24
VSS_194
BH23
VSS_196
Y23
VSS_98
AK15
VSS_180
AD12
VSS
U38I
SP@CANTIGA_1p2
VSS
U38I
SP@CANTIGA_1p2
VSS_199
BG21
VSS_201
AW21
VSS_202
AU21
VSS_203
AP21
VSS_204
AN21
VSS_205
AH21
VSS_206
AF21
VSS_207
AB21
VSS_208
R21
VSS_209
M21
VSS_210
J21
VSS_211
G21
VSS_212
BC20
VSS_213
BA20
VSS_214
AW20
VSS_215
AT20
VSS_216
AJ20
VSS_217
AG20
VSS_218
Y20
VSS_219
N20
VSS_220
K20
VSS_221
F20
VSS_222
C20
VSS_223
A20
VSS_224
BG19
VSS_225
A18
VSS_226
BG17
VSS_227
BC17
VSS_228
AW17
VSS_229
AT17
VSS_230
R17
VSS_231
M17
VSS_232
H17
VSS_233
C17
VSS_235
BA16
VSS_237
AU16
VSS_238
AN16
VSS_239
N16
VSS_240
K16
VSS_241
G16
VSS_242
E16
VSS_243
BG15
VSS_245
W15
VSS_246
A15
VSS_247
BG14
VSS_248
AA14
VSS_249
C14
VSS_250
BG13
VSS_251
BC13
VSS_252
BA13
VSS_255
AN13
VSS_256
AJ13
VSS_257
AE13
VSS_258
N13
VSS_259
L13
VSS_260
G13
VSS_261
E13
VSS_262
BF12
VSS_263
AV12
VSS_264
AT12
VSS_265
AM12
VSS_266
AA12
VSS_267
J12
VSS_268
A12
VSS_269
BD11
VSS_270
BB11
VSS_271
AY11
VSS_272
AN11
VSS_273
AH11
VSS_275
Y11
VSS_276
N11
VSS_277
G11
VSS_278
C11
VSS_279
BG10
VSS_280
AV10
VSS_281
AT10
VSS_282
AJ10
VSS_283
AE10
VSS_284
AA10
VSS_293
BH8
VSS_292
B9
VSS_291
G9
VSS_290
AD9
VSS_289
AM9
VSS_288
AN9
VSS_287
BC9
VSS_285
M10
VSS_286
BF9
VSS_297
AH8
VSS_298
Y8
VSS_299
L8
VSS_300
E8
VSS_301
B8
VSS_302
AY7
VSS_303
AU7
VSS_304
AN7
VSS_305
AJ7
VSS_306
AE7
VSS_307
AA7
VSS_308
N7
VSS_309
J7
VSS_310
BG6
VSS_311
BD6
VSS_312
AV6
VSS_313
AT6
VSS_244
AC15
VSS_314
AM6
VSS_315
M6
VSS_316
C6
VSS_317
BA5
VSS_318
AH5
VSS_319
AD5
VSS_320
Y5
VSS_321
L5
VSS_322
J5
VSS_323
H5
VSS_324
F5
VSS_325
BE4
VSS_327
BC3
VSS_328
AV3
VSS_329
AL3
VSS_NCTF_1
AF32
VSS_NCTF_2
AB32
VSS_NCTF_3
V32
VSS_NCTF_4
AJ30
VSS_NCTF_5
AM29
VSS_NCTF_6
AF29
VSS_NCTF_7
AB29
VSS_NCTF_8
U26
VSS_NCTF_9
U23
VSS_NCTF_10
AL20
VSS_NCTF_11
V20
VSS_NCTF_12
AC19
VSS_NCTF_13
AL17
VSS_NCTF_14
AJ17
VSS_NCTF_15
AA17
VSS_NCTF_16
U17
VSS_SCB_1
BH48
VSS_SCB_2
BH1
VSS_SCB_3
A48
VSS_SCB_4
C1
VSS_SCB_6
A3
NC_26
E1
NC_27
D2
NC_28
C3
NC_29
B4
NC_30
A5
NC_31
A6
NC_32
A43
NC_33
A44
NC_34
B45
NC_35
C46
NC_36
D47
NC_37
B47
NC_38
A46
NC_39
F48
NC_40
E48
NC_41
C48
NC_42
B48
VSS_330
R3
VSS_331
P3
VSS_333
BA2
VSS_336
AR2
VSS_335
AU2
VSS_337
AP2
VSS_332
F3
VSS_334
AW2
VSS_341
AE2
VSS_340
AF2
VSS_339
AH2
VSS_338
AJ2
VSS_342
AD2
VSS_343
AC2
VSS_344
Y2
VSS_345
M2
VSS_346
K2
VSS_347
AM1
VSS_348
AA1
VSS_349
P1
VSS_350
H1
VSS_294
BB8
VSS_295
AV8
VSS_296
AT8
VSS_351
U24
VSS_352
U28
VSS_353
U25
VSS_354
U29
VSS_200
L12
VSS_355
AJ6
NC_43
A47
VSS
VSS NCTF
VSS SCB
NC
U38J
SP@CANTIGA_1p2
VSS
VSS NCTF
VSS SCB
NC
U38J
SP@CANTIGA_1p2
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDA_SDOUT_R
HDA_SDIN2
HDA_SDIN3
HDA_RST#_R
HDA_SYNC_R
HDA_BIT_CLK_R
ICH_GPIO56
CLK_32KX1
CLK_32KX2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
ICH_INTVRMEN
SATA_RBIAS_PN
H_SMI#_R
H_DPRSTP#_R
H_DPSLP#_R
H_THERMTRIP_R
H_FERR#_R
H_THERMTRIP_RR
SRTC_RST#
RTC_RST#
HDA_SDOUT_R
HDA_SYNC_R
HDA_BIT_CLK_R
HDA_RST#_R
VCCRTC_1
VCCRTC_2
RTC_N03
RTC_N01
ICH_TP3
HDA_SDOUT_R
HDA_SDIN2
HDA_SDIN3
SATA_RXN0<24>
SATA_RXP0<24>
SATA_TXN0<24>
SATA_TXP0<24>
SATA_LED#<31>
ACZ_SDIN0<25>
ACZ_SDIN1<25>
LAD3 <23,32>
LAD1 <23,32>
LAD2 <23,32>
LAD0 <23,32>
LFRAME# <23,32>
GATEA20 <32>
H_IGNNE# <3>
H_STPCLK# <3>
H_NMI <3>
H_A20M# <3>
RCIN# <32>
ICH_DPRSTP# <3,6,35>
H_DPSLP# <3>
PM_THRMTRIP# <3,6>
H_INTR <3>
H_INIT# <3>
H_PWRGD <3>
H_FERR# <3>
H_SMI# <3>
ACZ_SYNC_AUDIO <25> ACZ_RST#_AUDIO <25>
BIT_CLK_AUDIO <25>
ACZ_SDOUT_AUDIO <25>
SATA_TXP4 <24>
SATA_TXN4 <24>
SATA_RXN4 <24>
SATA_RXP4 <24>
CLK_PCIE_SATA <2>
CLK_PCIE_SATA# <2>
ACZ_SDOUT_MDC <25>
ACZ_SYNC_MDC <25>
BIT_CLK_MDC <25>
ACZ_RST#_MDC <25>
SATA_RXN1<24>
SATA_RXP1<24>
SATA_TXN1<24>
SATA_TXP1<24>
ICH_TP3<14>
HDA_SDOUT_HDMI <6>
HDA_SYNC_HDMI <6>
HDA_BIT_CLK_HDMI <6>
HDA_RST#_HDMI <6>
HDA_SDIN_HDMI <6>
MXM_SDOUT_HDMI <18>
MXM_SYNC_HDMI <18>
MXM_SDIN_HDMI <18>
MXM_RST#_HDMI <18>
MXM_BIT_CLK_HDMI <18>
+VCCRTC
+1.05V
+1.05V
+3V
+3V
+1.05V
+1.5V
+VCCRTC
+5VPCU
+3VPCU
+3V_S5
+3V
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
ICH9M HOST
1A
12 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
ICH9M HOST
1A
12 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
ICH9M HOST
1A
12 40Thursday, August 28, 2008
ZY2 & ZY6
No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm)
Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm)
PU L<2"
SATABIAS L<0.5"
OC Pin need PU, ZS2 PU at LED side.
Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
Internal VRM enabled for
VccSus1_05, VccSus1_5,
VccCL1_5, VccLAN1_05 and
VccCL1_05.
Weak integrated PD on the HDA_SDOUT pin.
Weak integrated PD on the HDA_SYNC pins
24.000 MHz is output from the ICH9M.
Internal pull-down
resistors that are
always enabled
LDRQ0/1# : Internal PU
24.9 Ohm pull up to 1.5V
for GLAN_COMPI/O is
required, no matter
intel LAN is used or
not.
20MIL
20MIL
20MIL
RTC
Pin Name
0
0
01
11
Enter XOR Chain
Set PCIE port config bit 1
Normal opration(Default)
RSVD
Description
1
HDA_SDOUT
0
ICH_TP3
HDA_DOCK_EN/
GPIO33
SATALED#
TP3
HDA_SDOUT
Strap description
Sampled
Configuration PU/PD
XOR Chain Entrance
PCI Express Lane Reversal
(Lanes 1-4)
PWROK
XOR Chain Entrance /PCI Express*
Port Config 1 bit 1(Port 1-4)
Flash Descriptor Security
Override Strap
0 = The Flash Descriptor Security will be overridden.
1 = The security measures defined
in the Flash Descriptor will be in effect
Internal PU
This strap should only be enabled in manufacturing
environments using an external pull-up resistor.
PWROK
PWROK
PWROK
HD Audio
South Bridge Strap Pin (1/3)
10/16: R517 Change to E@
11/8 REV:B Y9 change footprint
11/26 REV:B C410 &C409 change to 15p
97/03/25 REV: C Change to NPO
12
G8
*SHORT_ PAD
G8
*SHORT_ PAD
R307 33_4R307 33_4
R516 *E@33_4R516 *E@33_4
R289 *I@0_4R289 *I@0_4
R439 20K_6R439 20K_6
R306 33_4R306 33_4R428 33_4R428 33_4
R294 33_4R294 33_4
R440 20K_6R440 20K_6
R285 *I@33_4R285 *I@33_4
C391
1U/6V_4
C391
1U/6V_4
1 3
2
Q28
MMBT3904
Q28
MMBT3904
R308 *I@33_4R308 *I@33_4
R406 *1K_4R406 *1K_4
R272
1K_4
R272
1K_4
T39T39
R312 0_4R312 0_4
12
G7
*SHORT_ PAD
G7
*SHORT_ PAD
R513 *E@33_4R513 *E@33_4
R297 56.2/F_4R297 56.2/F_4
C479
*10P/50V_4
C479
*10P/50V_4
R434
*56_4
R434
*56_4
C410 15P/50V_4C410 15P/50V_4
T40T40
C330
*10P/50V_4
C330
*10P/50V_4
R279 *I@33_4R279 *I@33_4
R360 1M/F_6R360 1M/F_6
R351 24.9/F_4R351 24.9/F_4
R271 16K_6R271 16K_6
R296 *0_4R296 *0_4
T65T65
R517 *E@33_4R517 *E@33_4
R368
10M_6
R368
10M_6
T38T38
R393 332K/F_4R393 332K/F_4
C314
1U/10V_4
C314
1U/10V_4
R282 33_4R282 33_4
R268
150K/F_6
R268
150K/F_6
4 1
23
Y9
32.768KHZ
Y9
32.768KHZ
C344
*10P/50V_4
C344
*10P/50V_4
C409 15P/50V_4C409 15P/50V_4
R432 56_4R432 56_4
RTCX1
C23
RTCX2
C24
INTVRMEN
B22
INTRUDER#
C22
GLAN_CLK
E25
LAN_RSTSYNC
C13
LAN_RXD0
F14
LAN_RXD1
G13
LAN_RXD2
D14
LAN_TXD0
D13
LAN_TXD1
D12
LAN_TXD2
E13
HDA_BIT_CLK
AF6
HDA_SYNC
AH4
HDA_RST#
AE7
HDA_SDIN0
AF4
HDA_SDIN1
AG4
HDA_SDIN2
AH3
HDA_SDOUT
AG5
SATALED#
AG8
SATA0RXN
AJ16
SATA0RXP
AH16
SATA0TXN
AF17
SATA0TXP
AG17
SATA1RXN
AH13
SATA1RXP
AJ13
SATA1TXN
AG14
SATA1TXP
AF14
SATA_CLKN
AH18
SATA_CLKP
AJ18
SATARBIAS#
AJ7
SATARBIAS
AH7
FWH0/LAD0
K5
FWH1/LAD1
K4
FWH2/LAD2
L6
FWH3/LAD3
K2
LDRQ0#
J3
LDRQ1#/GPIO23
J1
FWH4/LFRAME#
K3
A20GATE
N7
A20M#
AJ27
DPRSTP#
AJ25
DPSLP#
AE23
FERR#
AJ26
CPUPWRGD
AD22
IGNNE#
AF25
INIT#
AE22
INTR
AG25
RCIN#
L3
SMI#
AF24
NMI
AF23
STPCLK#
AH27
THRMTRIP#
AG26
RTCRST#
A25
GLAN_DOCK#/GPIO56
B10
GLAN_COMPO
B27
GLAN_COMPI
B28
HDA_SDIN3
AE5
SATA4TXN
AG12
SATA4RXN
AH11
SATA4TXP
AF12
SATA4RXP
AJ11
TP8
AG27
HDA_DOCK_EN#/GPIO33
AG7
HDA_DOCK_RST#/GPIO34
AE8
LAN100_SLP
A22
SATA5RXN
AH9
SATA5RXP
AJ9
SATA5TXN
AE10
SATA5TXP
AF10
SRTCRST#
F20
RTCLAN / GLAN
IHDA
SATA
LPCCPU
U35A
ICH9M REV 1.0
RTCLAN / GLAN
IHDA
SATA
LPCCPU
U35A
ICH9M REV 1.0
T44T44
R299 0_4R299 0_4
R295 33_4R295 33_4
R270
68.1K/F_4
R270
68.1K/F_4
D19 CH500HD19 CH500H
R310 *1K_4R310 *1K_4
12
CN26
RTC_CONN
CN26
RTC_CONN
R311 54.9/F_4R311 54.9/F_4
C402
*10P/50V_4
C402
*10P/50V_4
R515 *E@0_4R515 *E@0_4
R309 33_4R309 33_4
R426
24.9/F_4
R426
24.9/F_4
R376 10K_4R376 10K_4
R514 *E@33_4R514 *E@33_4
R427 *I@33_4R427 *I@33_4
R343 10K_4R343 10K_4
C354
*10P/50V_4
C354
*10P/50V_4
R326 8.2K_4R326 8.2K_4
C458
1U/6V_4
C458
1U/6V_4
R298
*56_4
R298
*56_4
R435 0_4R435 0_4
D20 CH500HD20 CH500H
R429 33_4R429 33_4
R433
56_4
R433
56_4
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
http://hobi-elektronika.net
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GLAN_TXP_SB
PCIE_TXP1_C
GLAN_TXN_SB
PCIE_TXN1_C
SB_USBBIAS
DMI_IRCOMP_R
AD3
AD25
AD28
AD9
AD10
AD20
AD12
AD2
AD15
AD13
AD7
AD26
AD8
AD4
AD16
AD17
AD21
AD19
AD29
AD1
AD24
AD22
AD23
AD27
AD11
AD5
AD14
AD31
AD6
AD0
AD30
AD18
INTB#
INTA#
PCIRST#
REQ0#
GNT0#
PCI_PME#
TRDY#
FRAME#
IRDY#
PAR
DEVSEL#
STOP#
PERR#
SERR#
USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6
USBOC#8
USBOC#9
USBOC#10
USBOC#11
USBOC#9
USBOC#8
USBOC#5
USBOC#6
USBOC#7
USBOC#0USBOC#3
USBOC#2
USBOC#4 USBOC#1
USBOC#10
USBOC#11
USBP9-
USBP9+
INTE#
FRAME#
DEVSEL#
TRDY#
INTC#
SERR#
STOP#
REQ1#
REQ3#
INTD#
REQ2#
INTH#
INTA#
INTF#
IRDY#
PERR#
LOCK#
INTG#
INTB#
REQ0#
REQ3#
GNT3#
GNT2#
REQ2#
REQ1#
GNT1#
LOCK#
INTC#
INTD#
INTF#
INTE#
INTH#
INTG#
PLT_RST-R#
SPI_CLK
SPI_CS0#
SPI_MOSO
SPI_MOSI
PCIE_TXP4_C
PCIE_TXN4_C
USBOC#7
USBP8-
USBP8+
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN3_C
PCIE_TXP3_C
PLT_RST-R#
GNT3#
GNT0#
SPI_CS1#
SPI_CLK_R
SPI_CS0#_R
SPI_MOSI_R
SPI_MOSO_R
SPI_CLK_R
SPI_CS0#_R
SPI_MOSO
SPI_MOSI_R
SPI_CS1#
SPI_MOSI_H
MCH_CFG_6 MCH_CFG_6_R
SPI_MOSISPI_MOSI_H
PCIE_RXN1<29>
PCIE_RXP1<29>
GLAN_RXP<21>
GLAN_TXP<21>
GLAN_RXN<21>
GLAN_TXN<21>
PCIE_TXP1<29>
PCIE_TXN1<29>
CLK_PCIE_ICH# <2>
CLK_PCIE_ICH <2>
USBP7- <29>
USBP7+ <29>
USBP6+ <29>
USBP6- <29>
USBP2+ <23>
DMI_RXN0 <6>
DMI_RXP0 <6>
DMI_RXN1 <6>
DMI_RXN2 <6>
DMI_RXN3 <6>
DMI_RXP1 <6>
DMI_RXP2 <6>
DMI_RXP3 <6>
DMI_TXN0 <6>
DMI_TXP0 <6>
DMI_TXN1 <6>
DMI_TXN2 <6>
DMI_TXN3 <6>
DMI_TXP1 <6>
DMI_TXP2 <6>
DMI_TXP3 <6>
USBP0- <30>
USBP0+ <30>
AD[0..31]<27>
INTA#<27>
CBE0# <27>
CBE3# <27>
CBE2# <27>
CBE1# <27>
PCIRST# <23,27>
REQ0# <27>
GNT0# <27>
PCI_PME# <27>
TRDY# <27>
FRAME# <27>
IRDY# <27>
PAR <27>
STOP# <27>
DEVSEL# <27>
PLTRST# <18,21,23,28,29,32>
PLT_RST# <6>
PCLK_ICH <2>
USBP5+ <22>
USBP5- <22>
PCIE_RXN4<23>
PCIE_RXP4<23>
PCIE_TXP4<23>
PCIE_TXN4<23>
GNT3#
USBP2- <23>
USBP1- <30>
USBP1+ <30>
USBP8- <29>
USBP8+ <29>
PCIE_RXN2<23>
PCIE_RXP2<23>
PCIE_TXN2<23>
PCIE_TXP2<23>
USBP9- <30>
USBP9+ <30>
JMB_RXN<28>
JMB_RXP<28>
JMB_TXN<28>
JMB_TXP<28>
USBP10- <31>
USBP10+ <31>
USBP11- <19>
USBP11+ <19>
USBP3+ <23>
USBP3- <23>
MCH_CFG_6<6>
MCH_CFG_6_R <6>
+1.5V
+3V_S5
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
ICH9M PCIE / PCI / USB
1A
13 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
ICH9M PCIE / PCI / USB
1A
13 40Thursday, August 28, 2008
ZY2 & ZY6
Size Document Number Rev
Date: Sheet
of
Quanta Computer Inc.
PROJECT :
ICH9M PCIE / PCI / USB
1A
13 40Thursday, August 28, 2008
ZY2 & ZY6
NEW CARD
BLUETOOTH
Wireless
NEW CARD
M/B USB PortGLAN
INTERUPT
PCI ROUTING
TABLE
REQ0# / GNT0# OZ601T
IDSEL
INTA#
DEVICE
AD20
CCD
Wireless
L<0.5",Avoid routing next to clock/high speed signals.
PME# internal PU 18K~42K
CARD READER
D/B USB Port
D/B USB Port
Finger Printer
DOCKING
TV CARD
South Bridge Strap Pin (2/3)
SPI_CS#1PCI_GNT#0
PCI
01
LPC
11
SPI(Default)
10
Boot Location
PCI Express Port
Config 1 bit 0 (Port 1-4)
PWROK
0 = Default
1 = Setting bit 0
HDA_SYNC
GNT2# / GPIO53
PWROK
0 = Setting bit 2
1 = Default
PCI Express Port
Config 2 bit 2 (Port 5-6)
GNT1# / GPIO51
0 = DMI for ESI-compatible
1 = Default
PWROK
ESI Strap(Server Only)
GNT3# / GPIO55
0 = "top-block swap" mode
1 = Default
PWROK
Top-Block Swap Override
SPI_MOSI
0 = INT TPM disable(Default)
1 = INT TPM enable
CLPWROK
Integrated TPM Enable
GNT0#
PWROK
Boot BIOS Selection 0
SPI_CS1# /
GPIO58 / CLGPIO6
CLPWROKBoot BIOS Selection 1
Pin Name Strap description
Sampled
Configuration PU/PD
TPM SPI FLASH
M/B USB Port
MINI_TV
TM & AS
LOW COST
N
Y
TPM SW
PERN1
N29
PERP1
N28
PETN1
P27
PETP1
P26
PERN2
L29
PERP2
L28
PETN2
M27
PETP2
M26
PERN3
J29
PERP3
J28
PETN3
K27
PETP3
K26
PERN4
G29
PERP4
G28
PETN4
H27
PETP4
H26
PERN5
E29
PERP5
E28
PETN5
F27
PETP5
F26
PERN6/GLAN_RXN
C29
PERP6/GLAN_RXP
C28
PETN6/GLAN_TXN
D27
PETP6/GLAN_TXP
D26
DMI0RXN
V27
DMI0RXP
V26
DMI0TXN
U29
DMI0TXP
U28
DMI1RXN
Y27
DMI1RXP
Y26
DMI1TXN
W29
DMI1TXP
W28
DMI2RXN
AB27
DMI2RXP
AB26
DMI2TXN
AA29
DMI2TXP
AA28
DMI3RXN
AD27
DMI3RXP
AD26
DMI3TXN
AC29
DMI3TXP
AC28
DMI_CLKN
T26
DMI_CLKP
T25
DMI_ZCOMP
AF29
DMI_IRCOMP
AF28
OC0#/GPIO59
N4
OC1#/GPIO40
N5
OC2#/GPIO41
N6
OC3#/GPIO42
P6
OC4#/GPIO43
M1
OC5#/GPIO29
N2
OC6#/GPIO30
M4
OC7#/GPIO31
M3
USBP0N
AC5
USBP0P
AC4
USBP1N
AD3
USBP1P
AD2
USBP2N
AC1
USBP2P
AC2
USBP3N
AA5
USBP3P
AA4
USBP4N
AB2
USBP4P
AB3
USBP5N
AA1
USBP5P
AA2
USBP6N
W5
USBP6P
W4
USBP7N
Y3
USBP7P
Y2
USBRBIAS#
AG1
USBRBIAS
AG2
SPI_CLK
D23
SPI_CS0#
D24
SPI_CS1#/GPIO58/CLGPIO6
F23
SPI_MOSI
D25
SPI_MISO
E23
OC8#/GPIO44
N3
OC9#/GPIO45
N1
USBP8P
W2
USBP8N
W1
USBP9N
V2
USBP9P
V3
USBP10N
U5
USBP11N
U1
USBP10P
U4
USBP11P
U2
OC10#/GPIO46
P5
OC11#/GPIO47
P3
PCI-Express
Direct Media Interface
USB
SPI
U35D
ICH9M REV 1.0
PCI-Express
Direct Media Interface
USB
SPI
U35D
ICH9M REV 1.0
R564 *0_4R564 *0_4
R301
22.6/F_4
R301
22.6/F_4
10
9
8
7
6
1
2
3
4
5
RN22
10K_10P8R
RN22
10K_10P8R
1
3
5
78
6
4
2
RN21
10K_8P4R
RN21
10K_8P4R
C392 .1U/10V_4C392 .1U/10V_4
R340 *1K_4R340 *1K_4
10
9
8
7
6
1
2
3
4
5
RN25
8.2K_10P8R
RN25
8.2K_10P8R
*.1U/16V_4
C411
*.1U/16V_4
C411
R329 *TPM@10K_4R329 *TPM@10K_4
T59T59
C393 .1U/10V_4C393 .1U/10V_4
R348 *15_4R348 *15_4
C386 .1U/10V_4C386 .1U/10V_4
2
1
4
3 5
U30
TC7SH08FU
U30
TC7SH08FU
C397 .1U/10V_4C397 .1U/10V_4
R344 *1K_4R344 *1K_4
AD0
D11
AD1
C8
AD2
D9
AD3
E12
AD4
E9
AD5
C9
AD6
E10
AD7
B7
AD8
C7
AD9
C5
AD10
G11
AD11
F8
AD12
F11
AD13
E7
AD14
A3
AD15
D2
AD16
F10
AD17
D5
AD18
D10
AD19
B3
AD20
F7
AD21
C3
AD22
F3
AD23
F4
AD24
C1
AD25
G7
AD26
H7
AD27
D1
AD28
G5
AD29
H6
AD30
G1
AD31
H3
REQ0#
F1
GNT0#
G4
REQ1#/GPIO50
B6
GNT1#/GPIO51
A7
REQ2#/GPIO52
F13
GNT2#/GPIO53
F12
REQ3#/GPIO54
E6
GNT3#/GPIO55
F6
C/BE0#
D8
C/BE1#
B4
C/BE2#
D6
C/BE3#
A5
IRDY#
D3
PAR
E3
PCIRST#
R1
DEVSEL#
C6
PERR#
E4
PLOCK#
C2
SERR#
J4
STOP#
A4
TRDY#
F5
FRAME#
D7
PLTRST#
C14
PCICLK
D4
PME#
R2
PIRQA#
J5
PIRQB#
E1
PIRQC#
J6
PIRQD#
C4
PIRQH#/GPIO5
G2
PIRQG#/GPIO4
F2
PIRQF#/GPIO3
K6
PIRQE#/GPIO2
H4
PCI
Interrupt I/F
U35B
ICH9M REV 1.0
PCI
Interrupt I/F
U35B
ICH9M REV 1.0
OFF
1
ON
3
OFF
2
ON
4
U44
*TPM@DHN-02F-T-V-T/R
U44
*TPM@DHN-02F-T-V-T/R
C385 .1U/10V_4C385 .1U/10V_4
10
9
8
7
6
1
2
3
4
5
RN23
8.2K_10P8R
RN23
8.2K_10P8R
10
9
8
7
6
1
2
3
4
5
RN24
8.2K_10P8R
RN24
8.2K_10P8R
R367 0_4R367 0_4
C408
.1U/50V_6
C408
.1U/50V_6
R369 *15_4R369 *15_4
C464 .1U/10V_4C464 .1U/10V_4
R563 *0_4R563 *0_4
CE
1
SO
2
WP
3
VSS
4
SI
5
SCK
6
HOLD
7
VDD
8
U31
*W25X16VSSIG
U31
*W25X16VSSIG
C376 .1U/10V_4C376 .1U/10V_4
C463 .1U/10V_4C463 .1U/10V_4
R357
100K_6
R357
100K_6
R350 *15_4R350 *15_4
R347 *1K_4R347 *1K_4
C378 .1U/10V_4C378 .1U/10V_4
T46T46
R423 24.9/F_4R423 24.9/F_4
R370 *15_4R370 *15_4
C387 .1U/10V_4C387 .1U/10V_4
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