Xilinx UG181 User Manual
LogiCORE™ IP
SPI-4.2 Lite v4.3
User Guide
UG181 June 27, 2008
R
R
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate
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SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
The following table shows the revision history for this document.
Date Version Revision
8/31/05 1.1 Initial Xilinx release.
1/18/06 1.2 Updated release version, tool version, and release date.
7/13/06 2.0 Updated version to 4.1, release date, ISE to v8.2i.
2/15/07 3.0 Updated version to 4.2, ISE to v9.1i, added Virtex-3E support.
4/02/07 3.1 Added support for Spartan-3A DSP devices.
4/16/08 4.0 Updated for ISE v10.1.
6/27/08 4.5 Updated the ISE v10.1 SP1 release.
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Table of Contents
Preface: About This Guide
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 1: Introduction
About the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended Design Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI-4.2 Lite Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2: Core Architecture
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Sink Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Source Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sink Core Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Sink SPI-4.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sink User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Source Core Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Source SPI-4.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Source User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 3: Generating the Core
CORE Generator Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Main Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Sink Status Options Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Sink Other Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FIFO Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Source Status Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Source Other Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Bursting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FIFO Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Calendar COE File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 4: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Know the Degree of Difficulty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Understand Signal Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Keep it Registered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Recognize Timing Critical Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Use Supported Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Make Only Allowed Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Initializing the SPI-4.2 Lite Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Sink Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI-4.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Sink User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Sink Static Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Sink Data Capture Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Synchronization and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Source Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Source SPI-4.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Source User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Source Static Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Synchronization and Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 5: Constraining the Core
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Sink Core Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DCM and Static Alignment Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Sink Core Optional Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
IDelayCtrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
I/O Standards Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Area Group Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timing Ignore Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Source Core Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Source Core Optional Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
I/O Standards Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Area Group Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Timing Ignore Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
User Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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Constraints Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
New Target Region or Device Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Modifying the UCF File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 6: Special Design Considerations
Sink Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Embedded Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
User Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Source Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Slave Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Multiple Core Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Instantiating Multiple Cores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Generating the Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Creating Top-Level UCF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Chapter 7: Simulating and Implementing the Core
Functional Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Generating a Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Synthesis of Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Xilinx Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Example Design Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
NGDBuild . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Mapping the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Static Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Generating a Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Appendix A: SPI-4.2 Lite Control Word
Appendix B: SPI-4.2 Lite Calendar Programming
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Appendix C: SPI-4.2 Lite Core Verification
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Schedule of Figures
Chapter 2: Core Architecture
Figure 2-1: SPI-4.2 Lite Core in a Typical Link Layer Application. . . . . . . . . . . . . . . . . . . 18
Figure 2-2: Sink Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2-3: Source Core Block Diagram and I/O Interface Signals . . . . . . . . . . . . . . . . . . 31
Chapter 3: Generating the Core
Figure 3-1: SPI-4.2 Lite Sink and Source Main Customization Screen . . . . . . . . . . . . . . . 44
Chapter 4: Designing with the Core
Figure 4-1: SPI-4.2 Interface to the 64-Bit User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4-2: Sink Data Path - Short Packet Transfers with Minimum SOP Spacing
Enforced. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4-3: Sink Training Valid Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 4-4: Sink FIFO Almost Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-5: Sink FIFO Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-6: Status FIFO Calendar and Status Memory Block Diagram. . . . . . . . . . . . . . . 62
Figure 4-7: Sink Calendar Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 4-8: Typical Flow Control Implementation for 4-Channel System . . . . . . . . . . . . 64
Figure 4-9: Sink Status FIFO Interface Example 1: 10-channel Configuration. . . . . . . . . 65
Figure 4-10: Sink Status FIFO Interface Example: 64-channel Configuration . . . . . . . . . 66
Figure 4-11: Sink Status Path - User Interface to SPI-4.2 Interface. . . . . . . . . . . . . . . . . . . 67
Figure 4-12: FIFO Almost Full Mode “00” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4-13: FIFO Almost Full Mode “01” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4-14: FIFO Almost Full Mode “10” or “11” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 4-15: Sink Startup Sequence State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 4-16: Short Packet Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 4-17: Sequential Payload Control Word Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 4-18: Example of Error Flag SnkFFDIP4Err . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 4-19: Example of Error Flag SnkFFDIP4Err and SnkFFPayloadDIP4 . . . . . . . . . . 75
Figure 4-20: Example of Error Flag SnkFFPayloadErr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 4-21: Source Data Path: User Interface to SPI-4.2 Interface. . . . . . . . . . . . . . . . . . . 77
Figure 4-22: Source Data Path - Minimum SOP Spacing Enforced . . . . . . . . . . . . . . . . . . 78
Figure 4-23: Source Data Path - Short Packet Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 4-24: Source FIFO Almost-full Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 4-25: Source FIFO Overflow Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 4-26: Writing to the Source FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 4-27: Typical User Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 4-28: Source Calendar Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 4-29: Addressable Status FIFO Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 4-30: Addressable Status FIFO Interface: 4-Channel Configuration . . . . . . . . . . . 89
Figure 4-31: Addressable Status FIFO Interface: 256-channel configuration . . . . . . . . . . 90
Figure 4-32: Addressable Status FIFO Interface - SPI-4.2 Interface to User Interface . . 91
Figure 4-33: Transparent Status FIFO Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . 92
Figure 4-34: Transparent Source Status FIFO Interface: 256-channel Configuration . . . 93
Figure 4-35: Example Of Source Burst Mode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 4-36: Example Of Source Burst Mode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 4-37: Source Startup Sequence State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 6: Special Design Considerations
Figure 6-1: Embedded Clocking Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 6-2: Example: Sink User Clocking Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 6-3: Sink User Clocking: Global Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 6-4: Sink User Clocking: Regional Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 6-5: Source Clocking: Master and Slave Implementation . . . . . . . . . . . . . . . . . . . 116
Figure 6-6: Source Clocking: Global Clocking for SysClk. . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 6-7: Source Clocking: Global Clocking for TSClk . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 6-8: Source Clocking: Regional Clocking for SysClk. . . . . . . . . . . . . . . . . . . . . . . 118
Figure 6-9: Source Clocking: Regional Clocking for TSClk . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 6-10: Slave Clocking Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Schedule of Tables
Chapter 2: Core Architecture
Table 2-1: Sink SPI-4.2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 2-2: Sink Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2-3: Sink FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2-4: Sink Calendar Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2-5: Sink Status FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2-6: Sink Static Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 2-7: Sink Core Clocks: Embedded Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2-8: Sink Core Clocks: Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2-9: Sink Core Clocks: User Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 2-10: Source SPI-4.2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 2-11: Source Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2-12: Source FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 2-13: Source Calendar Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 2-14: Source Status FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 2-15: Source Static Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-16: Source Core Clocks: Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-17: Source Core Clock Status Signals: Master Configuration . . . . . . . . . . . . . . . . 40
Table 2-18: Source Core Clocks: Slave Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 3: Generating the Core
Chapter 4: Designing with the Core
Table 4-1: Formatting SPI-4.2 Interface Data (RDat) 64-bit User Interface (Example) . . 56
Table 4-2: SPI-4.2 Control Word Mapping to 64-bit User Interface . . . . . . . . . . . . . . . . . . 57
Table 4-3: SPI-4.2 Control Word Mapping to 32-bit User Interface . . . . . . . . . . . . . . . . . . 57
Table 4-4: Status Written into SnkStat per Channel per Write Cycle. . . . . . . . . . . . . . . . . 65
Table 4-5: Status Written to Status FIFO Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 4-6: Example of Formatting Source FIFO Data for a 64-bit User Interface. . . . . . . 79
Table 4-7: SPI-4.2 Control Word Mapping to 32-bit Interface . . . . . . . . . . . . . . . . . . . . . . . 80
Table 4-8: SPI-4.2 Control Word Mapping to 64-bit User Interface . . . . . . . . . . . . . . . . . . 81
Table 4-9: Status Written into SrcStat per Channel per Clock Cycle . . . . . . . . . . . . . . . . . 89
Table 4-10: Status Read Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 4-11: Status for the 256-channel Source Calendar Initialization System . . . . . . . . 92
Chapter 6: Special Design Considerations
Table 6-1: Sink Core Embedded Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 6-2: Sink Core User Clocking Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Table 6-3: SysClk Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 6-4: TSClk Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Appendix A: SPI-4.2 Lite Control Word
Table A-1: SPI-4.2 Lite Control Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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About This Guide
This user guide describes the function and operation of the Xilinx LogiCORE™ IP SPI-4.2
(PL4) Lite core, and provides information about designing, customizing, and
implementing the core.
Contents
This guide contains the following chapters:
• Preface, “About this Guide” describes the organization and purpose of the user guide
and the conventions used in this document.
• Chapter 1, “Introduction” introduces the SPI-4.2 Lite core and provides related
information, including recommended design experience, additional resources,
technical support, and submitting feedback to Xilinx.
• Chapter 2, “Core Architecture” describes the SPI-4.2 Lite core architecture and
interface signals.
• Chapter 3, “Generating the Core” describes how to generate the SPI-4.2 Lite core
using the Xilinx CORE Generator™.
• Chapter 4, “Designing with the Core” describes how to use the Xilinx SPI-4.2 Lite core
in a user application.
• Chapter 5, “Constraining the Core” describes how to constrain the core.
• Chapter 6, “Special Design Considerations” describes how to instantiate multiple SPI-
4.2 Lite cores in a design.
• Chapter 7, “Simulating and Implementing the Core” instructs you how to simulate
and implement the SPI-4.2 Lite core in their design.
• Appendix A, “SPI-4.2 Lite Control Word” defines the SPI-4.2 control word format.
• Appendix B, “SPI-4.2 Lite Calendar Programming” contains examples that describe
how to program calendars for the Source Status FIFO and Sink Status FIFO of the SPI-
4.2 Lite core.
• Appendix C, “SPI-4.2 Lite Core Verification” describes the software verification of the
SPI-4.2 Lite core.
Preface
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Conventions
Typographical
Preface: About This Guide
This document uses the following conventions. An example illustrates each convention.
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Messages, prompts, and
Courier font
program files that the system
displays
speed grade: - 100
Courier bold
Helvetica bold
Italic font
Square brackets [ ]
Braces { }
Literal commands that you
enter in a syntactical statement
Commands that you select
from a menu
Keyboard shortcuts Ctrl+C
Variables in a syntax
statement for which you must
supply values
References to other manuals
Emphasis in text
An optional entry or
parameter. However, in bus
specifications, such as
bus[7:0], they are required.
A list of items from which you
must choose one or more
ngdbuild design_name
File → Open
ngdbuild design_name
See the Development System
Reference Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
ngdbuild [ option_name]
design_name
lowpwr ={on|off}
Vertical bar |
Vertical ellipsis
.
.
.
Horizontal ellipsis . . .
12 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
Separates items in a list of
choices
Repetitive material that has
been omitted
Repetitive material that has
been omitted
lowpwr ={on|off}
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
allow block block_name
loc1 loc2 ... locn;
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Conventions
Online Document
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The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Blue, underlined text
Cross-reference link to a
location in the current
document
Hyperlink to a website (URL)
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Go to www.xilinx.com
for the
latest speed files.
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Preface: About This Guide
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Introduction
The SPI-4.2 (PL4) Lite core implements and is functionally compliant to the OIF-SPI-4-02.1
System Packet Interface Phase 2 specification and supports both VHDL and Verilog design
environments.
This chapter introduces the SPI-4.2 Lite core and provides related information, including
recommended design experience, additional resources, technical support, and how to
submit feedback to Xilinx.
About the Core
The SPI-4.2 Lite core is a Xilinx CORE Generator IP core, included in the latest IP Update
on the Xilinx IP Center.
Chapter 1
For detailed information about the core, see
www.xilinx.com/products/ipcenter/DO-DI-POSL4MC.htm
For information about system requirements, installation, and licensing options, see the
SPI-4.2 Lite Getting Started Guide.
Recommended Design Experience
Although the SPI-4.2 Lite core is a fully verified solution, the challenge associated with
implementing a complete design varies depending on the configuration and functionality
of the application. For best results, previous experience building high performance,
pipelined FPGA designs using Xilinx implementation software and user constraints files
(UCF) is recommended.
Contact your local Xilinx representative for a closer review and estimation for your specific
requirements.
Additional Core Resources
For detailed information and updates about the SPI-4.2 Lite core, see the following
documents, located on the SPI-4.2 product lounge page at:
www.xilinx.com/ipcenter/posphyl4/spi42_core.htm
• SPI-4.2 Lite Data Sheet
• SPI-4.2 Lite Release Notes
• SPI-4.2 Lite Getting Started Guide
.
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Technical Support
To obtain technical support specific to the SPI-4.2 Lite core, visit www.xilinx.com/support.
Questions are routed to a team of engineers with expertise using the SPI-4.2 Lite core.
Xilinx will provide technical support for use of this product as described in the SPI-4.2 Lite
User Guide and the SPI-4.2 Lite Getting Started Guide. Xilinx cannot guarantee timing,
functionality, or support of this product for designs that do not follow these guidelines.
Feedback
Xilinx welcomes comments and suggestions about the SPI-4.2 Lite core and the
documentation provided with the core.
SPI-4.2 Lite Core
For comments or suggestions about the SPI-4.2 Lite core, please submit a webcase from
www.xilinx.com/support/clearexpress/websupport.htm
following information:
• Product name
• Core version number
• Explanation of your comments
Chapter 1: Introduction
. Be sure to include the
Document
For comments or suggestions about this document, please submit a WebCase from
www.xilinx.com/support/clearexpress/websupport.htm
following information:
• Document title
• Document number
• Page number(s) to which your comments refer
• Explanation of your comments
. Be sure to include the
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Core Architecture
This chapter describes the SPI-4.2 Lite core architecture and interface signals.
System Overview
The SPI-4.2 Lite core is comprised of two separate cores that enable the transmission
(Source core) and reception (Sink core) of data.
• Sink Core. Receives data from the SPI-4.2 interface. It takes the 16-bit interface and
maps it to a 32-bit or 64-bit interface enabling the internal logic to run at a quarter of
the line rate.
• Source Core. Transmits data on the SPI-4.2 interface. Payload data written into the
core as 32-bit or 64-bit words (two or four 16-bit SPI-4.2 Lite words, respectively) is
mapped onto the 16-bit SPI-4.2 interface.
Chapter 2
Figure 2-1 illustrates the interfaces of the SPI-4.2 Lite core and shows it in a typical link-
layer application.
In the link layer example, the SPI-4.2 interface connects an external physical-layer device to
a link-layer implemented in a Virtex™-4 FPGA. The user logic reads data from the Sink
core and writes data into the Source core. A standard FIFO interface is provided for this
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Chapter 2: Core Architecture
data access and facilitates integration within a system. Dedicated signals are used to
configure the Sink and Source cores in circuit and monitor a suite of status registers.
Sink Core
SPI-4.2
Interface
SPI-4.2 Lite
PHY Layer Device
(Xilinx FPGA
or
ASSP)
Figure 2-1: SPI-4.2 Lite Core in a Typical Link Layer Application
Rx Data Path
Rx Status Path
Tx Data Path
Tx Status Path
Virtex-4 or Spartan-3 Device
SPI-4.2 Lite Sink Core
SPI-4.2
Sink
Interface
SPI-4.2 Lite Source Core
SPI-4.2
Source
Interface
User
Sink
Interface
User
Source
Interface
User
Interface
User’s Logic
(Link Layer
Processor)
The Sink core receives data from the SPI-4.2 interface. It takes the 16-bit interface and maps
it to a 32-bit or 64-bit interface enabling the internal logic to run at a half (for 32-bit) or an
quarter (for 64-bit) of the line rate. The user data and the corresponding control signals are
accessed with a standard FIFO interface. The FIFO read and write operations are
performed in independent clock domains.
The Sink core implements the following features:
• Supports 32-bit or 64-bit user data width
• Dedicated output signal indicating loss of valid RDClk
• Provides a FIFO reset signal for clearing contents of the data pipe during operation
• Provides support for forcing the insertion of DIP-2 errors for system testing
• Regional clocking option (for Virtex-4 and Virtex-5 devices only, saves global clocking
• Provides both embedded and user clocking options
For more information on core features, see Chapter 4, “Designing with the Core.”
Source Core
The Source core transmits data on the SPI-4.2 interface. Payload data written into the core
as 32-bit or 64-bit words (two or four 16-bit SPI-4.2 Lite words, respectively) are mapped
onto the 16-bit SPI-4.2 interface. While packet data written into the core may not be 32-bit
or 64-bit aligned, the core optimally maps the data to 16-bit words such that no filler idle
cycles are inserted. The data along with the control signals are written into the core via a
resources)
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Sink Core Interfaces
standard FIFO interface, and the FIFO read and write operations are performed in
independent clock domains.
The Source core implements the following features:
• Supports 32-bit or 64-bit user data width.
• Optionally transmits only complete data bursts.
• Provides both master and slave clocking to facilitate multiple core implementations.
• Enables addressable or transparent access to SPI-4.2 flow control data.
• Provides a FIFO reset signal for clearing contents of the data pipe during operation.
• Provides support for forcing the insertion of DIP-4 errors for system testing.
For more information on core features, see Chapter 4, “Designing with the Core.”
Sink Core Interfaces
The Sink core has five functional modules:
• Sink Data FIFO
• Sink Data Receive
• Sink Status Registers
• Sink Calendar
• Sink Status Transmit
R
The Sink core has the following interfaces:
• Sink SPI-4.2 Interface
• Sink User Interface
♦ Sink Control and Status Interface
♦ Sink FIFO Interface
♦ Sink Status and Flow Control Interface
- Calendar Control Interface
- Status FIFO Interface
♦ Sink Configuration Interface
♦ Sink Clocking Interface
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4
a
Chapter 2: Core Architecture
The functional modules and signals which comprise the different interfaces are shown in
Figure 2-2 and defined in tables in the following sections.
Control
and
Status
nterface
FIFO
nterface
FIFO
Status
nterface
alendar
Control
nterface
SnkEn
SnkOof
SnkBusErr
SnkTrainValid
SnkFFClk
SnkFFRdEn_n
SnkFFAddr[7:0]
SnkFFData[63:0] or [31:0]
SnkFFMod[2:0] or [1:0]
SnkFFSOP
SnkFFEOP
SnkFFErr
SnkFFPayloadErr
SnkFFDIP4Err
SnkFFPa
yloadDIP4
SnkFFBurstErr
SnkFFAlmostEmpty_n
SnkFFEmpty_n
SnkFFValid
SnkAlmostFull_n
SnkOverflow_n
SnkStatClk
SnkStatAddr[3:0]
SnkStat[31:0]
SnkStatWrEn_n
SnkStatMask[15:0]
SnkCalClk
SnkCalWrEn_n
SnkCalAddr[8:0]
SnkCalData[7:0]
SnkCalDataOut[7:0]
SPI-4.2 Lite Sink Core
Sink Data
FIFO
Sink Status
Registers
Sink
Calendar
Sink Data
Receive
Sink Status
Transmit
RDClk
RDat[15:0]
RCtl
SPI-
Sin
Interf
RSClk
RStat[1:0]
Static Configuration Signals
Reset_n
SnkFifoReset_n
Figure 2-2: Sink Core Block Diagram
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Sink Core Interfaces
Sink SPI-4.2 Interface
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The SPI-4.2 interface uses LVDS I/O buffers to receive 16-bit data words. The 16-bit data
words received on the SPI-4.2 interface are combined into 32-bit or 64-bit data words by the
SPI-4.2 Lite core, which allows the user interface to run at a half (32-bit interface) or quarter
(64-bit interface) of the data rate. For example, for a 200 Mbps data rate and a 32-bit
interface, you can read data from the Sink core at 100 MHz, and if a 64-bit interface is used,
you can read data from the Sink core at 50 MHz and maintain the same data rate.
The resulting data words are written into an asynchronous FIFO. The received 16-bit
control words are stored out of band in the FIFO, along with the corresponding data word.
The received control words that are not idle or training words can contain the information
listed below:
• Start or continuation of the following packet
• Link address of the following packet
• End of the preceding packet
• Number of valid bytes in the last word of the preceding packet
• Error conditions in the preceding packet
In addition to receiving 16-bit data words, the SPI-4.2 interface also sends flow control data
at 1/4 rate (or 1/8 rate) of its data interface. The 32-bit status (2-bit status for each channel)
from the user interface is processed and formatted by the SPI-4.2 Lite core to be transmitted
on RStat. Tab le 2 -1 defines the Sink SPI-4.2 interface signals.
Table 2-1: Sink SPI-4.2 Interface Signals
Name Direction
RDClk_P
RDClk_N
RDat_P[15:0]
RDat_N[15:0]
RCtl_P
Input n/a SPI-4.2 Receive Data Clock (LVDS): Source synchronous clock received with
Input RDClk SPI-4.2 Receive Data Bus (LVDS): The 16-bit data bus used to receive SPI-4.2
Input RDClk SPI-4.2 Receive Control (LVDS): Signal that indicates whether data or control
RCtl_N
RSClk Output n/a SPI-4.2 Receive Status Clock: Source synchronous clock transmitted with
RStat[1:0] Output RSClk SPI-4.2 Receive FIFO Status: FlFO Status Channel flow control interface. You
Clock
Domain
Description
RDat and RCtl. The rising and falling edges of this clock (DDR) are used to
clock RDat and RCtl.
data and control information.
information is present on the RDat bus. When
present on RDat. When RCtl is asserted, control information is present on
RDat.
RStat at 1/2 or 1/4 rate of the RDClk. The rate of the status clock is controlled
by the static configuration signal RSClkDiv. You can select this signal to be
transmitted as LVTTL or LVDS.
can select this bus to be transmitted as LVTTL or LVDS.
RCtl is deasserted, data is
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Sink User Interface
The Sink User Interface includes all signals other than those on the SPI-4.2 Interface. The
high-performance logic on the Sink back-end enables the user interface to run at higher
frequencies than the SPI-4.2 Interface. This is sometimes required if a large percentage of
the traffic consists of small packets.
The User Interface is subdivided into five smaller interfaces. Each of these interfaces are
presented in detail below:
• Control and Status Interface: The signals of this interface apply to the operation of
the Sink core.
• FIFO Interface: The signals of this interface allow you to access data received on the
SPI-4.2 Interface.
• Status and Flow Control Interface: The signals of this interface send flow control
information on the SPI-4.2 Interface.
• Static Configuration Interface: The signals of this interface allow you to configure the
core.
• Clocking Interface: The signals of this interface report the status of the clocks and
include the general purpose clocks.
Chapter 2: Core Architecture
Sink Control and Status Interface
The Sink core control and status signals either control the operation of the entire Sink core
or provide status information that is not associated with a particular channel (port) or
packet. Tab le 2 -2 defines the Sink control and status signals.
Table 2-2: Sink Control and Status Signals
Name Direction
Reset_n Input n/a Reset: Active Low signal that asynchronously initializes internal flip-flops,
SnkFifoReset_n Input SnkFFClk Sink FIFO Reset: Active low signal enables you to reset the Sink FIFO and
SnkEn Input SnkStatClk Sink Enable: Active high signal that enables the Sink core. When SnkEn is
Clock
Domain
Description
registers, and counters. When Reset_n is asserted, the Sink core will go out
of frame and the entire data path is cleared (including the FIFO). The Sink
core will also assert SnkOof, and deassert SnkBusErr and SnkTrainValid.
When Reset_n is asserted, the Sink core will transmit framing "11" on RStat
and continue to drive RSClk.
Following the deassertion of Reset_n, the sink calendar should be
programmed if the calendar is initialized in-circuit.
the associated data path logic. This enables the FIFO to be cleared while
remaining in frame.
Coming out of SnkFifoReset_n, the Sink core will discard all data on the SPI-
4.2 interface until a valid SOP control word is received.
deasserted, the Sink core will go out of frame and will not store any
additional data in the FIFO. The current contents of the FIFO remain intact.
The Sink core will also assert SnkOof, and deassert SnkBusErr and
SnkTrainValid. When SnkEn is deasserted, the Sink core will transmit
framing "11" on RStat and continue to drive RSClk.
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Table 2-2: Sink Control and Status Signals (Continued)
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Name Direction
SnkOof Output SnkFFClk Sink Out-of-Frame: Active high signal that indicates that the SPI-4.2 Lite
SnkBusErr Output SnkFFClk Sink Bus Error: Active high signal that indicates SPI-4.2 protocol violations
SnkBusErrStat[7:0] Output SnkFFClk Sink Bus Error Status: Each bit of this bus corresponds to a specific Sink Bus
Clock
Domain
Description
Sink block is not in frame. This signal is asserted when SnkEn is deasserted
or the Sink block loses synchronization with the data received on the SPI-4.2
Interface. This signal is deasserted once the Sink block reacquires
synchronization with the received SPI-4.2 data.
or bus errors that are not associated with a particular packet. Information on
the specific error condition that caused the SnkBusErr assertion is provided
on SnkBusErrStat
Error condition and is asserted concurrently with SnkBusErr. The error
conditions detected are reported as follows:
SnkBusErrStat [0]: Minimum SOP spacing violation
SnkBusErrStat [1]: Control word with EOP not preceded by a data word
SnkBusErrStat [2]: Payload control word not followed by a data word
SnkBusErrStat [3]: DIP4 error received during training or on idles
SnkBusErrStat [4]: Reserved control words received
SnkBusErrStat [5]: Non-zero address bits on control words received (except
on payload and training control words)
SnkBusErrStat [6:7]: Reserved bits (tied low)
SnkTrainValid Output SnkFFClk Sink Training Valid: Active high signal that indicates that a valid training
pattern has been received. This signal is asserted for the duration of the
training pattern (20 SPI-4.2 bus clock cycles or 5 RDClk0_GP clock cycles), if
the training pattern received is successfully decoded.
Sink FIFO Interface
The Sink FIFO Interface signals allow you to access the data (received on the SPI-4.2
Interface) that is stored in the FIFO. The signals on this interface is defined in Ta bl e 2- 3.
Table 2-3: Sink FIFO Signals
Name
SnkFFClk Input Sink FIFO Clock: All Sink FIFO Interface signals are synchronous to the rising edge of
SnkFFRdEn_n Input Sink FIFO Read-Enable: When detected low at the rising edge of SnkFFClk, data and
SnkFFAddr[7:0] Output Sink FIFO Channel Address: Channel number associated with the data on SnkFFData.
SnkFFData[31:0]
or
SnkFFData[63:0]
SnkFFMod[1:0]
or
SnkFFMod[2:0]
Direction
this clock.
status information is available from the FIFO on the next rising edge of SnkFFClk.
Output Sink FIFO Data Out: The Sink FIFO data bus. Bit 0 is the LSB.
The core can be configured to have a 32- or 64-bit Interface. The 64-bit interface enables
running at half the clock rate required for a 32-bit interface.
Output Sink FIFO Modulo: This signal indicates which bytes on the SnkFFData bus are valid
when the SnkFFEOP signal is asserted.
SnkFFMod[1:0] is used with a 32-bit interface.
SnkFFMod[2:0] is used with a 64-bit interface.
Description
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Table 2-3: Sink FIFO Signals (Continued)
Chapter 2: Core Architecture
Name
Direction
Description
SnkFFSOP Output Sink FIFO Start of Packet: When asserted (active high), this signal indicates the start of
a packet is being read out of the Sink FIFO.
SnkFFEOP Output Sink FIFO End of Packet: When asserted (active high), this signal indicates that the end
of a packet is being read out of the Sink FIFO.
SnkFFErr Output Sink FIFO Error: When asserted (active high), this signal indicates that the current
packet is terminated with an EOP abort condition. This signal is only asserted when
SnkFFEOP is asserted.
SnkFFEmpty_n Output Sink FIFO Empty: When asserted (active low), this signal indicates that the Sink FIFO
is empty. No data can be read until this signal is deasserted. This signal is asserted with
the last data word read out of the FIFO.
SnkFFAlmostEmpty_n Output Sink FIFO Almost Empty: When this signal is asserted (active low), it indicates that one
word remains in the FIFO, and you should deassert the read enable signal on the next
clock cycle. The user ’s read logic should evaluate the SnkFFEmpty_n signal to verify
that there is no data in the FIFO in case an additional word was simultaneously written
into the FIFO. An example of the behavior of this interface signal is provided with the
SPI-4.2 Lite core in the Design Example (see the pl4_lite_fifo_loopback_read.v/vhd file.)
SnkFFValid Output Sink FIFO Read Valid: When asserted (active high), this signal indicates that the
information on SnkFFData, SnkFFAddr, SnkFFSOP, SnkFFEOP, SnkFFBurstErr,
SnkFFMod, SnkFFErr, SnkFFDIP4Err, and SnkFFPayloadErr is valid.
SnkFFDIP4Err Output Sink FIFO DIP-4 Error: When asserted (active high), this signal indicates that a DIP-4
parity error was detected with the SPI-4.2 control word ending a packet or burst of data.
This signal is asserted at the end of that packet or burst of data.
SnkFFPayloadDIP4 Output Sink FIFO Payload DIP4 Error: When asserted (active high), this signal indicates that a
DIP-4 parity error was detected with the SPI-4.2 control word starting a packet or burst
of data. This signal is asserted at the end of that packet or burst of data.
SnkFFBurstErr Output Sink FIFO Burst Error: When asserted (active high), this signal indicates that the Sink
core has received data that was terminated on a non-credit boundary without an EOP.
SnkFFBurstErr may be used by the user’s logic to indicate missing EOPs, or incorrectly
terminated bursts. In this case the Sink core does not assert SnkFFEOP or SnkFFErr.
SnkFFPayloadErr Output Sink FIFO Payload Error: When asserted (active high), this signal indicates that the
received data was not preceded by a valid payload control word. Since it is not clear
what the packet Address and SOP should be, it is flagged as an error. This is asserted
with each data word coming out of the FIFO, and will remain asserted until a valid
payload control word is followed by data.
SnkAlmostFull_n Output Sink Almost Full: When asserted (active low), this signal indicates that the Sink core is
approaching full (as defined by the parameter SnkAFThresAssert), and that immediate
action should be taken to prevent overflow.
SnkOverflow_n Output Sink Overflow: When asserted (active low), this signal indicates that the Sink core has
overflowed and is in an error condition. Data will be lost if SnkOverflow_n is asserted,
since no data is written into the FIFO when the overflow signal is asserted.
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Sink Core Interfaces
Sink Status and Flow Control Interface (Calendar Control and Status FIFO)
The Sink Status and Flow Control interface enables you to send flow control data on the
SPI-4.2 Interface. The status information is sent based on the channel order and channel
frequency defined in the programmable calendar. Ta bl e 2- 4 and Ta bl e 2- 5 define the
calendar interface and status FIFO interface signals.
Table 2-4: Sink Calendar Control Signals
R
Name Direction
SnkCalClk Input n/a Sink Calendar Clock: All Sink calendar signals are synchronous to
SnkCalWrEn_n Input SnkCalClk Sink Calendar Write Enable: When this signal is asserted (active
SnkCalAddr[8:0] Input SnkCalClk Sink Calendar Address: When SnkCalWrEn_n is asserted, this bus
SnkCalData[7:0] Input SnkCalClk Sink Calendar Data: This bus contains the channel number to write
SnkCalDataOut[7:0] Output SnkCalClk Sink Calendar Data Output: This bus contains the channel number
Clock
Domain
Description
this clock.
low), the Sink Calendar is written with the data on the SnkCalData
bus on the rising edge of SnkCalClk. When the signal is deasserted,
the Sink Calendar data can be read on SnkCalDataOut.
indicates the calendar address to which the data on SnkCalData is
written. When SnkCalWrEn_n is deasserted, this bus indicates the
calendar address from which the channel number on SnkCalDataOut
is driven.
into the calendar buffer when SnkCalWrEn_n is enabled. The channel
numbers written into the calendar indicate the order that status is
sent on RStat.
that is read from the calendar buffer when SnkCalWrEn_n is disabled.
The channel numbers read from the calendar indicate the order that
status is sent on RStat.
Table 2-5: Sink Status FIFO Signals
Name Direction
SnkStatClk Input n/s Sink Status Clock: All Sink Status write signals are synchronous to
SnkStat[31:0] Input SnkStatClk Sink Status Bus: This 32-bit bus is used to write status information
SnkDIP2ErrRequest Input SnkStatClk Sink DIP2 Error Request: This is an active high signal that requests
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Clock
Domain
Description
this clock.
into the Status FIFO. You can write the status for 16 channels each
clock cycle.
The 16-channel status that are accessed simultaneously are grouped
in the following manner: channels 15 to 0, channels 31 to 16, channels
47 to 32, . . . , channels 255 to 239.
an incorrect DIP-2 to be sent out of the RStat bus. When this signal is
asserted, Sink Status FIFO responds by inverting the next DIP2 value
that it transmits.
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Table 2-5: Sink Status FIFO Signals (Continued)
Chapter 2: Core Architecture
Name Direction
SnkStatAddr[3:0] Input SnkStatClk Sink Status Address bus: The Sink Status Address determines the
SnkStatWr_n Input SnkStatClk Sink Status Write: The Sink Status Write (active low) qualifies the
SnkStatMask[15:0] Input SnkStatClk Sink Status Mask Bus: The Sink Status Mask determines if the 2-bit
Clock
Domain
Description
group of 16-channel status that SnkStat will be updating.
Bank 0: SnkStatAddr=0, channels 15 to 0
Bank 1: SnkStatAddr=1, channels 31 to 16
Bank 2: SnkStatAddr=2, channels 47 to 32
. . .
Bank 15: SnkStatAddr=15, channels 255 to 239
SnkStatMask signal. When SnkStatWr_n is asserted (active low),
status for the different channels is updated. When SnkStatWr_n is
deasserted (active high), SnkStat input is ignored.
status among the corresponding group of 16 channels of status on
SnkStat (being addressed by SnkStatAddr) will be updated when
SnkStatWr_n is asserted (active low):
SnkStatMask[x] = 1, status for channel (x+(SnkStatAddr*16)) will be
updated.
SnkStatMask[y] = 0, status for channel (y+(SnkStatAddr*16)) will not
be updated.
For example, if SnkStatMask[15] = 1 and SnkStatAddr = 1, then
SnkStat[31:30] = 00 will overwrite the current status on channel 31. If
SnkStatMask is all zeros, none of the sixteen 2-bit status values will
be updated. If SnkStatMask is all ones, all sixteen of the 2-bit status
values will be updated.
Sink Static Configuration Interface
These signals are inputs to the core that are statically driven by setting them to a constant
value in the top-level wrapper file. The SPI-4.2 Lite release includes a wrapper file that has
the static configuration signals connected to the values selected in the CORE Generator
GUI. Customization of these signals can be done using the GUI.
Two of the Sink Static Configuration signals can be changed in circuit. There are static
registers for
To change these parameters while the core is operational,
If you sets the configuration signal to an illegal number, the core is automatically set to the
minimum value. Ta bl e 2 -6 defines the Sink Static Configuration signals.
SnkCalendar_M and SnkCalendar_Len that are synchronous to SnkStatClk.
SnkEn must first be deasserted.
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Sink Core Interfaces
Table 2-6: Sink Static Configuration Signals
Name Direction Range Description
R
NumDip4Errors[3:0] Static
Input
NumTrainSequences[3:0] Static
Input
1-15
Value of 0 is set to 1
1-15
Value of 0 is set to 1
SnkCalendar_M[7:0] Input 0-255
(effective range 1-256)
SnkCalendar_Len[8:0] Input 0-511
(effective range 1-512)
Number of DIP-4 Errors: The Sink Interface will go
out-of-frame (assert SnkOof) and stop accepting data
from the SPI-4.2 bus after receiving NumDip4Errors
consecutive DIP-4 errors.
Number of Complete Training Sequences: A
complete training pattern consists of 10 training
control words and 10 training data words. The Sink
interface requires NumTrainSequences consecutive
training patterns before going in frame (deasserting
SnkOof) and accepting data from the SPI-4.2 bus.
Sink Calendar Period: The SnkCalendar_M parameter
sets the number of repetitions of the calendar sequence
before the DIP-2 parity and framing words are
inserted.
The core implements this parameter as a static register
synchronous to SnkStatClk, and it can be updated in
circuit by first deasserting SnkEn.
Note that the Sink Calendar Period equals
SnkCalendar_M + 1. For example, if
SnkCalendar_M=22, the Sink Calendar Period will be
equal to 23.
Sink Calendar Length: The SnkCalendar_Len
parameter sets the length of the calendar sequence.
The core implements this parameter as a static register
synchronous to SnkStatClk, and it can be updated in
circuit by first deasserting SnkEn.
Note that the Sink Calendar Length equals
SnkCalendar_Len + 1. For example, if
SnkCalendar_Len=15, the Sink Calendar Length will
be equal to 16.
SnkAFThresAssert[8:0] Static
Input
1–508
Values less than1 are
set to 1.
Values greater than
508 are set to 508.
Sink Almost Full Threshold Assert: The
SnkAFThresAssert parameter defines the minimum
number of empty FIFO locations that exist when
SnkAlmostFull_n is asserted. Note that the assert
threshold must be less than or equal to the negate
threshold (SnkAFThresNegate).
When SnkAlmostFull_n is asserted, the core initiates
the flow control mechanism selected by the parameter
FifoAFMode. The FifoAFMode defines when the
interface stops sending valid FIFO status levels and
begins sending flow control information on RStat. This
indicates to the transmitting device that the core is
almost full and additional data cannot be sent.
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Table 2-6: Sink Static Configuration Signals (Continued)
Name Direction Range Description
Chapter 2: Core Architecture
SnkAFThresNegate[8:0] Static
Input
RSClkDiv Static
Input
RSClkPhase Static
Input
FifoAFMode[1:0] Static
Input
SnkAFThresAssert to
508
Values less than
SnkAFThresAssert are
set to
SnkAFThresAsset.
Values greater than
508 are set to 508.
Sink Almost Full Threshold Negate: The
SnkAFThresNegate parameter defines the minimum
number of empty FIFO locations that exist when
SnkAlmostFull_n is deasserted. Note that the negate
threshold must be greater or equal to the assert
threshold (SnkAFThresAssert).
When SnkAlmostFull_n is deasserted, the core stops
sending flow control (deasserts SnkAlmostFull_n) and
resumes transmission of valid FIFO status levels. This
indicates to the transmitting device that additional
data can be sent.
n/a Sink Status Clock Divide: This static input is used to
determine if the RSClk is 1/4 of the data rate, which is
compliant with the OIF specification, or 1/8 of the data
rate, which is required by some PHY ASSPs:
0: RSClkDiv = 1/4 rate (default value)
1: RSClkDiv = 1/8 rate
n/a Sink Status Clock Phase: This static input determines
whether the FIFO Status Channel data (RStat[1:0])
changes on the rising edge of RSClk or the falling edge
of RSClk:
0: RSClkPhase = rising edge of RSClk (default value)
1: RSClkPhase = falling edge of RSClk
n/a Sink Almost Full Mode: Selects the mode of operation
for the Sink interface when the Sink core reaches the
Almost Full threshold (SnkAFThresAssert).
If FifoAFMode is set to “00,” the Sink interface goes
out-of-frame when the core is almost full, and the Sink
Status logic sends the framing sequence “11” until Sink
core is not almost full.
If FifoAFMode is set to “01,” the Sink interface remains
in frame (SnkOof deasserted), and the Sink Status logic
sends satisfied “10” on all channels until
SnkAlmostFull_n is deasserted.
If FifoAFMode is set to “10” or “11,” the Sink interface
will remain in frame (SnkOof deasserted), and the Sink
Status logic continues to drive out the user’s status
information (i.e., continues in normal operation). In
this case, you should take immediate action to prevent
overflow and loss of data.
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Sink Clocking Interface
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The Sink core supports two clocking implementations: embedded clocking and user
clocking. The embedded clocking configuration provides a complete solution with the
clock circuitry embedded within the Sink core. The user clocking configuration allows the
clocking scheme to be implemented external to the Sink core.
A list of the Sink clocks for embedded clocking and their description is provided in
Tab le 2 -7. Ta bl e 2-8 defines the DCM reset and clock status signals, and Tab le 2 -9 defines
the user clocking signals. The minimum frequency for all clocks is dependent on the
minimum frequency of the DCM.
Table 2-7: Sink Core Clocks: Embedded Clocking
Clock Pins Direction Description Max. Frequency
RDClk0_GP Output
(User Interface)
RDClk180_GP Output
(User Interface)
RDClk0 General Purpose:
This clock is the full Rate
Receive Data Clock. It is
used for clocking the
internal logic of the core and
is routed to the User
Interface for use by the
user’s logic.
RDClk180 General
Purpose: This clock is the
inverted equivalent of
RDClk0_GP. It is used for
clocking the internal logic of
the core and is routed to the
User Interface for use by the
user’s logic.
Table 2-8: Sink Core Clocks: Status Signals
Name Direction
Clock
Domain
Virtex-5: 275 MHz
Virtex-4: 190 MHz
Virtex-II Pro: 160 MHz
Virtex-II: 160 MHz
Spartan-3: 115 MHz
Spartan-3E: 90 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
Virtex-5: 275 MHz
Virtex-4: 190 MHz
Virtex-II Pro: 160 MHz
Virtex-II: 160 MHz
Spartan-3: 115 MHz
Spartan-3E: 90 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
Description
DCMReset_RDClk Input N/A Reset of RDClk’s DCM
Locked_RDClk Output N/A Locked status of RDClk’s DCM
DCMLost_RDClk Output N/A Indicates RDClk input has stopped (status bit
one of RDClk DCM)
SnkClksRdy Output N/A Indicates all Sink core clocks are ready for use
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Chapter 2: Core Architecture
Table 2-9: Sink Core Clocks: User Clocking
Clock Pins Direction Description Max. Frequency
RDClk0_USER Input
RDClk180_USERInput
Source Core Interfaces
The Source core includes five functional modules:
• Source Data FIFO
• Source Data Transmit
• Source Status Registers
• Source Calendar
• Source Status Receive
(User Interface)
(User Interface)
RDClk0_USER: This clock
is used for clocking the
internal logic of the core.
RDClk180_USER: This
clock is the inverted
equivalent of
RDClk0_USER. It is used
for clocking the internal
logic of the core.
Virtex-5: 275 MHz
Virtex-4: 190 MHz
Virtex-II Pro: 160 MHz
Virtex-II: 160 MHz
Spartan-3: 115 MHz
Spartan-3E: 90 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
Virtex-5: 275 MHz
Virtex-4: 190 MHz
Virtex-II Pro: 160 MHz
Virtex-II: 160 MHz
Spartan-3: 115 MHz
Spartan-3E: 90 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
The Source core is comprised of the following interfaces:
• Source SPI-4.2 Interface
• Source User Interface
♦ Source Control and Status Interface
♦ Source FIFO Interface
♦ Source Status and Flow Control Interface
- Calendar Control Interface
- Status FIFO Interface
♦ Source Configuration Signals Interface
♦ Source Clocking Interface
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